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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 527360 (0x80c00)
Types: M200_UCODE
Names: »M207_36.M200_UCODE«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─⟦this⟧ »M207_36.M200_UCODE«
└─⟦this⟧ »M207_36.M200_UCODE«
└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
└─⟦this⟧ »M207_36.M200_UCODE«
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
└─⟦this⟧ »M207_36.M200_UCODE«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─⟦this⟧ »M207_36.M200_UCODE«
0100 ; -------------------------------------------------------------------------------------- 0100 ; no details_d8a4b6 0100 ; Initial Register File (adr, typ, val, frame:offset) where non-zero 0100 ; 000 TR00:00 0000000000000100 VR00:00 0000000008000000 0100 ; 001 TR00:01 00000000c0000000 VR00:01 0000000048000000 0100 ; 002 TR00:02 0000000068000060 VR00:02 0000000088000000 0100 ; 003 TR00:03 00000000a8000060 VR00:03 0000000000000000 0100 ; 004 TR00:04 0000000000000058 VR00:04 0000000000000000 0100 ; 005 TR00:05 0000000000000005 VR00:05 0000000000000000 0100 ; 006 TR00:06 0000000000000000 VR00:06 0000000000000000 0100 ; 007 TR00:07 0000000000000000 VR00:07 0000000000000000 0100 ; 008 TR00:08 0000000000000000 VR00:08 0000000000000000 0100 ; 009 TR00:09 0000000000000000 VR00:09 0000000000000000 0100 ; 00a TR00:0a 0000000000000000 VR00:0a 0000000000000000 0100 ; 00b TR00:0b 0000000000000000 VR00:0b 0000000000000000 0100 ; 00c TR00:0c 0000000000000000 VR00:0c 0000000000000000 0100 ; 00d TR00:0d 0000000000000000 VR00:0d 0000000000000000 0100 ; 00e TR00:0e 0000000000000000 VR00:0e 0000000000000000 0100 ; 00f TR00:0f 0000000000000000 VR00:0f 0000000000000000 0100 ; 010 TR00:10 0000000000000000 VR00:10 0000000000000000 0100 ; 011 TR00:11 0000000000000000 VR00:11 0000000000000000 0100 ; 012 TR00:12 0000000000000000 VR00:12 0000000000000000 0100 ; 013 TR00:13 0000000000000000 VR00:13 0000000000000000 0100 ; 014 TR00:14 0000000000000000 VR00:14 0000000000000000 0100 ; 015 TR00:15 0000000000000000 VR00:15 0000000000000000 0100 ; 016 TR00:16 0000000000000000 VR00:16 0000000000000000 0100 ; 017 TR00:17 0000000000000000 VR00:17 0000000000000000 0100 ; 018 TR00:18 0000000000000000 VR00:18 0000000000000000 0100 ; 019 TR00:19 0000000000000000 VR00:19 0000000000000000 0100 ; 01a TR00:1a 0000000000000000 VR00:1a 0000000000000000 0100 ; 01b TR00:1b 0000000000000000 VR00:1b 0000000000000000 0100 ; 01c TR00:1c 0000000000000000 VR00:1c 0000000000000000 0100 ; 01d TR00:1d 0000000000000000 VR00:1d 0000000000000000 0100 ; 01e TR00:1e 0000000000000000 VR00:1e 0000000000000000 0100 ; 01f TR00:1f 0000000000000000 VR00:1f 0000000000000000 0100 ; 020 TR01:00 ffffffffffffff00 VR01:00 0000000000000000 0100 ; 021 TR01:01 0000000080000000 VR01:01 0000000000000000 0100 ; 022 TR01:02 0000000040000000 VR01:02 0000000000000000 0100 ; 023 TR01:03 0000000020000000 VR01:03 0000000000000000 0100 ; 024 TR01:04 0000000000000000 VR01:04 0000000000000000 0100 ; 025 TR01:05 0000000000000000 VR01:05 0000000000000000 0100 ; 026 TR01:06 0000000000000000 VR01:06 0000000000000000 0100 ; 027 TR01:07 0000000000000000 VR01:07 0000000000000000 0100 ; 028 TR01:08 0000000000000000 VR01:08 0000000000000000 0100 ; 029 TR01:09 0000000000000000 VR01:09 0000000000000000 0100 ; 02a TR01:0a 0000000000000000 VR01:0a 0000000000000000 0100 ; 02b TR01:0b 0000000000000000 VR01:0b 0000000000000000 0100 ; 02c TR01:0c 0000000000000000 VR01:0c 0000000000000000 0100 ; 02d TR01:0d 0000000000000000 VR01:0d 0000000000000000 0100 ; 02e TR01:0e 0000000000000000 VR01:0e 0000000000000000 0100 ; 02f TR01:0f 0000000000000000 VR01:0f 0000000000000000 0100 ; 030 TR01:10 0000000000000000 VR01:10 0000000000000000 0100 ; 031 TR01:11 0000000000000000 VR01:11 0000000000000000 0100 ; 032 TR01:12 0000000000000000 VR01:12 0000000000000000 0100 ; 033 TR01:13 0000000000000000 VR01:13 0000000000000000 0100 ; 034 TR01:14 0000000000000000 VR01:14 0000000000000000 0100 ; 035 TR01:15 0000000000000000 VR01:15 0000000000000000 0100 ; 036 TR01:16 0000000000000000 VR01:16 0000000000000000 0100 ; 037 TR01:17 0000000000000000 VR01:17 0000000000000000 0100 ; 038 TR01:18 0000000000000000 VR01:18 0000000000000000 0100 ; 039 TR01:19 0000000000000000 VR01:19 0000000000000000 0100 ; 03a TR01:1a 0000000000000000 VR01:1a 0000000000000000 0100 ; 03b TR01:1b 0000000000000000 VR01:1b 0000000000000000 0100 ; 03c TR01:1c 0000000000000000 VR01:1c 0000000000000000 0100 ; 03d TR01:1d 0000000000000000 VR01:1d 0000000000000000 0100 ; 03e TR01:1e 0000000000000000 VR01:1e 0000000000000000 0100 ; 03f TR01:1f 0000000000000000 VR01:1f 0000000000000000 0100 ; 040 TR02:00 0000000000000001 VR02:00 0000000000000010 0100 ; 041 TR02:01 000000000000003f VR02:01 0000000000000000 0100 ; 042 TR02:02 0000000000000000 VR02:02 0000000000000000 0100 ; 043 TR02:03 0000000000000021 VR02:03 0000000000000000 0100 ; 044 TR02:04 0000000000000029 VR02:04 0000000000000000 0100 ; 045 TR02:05 0000000000000000 VR02:05 0000000000000000 0100 ; 046 TR02:06 0000000000000300 VR02:06 0000000000000000 0100 ; 047 TR02:07 0000000010000000 VR02:07 0000000000000000 0100 ; 048 TR02:08 0000000018000000 VR02:08 0000000000000000 0100 ; 049 TR02:09 0000000020000000 VR02:09 0000000000000000 0100 ; 04a TR02:0a 0000000000000009 VR02:0a 0000000000000000 0100 ; 04b TR02:0b ffffffffffffff80 VR02:0b 0000000000000000 0100 ; 04c TR02:0c 000007c000000000 VR02:0c 0000000000000000 0100 ; 04d TR02:0d 0000000000000029 VR02:0d 0400000000000000 0100 ; 04e TR02:0e 0000000000000021 VR02:0e ff00000000000000 0100 ; 04f TR02:0f 0000000000000000 VR02:0f 0000000000000000 0100 ; 050 TR02:10 0000000040000000 VR02:10 ffffffffffffffff 0100 ; 051 TR02:11 0000000000000008 VR02:11 0000000000000001 0100 ; 052 TR02:12 0000000000000000 VR02:12 0000000000000040 0100 ; 053 TR02:13 0000000000000400 VR02:13 0000000000001fff 0100 ; 054 TR02:14 0000001000000000 VR02:14 0000000010000000 0100 ; 055 TR02:15 0000000008000000 VR02:15 0000000020000000 0100 ; 056 TR02:16 000000000000007e VR02:16 0000000030000000 0100 ; 057 TR02:17 0000800000000000 VR02:17 00000000f8000080 0100 ; 058 TR02:18 0000000000000000 VR02:18 000000000000007f 0100 ; 059 TR02:19 000000000000007f VR02:19 0000000000000000 0100 ; 05a TR02:1a 000000000000003f VR02:1a 0000000000000002 0100 ; 05b TR02:1b 0000000000000000 VR02:1b 00000000ffffffff 0100 ; 05c TR02:1c 0000000008000000 VR02:1c 0000000000000000 0100 ; 05d TR02:1d 00000000f8000000 VR02:1d 0000000000000010 0100 ; 05e TR02:1e 0000000007ffff80 VR02:1e 0000000007ffff80 0100 ; 05f TR02:1f 0000000000000180 VR02:1f 0000000000000060 0100 ; 060 TR03:00 0000000000000000 VR03:00 0000000000000000 0100 ; 061 TR03:01 0000000000000000 VR03:01 0000000000000000 0100 ; 062 TR03:02 0000000000000000 VR03:02 0000000000000000 0100 ; 063 TR03:03 0000000000000000 VR03:03 0000000000000000 0100 ; 064 TR03:04 0000000000000000 VR03:04 0000000000000000 0100 ; 065 TR03:05 0000000000000000 VR03:05 0000000000000000 0100 ; 066 TR03:06 0000000000000000 VR03:06 0000000000000000 0100 ; 067 TR03:07 0000000000000000 VR03:07 0000000000000000 0100 ; 068 TR03:08 0000000000000000 VR03:08 0000000000000000 0100 ; 069 TR03:09 0000000000000000 VR03:09 0000000000000000 0100 ; 06a TR03:0a 0000000000000000 VR03:0a 0000000000000000 0100 ; 06b TR03:0b 0000000000000000 VR03:0b 0000000000000000 0100 ; 06c TR03:0c 0000000000000000 VR03:0c 0000000000000000 0100 ; 06d TR03:0d 0000000000000000 VR03:0d 0000000000000000 0100 ; 06e TR03:0e 0000000000000000 VR03:0e 0000000000000000 0100 ; 06f TR03:0f 0000000000000000 VR03:0f 0000000000000000 0100 ; 070 TR03:10 0000000000000000 VR03:10 0000000000000004 0100 ; 071 TR03:11 0000000000000000 VR03:11 0000000000000000 0100 ; 072 TR03:12 0000000000000000 VR03:12 0000000000000000 0100 ; 073 TR03:13 0000000000000000 VR03:13 0000000000000000 0100 ; 074 TR03:14 0000000000000000 VR03:14 0000000000000000 0100 ; 075 TR03:15 0000000000000000 VR03:15 0000000000000000 0100 ; 076 TR03:16 0000000000000000 VR03:16 0000000000000000 0100 ; 077 TR03:17 0000000000000000 VR03:17 0bad0bad0bad0bad 0100 ; 078 TR03:18 0404000100000000 VR03:18 0000000000000000 0100 ; 079 TR03:19 0000000000000000 VR03:19 0000000000000000 0100 ; 07a TR03:1a 0000000000000000 VR03:1a 0000000000000000 0100 ; 07b TR03:1b 0000000000000000 VR03:1b 0000200000000000 0100 ; 07c TR03:1c 0000000000000000 VR03:1c 0000000000000000 0100 ; 07d TR03:1d 0000000000000000 VR03:1d 0000000000000000 0100 ; 07e TR03:1e 0000000000000000 VR03:1e 0000000000000004 0100 ; 07f TR03:1f 0000000000000000 VR03:1f 0000000000000000 0100 ; 080 TR04:00 0000000000000000 VR04:00 0000000000000000 0100 ; 081 TR04:01 0000000000000000 VR04:01 0000000000000001 0100 ; 082 TR04:02 0000000000000000 VR04:02 0000000000000000 0100 ; 083 TR04:03 0000000000000000 VR04:03 0000000000000000 0100 ; 084 TR04:04 0000000000000000 VR04:04 0000000000000000 0100 ; 085 TR04:05 0000000000000000 VR04:05 0000000000000000 0100 ; 086 TR04:06 0000000000000000 VR04:06 0000000000000000 0100 ; 087 TR04:07 0000000000000000 VR04:07 0000000000000000 0100 ; 088 TR04:08 0000000000000000 VR04:08 0000000000000000 0100 ; 089 TR04:09 0000000000000000 VR04:09 0000000000000000 0100 ; 08a TR04:0a 0000000000000028 VR04:0a 0000000000000000 0100 ; 08b TR04:0b 0000000000000000 VR04:0b 0000000000000000 0100 ; 08c TR04:0c 0000000000000000 VR04:0c 0000000000000000 0100 ; 08d TR04:0d 0000000000000180 VR04:0d 0000000000000080 0100 ; 08e TR04:0e 0000000000000000 VR04:0e 0000000000000100 0100 ; 08f TR04:0f 0000000000000000 VR04:0f 0000000000000180 0100 ; 090 TR04:10 0000000000000000 VR04:10 0000000000000500 0100 ; 091 TR04:11 0000000000000000 VR04:11 0000000000001f80 0100 ; 092 TR04:12 0000000000000000 VR04:12 000ffcf00000a000 0100 ; 093 TR04:13 0000000000000000 VR04:13 0000000000200000 0100 ; 094 TR04:14 0000000000000000 VR04:14 0000000000000000 0100 ; 095 TR04:15 0000000000000000 VR04:15 0000000000000000 0100 ; 096 TR04:16 0000000000000000 VR04:16 0000000000000000 0100 ; 097 TR04:17 0000000000000000 VR04:17 0000000000000000 0100 ; 098 TR04:18 0000000000000000 VR04:18 0000000000000000 0100 ; 099 TR04:19 0000000000000000 VR04:19 0000000000000000 0100 ; 09a TR04:1a 0000000000000000 VR04:1a 0000000000000000 0100 ; 09b TR04:1b 0000000000000000 VR04:1b 000000000000a000 0100 ; 09c TR04:1c 0000000000000000 VR04:1c 0000040000000000 0100 ; 09d TR04:1d 0000000000000000 VR04:1d 0000000000000000 0100 ; 09e TR04:1e 0000000000000000 VR04:1e 0000000000000000 0100 ; 09f TR04:1f 0000000000000000 VR04:1f 0000000000000000 0100 ; 0a0 TR05:00 0000000000000001 VR05:00 0000000000000001 0100 ; 0a1 TR05:01 0000000000000004 VR05:01 0000000000000003 0100 ; 0a2 TR05:02 0000004000000000 VR05:02 0000000000000005 0100 ; 0a3 TR05:03 0000000000000006 VR05:03 0000000000000006 0100 ; 0a4 TR05:04 000000000000000a VR05:04 0000000000000007 0100 ; 0a5 TR05:05 000000000000000e VR05:05 0000000000000008 0100 ; 0a6 TR05:06 000000000000000f VR05:06 0000000000000009 0100 ; 0a7 TR05:07 0000000000000013 VR05:07 000000000000000a 0100 ; 0a8 TR05:08 0000000000000014 VR05:08 000000000000000b 0100 ; 0a9 TR05:09 0000000000000016 VR05:09 000000000000000c 0100 ; 0aa TR05:0a 0000000000000026 VR05:0a 000000000000000d 0100 ; 0ab TR05:0b 0000000000000036 VR05:0b 000000000000000e 0100 ; 0ac TR05:0c 0000000000000039 VR05:0c 0000000000002300 0100 ; 0ad TR05:0d 0000000000000040 VR05:0d 0000000000000020 0100 ; 0ae TR05:0e 0000000000000046 VR05:0e 0000000000000025 0100 ; 0af TR05:0f 000000000000005f VR05:0f 0000000000000031 0100 ; 0b0 TR05:10 0000000000000060 VR05:10 000000000000003f 0100 ; 0b1 TR05:11 000000f000000000 VR05:11 00000000fff90000 0100 ; 0b2 TR05:12 000000000000007b VR05:12 0000000000000480 0100 ; 0b3 TR05:13 0000000000000680 VR05:13 000000000000006c 0100 ; 0b4 TR05:14 000000000000009e VR05:14 0000000000000074 0100 ; 0b5 TR05:15 0000000000000118 VR05:15 000000000000007c 0100 ; 0b6 TR05:16 0000000000000158 VR05:16 00000000000000ff 0100 ; 0b7 TR05:17 0000000000000200 VR05:17 0000000000000076 0100 ; 0b8 TR05:18 0000000000000300 VR05:18 0000000000000200 0100 ; 0b9 TR05:19 0000000000000380 VR05:19 0000000000000580 0100 ; 0ba TR05:1a 0000000000000800 VR05:1a 00000000000003ff 0100 ; 0bb TR05:1b 0000000000001f80 VR05:1b 0000000000000400 0100 ; 0bc TR05:1c 0000000007ff8000 VR05:1c 0000000000002400 0100 ; 0bd TR05:1d 0000000008000008 VR05:1d 0000000000007fff 0100 ; 0be TR05:1e 0000000008000046 VR05:1e 000000000000ffff 0100 ; 0bf TR05:1f 0000000000000047 VR05:1f 5f5f5f5f5f5f5f5f 0100 ; 0c0 TR06:00 000000000800009e VR06:00 0000000040000000 0100 ; 0c1 TR06:01 0000000020000060 VR06:01 000000000000000f 0100 ; 0c2 TR06:02 00000000f6000000 VR06:02 0000000080000000 0100 ; 0c3 TR06:03 0d04000f00000001 VR06:03 0002000000000000 0100 ; 0c4 TR06:04 0000000080000118 VR06:04 0000000000000033 0100 ; 0c5 TR06:05 0000000080000158 VR06:05 00000000000000f0 0100 ; 0c6 TR06:06 0000000088000000 VR06:06 0000000000008000 0100 ; 0c7 TR06:07 fffffffffffffe80 VR06:07 00000000c0000000 0100 ; 0c8 TR06:08 0000000000000580 VR06:08 0000000100000001 0100 ; 0c9 TR06:09 0000000000000064 VR06:09 0000004000000040 0100 ; 0ca TR06:0a 0000000000000015 VR06:0a 0000004100000041 0100 ; 0cb TR06:0b 0000000007ffe000 VR06:0b 0000007fffffffff 0100 ; 0cc TR06:0c 000000000800006c VR06:0c 000000000004c4b4 0100 ; 0cd TR06:0d 00000000000002a0 VR06:0d 0000000000000028 0100 ; 0ce TR06:0e 00000000ffff0000 VR06:0e 0004000000000000 0100 ; 0cf TR06:0f 0000000f00000000 VR06:0f 0000000000000032 0100 ; 0d0 TR06:10 ffffffffc0000000 VR06:10 00ffffff0000000f 0100 ; 0d1 TR06:11 ff00000000000000 VR06:11 0200000000000000 0100 ; 0d2 TR06:12 00000000e0000176 VR06:12 8000000000000000 0100 ; 0d3 TR06:13 ffff000000000000 VR06:13 8200000000000000 0100 ; 0d4 TR06:14 00000000000000c0 VR06:14 0000000000000041 0100 ; 0d5 TR06:15 ffffffffffff0000 VR06:15 00000000000002a0 0100 ; 0d6 TR06:16 fffffffffffffe00 VR06:16 000000007fffffff 0100 ; 0d7 TR06:17 000000000000000d VR06:17 ffffffff80000000 0100 ; 0d8 TR06:18 0000000000000076 VR06:18 0000000000000027 0100 ; 0d9 TR06:19 00000000d0000000 VR06:19 00000000000010c0 0100 ; 0da TR06:1a 0000000008000000 VR06:1a 0000000000000042 0100 ; 0db TR06:1b 000000000000002e VR06:1b 00000000000000fe 0100 ; 0dc TR06:1c fffffffffffffd00 VR06:1c 0000000000001008 0100 ; 0dd TR06:1d 0000000000000039 VR06:1d 0000000100000000 0100 ; 0de TR06:1e 00000000c0000116 VR06:1e 0000000200000000 0100 ; 0df TR06:1f 0000000000002000 VR06:1f 0000000000002000 0100 ; 0e0 TR07:00 0000000000000280 VR07:00 ffffffffffffff80 0100 ; 0e1 TR07:01 0000003000000000 VR07:01 000fffff00000000 0100 ; 0e2 TR07:02 ffff00000000000e VR07:02 0100000000000000 0100 ; 0e3 TR07:03 0000000060000000 VR07:03 0000000000000011 0100 ; 0e4 TR07:04 000000000000016c VR07:04 000000000000fff0 0100 ; 0e5 TR07:05 00ff000000000000 VR07:05 0000ffffffffffff 0100 ; 0e6 TR07:06 0001000000000000 VR07:06 000000000000004e 0100 ; 0e7 TR07:07 0000005000000000 VR07:07 0000000000000f80 0100 ; 0e8 TR07:08 00000000f0000000 VR07:08 ffffffff00000000 0100 ; 0e9 TR07:09 0000000048000000 VR07:09 7fffffffffffffff 0100 ; 0ea TR07:0a 0000000030000000 VR07:0a 0000000000000026 0100 ; 0eb TR07:0b 0000000088000011 VR07:0b 0000000000000036 0100 ; 0ec TR07:0c 00000000a8000071 VR07:0c 0000008000000040 0100 ; 0ed TR07:0d 0000000000000174 VR07:0d 0000000000000280 0100 ; 0ee TR07:0e 0000000080000029 VR07:0e 0000000000000380 0100 ; 0ef TR07:0f 0000007f00000000 VR07:0f 0000000000000021 0100 ; 0f0 TR07:10 0100000000000000 VR07:10 0000000000000016 0100 ; 0f1 TR07:11 0200000000000000 VR07:11 00000000ffff00ff 0100 ; 0f2 TR07:12 fec7000000000000 VR07:12 0000000000000012 0100 ; 0f3 TR07:13 0000000000001001 VR07:13 0000000000000043 0100 ; 0f4 TR07:14 000000000ff00000 VR07:14 00000000000000a0 0100 ; 0f5 TR07:15 00000000ffffffff VR07:15 ffffffffffffff00 0100 ; 0f6 TR07:16 0000037000000000 VR07:16 0000800000000000 0100 ; 0f7 TR07:17 000000000000003e VR07:17 0000005500000000 0100 ; 0f8 TR07:18 0000040400000050 VR07:18 8000005500000000 0100 ; 0f9 TR07:19 0000000040000020 VR07:19 0000000000000038 0100 ; 0fa TR07:1a 000000000000004e VR07:1a 0000000088000011 0100 ; 0fb TR07:1b 00000000000000ff VR07:1b ffffff8000000000 0100 ; 0fc TR07:1c 00000001ffffffff VR07:1c 0000008000000000 0100 ; 0fd TR07:1d 00000000f800007f VR07:1d 0000007f00000000 0100 ; 0fe TR07:1e 0000000080000010 VR07:1e 0000000000000045 0100 ; 0ff TR07:1f 0000000000000081 VR07:1f 0000000000000044 0100 ; 100 TR08:00 ffffffffffffffff VR08:00 00fe007f00000000 0100 ; 101 TR08:01 0000000060000060 VR08:01 00000000003fffff 0100 ; 102 TR08:02 0000000000000044 VR08:02 0001000000000000 0100 ; 103 TR08:03 ffffffffffffffe0 VR08:03 000000000000004c 0100 ; 104 TR08:04 000ffc000000a000 VR08:04 0000000000000013 0100 ; 105 TR08:05 0000008000000000 VR08:05 0000000000000030 0100 ; 106 TR08:06 000007c008000000 VR08:06 00000000000005ff 0100 ; 107 TR08:07 ffffffffe0000000 VR08:07 00ff000000000000 0100 ; 108 TR08:08 fffffffffffffecc VR08:08 1000000000000000 0100 ; 109 TR08:09 000000000800014c VR08:09 0000001000000000 0100 ; 10a TR08:0a 0000000007ffbf00 VR08:0a 00008000ffffffff 0100 ; 10b TR08:0b 8000000000000000 VR08:0b 0000808000000000 0100 ; 10c TR08:0c 2000000000000000 VR08:0c 00000000000000e0 0100 ; 10d TR08:0d 0000000000000050 VR08:0d 00000000000000e1 0100 ; 10e TR08:0e 000000003800001f VR08:0e 00000000000000e2 0100 ; 10f TR08:0f 0000000100000000 VR08:0f 00000000000000e3 0100 ; 110 TR08:10 fffff83ff7ffffff VR08:10 00000000000000e4 0100 ; 111 TR08:11 0000000000000054 VR08:11 0000000000000061 0100 ; 112 TR08:12 000000000000017c VR08:12 0000000000000062 0100 ; 113 TR08:13 1020a040101011c0 VR08:13 0000000000000063 0100 ; 114 TR08:14 000000000000001c VR08:14 0000000000000065 0100 ; 115 TR08:15 000000000000001b VR08:15 000000000000002f 0100 ; 116 TR08:16 0000000080000008 VR08:16 000000000000004f 0100 ; 117 TR08:17 0000000000004000 VR08:17 000000000000005f 0100 ; 118 TR08:18 0000000088000008 VR08:18 000000000000fe00 0100 ; 119 TR08:19 0000060000000000 VR08:19 fffe010000000080 0100 ; 11a TR08:1a 00000000a0000068 VR08:1a 0000000000002710 0100 ; 11b TR08:1b 0000000020000068 VR08:1b 0001ff8000000000 0100 ; 11c TR08:1c 0010000000000000 VR08:1c 0000000000000049 0100 ; 11d TR08:1d 000000000000001f VR08:1d 0408000000000000 0100 ; 11e TR08:1e 7ff0000000000000 VR08:1e 8204000000000000 0100 ; 11f TR08:1f 3ff0000000000000 VR08:1f 00000000000000d0 0100 ; 120 TR09:00 7fe0000000000000 VR09:00 000000000000007b 0100 ; 121 TR09:01 00000000000003ff VR09:01 00f0000000000000 0100 ; 122 TR09:02 00000000000007ff VR09:02 0000000000000300 0100 ; 123 TR09:03 ffffffffffffffcd VR09:03 0000000000000034 0100 ; 124 TR09:04 00000000e0000060 VR09:04 000000000000fc00 0100 ; 125 TR09:05 00000000e0000020 VR09:05 fff9000000000000 0100 ; 126 TR09:06 000000000000031f VR09:06 0000000000000070 0100 ; 127 TR09:07 00000000000000a0 VR09:07 1819113111161715 0100 ; 128 TR09:08 00000000e0000000 VR09:08 0000000000000014 0100 ; 129 TR09:09 0000000040000029 VR09:09 0000000008000100 0100 ; 12a TR09:0a 000000000fffff80 VR09:0a 0000000028000160 0100 ; 12b TR09:0b 00000000000000ad VR09:0b 00000000000002d0 0100 ; 12c TR09:0c 00000000e0000040 VR09:0c bff0000000000000 0100 ; 12d TR09:0d 000000000000004c VR09:0d 0006000000000000 0100 ; 12e TR09:0e 0000000020000040 VR09:0e 0000000000e00000 0100 ; 12f TR09:0f 8000000080000000 VR09:0f 0000000007ffff00 0100 ; 130 TR09:10 0000000008000025 VR09:10 0000000000000081 0100 ; 131 TR09:11 0000000020000020 VR09:11 0000000000000052 0100 ; 132 TR09:12 fffff83fffffffff VR09:12 0000000000000320 0100 ; 133 TR09:13 00000000f4000004 VR09:13 0000000000000050 0100 ; 134 TR09:14 0000000000000500 VR09:14 000000000000031f 0100 ; 135 TR09:15 fffffffffffffd80 VR09:15 000000ff00000000 0100 ; 136 TR09:16 0000000001800000 VR09:16 00000fffffffffff 0100 ; 137 TR09:17 ffffffff7fffff88 VR09:17 fffeffffffffffff 0100 ; 138 TR09:18 0000024000000000 VR09:18 fffffffffffeffff 0100 ; 139 TR09:19 0d01000100000001 VR09:19 0000000000000088 0100 ; 13a TR09:1a fffff83fe7ffffff VR09:1a 0000000000520000 0100 ; 13b TR09:1b 0000200000000000 VR09:1b 0000000000000082 0100 ; 13c TR09:1c 0000180000000000 VR09:1c 0000000000000046 0100 ; 13d TR09:1d 00001fc000000000 VR09:1d 0000000001ffe000 0100 ; 13e TR09:1e 0000000000020000 VR09:1e 0000000000000048 0100 ; 13f TR09:1f 0000000007ffff00 VR09:1f 0000000000000051 0100 ; 140 TR0a:00 0000000088000000 VR0a:00 0000000000000000 0100 ; 141 TR0a:01 0000000000000000 VR0a:01 0000000000000000 0100 ; 142 TR0a:02 0000000000000000 VR0a:02 0000000000000000 0100 ; 143 TR0a:03 0000000000000000 VR0a:03 0000000000000000 0100 ; 144 TR0a:04 0000000000000000 VR0a:04 0000000000000000 0100 ; 145 TR0a:05 0000000000000000 VR0a:05 0000000000000000 0100 ; 146 TR0a:06 0000000000000000 VR0a:06 0000000000000000 0100 ; 147 TR0a:07 0000000000000000 VR0a:07 0000000000000000 0100 ; 148 TR0a:08 0000000000000000 VR0a:08 0000000000000000 0100 ; 149 TR0a:09 0000000000000000 VR0a:09 0000000000000000 0100 ; 14a TR0a:0a 0000000000000000 VR0a:0a 0000000000000000 0100 ; 14b TR0a:0b 0000000000000000 VR0a:0b 0000000000000000 0100 ; 14c TR0a:0c 0000000000000000 VR0a:0c 0000000000000000 0100 ; 14d TR0a:0d 0000000000000000 VR0a:0d 0000000000000000 0100 ; 14e TR0a:0e 0000000000000000 VR0a:0e 0000000000000000 0100 ; 14f TR0a:0f 0000000000000000 VR0a:0f 0000000000000000 0100 ; 150 TR0a:10 0000000000000000 VR0a:10 0000000000000000 0100 ; 151 TR0a:11 0000000000000000 VR0a:11 0000000000000000 0100 ; 152 TR0a:12 0000000000000000 VR0a:12 0000000000000000 0100 ; 153 TR0a:13 0000000000000000 VR0a:13 0000000000000000 0100 ; 154 TR0a:14 0000000000000000 VR0a:14 0000000000000000 0100 ; 155 TR0a:15 0000000000000000 VR0a:15 0000000000000000 0100 ; 156 TR0a:16 0000000000000000 VR0a:16 0000000000000000 0100 ; 157 TR0a:17 0000000000000000 VR0a:17 0000000000000000 0100 ; 158 TR0a:18 0000000000000000 VR0a:18 0000000000000000 0100 ; 159 TR0a:19 0000000000000000 VR0a:19 0000000000000000 0100 ; 15a TR0a:1a 0000000000000000 VR0a:1a 0000000000000000 0100 ; 15b TR0a:1b 0000000000000000 VR0a:1b 0000000000000000 0100 ; 15c TR0a:1c 0000000000000000 VR0a:1c 0000000000000000 0100 ; 15d TR0a:1d 0000000000000000 VR0a:1d 0000000000000000 0100 ; 15e TR0a:1e 0000000000000000 VR0a:1e 0000000000000000 0100 ; 15f TR0a:1f 0000000000000000 VR0a:1f 0000000000000000 0100 ; 160 TR0b:00 ffffffffffffffff VR0b:00 ffffffffffffffff 0100 ; 161 TR0b:01 ffffffffffffffff VR0b:01 ffffffffffffffff 0100 ; 162 TR0b:02 ffffffffffffffff VR0b:02 ffffffffffffffff 0100 ; 163 TR0b:03 ffffffffffffffff VR0b:03 ffffffffffffffff 0100 ; 164 TR0b:04 ffffffffffffffff VR0b:04 ffffffffffffffff 0100 ; 165 TR0b:05 ffffffffffffffff VR0b:05 ffffffffffffffff 0100 ; 166 TR0b:06 ffffffffffffffff VR0b:06 ffffffffffffffff 0100 ; 167 TR0b:07 ffffffffffffffff VR0b:07 ffffffffffffffff 0100 ; 168 TR0b:08 ffffffffffffffff VR0b:08 ffffffffffffffff 0100 ; 169 TR0b:09 ffffffffffffffff VR0b:09 ffffffffffffffff 0100 ; 16a TR0b:0a ffffffffffffffff VR0b:0a ffffffffffffffff 0100 ; 16b TR0b:0b ffffffffffffffff VR0b:0b ffffffffffffffff 0100 ; 16c TR0b:0c ffffffffffffffff VR0b:0c ffffffffffffffff 0100 ; 16d TR0b:0d ffffffffffffffff VR0b:0d ffffffffffffffff 0100 ; 16e TR0b:0e ffffffffffffffff VR0b:0e ffffffffffffffff 0100 ; 16f TR0b:0f ffffffffffffffff VR0b:0f ffffffffffffffff 0100 ; 170 TR0b:10 ffffffffffffffff VR0b:10 ffffffffffffffff 0100 ; 171 TR0b:11 ffffffffffffffff VR0b:11 ffffffffffffffff 0100 ; 172 TR0b:12 ffffffffffffffff VR0b:12 ffffffffffffffff 0100 ; 173 TR0b:13 ffffffffffffffff VR0b:13 ffffffffffffffff 0100 ; 174 TR0b:14 ffffffffffffffff VR0b:14 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0000000000000000 VR15:1b 0000000000000000 0100 ; 2bc TR15:1c 0000000000000000 VR15:1c 0000000000000000 0100 ; 2bd TR15:1d 0000000000000000 VR15:1d 0000000000000000 0100 ; 2be TR15:1e 0000000000000000 VR15:1e 0000000000000000 0100 ; 2bf TR15:1f 0000000000000000 VR15:1f 0000000000000000 0100 ; 2c0 TR16:00 000000000000007f VR16:00 0000000000000000 0100 ; 2c1 TR16:01 0000000080000000 VR16:01 0000000000000000 0100 ; 2c2 TR16:02 0000000000000000 VR16:02 0000000000000000 0100 ; 2c3 TR16:03 0000000000000000 VR16:03 0000000000000000 0100 ; 2c4 TR16:04 0000000000000000 VR16:04 0000000000000000 0100 ; 2c5 TR16:05 0000000000000000 VR16:05 0000000000000000 0100 ; 2c6 TR16:06 0000000000000000 VR16:06 0000000000000000 0100 ; 2c7 TR16:07 0000000000000000 VR16:07 0000000000000000 0100 ; 2c8 TR16:08 0000000000000000 VR16:08 0000000000000000 0100 ; 2c9 TR16:09 0000000000000000 VR16:09 0000000000000000 0100 ; 2ca TR16:0a 0000000000000000 VR16:0a 0000000000000000 0100 ; 2cb TR16:0b 0000000000000000 VR16:0b 0000000000000000 0100 ; 2cc TR16:0c 0000000000000000 VR16:0c 0000000000000000 0100 ; 2cd TR16:0d 0000000000000000 VR16:0d 0000000000000000 0100 ; 2ce TR16:0e 0000000000000000 VR16:0e 0000000000000000 0100 ; 2cf TR16:0f 0000000000000000 VR16:0f 0000000000000000 0100 ; 2d0 TR16:10 0000000000000000 VR16:10 0000000000000000 0100 ; 2d1 TR16:11 0000000000000000 VR16:11 0000000000000000 0100 ; 2d2 TR16:12 0000000000000000 VR16:12 0000000000000000 0100 ; 2d3 TR16:13 0000000000000000 VR16:13 0000000000000000 0100 ; 2d4 TR16:14 0000000000000000 VR16:14 0000000000000000 0100 ; 2d5 TR16:15 0000000000000000 VR16:15 0000000000000000 0100 ; 2d6 TR16:16 0000000000000000 VR16:16 0000000000000000 0100 ; 2d7 TR16:17 0000000000000000 VR16:17 0000000000000000 0100 ; 2d8 TR16:18 0000000000000000 VR16:18 0000000000000000 0100 ; 2d9 TR16:19 0000000000000000 VR16:19 0000000000000000 0100 ; 2da TR16:1a 0000000000000000 VR16:1a 0000000000000000 0100 ; 2db TR16:1b 0000000000000000 VR16:1b 0000000000000000 0100 ; 2dc TR16:1c 0000000000000000 VR16:1c 0000000000000000 0100 ; 2dd TR16:1d 0000000000000000 VR16:1d 0000000000000000 0100 ; 2de TR16:1e 0000000000000000 VR16:1e 0000000000000000 0100 ; 2df TR16:1f 0000000000000000 VR16:1f 0000000000000000 0100 ; 2e0 TR17:00 0000000000000000 VR17:00 0000000000000000 0100 ; 2e1 TR17:01 0000000000000000 VR17:01 0000000000000000 0100 ; 2e2 TR17:02 0000000000000000 VR17:02 0000000000000000 0100 ; 2e3 TR17:03 0000000000000000 VR17:03 0000000000000000 0100 ; 2e4 TR17:04 0000000000000000 VR17:04 0000000000000000 0100 ; 2e5 TR17:05 0000000000000000 VR17:05 0000000000000000 0100 ; 2e6 TR17:06 0000000000000000 VR17:06 0000000000000000 0100 ; 2e7 TR17:07 0000000000000000 VR17:07 0000000000000000 0100 ; 2e8 TR17:08 0000000000000000 VR17:08 0000000000000000 0100 ; 2e9 TR17:09 0000000000000000 VR17:09 0000000000000000 0100 ; 2ea TR17:0a 0000000000000000 VR17:0a 0000000000000000 0100 ; 2eb TR17:0b 0000000000000000 VR17:0b 0000000000000000 0100 ; 2ec TR17:0c 0000000000000000 VR17:0c 0000000000000000 0100 ; 2ed TR17:0d 0000000000000000 VR17:0d 0000000000000000 0100 ; 2ee TR17:0e 0000000000000000 VR17:0e 0000000000000000 0100 ; 2ef TR17:0f 0000000000000000 VR17:0f 0000000000000000 0100 ; 2f0 TR17:10 0000000000000000 VR17:10 0000000000000000 0100 ; 2f1 TR17:11 0000000000000000 VR17:11 0000000000000000 0100 ; 2f2 TR17:12 0000000000000000 VR17:12 0000000000000000 0100 ; 2f3 TR17:13 0000000000000000 VR17:13 0000000000000000 0100 ; 2f4 TR17:14 ffffffffffff0000 VR17:14 0000000007fffd80 0100 ; 2f5 TR17:15 0000000000000600 VR17:15 000ffcf00000a000 0100 ; 2f6 TR17:16 0000000000000180 VR17:16 0000000000000180 0100 ; 2f7 TR17:17 0000000000000100 VR17:17 0000000000000600 0100 ; 2f8 TR17:18 0000000000000500 VR17:18 0000000649534e00 0100 ; 2f9 TR17:19 fd00000000000000 VR17:19 0000000000098969 0100 ; 2fa TR17:1a fe00000000000000 VR17:1a ffff000000000000 0100 ; 2fb TR17:1b 8f8f000000000000 VR17:1b 000000000000ff00 0100 ; 2fc TR17:1c 4f4f000000000000 VR17:1c 0003ffffffffffff 0100 ; 2fd TR17:1d 0000000000000000 VR17:1d 0000000000000000 0100 ; 2fe TR17:1e 0000000080000000 VR17:1e 0000000000000500 0100 ; 2ff TR17:1f 0000000000000000 VR17:1f 0000000000000000 0100 ; 300 TR18:00 0000000080000000 VR18:00 0000000000000000 0100 ; 301 TR18:01 0000000000000000 VR18:01 0000000000000000 0100 ; 302 TR18:02 0000000000000000 VR18:02 0000000000000000 0100 ; 303 TR18:03 0000000000000000 VR18:03 0000000000000000 0100 ; 304 TR18:04 0000000000000000 VR18:04 0000000000000000 0100 ; 305 TR18:05 0000000000000000 VR18:05 0000000000000000 0100 ; 306 TR18:06 0000000000000000 VR18:06 0000000000000000 0100 ; 307 TR18:07 0000000000000000 VR18:07 0000000000000000 0100 ; 308 TR18:08 0000000000000000 VR18:08 0000000000000000 0100 ; 309 TR18:09 0000000000000000 VR18:09 0000000000000000 0100 ; 30a TR18:0a 0000000000000000 VR18:0a 0000000000000000 0100 ; 30b TR18:0b 0000000000000000 VR18:0b 0000000000000000 0100 ; 30c TR18:0c 0000000000000000 VR18:0c 0000000000000000 0100 ; 30d TR18:0d 0000000000000000 VR18:0d 0000000000000000 0100 ; 30e TR18:0e 0000000000000000 VR18:0e 0000000000000000 0100 ; 30f TR18:0f 0000000000000000 VR18:0f 0000000000000000 0100 ; 310 TR18:10 0000000000000000 VR18:10 0000000000000000 0100 ; 311 TR18:11 0000000000000000 VR18:11 0000000000000000 0100 ; 312 TR18:12 0000000007ffe700 VR18:12 0000000000000000 0100 ; 313 TR18:13 0000000000000000 VR18:13 0000000000000000 0100 ; 314 TR18:14 0000000000000000 VR18:14 0000000000000000 0100 ; 315 TR18:15 0000000000000000 VR18:15 0000000000000000 0100 ; 316 TR18:16 0000000000000000 VR18:16 0000000000000000 0100 ; 317 TR18:17 0000000000000000 VR18:17 0000000000000000 0100 ; 318 TR18:18 0000000000000000 VR18:18 0000000000000000 0100 ; 319 TR18:19 0000000000000000 VR18:19 0000000000000000 0100 ; 31a TR18:1a 0000000000000000 VR18:1a 0000000000000000 0100 ; 31b TR18:1b 0000000000000000 VR18:1b 0000000000000000 0100 ; 31c TR18:1c 0000000000000000 VR18:1c 0000000000000000 0100 ; 31d TR18:1d 0000000000000000 VR18:1d 0000000000000000 0100 ; 31e TR18:1e 0000000000000000 VR18:1e 0000000000000000 0100 ; 31f TR18:1f 0000000000000000 VR18:1f 0000000000000000 0100 ; 320 TR19:00 0000000000000000 VR19:00 0000000000000000 0100 ; 321 TR19:01 0000000000000000 VR19:01 0000000000000000 0100 ; 322 TR19:02 0000000000000000 VR19:02 0000000000000000 0100 ; 323 TR19:03 0000000000000000 VR19:03 0000000000000000 0100 ; 324 TR19:04 0000000000000000 VR19:04 0000000000000000 0100 ; 325 TR19:05 0000000000000000 VR19:05 0000000000000000 0100 ; 326 TR19:06 0000000000000000 VR19:06 0000000000000000 0100 ; 327 TR19:07 0000000000000000 VR19:07 0000000000000000 0100 ; 328 TR19:08 0000000000000000 VR19:08 0000000000000008 0100 ; 329 TR19:09 0000000000000000 VR19:09 0000000000000000 0100 ; 32a TR19:0a 0000000000000000 VR19:0a 0000000000000000 0100 ; 32b TR19:0b 0000000000000000 VR19:0b 0000000000000000 0100 ; 32c TR19:0c 0000000000000000 VR19:0c 0000000000000000 0100 ; 32d TR19:0d 0000000000000000 VR19:0d 0000000000000000 0100 ; 32e TR19:0e 0000000000000000 VR19:0e 0000000000000000 0100 ; 32f TR19:0f 0000000000000000 VR19:0f 0000000000000000 0100 ; 330 TR19:10 0000000000000000 VR19:10 0000000000000000 0100 ; 331 TR19:11 0000000000000000 VR19:11 0000000000000000 0100 ; 332 TR19:12 0000000000000000 VR19:12 0000000000000000 0100 ; 333 TR19:13 0000000000000000 VR19:13 0000000000000000 0100 ; 334 TR19:14 0000000000000000 VR19:14 0000000000000000 0100 ; 335 TR19:15 0000000000000000 VR19:15 0000000000000000 0100 ; 336 TR19:16 0000000000000000 VR19:16 0000000000000000 0100 ; 337 TR19:17 0000000000000000 VR19:17 0000000000000000 0100 ; 338 TR19:18 0000000000000000 VR19:18 0000000000000000 0100 ; 339 TR19:19 0000000000000000 VR19:19 0000000000000000 0100 ; 33a TR19:1a 0000000000000000 VR19:1a 0000000000000000 0100 ; 33b TR19:1b 0000000000000000 VR19:1b 0000000000000000 0100 ; 33c TR19:1c 0000000000000000 VR19:1c 0000000000000000 0100 ; 33d TR19:1d 0000000000000000 VR19:1d 0000000000000000 0100 ; 33e TR19:1e 0000000000000000 VR19:1e 0000000000000000 0100 ; 33f TR19:1f 0000000000000000 VR19:1f 0000000000000000 0100 ; 340 TR1a:00 0000000000000000 VR1a:00 0000000000000000 0100 ; 341 TR1a:01 0000000000000000 VR1a:01 0000000000000000 0100 ; 342 TR1a:02 0000000000000000 VR1a:02 0000000000000000 0100 ; 343 TR1a:03 0000000000000000 VR1a:03 0000000000000000 0100 ; 344 TR1a:04 0000000000000000 VR1a:04 0000000000000000 0100 ; 345 TR1a:05 0000000000000000 VR1a:05 0000000000000000 0100 ; 346 TR1a:06 0000000000000000 VR1a:06 0000000000000000 0100 ; 347 TR1a:07 0000000000000000 VR1a:07 0000000000000000 0100 ; 348 TR1a:08 0000000000000000 VR1a:08 0000000000000000 0100 ; 349 TR1a:09 0000000000000000 VR1a:09 0000000000000000 0100 ; 34a TR1a:0a 0000000000000000 VR1a:0a 0000000000000000 0100 ; 34b TR1a:0b 0000000000000000 VR1a:0b 0000000000000000 0100 ; 34c TR1a:0c 0000000000000000 VR1a:0c 0000000000000000 0100 ; 34d TR1a:0d 0000000000000000 VR1a:0d 0000000000000000 0100 ; 34e TR1a:0e 0000000000000000 VR1a:0e 0000000000000000 0100 ; 34f TR1a:0f 0000000000000000 VR1a:0f 0000000000000000 0100 ; 350 TR1a:10 0000000000000000 VR1a:10 0000000000000000 0100 ; 351 TR1a:11 0000000000000000 VR1a:11 0000000000000000 0100 ; 352 TR1a:12 0000000000000000 VR1a:12 0000000000000000 0100 ; 353 TR1a:13 0000000000000000 VR1a:13 0000000000000000 0100 ; 354 TR1a:14 0000000000000000 VR1a:14 0000000000000000 0100 ; 355 TR1a:15 0000000000000000 VR1a:15 0000000000000000 0100 ; 356 TR1a:16 0000000000000000 VR1a:16 0000000000000000 0100 ; 357 TR1a:17 0000000000000000 VR1a:17 0000000000000000 0100 ; 358 TR1a:18 0000000000000000 VR1a:18 0000000000000000 0100 ; 359 TR1a:19 0000000000000000 VR1a:19 0000000000000000 0100 ; 35a TR1a:1a 0000000000000000 VR1a:1a 0000000000000000 0100 ; 35b TR1a:1b 0000000000000000 VR1a:1b 0000000000000000 0100 ; 35c TR1a:1c 0000000000000000 VR1a:1c 0000000000000000 0100 ; 35d TR1a:1d 0000000000000000 VR1a:1d 0000000000000000 0100 ; 35e TR1a:1e 0000000000000000 VR1a:1e 0000000000000000 0100 ; 35f TR1a:1f 0000000000000000 VR1a:1f 0000000000000000 0100 ; 360 TR1b:00 0000000000000000 VR1b:00 0000000000000000 0100 ; 361 TR1b:01 0000000000000000 VR1b:01 0000000000000000 0100 ; 362 TR1b:02 0000000000000000 VR1b:02 0000000000000000 0100 ; 363 TR1b:03 0000000000000000 VR1b:03 0000000000000000 0100 ; 364 TR1b:04 000000000000005d VR1b:04 000000000000005d 0100 ; 365 TR1b:05 0000000000000000 VR1b:05 0000000000000000 0100 ; 366 TR1b:06 0000000000000000 VR1b:06 0000000000000000 0100 ; 367 TR1b:07 0000000000000000 VR1b:07 0000000000000000 0100 ; 368 TR1b:08 0000000000000000 VR1b:08 0000000000000000 0100 ; 369 TR1b:09 0000000000000000 VR1b:09 0000000000000000 0100 ; 36a TR1b:0a 0000000000000000 VR1b:0a 0000000000000000 0100 ; 36b TR1b:0b 0000000000000000 VR1b:0b 0000000000000080 0100 ; 36c TR1b:0c 0000000000000000 VR1b:0c 0000000000000100 0100 ; 36d TR1b:0d 0000000000000080 VR1b:0d 000000000000001f 0100 ; 36e TR1b:0e ffff000040000000 VR1b:0e 0000000000000000 0100 ; 36f TR1b:0f 0000000000007f80 VR1b:0f ffffffffffff0000 0100 ; 370 TR1b:10 000000000000007f VR1b:10 0000000000000001 0100 ; 371 TR1b:11 000000008000003f VR1b:11 fffff00000000000 0100 ; 372 TR1b:12 000000000000003f VR1b:12 0000000000000000 0100 ; 373 TR1b:13 fffe000000000601 VR1b:13 0000000000000001 0100 ; 374 TR1b:14 fffe000040000601 VR1b:14 0000000000000000 0100 ; 375 TR1b:15 000000000000003f VR1b:15 0000000000000001 0100 ; 376 TR1b:16 0000000000000021 VR1b:16 0000000000000000 0100 ; 377 TR1b:17 0000000000000029 VR1b:17 0000000000000000 0100 ; 378 TR1b:18 0000000000000011 VR1b:18 0000000000000000 0100 ; 379 TR1b:19 0000000000000019 VR1b:19 0000000000000000 0100 ; 37a TR1b:1a 0000000000001fc1 VR1b:1a ffff000000000000 0100 ; 37b TR1b:1b 000000000000003f VR1b:1b 0000000000000000 0100 ; 37c TR1b:1c 0000000000000049 VR1b:1c 0000000000000000 0100 ; 37d TR1b:1d 0000000000000076 VR1b:1d 0000000000000000 0100 ; 37e TR1b:1e 0000000000000009 VR1b:1e 0000000000000000 0100 ; 37f TR1b:1f 0000000000000000 VR1b:1f 0000000000000000 0100 ; 380 TR1c:00 0000000080000000 VR1c:00 0000000000000000 0100 ; 381 TR1c:01 0000000000000000 VR1c:01 0000000000000000 0100 ; 382 TR1c:02 0000000000000000 VR1c:02 0000000000000000 0100 ; 383 TR1c:03 0000000000000000 VR1c:03 0000000000000000 0100 ; 384 TR1c:04 0000000000000000 VR1c:04 0000000000000000 0100 ; 385 TR1c:05 0000000000000000 VR1c:05 0000000000000000 0100 ; 386 TR1c:06 0000000000000000 VR1c:06 0000000000000000 0100 ; 387 TR1c:07 0000000000000000 VR1c:07 0000000000000000 0100 ; 388 TR1c:08 0000000000000000 VR1c:08 0000000000000000 0100 ; 389 TR1c:09 0000000000000000 VR1c:09 0000000000000000 0100 ; 38a TR1c:0a 0000000000000000 VR1c:0a 0000000000000000 0100 ; 38b TR1c:0b 0000000000000000 VR1c:0b 0000000000000000 0100 ; 38c TR1c:0c 0000000000000000 VR1c:0c 0000000000000000 0100 ; 38d TR1c:0d 0000000000000000 VR1c:0d 0000000000000000 0100 ; 38e TR1c:0e 0000000000000000 VR1c:0e 0000000000000000 0100 ; 38f TR1c:0f 0000000000000000 VR1c:0f 0000000000000000 0100 ; 390 TR1c:10 0000000000000000 VR1c:10 0000000000000000 0100 ; 391 TR1c:11 0000000000000000 VR1c:11 0000000000000000 0100 ; 392 TR1c:12 0000000000000000 VR1c:12 0000000000000000 0100 ; 393 TR1c:13 0000000000000000 VR1c:13 0000000000000000 0100 ; 394 TR1c:14 0000000000000000 VR1c:14 0000000000000000 0100 ; 395 TR1c:15 0000000000000000 VR1c:15 0000000000000000 0100 ; 396 TR1c:16 0000000000000000 VR1c:16 0000000000000000 0100 ; 397 TR1c:17 0000000000000000 VR1c:17 0000000000000000 0100 ; 398 TR1c:18 0000000000000000 VR1c:18 0000000000000000 0100 ; 399 TR1c:19 0000000000000000 VR1c:19 0000000000000000 0100 ; 39a TR1c:1a 0000000000000000 VR1c:1a 0000000000000000 0100 ; 39b TR1c:1b 0000000000000000 VR1c:1b 0000000000000000 0100 ; 39c TR1c:1c 0000000000000000 VR1c:1c 0000000000000000 0100 ; 39d TR1c:1d 0000000000000000 VR1c:1d 0000000000000000 0100 ; 39e TR1c:1e 0000000000000000 VR1c:1e 0000000000000000 0100 ; 39f TR1c:1f 0000000000000000 VR1c:1f 0000000000000000 0100 ; 3a0 TR1d:00 0000000000000001 VR1d:00 0000000000000000 0100 ; 3a1 TR1d:01 ffffffffffffffff VR1d:01 0000000000000000 0100 ; 3a2 TR1d:02 0000000000000000 VR1d:02 0000000000000000 0100 ; 3a3 TR1d:03 0000000000000000 VR1d:03 0000000000000000 0100 ; 3a4 TR1d:04 0000000000000000 VR1d:04 0000040000000000 0100 ; 3a5 TR1d:05 0000000000000000 VR1d:05 0000000000000000 0100 ; 3a6 TR1d:06 0000000000000000 VR1d:06 0000000000000000 0100 ; 3a7 TR1d:07 0000000000000000 VR1d:07 0000000000000000 0100 ; 3a8 TR1d:08 0000000000000000 VR1d:08 0000000000000000 0100 ; 3a9 TR1d:09 0000000000000000 VR1d:09 0000000000000000 0100 ; 3aa TR1d:0a 0000000000000000 VR1d:0a 0000000000000000 0100 ; 3ab TR1d:0b 0000000000000000 VR1d:0b 0000000000000000 0100 ; 3ac TR1d:0c 0000000000000000 VR1d:0c 000ffff00000bf80 0100 ; 3ad TR1d:0d 0000000000000068 VR1d:0d 0000000000000000 0100 ; 3ae TR1d:0e 0000000000000000 VR1d:0e 0000000000000000 0100 ; 3af TR1d:0f 0000000000000000 VR1d:0f 0000000000000000 0100 ; 3b0 TR1d:10 0000000000000000 VR1d:10 0000000000000000 0100 ; 3b1 TR1d:11 00000000000001f4 VR1d:11 0000000000000000 0100 ; 3b2 TR1d:12 0000000000000000 VR1d:12 fffffffffffffff0 0100 ; 3b3 TR1d:13 0000000000000000 VR1d:13 0000000000000000 0100 ; 3b4 TR1d:14 0000000000000000 VR1d:14 0000000000000000 0100 ; 3b5 TR1d:15 0000000000000000 VR1d:15 0000000000000000 0100 ; 3b6 TR1d:16 0000000000000000 VR1d:16 0000000000000000 0100 ; 3b7 TR1d:17 0000000000000000 VR1d:17 0000000000000000 0100 ; 3b8 TR1d:18 0000000000000000 VR1d:18 0000000000000000 0100 ; 3b9 TR1d:19 0000000000000000 VR1d:19 0000000000000000 0100 ; 3ba TR1d:1a 0000000000000000 VR1d:1a 0000000000000000 0100 ; 3bb TR1d:1b 0000000000000000 VR1d:1b 0000000000000000 0100 ; 3bc TR1d:1c 0000000000000000 VR1d:1c 0000000000000000 0100 ; 3bd TR1d:1d 0000000000000000 VR1d:1d 0000000000000000 0100 ; 3be TR1d:1e 0000000000000000 VR1d:1e 0000000000000000 0100 ; 3bf TR1d:1f 0000000000000000 VR1d:1f 0000000000000000 0100 ; 3c0 TR1e:00 0000000020000000 VR1e:00 0000000000000000 0100 ; 3c1 TR1e:01 0000000000000000 VR1e:01 0000000000000000 0100 ; 3c2 TR1e:02 0000000000000000 VR1e:02 0000000000000000 0100 ; 3c3 TR1e:03 0000000000000000 VR1e:03 0000000000000000 0100 ; 3c4 TR1e:04 0000000000000000 VR1e:04 0000000000000000 0100 ; 3c5 TR1e:05 0000000000000000 VR1e:05 0000000000000000 0100 ; 3c6 TR1e:06 0000000000000000 VR1e:06 0000000000000000 0100 ; 3c7 TR1e:07 0000000000000000 VR1e:07 0000000000000000 0100 ; 3c8 TR1e:08 0000000000000000 VR1e:08 0000000000000000 0100 ; 3c9 TR1e:09 0000000000000000 VR1e:09 0000000000000000 0100 ; 3ca TR1e:0a 0000000000000000 VR1e:0a 0000000000000000 0100 ; 3cb TR1e:0b 0000000000000000 VR1e:0b 0000000000000000 0100 ; 3cc TR1e:0c 0000000000000000 VR1e:0c 0000000000000000 0100 ; 3cd TR1e:0d 0000000000000000 VR1e:0d 0000000000000000 0100 ; 3ce TR1e:0e 0000000000000000 VR1e:0e 0000000000000000 0100 ; 3cf TR1e:0f 00000000c0000003 VR1e:0f 0000000000000000 0100 ; 3d0 TR1e:10 0000000000000030 VR1e:10 0000000000000000 0100 ; 3d1 TR1e:11 000000008000000d VR1e:11 0000000000000000 0100 ; 3d2 TR1e:12 0000000000000003 VR1e:12 0000000000000000 0100 ; 3d3 TR1e:13 0000000080000005 VR1e:13 0000000000000000 0100 ; 3d4 TR1e:14 00000000c0000002 VR1e:14 0000000000000000 0100 ; 3d5 TR1e:15 00000000c0000001 VR1e:15 0000000000000000 0100 ; 3d6 TR1e:16 00000000c0000000 VR1e:16 0000000000000000 0100 ; 3d7 TR1e:17 0000000000000002 VR1e:17 0000000000000000 0100 ; 3d8 TR1e:18 0000000000000020 VR1e:18 0000000000000000 0100 ; 3d9 TR1e:19 0000000000000010 VR1e:19 0000000000000000 0100 ; 3da TR1e:1a 0000000000000000 VR1e:1a 0000000000000000 0100 ; 3db TR1e:1b 0000000040000002 VR1e:1b 0000000000000000 0100 ; 3dc TR1e:1c 0000000080000009 VR1e:1c 0000000000000002 0100 ; 3dd TR1e:1d 0000000080000001 VR1e:1d 0000000000000001 0100 ; 3de TR1e:1e 0000000007ffff80 VR1e:1e 0000000000000000 0100 ; 3df TR1e:1f ffffffff07ffff80 VR1e:1f ffffffff07ffff80 0100 ; 3e0 TCSA0 00c80000b87d922c VCSA0 00cf0024444a4c00 0100 ; 3e1 TCSA1 0000000000000000 VCSA1 0000000000000000 0100 ; 3e2 TCSA2 0000000000000000 VCSA2 0000000000000000 0100 ; 3e3 TCSA3 0000000000000000 VCSA3 0000000000000000 0100 ; 3e4 TCSA4 0000000000000000 VCSA4 0000000000000000 0100 ; 3e5 TCSA5 0000000000000000 VCSA5 0000000000000000 0100 ; 3e6 TCSA6 0000000000000000 VCSA6 0000000000000000 0100 ; 3e7 TCSA7 0000000000000000 VCSA7 0000000000000000 0100 ; 3e8 TCSA8 0000000000000000 VCSA8 0000000000000000 0100 ; 3e9 TCSA9 0000000000000000 VCSA9 0000000000000000 0100 ; 3ea TCSAa 0000000000000000 VCSAa 0000000000000000 0100 ; 3eb TCSAb 0000000000000000 VCSAb 0000000000000000 0100 ; 3ec TCSAc 0000000000000000 VCSAc 0000000000000000 0100 ; 3ed TCSAd 0000000000000000 VCSAd 0000000000000000 0100 ; 3ee TCSAe 0000000000000000 VCSAe 0000000000000000 0100 ; 3ef TCSAf 0000000000000000 VCSAf 0000000000000000 0100 ; 3f0 TGP0 0000000000000000 VGP0 0000000000000000 0100 ; 3f1 TGP1 0000000000000000 VGP1 0000000000000000 0100 ; 3f2 TGP2 0000000000000000 VGP2 0000000000000000 0100 ; 3f3 TGP3 0000000000000000 VGP3 0000000000000000 0100 ; 3f4 TGP4 0000000000000000 VGP4 0000000000000000 0100 ; 3f5 TGP5 0000000000000000 VGP5 0000000000000000 0100 ; 3f6 TGP6 0000000000000000 VGP6 0000000000000000 0100 ; 3f7 TGP7 0000000000000000 VGP7 0000000000000000 0100 ; 3f8 TGP8 0000000000000000 VGP8 0000000000000000 0100 ; 3f9 TGP9 0000000000000000 VGP9 0000000000000000 0100 ; 3fa TGPa 0000000000000000 VGPa 0000000000000000 0100 ; 3fb TGPb 0000000000000000 VGPb 0000000000000000 0100 ; 3fc TGPc 0000000000000000 VGPc 0000000000000000 0100 ; 3fd TGPd 0000000000000000 VGPd 0000000000000000 0100 ; 3fe TGPe 0000000000000000 VGPe 0000000000000000 0100 ; 3ff TGPf 0000000000000000 VGPf 0000000000000000 0100 ; 0100 ; Defaults not shown: 0100 ; =================== 0100 ; dispatch_csa_free 0 0100 ; dispatch_ibuff_fill 0 0100 ; dispatch_ignore 0 0100 ; dispatch_mem_strt 4 MEMORY NOT STARTED 0100 ; dispatch_uses_tos 0 0100 ; fiu_fill_mode_src 1 0100 ; fiu_len_fill_lit 7f zero-fill 0x3f 0100 ; fiu_len_fill_reg_ctl 3 len=unchanged, fill=unchanged 0100 ; fiu_length_src 1 length_literal 0100 ; fiu_load_mdr 0 load_mdr 0100 ; fiu_load_oreg 0 load_oreg 0100 ; fiu_load_tar 0 load_tar 0100 ; fiu_load_var 0 load_var 0100 ; fiu_mem_start 19 nop_0x19 0100 ; fiu_offs_lit 00 0100 ; fiu_offset_src 1 offset_literal 0100 ; fiu_op_sel 0 extract 0100 ; fiu_oreg_src 1 merge data register 0100 ; fiu_rdata_src 1 mdr 0100 ; fiu_tivi_src 0 tar_var 0100 ; fiu_vmux_sel 2 VI 0100 ; ioc_adrbs 0 fiu 0100 ; ioc_fiubs 3 seq 0100 ; ioc_load_wdr 1 0100 ; ioc_random 0 noop 0100 ; ioc_tvbs 0 typ+val 0100 ; seq_b_timing 2 Late Condition, Hint True (or unconditional branch) 0100 ; seq_br_type 6 Continue 0100 ; seq_branch_adr 0000 0100 ; seq_cond_sel 46 SEQ.previously_latched_cond 0100 ; seq_en_micro 1 0100 ; seq_int_reads 3 TOP OF THE MICRO STACK 0100 ; seq_latch 0 0100 ; seq_lex_adr 0 0100 ; seq_random 00 ? 0100 ; typ_a_adr 00 GP00 0100 ; typ_alu_func 1f ZEROS 0100 ; typ_b_adr 00 GP00 0100 ; typ_c_adr 29 WRITE_DISABLE 0100 ; typ_c_lit 3 0100 ; typ_c_mux_sel 1 WDR 0100 ; typ_c_source 1 MUX 0100 ; typ_csa_cntl 6 NOP 0100 ; typ_frame 0 0100 ; typ_mar_cntl 0 NOP 0100 ; typ_priv_check 7 NOP 0100 ; typ_rand f INC_DEC_128 0100 ; val_a_adr 00 GP00 0100 ; val_alu_func 1f ZEROS 0100 ; val_b_adr 00 GP00 0100 ; val_c_adr 29 WRITE_DISABLE 0100 ; val_c_mux_sel 3 WDR 0100 ; val_c_source 1 MUX 0100 ; val_frame 0 0100 ; val_m_a_src 3 Bits 48…63 0100 ; val_m_b_src 3 Bits 48…63 0100 ; val_rand 0 NO_OP 0100 ; 0100 ; Early macro event: ME_STOP_MACH 0100 ; -------------------------------------------------------------------------------------- 0100 ME_STOP_MACH: 0100 0100 <halt> ; Flow R 0101 0101 seq_en_micro 0 0102 0102 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0103 0103 <halt> ; Flow R 0104 0104 <halt> ; Flow R 0105 0105 <halt> ; Flow R 0106 0106 <halt> ; Flow R 0107 0107 <halt> ; Flow R 0108 ; -------------------------------------------------------------------------------------- 0108 ; Early macro event: ME_GP_TIME 0108 ; -------------------------------------------------------------------------------------- 0108 ME_GP_TIME: 0108 0108 seq_br_type 7 Unconditional Call; Flow C 0x5db seq_branch_adr 05db 0x05db seq_en_micro 0 0109 0109 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 010a 010a <halt> ; Flow R 010b 010b <halt> ; Flow R 010c 010c <halt> ; Flow R 010d 010d <halt> ; Flow R 010e 010e <halt> ; Flow R 010f 010f <halt> ; Flow R 0110 ; -------------------------------------------------------------------------------------- 0110 ; Early macro event: ME_SL_TIME 0110 ; -------------------------------------------------------------------------------------- 0110 ME_SL_TIME: 0110 0110 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x763 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0763 0x0763 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0111 0111 fiu_tivi_src 2 tar_fiu; Flow J cc=True 0x765 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0765 0x0765 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR13:0d typ_frame 13 val_a_adr 21 VR02:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0112 0112 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0113 0113 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x760 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_random 6 load slice timer seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0760 0x0760 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 val_a_adr 2f VR02:0f val_frame 2 0114 0114 fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0115 0115 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x73a seq_br_type 1 Branch True seq_branch_adr 073a 0x073a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0116 0116 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0117 0117 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x73c fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 073c 0x073c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0118 ; -------------------------------------------------------------------------------------- 0118 ; Early macro event: ME_SPARE1 0118 ; -------------------------------------------------------------------------------------- 0118 ME_SPARE1: 0118 0118 <halt> ; Flow R 0119 0119 <halt> ; Flow R 011a 011a <halt> ; Flow R 011b 011b <halt> ; Flow R 011c 011c <halt> ; Flow R 011d 011d <halt> ; Flow R 011e 011e <halt> ; Flow R 011f 011f <halt> ; Flow R 0120 ; -------------------------------------------------------------------------------------- 0120 ; Early macro event: ME_PACKET 0120 ; -------------------------------------------------------------------------------------- 0120 ME_PACKET: 0120 0120 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 5 read response fifo ioc_tvbs 4 ioc+ioc seq_en_micro 0 0121 0121 ioc_fiubs 0 fiu ioc_random 15 clear transfer parity error ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0122 0122 ioc_load_wdr 0 ; Flow C cc=False 0x20c ioc_random 13 set cpu running seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR03:13 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0b GP0b typ_frame 3 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0123 0123 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b val_m_a_src 2 Bits 32…47 0124 0124 ioc_random 1c read ioc memory and increment address seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0125 0125 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0b GP0b 0126 0126 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x819 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 3 Unconditional Branch seq_branch_adr 0819 0x0819 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0127 0127 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0128 ; -------------------------------------------------------------------------------------- 0128 ; Early macro event: ME_STATUS 0128 ; -------------------------------------------------------------------------------------- 0128 ME_STATUS: 0128 0128 <halt> ; Flow R 0129 0129 <halt> ; Flow R 012a 012a <halt> ; Flow R 012b 012b <halt> ; Flow R 012c 012c <halt> ; Flow R 012d 012d <halt> ; Flow R 012e 012e <halt> ; Flow R 012f 012f <halt> ; Flow R 0130 ; -------------------------------------------------------------------------------------- 0130 ; Early macro event: ME_SPARE0 0130 ; -------------------------------------------------------------------------------------- 0130 ME_SPARE0: 0130 0130 <halt> ; Flow R 0131 0131 <halt> ; Flow R 0132 0132 <halt> ; Flow R 0133 0133 <halt> ; Flow R 0134 0134 <halt> ; Flow R 0135 0135 <halt> ; Flow R 0136 0136 <halt> ; Flow R 0137 0137 <halt> ; Flow R 0138 ; -------------------------------------------------------------------------------------- 0138 ; Early macro event: ME_REFRESH 0138 ; -------------------------------------------------------------------------------------- 0138 ME_REFRESH: 0138 0138 fiu_mem_start d start_physical_rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 0139 0139 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x2a63 fiu_tivi_src c mar_0xc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2a63 0x2a63 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 34 VR0d:14 val_alu_func 1c DEC_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 013a 013a ioc_tvbs 3 fiu+fiu; Flow C 0xba9 seq_br_type 7 Unconditional Call seq_branch_adr 0ba9 0x0ba9 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR0d:11 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0e VR0d:11 val_c_mux_sel 2 ALU val_frame d 013b 013b fiu_load_tar 1 hold_tar; Flow J cc=True 0x13e fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 013e 0x013e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_b_adr 31 TR0d:11 typ_frame d val_a_adr 34 VR0d:14 val_alu_func 7 INC_A val_b_adr 31 VR0d:11 val_frame d 013c 013c fiu_len_fill_reg_ctl 2 ; Flow R cc=True fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 013d 0x013d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR1d:01 val_alu_func 0 PASS_A val_frame 1d 013d 013d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 013e 013e fiu_mem_start d start_physical_rd; Flow J 0x2a64 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a64 0x2a64 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_frame 1d 013f 013f <halt> ; Flow R 0140 ; -------------------------------------------------------------------------------------- 0140 ; Late macro event: ML_IBUF_empty 0140 ; -------------------------------------------------------------------------------------- 0140 ML_IBUF_empty: 0140 0140 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_cond_sel 55 SEQ.E_MACRO_PEND seq_int_reads 0 TYP VAL BUS seq_random 28 Load_ibuff+Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0141 0141 seq_br_type 7 Unconditional Call; Flow C 0x3649 seq_branch_adr 3649 0x3649 seq_en_micro 0 0142 0142 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0143 0143 seq_en_micro 0 0144 0144 seq_en_micro 0 0145 ; -------------------------------------------------------------------------------------- 0145 ; Micro event: UE_MACHINE_STARTUP 0145 ; -------------------------------------------------------------------------------------- 0145 UE_MACHINE_STARTUP: 0145 0145 seq_br_type 3 Unconditional Branch; Flow J 0x2abb seq_branch_adr 2abb 0x2abb seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 09 TR04:16 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 0 PASS_A val_c_adr 09 VR04:16 val_c_mux_sel 2 ALU val_frame 4 0146 0146 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0147 0147 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0148 ; -------------------------------------------------------------------------------------- 0148 ; Late macro event: ML_break_class 0148 ; -------------------------------------------------------------------------------------- 0148 ML_break_class: 0148 0148 fiu_load_tar 1 hold_tar; Flow C cc=True 0x2d53 fiu_load_var 1 hold_var fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2d53 0x2d53 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR00:10 val_a_adr 24 VR07:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 0149 0149 ioc_tvbs 5 seq+seq; Flow J cc=True 0x14a ; Flow J cc=#0x0 0x2d65 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2d65 0x2d65 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 30 TR00:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 014a 014a ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 014b 014b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2d52 seq_br_type 1 Branch True seq_branch_adr 2d52 0x2d52 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3c TR05:1c typ_frame 5 014c 014c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 014d 014d fiu_mem_start 4 continue; Flow J cc=True 0x170 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0170 ML_CSA_Underflow seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 2a TR06:0a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR05:09 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 014e 014e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 014f 014f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d3a fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d3a 0x2d3a typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0150 ; -------------------------------------------------------------------------------------- 0150 ; Late macro event: ML_pullup 0150 ; -------------------------------------------------------------------------------------- 0150 ML_pullup: 0150 0150 <halt> ; Flow R 0151 0151 <halt> ; Flow R 0152 0152 <halt> ; Flow R 0153 0153 <halt> ; Flow R 0154 0154 <halt> ; Flow R 0155 0155 <halt> ; Flow R 0156 0156 <halt> ; Flow R 0157 0157 <halt> ; Flow R 0158 ; -------------------------------------------------------------------------------------- 0158 ; Late macro event: ML_TOS_INVLD 0158 ; -------------------------------------------------------------------------------------- 0158 ML_TOS_INVLD: 0158 0158 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0159 0159 <halt> ; Flow R 015a 015a <halt> ; Flow R 015b 015b <halt> ; Flow R 015c 015c <halt> ; Flow R 015d 015d <halt> ; Flow R 015e 015e <halt> ; Flow R 015f 015f <halt> ; Flow R 0160 ; -------------------------------------------------------------------------------------- 0160 ; Late macro event: ML_Resolve Reference 0160 ; -------------------------------------------------------------------------------------- 0160 ML_Resolve Reference: 0160 0160 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x165 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0165 0x0165 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR1d:13 val_frame 1d 0161 0161 fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_b_adr 2f TR02:0f typ_c_adr 10 TR02:0f typ_frame 2 val_a_adr 34 VR1d:14 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0b VR1d:14 val_c_source 0 FIU_BUS val_frame 1d 0162 0162 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0163 0x0163 seq_cond_sel 4a SEQ.ME_resolve_ref seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 19 TR02:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR1d:13 val_c_mux_sel 2 ALU val_frame 1d val_rand a PASS_B_HIGH 0163 0163 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? val_a_adr 33 VR1d:13 val_frame 1d 0164 0164 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a5c fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a5c 0x2a5c seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0165 0165 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a5c fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type c Dispatch True seq_branch_adr 2a5c 0x2a5c seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0166 0166 <halt> ; Flow R 0167 0167 <halt> ; Flow R 0168 ; -------------------------------------------------------------------------------------- 0168 ; Late macro event: ML_SEQ_STOP 0168 ; -------------------------------------------------------------------------------------- 0168 ML_SEQ_STOP: 0168 0168 <halt> ; Flow R 0169 0169 <halt> ; Flow R 016a 016a <halt> ; Flow R 016b 016b <halt> ; Flow R 016c 016c <halt> ; Flow R 016d 016d <halt> ; Flow R 016e 016e <halt> ; Flow R 016f 016f <halt> ; Flow R 0170 ; -------------------------------------------------------------------------------------- 0170 ; Late macro event: ML_CSA_Underflow 0170 ; -------------------------------------------------------------------------------------- 0170 ML_CSA_Underflow: 0170 0170 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0171 0171 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR05:05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0172 0172 fiu_mem_start 3 start-wr; Flow J cc=True 0x176 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0176 0x0176 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 0173 0173 fiu_mem_start 4 continue; Flow J cc=False 0x173 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0173 0x0173 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0174 0174 ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 0175 0175 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0176 0176 fiu_mem_start 4 continue; Flow J 0x173 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0173 0x0173 seq_lex_adr 2 seq_random 0b ? typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0177 0177 <halt> ; Flow R 0178 ; -------------------------------------------------------------------------------------- 0178 ; Late macro event: ML_CSA_overflow 0178 ; -------------------------------------------------------------------------------------- 0178 ML_CSA_overflow: 0178 0178 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0179 0179 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 3 017a 017a fiu_mem_start 2 start-rd; Flow J cc=True 0x17e fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 017e 0x017e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 017b 017b seq_b_timing 0 Early Condition; Flow J cc=True 0x17d seq_br_type 1 Branch True seq_branch_adr 017d 0x017d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 10 TOP 017c 017c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x17b fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 017b 0x017b typ_alu_func 0 PASS_A typ_c_adr 2b BOT - 1 typ_c_source 0 FIU_BUS typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 017d 017d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 017e 017e seq_br_type 3 Unconditional Branch; Flow J 0x17c seq_branch_adr 017c 0x017c seq_lex_adr 2 seq_random 0b ? typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 017f 017f <halt> ; Flow R 0180 ; -------------------------------------------------------------------------------------- 0180 ; Micro event: UE_MEM_EXP 0180 ; -------------------------------------------------------------------------------------- 0180 UE_MEM_EXP: 0180 0180 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xeed seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0eed 0x0eed seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0181 0181 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0182 0182 fiu_tivi_src 8 type_var; Flow J 0xeed ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0eed 0x0eed seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0183 0183 <halt> ; Flow R 0184 0184 <halt> ; Flow R 0185 0185 <halt> ; Flow R 0186 0186 <halt> ; Flow R 0187 0187 <halt> ; Flow R 0188 ; -------------------------------------------------------------------------------------- 0188 ; Micro event: UE_ECC 0188 ; -------------------------------------------------------------------------------------- 0188 UE_ECC: 0188 0188 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a94 seq_br_type 1 Branch True seq_branch_adr 2a94 0x2a94 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 0 PASS_A typ_c_adr 19 TR1d:06 typ_frame 1d val_c_adr 19 VR1d:06 val_frame 1d 0189 0189 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2ab7 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab7 0x2ab7 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 13 TR1d:0c typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 018a 018a fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x2a89 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a89 0x2a89 seq_cond_sel 63 CSA_HIT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1d typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR1d:0a val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR1d:05 val_c_mux_sel 2 ALU val_frame 1d 018b 018b fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x2a8b fiu_load_oreg 1 hold_oreg fiu_offs_lit 73 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8b 0x2a8b seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 018c 018c fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0x2a8b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8b 0x2a8b seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 018d 018d seq_br_type 7 Unconditional Call; Flow C 0x20e seq_branch_adr 020e 0x020e seq_en_micro 0 018e 018e ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3d VR12:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 018f 018f fiu_mem_start c start_if_incmplt; Flow R ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 6c INCOMPLETE_MEMORY_CYCLE seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 7 INC_A typ_b_adr 28 TR1d:08 typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 1 RESTORE_RDR val_b_adr 28 VR1d:08 val_frame 1d 0190 ; -------------------------------------------------------------------------------------- 0190 ; Micro event: UE_BKPT 0190 ; -------------------------------------------------------------------------------------- 0190 UE_BKPT: 0190 0190 <halt> ; Flow R 0191 0191 <halt> ; Flow R 0192 0192 <halt> ; Flow R 0193 0193 <halt> ; Flow R 0194 0194 <halt> ; Flow R 0195 0195 <halt> ; Flow R 0196 0196 <halt> ; Flow R 0197 0197 <halt> ; Flow R 0198 ; -------------------------------------------------------------------------------------- 0198 ; Micro event: UE_CHK_EXIT 0198 ; -------------------------------------------------------------------------------------- 0198 UE_CHK_EXIT: 0198 0198 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0199 0199 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 019a 019a seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 019b 019b <halt> ; Flow R 019c 019c <halt> ; Flow R 019d 019d <halt> ; Flow R 019e 019e <halt> ; Flow R 019f 019f <halt> ; Flow R 01a0 ; -------------------------------------------------------------------------------------- 01a0 ; Micro event: UE_FIELD_ERROR 01a0 ; -------------------------------------------------------------------------------------- 01a0 UE_FIELD_ERROR: 01a0 01a0 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 01a1 01a1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a2 01a2 fiu_tivi_src 8 type_var; Flow C 0x32ae ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32ae 0x32ae seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01a3 01a3 <halt> ; Flow R 01a4 01a4 <halt> ; Flow R 01a5 01a5 <halt> ; Flow R 01a6 01a6 <halt> ; Flow R 01a7 01a7 <halt> ; Flow R 01a8 ; -------------------------------------------------------------------------------------- 01a8 ; Micro event: UE_CLASS 01a8 ; -------------------------------------------------------------------------------------- 01a8 UE_CLASS: 01a8 01a8 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a9 01a9 fiu_tivi_src 8 type_var; Flow C 0x32a5 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01aa 01aa <halt> ; Flow R 01ab 01ab <halt> ; Flow R 01ac 01ac <halt> ; Flow R 01ad 01ad <halt> ; Flow R 01ae 01ae <halt> ; Flow R 01af 01af <halt> ; Flow R 01b0 ; -------------------------------------------------------------------------------------- 01b0 ; Micro event: UE_BIN_EQ 01b0 ; -------------------------------------------------------------------------------------- 01b0 UE_BIN_EQ: 01b0 01b0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b1 01b1 <halt> ; Flow R 01b2 01b2 <halt> ; Flow R 01b3 01b3 <halt> ; Flow R 01b4 01b4 <halt> ; Flow R 01b5 01b5 <halt> ; Flow R 01b6 01b6 <halt> ; Flow R 01b7 01b7 <halt> ; Flow R 01b8 ; -------------------------------------------------------------------------------------- 01b8 ; Micro event: UE_BIN_OP 01b8 ; -------------------------------------------------------------------------------------- 01b8 UE_BIN_OP: 01b8 01b8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b9 01b9 <halt> ; Flow R 01ba 01ba <halt> ; Flow R 01bb 01bb <halt> ; Flow R 01bc 01bc <halt> ; Flow R 01bd 01bd <halt> ; Flow R 01be 01be <halt> ; Flow R 01bf 01bf <halt> ; Flow R 01c0 ; -------------------------------------------------------------------------------------- 01c0 ; Micro event: UE_TOS_OP 01c0 ; -------------------------------------------------------------------------------------- 01c0 UE_TOS_OP: 01c0 01c0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c1 01c1 <halt> ; Flow R 01c2 01c2 <halt> ; Flow R 01c3 01c3 <halt> ; Flow R 01c4 01c4 <halt> ; Flow R 01c5 01c5 <halt> ; Flow R 01c6 01c6 <halt> ; Flow R 01c7 01c7 <halt> ; Flow R 01c8 ; -------------------------------------------------------------------------------------- 01c8 ; Micro event: UE_TOSI_OP 01c8 ; -------------------------------------------------------------------------------------- 01c8 UE_TOSI_OP: 01c8 01c8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c9 01c9 <halt> ; Flow R 01ca 01ca <halt> ; Flow R 01cb 01cb <halt> ; Flow R 01cc 01cc <halt> ; Flow R 01cd 01cd <halt> ; Flow R 01ce 01ce <halt> ; Flow R 01cf 01cf <halt> ; Flow R 01d0 ; -------------------------------------------------------------------------------------- 01d0 ; Micro event: UE_PAGE_X 01d0 ; -------------------------------------------------------------------------------------- 01d0 UE_PAGE_X: 01d0 01d0 fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 27 VR07:07 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 7 01d1 01d1 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 01d2 01d2 fiu_mem_start c start_if_incmplt; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 6e INCOMPLETE_MEMORY_CYCLE_FOR_PAGE_CROSSING seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 01d3 01d3 <halt> ; Flow R 01d4 01d4 <halt> ; Flow R 01d5 01d5 <halt> ; Flow R 01d6 01d6 <halt> ; Flow R 01d7 01d7 <halt> ; Flow R 01d8 ; -------------------------------------------------------------------------------------- 01d8 ; Micro event: UE_CHK_SYS 01d8 ; -------------------------------------------------------------------------------------- 01d8 UE_CHK_SYS: 01d8 01d8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 01d9 01d9 <halt> ; Flow R 01da 01da <halt> ; Flow R 01db 01db <halt> ; Flow R 01dc 01dc <halt> ; Flow R 01dd 01dd <halt> ; Flow R 01de 01de <halt> ; Flow R 01df 01df <halt> ; Flow R 01e0 ; -------------------------------------------------------------------------------------- 01e0 ; Micro event: UE_NEW_PAK 01e0 ; -------------------------------------------------------------------------------------- 01e0 UE_NEW_PAK: 01e0 01e0 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01e1 01e1 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01e2 01e2 seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 01e3 01e3 <halt> ; Flow R 01e4 01e4 <halt> ; Flow R 01e5 01e5 <halt> ; Flow R 01e6 01e6 <halt> ; Flow R 01e7 01e7 <halt> ; Flow R 01e8 ; -------------------------------------------------------------------------------------- 01e8 ; Micro event: UE_NEW_STS 01e8 ; -------------------------------------------------------------------------------------- 01e8 UE_NEW_STS: 01e8 01e8 <halt> ; Flow R 01e9 01e9 <halt> ; Flow R 01ea 01ea <halt> ; Flow R 01eb 01eb <halt> ; Flow R 01ec 01ec <halt> ; Flow R 01ed 01ed <halt> ; Flow R 01ee 01ee <halt> ; Flow R 01ef 01ef <halt> ; Flow R 01f0 ; -------------------------------------------------------------------------------------- 01f0 ; Micro event: UE_XFER_CP 01f0 ; -------------------------------------------------------------------------------------- 01f0 UE_XFER_CP: 01f0 01f0 <halt> ; Flow R 01f1 01f1 <halt> ; Flow R 01f2 01f2 <halt> ; Flow R 01f3 01f3 <halt> ; Flow R 01f4 01f4 <halt> ; Flow R 01f5 01f5 <halt> ; Flow R 01f6 01f6 <halt> ; Flow R 01f7 01f7 <halt> ; Flow R 01f8 ; -------------------------------------------------------------------------------------- 01f8 ; 0x0020-0x0030 Illegal - 01f8 ; 0x0037-0x0038 Illegal - 01f8 ; 0x003f-0x0040 Illegal - 01f8 ; 0x0047-0x0048 Illegal - 01f8 ; 0x004f-0x0050 Illegal - 01f8 ; 0x0057-0x0058 Illegal - 01f8 ; 0x005f-0x0067 Illegal - 01f8 ; 0x0077-0x007f Illegal - 01f8 ; 0x0083-0x0086 Illegal - 01f8 ; 0x0094 Illegal - 01f8 ; 0x00ae-0x00b2 Illegal - 01f8 ; 0x00c0-0x00c3 Illegal - 01f8 ; 0x00df Illegal - 01f8 ; 0x0102-0x0105 Illegal - 01f8 ; 0x0108 Illegal - 01f8 ; 0x0113 Illegal - 01f8 ; 0x0130-0x0131 Illegal - 01f8 ; 0x0134-0x0135 Illegal - 01f8 ; 0x0138-0x013b Illegal - 01f8 ; 0x0150-0x015a Illegal - 01f8 ; 0x0170-0x0176 Illegal - 01f8 ; 0x0180-0x0188 Illegal - 01f8 ; 0x018c Illegal - 01f8 ; 0x0190-0x019a Illegal - 01f8 ; 0x01a0-0x01a2 Illegal - 01f8 ; 0x01b0-0x01bd Illegal - 01f8 ; 0x01c8-0x01c9 Illegal - 01f8 ; 0x01e0-0x01ea Illegal - 01f8 ; 0x01f0-0x01f2 Illegal - 01f8 ; 0x0200-0x0204 Illegal - 01f8 ; 0x0207 Illegal - 01f8 ; 0x0280-0x0298 Illegal - 01f8 ; 0x02a1 Illegal - 01f8 ; 0x02a3 Illegal - 01f8 ; 0x02a6-0x02a7 Illegal - 01f8 ; 0x02ac-0x02bd Illegal - 01f8 ; 0x02c0-0x02c5 Illegal - 01f8 ; 0x02c8 Illegal - 01f8 ; 0x02ca Illegal - 01f8 ; 0x02cc-0x02cd Illegal - 01f8 ; 0x02d0-0x02fa Illegal - 01f8 ; 0x0300-0x0302 Illegal - 01f8 ; 0x0308-0x0310 Illegal - 01f8 ; 0x0313-0x0314 Illegal - 01f8 ; 0x0317 Illegal - 01f8 ; 0x031a Illegal - 01f8 ; 0x031f Illegal - 01f8 ; 0x0323 Illegal - 01f8 ; 0x0329 Illegal - 01f8 ; 0x032c Illegal - 01f8 ; 0x032f-0x0332 Illegal - 01f8 ; 0x0338-0x033f Illegal - 01f8 ; 0x0344-0x0345 Illegal - 01f8 ; 0x034a Illegal - 01f8 ; 0x034d Illegal - 01f8 ; 0x0352 Illegal - 01f8 ; 0x0357 Illegal - 01f8 ; 0x035a Illegal - 01f8 ; 0x035f-0x0369 Illegal - 01f8 ; 0x0370-0x0373 Illegal - 01f8 ; 0x0375-0x0376 Illegal - 01f8 ; 0x0379 Illegal - 01f8 ; 0x037c Illegal - 01f8 ; 0x037f-0x0383 Illegal - 01f8 ; 0x0388-0x038b Illegal - 01f8 ; 0x0390-0x0394 Illegal - 01f8 ; 0x03aa Illegal - 01f8 ; 0x03af-0x03b4 Illegal - 01f8 ; 0x03c0-0x03c3 Illegal - 01f8 ; 0x03c8-0x03cb Illegal - 01f8 ; 0x03d0 Illegal - 01f8 ; 0x03d7 Illegal - 01f8 ; 0x03e2 Illegal - 01f8 ; 0x03e7 Illegal - 01f8 ; 0x03f4 Illegal - 01f8 ; 0x03ff Illegal - 01f8 ; 0x1e00-0x1fff Illegal - 01f8 ; 0x3100-0x33ff Illegal - 01f8 ; 0x3500-0x35ff Illegal - 01f8 ; 0x3900-0x3bff Illegal - 01f8 ; 0x3d00-0x3dff Illegal - 01f8 ; 0x4000-0x40ff Illegal - 01f8 ; 0x0070-0x0076 QQUnknown InMicrocode 01f8 ; -------------------------------------------------------------------------------------- 01f8 MACRO_01f8_QQUnknown_InMicrocode: 01f8 MACRO_Illegal_-: 01f8 01f8 dispatch_brk_class 0 ; Flow C 0x32ab dispatch_csa_valid 0 dispatch_uadr 01f8 seq_br_type 7 Unconditional Call seq_branch_adr 32ab 0x32ab seq_random 05 ? 01f9 01f9 ioc_random 14 clear cpu running; Flow R seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 01 Halt+? 01fa 01fa <halt> ; Flow R 01fb 01fb <halt> ; Flow R 01fc 01fc <halt> ; Flow R 01fd 01fd <halt> ; Flow R 01fe 01fe <halt> ; Flow R 01ff 01ff <halt> ; Flow R 0200 0200 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 seq_random 01 Halt+? 0201 0201 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 seq_random 01 Halt+? 0202 0202 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 seq_random 01 Halt+? 0203 0203 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 seq_random 01 Halt+? 0204 0204 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 seq_random 01 Halt+? 0205 0205 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 seq_random 01 Halt+? 0206 0206 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 seq_random 01 Halt+? 0207 0207 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 seq_random 01 Halt+? 0208 0208 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 seq_random 01 Halt+? 0209 0209 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 seq_random 01 Halt+? 020a ; -------------------------------------------------------------------------------------- 020a ; Comes from: 020a ; 058e C False from color 0x058d 020a ; 0bc5 C False from color 0x0ba9 020a ; 0bd1 C from color 0x0ba9 020a ; 0bf7 C False from color 0x0ba9 020a ; 0c03 C from color 0x0ba9 020a ; 22cc C from color 0x0000 020a ; 2ac3 C False from color 0x2abd 020a ; 2ad3 C False from color 0x2abd 020a ; 2ad6 C False from color 0x2abd 020a ; 2ade C True from color 0x2adb 020a ; 2ae4 C True from color 0x2adb 020a ; 3319 C from color 0x0000 020a ; 331c C from color 0x0000 020a ; 332b C from color 0x0000 020a ; 3335 C False from color 0x0000 020a ; 3337 C False from color 0x0000 020a ; 334c C from color MACRO_Action_Accept_Activation 020a ; 334f C from color MACRO_Action_Accept_Activation 020a ; 3353 C from color MACRO_Action_Accept_Activation 020a ; 3360 C from color 0x2ee5 020a ; 3362 C from color 0x2ee5 020a ; 3692 C False from color 0x05a7 020a ; 369e C from color 0x369e 020a ; 369f C from color 0x369e 020a ; 36a6 C from color 0x05a7 020a ; 36a9 C False from color 0x05a7 020a ; 36ac C False from color 0x05a7 020a ; 36b0 C False from color 0x05a7 020a ; 36b3 C True from color 0x05a7 020a ; 36bb C from color 0x05a7 020a ; 36c9 C from color 0x05a7 020a ; -------------------------------------------------------------------------------------- 020a 020a ioc_random 14 clear cpu running; Flow J 0x200 seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 020b ; -------------------------------------------------------------------------------------- 020b ; Comes from: 020b ; 081b C False from color 0x0000 020b ; 083c C False from color 0x0000 020b ; 0854 C False from color 0x0820 020b ; -------------------------------------------------------------------------------------- 020b 020b ioc_random 14 clear cpu running; Flow J 0x201 seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 020c ; -------------------------------------------------------------------------------------- 020c ; Comes from: 020c ; 0122 C False from color 0x0000 020c ; 081e C from color 0x0000 020c ; 0827 C False from color 0x0000 020c ; 0847 C True from color 0x0820 020c ; 0848 C True from color 0x0820 020c ; 0849 C True from color 0x0820 020c ; 0872 C True from color 0x0821 020c ; -------------------------------------------------------------------------------------- 020c 020c ioc_random 14 clear cpu running; Flow J 0x202 seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 020d ; -------------------------------------------------------------------------------------- 020d ; Comes from: 020d ; 01b0 C from color UE_BIN_EQ 020d ; 01b8 C from color UE_BIN_OP 020d ; 01c0 C from color UE_TOS_OP 020d ; 01c8 C from color UE_TOSI_OP 020d ; 06bc C from color 0x062d 020d ; 06c4 C False from color 0x06c3 020d ; 06c9 C from color 0x06b6 020d ; 06cc C False from color 0x06cb 020d ; 06dc C False from color 0x0000 020d ; 08be C False from color 0x0127 020d ; 08d2 C True from color 0x0127 020d ; 08e6 C True from color 0x08e6 020d ; 08e7 C True from color 0x08e6 020d ; 08eb C True from color 0x08e6 020d ; 08ee C True from color 0x08e6 020d ; 08f1 C True from color 0x08e6 020d ; 08f4 C True from color 0x08e6 020d ; 098c C from color 0x098c 020d ; 09ae C from color 0x09ae 020d ; 09be C from color 0x09be 020d ; 0a7c C from color 0x0a7c 020d ; 0a90 C from color 0x0a90 020d ; 0aa4 C from color 0x0a33 020d ; 0d54 C False from color 0x0000 020d ; 0eef C True from color 0x0000 020d ; 0ef3 C True from color 0x0000 020d ; 0ef5 C from color 0x0000 020d ; 0ef6 C from color 0x0000 020d ; 0f08 C False from color 0x0000 020d ; 191b C from color 0x191b 020d ; 191c C from color 0x191b 020d ; 191d C from color 0x191b 020d ; 191e C from color 0x191b 020d ; 1922 C from color 0x1922 020d ; 1926 C from color 0x1926 020d ; 192a C from color 0x0000 020d ; 2a70 C True from color 0x0000 020d ; 2a72 C True from color 0x0000 020d ; 2a74 C True from color 0x0000 020d ; 2a76 C True from color 0x0000 020d ; 2a78 C True from color 0x0000 020d ; 2a7b C True from color 0x0000 020d ; 2aba C from color 0x0127 020d ; 34a0 C from color 0x349b 020d ; 3957 C False from color 0x0000 020d ; 39f9 C False from color 0x39f7 020d ; 3a08 C False from color 0x0000 020d ; 3b60 C from color 0x3b5b 020d ; -------------------------------------------------------------------------------------- 020d 020d ioc_random 14 clear cpu running; Flow J 0x203 seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 020e ; -------------------------------------------------------------------------------------- 020e ; Comes from: 020e ; 018d C from color 0x0127 020e ; -------------------------------------------------------------------------------------- 020e 020e ioc_random 14 clear cpu running; Flow J 0x204 seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 020f 020f ioc_random 14 clear cpu running; Flow J 0x205 seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 0210 ; -------------------------------------------------------------------------------------- 0210 ; Comes from: 0210 ; 0116 C from color 0x0000 0210 ; 01d0 C from color UE_PAGE_X 0210 ; 01d8 C from color UE_CHK_SYS 0210 ; 026a C from color 0x026a 0210 ; 0299 C from color 0x0299 0210 ; 029d C from color 0x0000 0210 ; 02b6 C from color 0x0000 0210 ; 02d5 C from color 0x02ca 0210 ; 02ea C from color 0x0000 0210 ; 0311 C from color 0x0000 0210 ; 0315 C from color 0x0000 0210 ; 0316 C from color 0x0000 0210 ; 0326 C from color MACRO_Action_Set_Priority 0210 ; 0329 C from color MACRO_Action_Set_Priority 0210 ; 032a C from color 0x032a 0210 ; 032b C from color 0x032b 0210 ; 032e C from color 0x032c 0210 ; 0330 C from color 0x032f 0210 ; 0337 C from color 0x0000 0210 ; 0339 C from color 0x0338 0210 ; 033b C from color 0x033a 0210 ; 033c C from color 0x033c 0210 ; 033d C from color 0x033d 0210 ; 0382 C from color 0x0380 0210 ; 0385 C from color 0x0383 0210 ; 0393 C from color 0x0000 0210 ; 039a C from color 0x0398 0210 ; 03ac C from color 0x0398 0210 ; 03ad C from color 0x03ad 0210 ; 03b0 C from color 0x03ae 0210 ; 03be C from color 0x0000 0210 ; 03d3 C from color 0x03d1 0210 ; 03ef C from color 0x0000 0210 ; 03f8 C from color 0x03f8 0210 ; 0420 C from color 0x0000 0210 ; 0424 C from color 0x0421 0210 ; 042a C from color 0x0000 0210 ; 0447 C from color 0x0000 0210 ; 0468 C from color 0x0000 0210 ; 047f C from color 0x0000 0210 ; 0499 C from color 0x0000 0210 ; 049e C from color 0x0000 0210 ; 04af C from color 0x0000 0210 ; 04b2 C from color 0x04b2 0210 ; 04bc C from color 0x04bb 0210 ; 04bd C from color 0x04bd 0210 ; 04be C from color 0x04be 0210 ; 04c2 C from color 0x04c2 0210 ; 04c3 C from color 0x04c3 0210 ; 04c4 C from color 0x04c4 0210 ; 04f5 C from color 0x04f5 0210 ; 04f7 C from color 0x04f7 0210 ; 04f8 C from color 0x04f8 0210 ; 04f9 C from color 0x04f9 0210 ; 0516 C from color 0x0515 0210 ; 0518 C from color 0x0518 0210 ; 0519 C from color 0x0519 0210 ; 0556 C from color MACRO_Action_Pop_Auxiliary 0210 ; 0564 C from color 0x0564 0210 ; 0566 C from color 0x0565 0210 ; 0571 C from color 0x0000 0210 ; 0572 C from color 0x0572 0210 ; 0575 C from color 0x0573 0210 ; 0577 C from color 0x0576 0210 ; 057b C from color 0x0573 0210 ; 057e C from color 0x0573 0210 ; 0581 C from color 0x0573 0210 ; 0583 C from color 0x0582 0210 ; 0585 C from color 0x0584 0210 ; 0587 C from color 0x0586 0210 ; 058c C from color 0x0573 0210 ; 05a9 C from color 0x05a7 0210 ; 05ae C from color 0x05a7 0210 ; 05b2 C from color 0x05af 0210 ; 05b3 C from color 0x05b3 0210 ; 05b4 C from color 0x05b4 0210 ; 05c6 C from color 0x05a7 0210 ; 05d1 C from color 0x05d0 0210 ; 05d5 C from color 0x05a7 0210 ; 05d7 C from color 0x05d6 0210 ; 05e8 C from color 0x05db 0210 ; 05ea C from color 0x05e9 0210 ; 05eb C from color 0x05eb 0210 ; 05f8 C from color 0x05ec 0210 ; 05f9 C from color 0x05f9 0210 ; 05fa C from color 0x05fa 0210 ; 0605 C from color 0x05fb 0210 ; 060f C from color 0x0000 0210 ; 0616 C from color 0x0000 0210 ; 061a C from color 0x0000 0210 ; 061f C from color 0x0000 0210 ; 0624 C from color 0x05fb 0210 ; 062c C from color 0x062a 0210 ; 062e C from color 0x062e 0210 ; 0644 C from color 0x0000 0210 ; 0663 C from color 0x0000 0210 ; 0667 C from color 0x0664 0210 ; 0668 C from color 0x0668 0210 ; 0669 C from color 0x0669 0210 ; 0682 C from color 0x066a 0210 ; 0683 C from color 0x0683 0210 ; 0685 C from color 0x0684 0210 ; 0694 C from color 0x0693 0210 ; 06b5 C from color 0x0000 0210 ; 06b9 C from color 0x06b6 0210 ; 06be C from color 0x062d 0210 ; 06c2 C from color 0x06b6 0210 ; 06c6 C from color 0x06c3 0210 ; 06ca C from color 0x06b6 0210 ; 06d1 C from color 0x06ce 0210 ; 06da C from color 0x06d2 0210 ; 06db C from color 0x06db 0210 ; 06e3 C from color 0x06ce 0210 ; 06e7 C from color 0x06e6 0210 ; 06fb C from color 0x06d2 0210 ; 06fc C from color 0x06fc 0210 ; 0700 C from color 0x06fd 0210 ; 0716 C from color 0x0000 0210 ; 071b C from color 0x0717 0210 ; 071f C from color 0x071c 0210 ; 073a C from color 0x0000 0210 ; 073c C from color 0x0117 0210 ; 073d C from color 0x073d 0210 ; 0745 C from color 0x0000 0210 ; 0758 C from color 0x0203 0210 ; 0773 C from color 0x0773 0210 ; 079e C from color 0x0799 0210 ; 07a2 C from color 0x0799 0210 ; 07b3 C from color 0x07b1 0210 ; 07b8 C from color 0x07b5 0210 ; 07bf C from color 0x07b9 0210 ; 07c0 C from color 0x07c0 0210 ; 07c2 C from color 0x07c1 0210 ; 07c3 C from color 0x07c3 0210 ; 07d9 C from color 0x07c4 0210 ; 07ee C from color 0x07e8 0210 ; 0806 C from color 0x07ef 0210 ; 0807 C from color 0x0807 0210 ; 0982 C from color MACRO_Declare_Variable_Any 0210 ; 0992 C from color MACRO_Declare_Variable_Any,Visible 0210 ; 09a4 C from color MACRO_Execute_Any,Equal 0210 ; 09b4 C from color MACRO_Execute_Any,Not_Equal 0210 ; 09c6 C from color MACRO_Execute_Any,Address 0210 ; 0a28 C from color MACRO_Execute_Any,Convert 0210 ; 0a3a C from color MACRO_Execute_Any,Convert 0210 ; 0a52 C from color 0x0a52 0210 ; 0a53 C from color 0x0a53 0210 ; 0a54 C from color 0x0a54 0210 ; 0a63 C from color 0x0a63 0210 ; 0a64 C from color 0x0a64 0210 ; 0a65 C from color 0x0a65 0210 ; 0a72 C from color 0x0a4e 0210 ; 0a86 C from color 0x0a4e 0210 ; 0a9a C from color MACRO_Execute_Any,Convert 0210 ; 0abd C from color 0x0abd 0210 ; 0abe C from color 0x0abe 0210 ; 0abf C from color 0x0abf 0210 ; 0ac3 C from color 0x0ac3 0210 ; 0ac5 C from color 0x0ac5 0210 ; 0dbb C from color 0x0db1 0210 ; 0e05 C from color 0x0000 0210 ; 0e0c C from color 0x0000 0210 ; 0e19 C from color 0x0000 0210 ; 0eac C from color 0x0000 0210 ; 0eb7 C from color 0x0000 0210 ; 0ebb C from color 0x0000 0210 ; 0ed1 C from color 0x0000 0210 ; 0ed7 C from color 0x0ed6 0210 ; 0f01 C from color 0x0ef8 0210 ; 0f04 C from color 0x0f02 0210 ; 0f0f C from color 0x0000 0210 ; 0f16 C from color 0x0f16 0210 ; 0f1a C from color 0x0ef8 0210 ; 0f1b C from color 0x0f1b 0210 ; 0f25 C from color 0x0ef8 0210 ; 0f2d C from color 0x0ef8 0210 ; 0f2e C from color 0x0f2e 0210 ; 0f37 C from color 0x0ef8 0210 ; 0f38 C from color 0x0f38 0210 ; 0f3b C from color 0x0ef8 0210 ; 0f40 C from color 0x0ef8 0210 ; 0f41 C from color 0x0ef8 0210 ; 0f5b C from color 0x0ef8 0210 ; 0f67 C from color 0x0f64 0210 ; 0f6c C from color 0x0f62 0210 ; 0f7c C from color 0x0ef8 0210 ; 0f87 C from color 0x0ef8 0210 ; 0fb2 C from color 0x0ef8 0210 ; 0fb8 C from color 0x0fb8 0210 ; 0fbd C from color 0x0fb9 0210 ; 0fbf C from color 0x0fbe 0210 ; 0fcc C from color 0x0fcc 0210 ; 0fef C from color 0x0fd0 0210 ; 1001 C from color 0x0fd0 0210 ; 1017 C from color 0x0fd0 0210 ; 1053 C from color 0x0fd0 0210 ; 1054 C from color 0x0fd0 0210 ; 105b C from color 0x105b 0210 ; 105c C from color 0x1055 0210 ; 1068 C from color 0x1064 0210 ; 106a C from color 0x0fc7 0210 ; 1071 C from color 0x0ef8 0210 ; 1074 C from color 0x0ef8 0210 ; 1078 C from color 0x0ef8 0210 ; 10ba C from color 0x10ba 0210 ; 10bb C from color 0x10bb 0210 ; 10bc C from color 0x10bc 0210 ; 10c0 C from color 0x10c0 0210 ; 10c1 C from color 0x10c1 0210 ; 10c2 C from color 0x10c2 0210 ; 10d3 C from color 0x10d2 0210 ; 1100 C from color 0x1100 0210 ; 1104 C from color 0x1104 0210 ; 1108 C from color 0x1108 0210 ; 110c C from color 0x110c 0210 ; 1111 C from color 0x1110 0210 ; 1112 C from color 0x1112 0210 ; 1113 C from color 0x1113 0210 ; 1117 C from color 0x1117 0210 ; 1118 C from color 0x1118 0210 ; 1119 C from color 0x1119 0210 ; 1146 C from color 0x110d 0210 ; 11f5 C from color 0x11f0 0210 ; 11f6 C from color 0x11f6 0210 ; 11f7 C from color 0x11f7 0210 ; 11fb C from color 0x11fb 0210 ; 11fc C from color 0x11fc 0210 ; 11fd C from color 0x11fd 0210 ; 1253 C from color 0x124e 0210 ; 1254 C from color 0x1254 0210 ; 1255 C from color 0x1255 0210 ; 1259 C from color 0x1259 0210 ; 125a C from color 0x125a 0210 ; 125b C from color 0x125b 0210 ; 1627 C from color MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 0210 ; 1639 C from color MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 0210 ; 164b C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 0210 ; 165d C from color MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 0210 ; 1786 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1788 C from color 0x1787 0210 ; 178f C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1793 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1b1f C from color MACRO_Execute_Access,Deallocate 0210 ; 1c95 C from color 0x0000 0210 ; 1c96 C from color 0x1c96 0210 ; 1ca7 C from color 0x1ca7 0210 ; 1ca8 C from color 0x1ca8 0210 ; 1ca9 C from color 0x1ca9 0210 ; 1d0d C from color 0x0000 0210 ; 1d2e C from color 0x1d2c 0210 ; 1d30 C from color 0x1d2f 0210 ; 1d32 C from color 0x1d31 0210 ; 1d33 C from color 0x1d33 0210 ; 1d36 C from color 0x1d36 0210 ; 1d38 C from color 0x1d38 0210 ; 1d3a C from color 0x1d3a 0210 ; 1d3b C from color 0x1d3b 0210 ; 1d3d C from color 0x1d3c 0210 ; 1d3e C from color 0x1d3e 0210 ; 1d3f C from color 0x1d3f 0210 ; 1d40 C from color 0x1d40 0210 ; 1d42 C from color 0x1d42 0210 ; 1d44 C from color 0x1d44 0210 ; 1d4b C from color 0x1d4a 0210 ; 1d4c C from color 0x1d4c 0210 ; 1d4d C from color 0x1d4d 0210 ; 1d51 C from color 0x1d51 0210 ; 1d52 C from color 0x1d52 0210 ; 1d53 C from color 0x1d53 0210 ; 1e90 C from color 0x1e8f 0210 ; 1e91 C from color 0x1e91 0210 ; 1ec1 C from color 0x1ec1 0210 ; 1f64 C from color 0x1f64 0210 ; 1f66 C from color 0x1f66 0210 ; 1f67 C from color 0x1f67 0210 ; 1f68 C from color 0x1f68 0210 ; 1fe2 C from color MACRO_Complete_Type_Array,By_Constraining 0210 ; 2031 C from color 0x2010 0210 ; 2071 C from color 0x2071 0210 ; 2072 C from color 0x2072 0210 ; 2073 C from color 0x2073 0210 ; 2077 C from color 0x2077 0210 ; 2078 C from color 0x2078 0210 ; 2079 C from color 0x2079 0210 ; 20aa C from color 0x20aa 0210 ; 20ab C from color 0x20ab 0210 ; 20ac C from color 0x20ac 0210 ; 20b0 C from color 0x20b0 0210 ; 20b1 C from color 0x20b1 0210 ; 20b2 C from color 0x20b2 0210 ; 217e C from color MACRO_Declare_Type_Array,Constrained 0210 ; 21da C from color 0x2003 0210 ; 21f1 C from color 0x21f1 0210 ; 21f3 C from color 0x21f3 0210 ; 21f4 C from color 0x21f4 0210 ; 21f5 C from color 0x21f5 0210 ; 2310 C from color 0x2310 0210 ; 2344 C from color 0x2342 0210 ; 238e C from color 0x238e 0210 ; 2448 C from color 0x2409 0210 ; 2491 C from color 0x2488 0210 ; 255b C from color MACRO_Complete_Type_Variant_Record,By_Defining 0210 ; 2568 C from color 0x2568 0210 ; 2569 C from color 0x2569 0210 ; 258e C from color MACRO_Complete_Type_Variant_Record,By_Defining 0210 ; 2669 C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 2687 C from color 0x2684 0210 ; 2688 C from color 0x2688 0210 ; 268d C from color 0x2689 0210 ; 269c C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 26c1 C from color 0x26c1 0210 ; 26c2 C from color 0x26c2 0210 ; 26c3 C from color 0x26c3 0210 ; 26c7 C from color 0x26c7 0210 ; 26c8 C from color 0x26c8 0210 ; 26c9 C from color 0x26c9 0210 ; 26e2 C from color 0x26e0 0210 ; 26e4 C from color 0x26e4 0210 ; 26e5 C from color 0x26e5 0210 ; 26e6 C from color 0x26e6 0210 ; 27e1 C from color 0x0000 0210 ; 292c C from color 0x0000 0210 ; 2a62 C from color ML_Resolve Reference 0210 ; 2a91 C from color 0x0127 0210 ; 2a93 C from color 0x0127 0210 ; 2a94 C from color 0x0127 0210 ; 2a99 C from color 0x0127 0210 ; 2b06 C from color 0x2b06 0210 ; 2b07 C from color 0x2b07 0210 ; 2b08 C from color 0x2b08 0210 ; 2b09 C from color 0x2b09 0210 ; 2b0a C from color 0x2b0a 0210 ; 2b0d C from color 0x2b0d 0210 ; 2b0e C from color 0x2b0e 0210 ; 2b0f C from color 0x2b0f 0210 ; 2b1c C from color 0x2b1c 0210 ; 2b1d C from color 0x2b1d 0210 ; 2b1e C from color 0x2b1e 0210 ; 2b22 C from color 0x2b22 0210 ; 2b23 C from color 0x2b23 0210 ; 2b24 C from color 0x2b24 0210 ; 2b64 C from color MACRO_Complete_Type_Task,By_Renaming 0210 ; 2b6e C from color 0x0000 0210 ; 2b71 C from color 0x2b71 0210 ; 2c26 C from color 0x0000 0210 ; 2c40 C from color 0x0000 0210 ; 2c4d C from color 0x2c4c 0210 ; 2c50 C from color 0x2c50 0210 ; 2c58 C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 0210 ; 2c7f C from color MACRO_Execute_Select,Member_Write,fieldnum 0210 ; 2c84 C from color 0x2c84 0210 ; 2c86 C from color 0x2c85 0210 ; 2cd5 C from color MACRO_Action_Elaborate_Subprogram 0210 ; 2cdb C from color MACRO_Action_Check_Subprogram_Elaborated 0210 ; 2d13 C from color 0x2d11 0210 ; 2d42 C from color ML_break_class 0210 ; 2d45 C from color 0x2d43 0210 ; 2d55 C from color 0x2d53 0210 ; 2dee C from color 0x0000 0210 ; 2df4 C from color 0x0000 0210 ; 2e27 C from color 0x0000 0210 ; 2eb0 C from color 0x2eb0 0210 ; 2ec6 C from color 0x0000 0210 ; 2ef8 C from color 0x2ee5 0210 ; 2f13 C from color 0x2ec7 0210 ; 2f28 C from color 0x06b6 0210 ; 2f3c C from color 0x2ec7 0210 ; 2f62 C from color 0x0000 0210 ; 2f7f C from color 0x2f73 0210 ; 2f95 C from color 0x0000 0210 ; 3296 C from color 0x3296 0210 ; 32c8 C from color 0x0000 0210 ; 32de C from color 0x0000 0210 ; 3377 C from color 0x0000 0210 ; 337c C from color 0x0000 0210 ; 3382 C from color 0x0000 0210 ; 3387 C from color 0x0000 0210 ; 338b C from color 0x0000 0210 ; 3393 C from color 0x0000 0210 ; 3394 C from color 0x3394 0210 ; 3399 C from color 0x3395 0210 ; 339c C from color 0x3395 0210 ; 339e C from color 0x3395 0210 ; 33a1 C from color 0x3395 0210 ; 33a2 C from color 0x33a2 0210 ; 33b8 C from color 0x3395 0210 ; 33b9 C from color 0x33b9 0210 ; 33ba C from color 0x0000 0210 ; 33c9 C from color 0x0f05 0210 ; 33cb C from color 0x33ca 0210 ; 33e6 C from color 0x0000 0210 ; 33f1 C from color 0x0000 0210 ; 33f4 C from color 0x0000 0210 ; 340e C from color 0x22cb 0210 ; 340f C from color 0x340f 0210 ; 3410 C from color 0x3410 0210 ; 3411 C from color 0x3411 0210 ; 3412 C from color 0x3412 0210 ; 341d C from color 0x0000 0210 ; 3450 C from color 0x02c9 0210 ; 3452 C from color 0x0fc7 0210 ; 346a C from color 0x0000 0210 ; 346b C from color 0x346b 0210 ; 346e C from color 0x0000 0210 ; 346f C from color 0x346f 0210 ; 3471 C from color 0x3470 0210 ; 3472 C from color 0x3472 0210 ; 3473 C from color 0x3473 0210 ; 347c C from color 0x347b 0210 ; 347d C from color 0x347d 0210 ; 347e C from color 0x347e 0210 ; 347f C from color 0x347f 0210 ; 348f C from color 0x348d 0210 ; 3490 C from color 0x3490 0210 ; 3495 C from color 0x3493 0210 ; 34b4 C from color 0x0000 0210 ; 34c4 C from color 0x0000 0210 ; 34cf C from color 0x0f05 0210 ; 34d1 C from color 0x34d0 0210 ; 34d4 C from color 0x34d2 0210 ; 34da C from color 0x0000 0210 ; 34db C from color 0x34db 0210 ; 34dd C from color 0x34dc 0210 ; 34e9 C from color 0x0000 0210 ; 34ec C from color 0x0000 0210 ; 34ef C from color 0x0000 0210 ; 352e C from color 0x0000 0210 ; 353a C from color 0x0000 0210 ; 3544 C from color 0x0000 0210 ; 3546 C from color 0x0000 0210 ; 3547 C from color 0x3547 0210 ; 3550 C from color 0x0000 0210 ; 3552 C from color 0x0000 0210 ; 3553 C from color 0x3553 0210 ; 358f C from color 0x0000 0210 ; 3597 C from color 0x3597 0210 ; 359e C from color 0x0000 0210 ; 35a0 C from color 0x35a0 0210 ; 3617 C from color 0x0000 0210 ; 361a C from color 0x3618 0210 ; 3639 C from color 0x362c 0210 ; 363a C from color 0x363a 0210 ; 365b C from color 0x3657 0210 ; 365d C from color 0x365c 0210 ; 3661 C from color 0x365e 0210 ; 36eb C from color 0x36e9 0210 ; 36ec C from color 0x36ec 0210 ; 36f1 C from color 0x0000 0210 ; 36f8 C from color 0x36f8 0210 ; 36f9 C from color 0x36f9 0210 ; 36fa C from color 0x36fa 0210 ; 3704 C from color 0x36f5 0210 ; 3716 C from color 0x0000 0210 ; 371a C from color 0x0000 0210 ; 371e C from color 0x371b 0210 ; 3721 C from color 0x0000 0210 ; 3724 C from color 0x3724 0210 ; 3725 C from color 0x3725 0210 ; 3726 C from color 0x3726 0210 ; 3727 C from color 0x3727 0210 ; 3728 C from color 0x3728 0210 ; 372e C from color 0x0000 0210 ; 3737 C from color 0x3735 0210 ; 373b C from color 0x3738 0210 ; 3744 C from color 0x3740 0210 ; 3757 C from color 0x3740 0210 ; 3764 C from color 0x3764 0210 ; 3765 C from color 0x3765 0210 ; 3766 C from color 0x3766 0210 ; 3768 C from color 0x3768 0210 ; 376c C from color 0x376c 0210 ; 376d C from color 0x3735 0210 ; 3772 C from color 0x0000 0210 ; 377a C from color 0x3767 0210 ; 377b C from color 0x377b 0210 ; 3784 C from color 0x3767 0210 ; 3786 C from color 0x0000 0210 ; 378c C from color 0x0000 0210 ; 3791 C from color 0x378d 0210 ; 3793 C from color 0x3792 0210 ; 379a C from color 0x3794 0210 ; 37a9 C from color 0x0000 0210 ; 37c1 C from color 0x0000 0210 ; 37db C from color MACRO_Execute_Select,Rendezvous 0210 ; 37fb C from color 0x37dc 0210 ; 3801 C from color 0x37ff 0210 ; 380a C from color 0x37fe 0210 ; 3819 C from color 0x37ff 0210 ; 3822 C from color 0x37ff 0210 ; 3839 C from color 0x0000 0210 ; 3881 C from color 0x387a 0210 ; 389a C from color 0x2abd 0210 ; 38bf C from color 0x38b3 0210 ; 38c2 C from color 0x38c0 0210 ; 38d5 C from color 0x38c8 0210 ; 391a C from color 0x0000 0210 ; 3920 C from color 0x0000 0210 ; 393a C from color 0x03fa 0210 ; 394a C from color 0x0913 0210 ; 3950 C from color 0x0000 0210 ; 3958 C from color 0x0000 0210 ; 396e C from color 0x03fa 0210 ; 396f C from color 0x03fa 0210 ; 3970 C from color 0x3970 0210 ; 3971 C from color 0x3971 0210 ; 3980 C from color 0x3972 0210 ; 3989 C from color 0x3974 0210 ; 39ab C from color 0x0000 0210 ; 39ad C from color 0x0000 0210 ; 39b1 C from color 0x39ae 0210 ; 39be C from color 0x0000 0210 ; 39e9 C from color 0x0000 0210 ; 39f1 C from color 0x0000 0210 ; 39f6 C from color 0x0000 0210 ; 39fa C from color 0x39f7 0210 ; 3a04 C from color 0x0000 0210 ; 3a09 C from color 0x0000 0210 ; 3a27 C from color 0x03fa 0210 ; 3a36 C from color 0x3a35 0210 ; 3a44 C from color 0x0000 0210 ; 3a4d C from color 0x0000 0210 ; 3a6f C from color 0x0000 0210 ; 3a81 C from color 0x3a81 0210 ; 3a82 C from color 0x3a82 0210 ; 3a85 C from color 0x3a85 0210 ; 3a86 C from color 0x3a86 0210 ; 3a88 C from color 0x3a88 0210 ; 3a89 C from color 0x3a89 0210 ; 3a8a C from color 0x3a8a 0210 ; 3a8b C from color 0x3a8b 0210 ; 3a91 C from color 0x3a91 0210 ; 3a92 C from color 0x3a92 0210 ; 3a93 C from color 0x3a93 0210 ; 3aad C from color 0x0000 0210 ; 3ab1 C from color 0x0000 0210 ; 3abd C from color 0x0000 0210 ; 3adf C from color 0x0000 0210 ; 3ae6 C from color 0x0000 0210 ; 3ae7 C from color 0x03fa 0210 ; 3b4b C from color 0x0000 0210 ; 3b4f C from color 0x3b4e 0210 ; 3b54 C from color 0x0200 0210 ; 3b56 C from color 0x3b55 0210 ; 3b5a C from color 0x0ef8 0210 ; 3b63 C from color 0x3b63 0210 ; 3b7b C from color 0x3b49 0210 ; 3b7d C from color 0x3b49 0210 ; 3b80 C from color 0x3b49 0210 ; 3b8a C from color 0x3b89 0210 ; 3b90 C from color 0x3b8b 0210 ; -------------------------------------------------------------------------------------- 0210 0210 ioc_random 14 clear cpu running; Flow J 0x206 seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 0211 ; -------------------------------------------------------------------------------------- 0211 ; Comes from: 0211 ; 03ae C True from color 0x03ae 0211 ; 06d6 C True from color 0x06d2 0211 ; 077c C False from color 0x0767 0211 ; 0783 C from color 0x0767 0211 ; 084b C False from color 0x0820 0211 ; 0878 C True from color 0x0821 0211 ; 0b70 C False from color 0x0b6e 0211 ; 0b74 C False from color 0x0b72 0211 ; 0b78 C False from color 0x0b76 0211 ; 0ed2 C False from color 0x0203 0211 ; 0fc2 C from color 0x0fbe 0211 ; 108b C from color 0x0ef8 0211 ; 3618 C True from color 0x3618 0211 ; 371b C False from color 0x371b 0211 ; 371d C True from color 0x371b 0211 ; 3781 C True from color 0x3767 0211 ; 3782 C False from color 0x3767 0211 ; 3783 C False from color 0x3767 0211 ; 3799 C False from color 0x3794 0211 ; 3b59 C True from color 0x0ef8 0211 ; -------------------------------------------------------------------------------------- 0211 0211 ioc_random 14 clear cpu running; Flow J 0x207 seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 0212 ; -------------------------------------------------------------------------------------- 0212 ; Comes from: 0212 ; 0ece C from color 0x0000 0212 ; -------------------------------------------------------------------------------------- 0212 0212 ioc_random 14 clear cpu running; Flow J 0x208 seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 0213 ; -------------------------------------------------------------------------------------- 0213 ; Comes from: 0213 ; 0ecd C from color 0x0000 0213 ; -------------------------------------------------------------------------------------- 0213 0213 ioc_random 14 clear cpu running; Flow J 0x209 seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 0214 ; -------------------------------------------------------------------------------------- 0214 ; 0x00bf Action Accept_Activation 0214 ; -------------------------------------------------------------------------------------- 0214 MACRO_Action_Accept_Activation: 0214 0214 dispatch_brk_class 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0214 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0215 0215 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a2 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0216 0216 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x217 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0219 0x0219 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0217 0217 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0218 0218 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3915 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3915 0x3915 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0219 0219 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 021a 021a seq_br_type 2 Push (branch address); Flow J 0x21b seq_branch_adr 0228 0x0228 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 021b 021b fiu_mem_start 2 start-rd; Flow J cc=False 0x220 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0220 0x0220 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 021c 021c <default> 021d 021d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 021e 021e ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 021f 021f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x221 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0220 0220 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0221 0221 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0222 0222 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0223 0223 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 0224 0224 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3277 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0225 0225 ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 val_c_adr 3c GP03 0226 0226 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0227 0227 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 val_b_adr 03 GP03 0228 0228 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0229 0229 <halt> ; Flow R 022a ; -------------------------------------------------------------------------------------- 022a ; 0x00bc Action Signal_Activated 022a ; -------------------------------------------------------------------------------------- 022a MACRO_Action_Signal_Activated: 022a 022a dispatch_brk_class 3 ; Flow C 0x337d dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 022a seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d 022b 022b fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 022c 022c fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a2 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 022d 022d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 022e 022e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 022f 022f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3959 seq_br_type 5 Call True seq_branch_adr 3959 0x3959 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0230 0230 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0231 0231 <halt> ; Flow R 0232 ; -------------------------------------------------------------------------------------- 0232 ; 0x00be Action Activate_Tasks 0232 ; -------------------------------------------------------------------------------------- 0232 MACRO_Action_Activate_Tasks: 0232 0232 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0232 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0233 0233 seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d 0234 0234 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR07:0f val_frame 7 0235 0235 ioc_load_wdr 0 ; Flow J cc=False 0x526 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0236 0236 fiu_mem_start 2 start-rd; Flow C 0x333d ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 333d 0x333d seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 0237 0237 seq_br_type 7 Unconditional Call; Flow C 0x23a seq_branch_adr 023a 0x023a seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0238 0238 seq_br_type 2 Push (branch address); Flow J 0x239 seq_branch_adr 0238 0x0238 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0239 0239 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3348 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3348 0x3348 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 023a 023a fiu_load_var 1 hold_var; Flow C cc=True 0x245 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 023b 023b typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 023c 023c fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 023d 023d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x394b fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 394b 0x394b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 03 GP03 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 023e 023e ioc_tvbs 2 fiu+val; Flow J cc=True 0x242 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 023f 023f seq_br_type 2 Push (branch address); Flow J 0x240 seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0240 0240 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3371 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0241 0241 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0242 0242 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x244 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0244 0x0244 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0243 0243 ioc_tvbs 2 fiu+val; Flow C 0x32a2 seq_br_type 7 Unconditional Call seq_branch_adr 32a2 0x32a2 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0244 0244 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0245 ; -------------------------------------------------------------------------------------- 0245 ; Comes from: 0245 ; 023a C True from color 0x0000 0245 ; 0253 C True from color 0x0000 0245 ; 02d1 C True from color 0x02ca 0245 ; -------------------------------------------------------------------------------------- 0245 0245 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 0246 0246 fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 0247 0247 <halt> ; Flow R 0248 ; -------------------------------------------------------------------------------------- 0248 ; 0x00bd Action Activate_Heap_Tasks 0248 ; -------------------------------------------------------------------------------------- 0248 MACRO_Action_Activate_Heap_Tasks: 0248 0248 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0248 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0249 0249 seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d 024a 024a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR05:18 val_frame 5 024b 024b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x25f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 025f 0x025f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 024c 024c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 024d 024d ioc_load_wdr 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 024e 024e fiu_mem_start 2 start-rd; Flow C 0x3345 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 024f 024f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x260 seq_br_type f Unconditional Case Call seq_branch_adr 0260 0x0260 seq_en_micro 0 0250 0250 seq_br_type 2 Push (branch address); Flow J 0x251 seq_branch_adr 0250 0x0250 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0251 0251 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3348 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3348 0x3348 seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 0252 0252 fiu_tivi_src c mar_0xc; Flow C cc=False 0x266 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0266 0x0266 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0253 0253 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0254 0254 ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0255 0255 fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0256 0256 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x394b fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 394b 0x394b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 02 GP02 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0257 0257 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x258 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 025d 0x025d seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 0258 0258 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0259 0259 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 025a 025a seq_b_timing 1 Latch Condition; Flow J cc=True 0x25d seq_br_type 1 Branch True seq_branch_adr 025d 0x025d typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025b 025b fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3371 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 025c 025c seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 025d 025d typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025e 025e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 23 TR02:03 typ_frame 2 025f 025f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0260 0260 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0261 0261 seq_br_type 3 Unconditional Branch; Flow J 0x252 seq_branch_adr 0252 0x0252 0262 0262 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0263 0263 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0264 0264 seq_b_timing 1 Latch Condition; Flow J cc=True 0x252 seq_br_type 1 Branch True seq_branch_adr 0252 0x0252 0265 0265 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 0266 0266 seq_br_type 7 Unconditional Call; Flow C 0x359a seq_branch_adr 359a 0x359a 0267 0267 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 0268 0x0268 seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 0268 0268 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x269 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 026a 0x026a typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR05:02 val_frame 5 0269 0269 ioc_tvbs 2 fiu+val; Flow J 0x25b seq_br_type 3 Unconditional Branch seq_branch_adr 025b 0x025b typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 026a 026a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 026b 026b seq_br_type 3 Unconditional Branch; Flow J 0x268 seq_branch_adr 0268 0x0268 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 026c ; -------------------------------------------------------------------------------------- 026c ; Comes from: 026c ; 0232 C True from color 0x0000 026c ; 0248 C True from color 0x0000 026c ; -------------------------------------------------------------------------------------- 026c 026c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x333d fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 333d 0x333d seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 026d 026d fiu_load_var 1 hold_var; Flow R cc=True fiu_mem_start 6 start_rd_if_false fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 026e 0x026e typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 026e 026e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x274 seq_br_type 5 Call True seq_branch_adr 0274 0x0274 seq_cond_sel 67 REFRESH_MACRO_EVENT 026f 026f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0270 0270 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x277 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0277 0x0277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0271 0271 seq_br_type 2 Push (branch address); Flow J 0x272 seq_branch_adr 026d 0x026d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0272 0272 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3348 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3348 0x3348 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 0273 0273 seq_br_type a Unconditional Return; Flow R 0274 ; -------------------------------------------------------------------------------------- 0274 ; Comes from: 0274 ; 026e C True from color MACRO_Action_Accept_Activation 0274 ; -------------------------------------------------------------------------------------- 0274 0274 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 0275 0275 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0276 0276 seq_br_type a Unconditional Return; Flow R 0277 0277 ioc_fiubs 1 val ; Flow J 0x221 seq_br_type 3 Unconditional Branch seq_branch_adr 0221 0x0221 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 0278 ; -------------------------------------------------------------------------------------- 0278 ; 0x00bb Action Signal_Completion,>R 0278 ; -------------------------------------------------------------------------------------- 0278 MACRO_Action_Signal_Completion,>R: 0278 0278 dispatch_brk_class 3 ; Flow C 0x337d dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0278 seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0279 0279 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2ab fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ab 0x02ab seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 027a 027a ioc_tvbs 1 typ+fiu; Flow J cc=True 0x291 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0291 0x0291 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 027b 027b fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2a1 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 02a1 0x02a1 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027c 027c fiu_mem_start 2 start-rd; Flow C 0x347b ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 347b 0x347b seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027d 027d fiu_mem_start 11 start_tag_query; Flow C cc=True 0x3493 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 3493 0x3493 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 20 VR02:00 val_frame 2 027e 027e seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 027f 027f fiu_mem_start 2 start-rd; Flow J 0x280 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0280 0280 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0281 0281 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x39a3 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 39a3 0x39a3 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0282 0282 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x2af fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 02af 0x02af seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 0283 0283 fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0284 0284 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02c0 0x02c0 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0285 0285 fiu_mem_start 2 start-rd; Flow J cc=True 0x29e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 029e 0x029e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 0286 0286 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0287 0287 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28f seq_br_type 1 Branch True seq_branch_adr 028f 0x028f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_rand 6 CHECK_CLASS_A_??_B 0288 0288 seq_br_type 7 Unconditional Call; Flow C 0x3a1d seq_branch_adr 3a1d 0x3a1d 0289 0289 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 028a 028a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 028b 028b fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x28c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0299 0x0299 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 028c 028c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x28d fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 028d 028d ioc_tvbs 1 typ+fiu; Flow C 0x3371 seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 028e 028e ioc_adrbs 2 typ ; Flow J 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 028f 028f ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0290 0290 seq_br_type 3 Unconditional Branch; Flow J 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0291 0291 ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0292 0292 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0293 0293 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0294 0294 ioc_load_wdr 0 ; Flow J cc=True 0x296 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0296 0x0296 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_frame 8 0295 0295 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A 0296 0296 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 0297 0297 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x371 seq_br_type 1 Branch True seq_branch_adr 0371 0x0371 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0298 0298 seq_br_type 3 Unconditional Branch; Flow J 0x371 seq_branch_adr 0371 0x0371 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0299 0299 fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 029a 029a fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 029b 029b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x289 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0289 0x0289 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 029c 029c seq_br_type 1 Branch True; Flow J cc=True 0x27f seq_branch_adr 027f 0x027f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 029d 029d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 029e 029e fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x29f fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 029f 029f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2a0 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02a0 02a0 ioc_tvbs 2 fiu+val; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02a1 02a1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 02a2 02a2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 7 val_rand a PASS_B_HIGH 02a3 02a3 ioc_load_wdr 0 ; Flow C cc=True 0x2e1 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 02e1 0x02e1 typ_alu_func 1a PASS_B typ_b_adr 2d TR02:0d typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 02a4 02a4 seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 02a5 02a5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a6 02a6 ioc_load_wdr 0 typ_b_adr 2e TR07:0e typ_frame 7 val_b_adr 39 VR02:19 val_frame 2 02a7 02a7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2c0 seq_br_type 1 Branch True seq_branch_adr 02c0 0x02c0 typ_c_adr 1b TR02:04 typ_frame 2 02a8 02a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a9 02a9 seq_br_type 2 Push (branch address); Flow J 0x2aa seq_branch_adr 02af 0x02af 02aa 02aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x399e fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 399e 0x399e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02ab 02ab seq_br_type 7 Unconditional Call; Flow C 0x2ad seq_branch_adr 02ad 0x02ad typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02ac 02ac seq_br_type 3 Unconditional Branch; Flow J 0x278 seq_branch_adr 0278 MACRO_Action_Signal_Completion,>R 02ad 02ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 02ae 02ae fiu_mem_start 3 start-wr; Flow J 0x3b4a fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 02af 02af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ad seq_br_type 5 Call True seq_branch_adr 02ad 0x02ad seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02b0 02b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 02b1 02b1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 02b2 02b2 ioc_load_wdr 0 ; Flow J 0x2b3 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 02b3 02b3 fiu_mem_start 2 start-rd; Flow J 0x3464 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3464 0x3464 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02b4 02b4 ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02b5 02b5 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 02b6 02b6 ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_b_adr 16 CSA/VAL_BUS 02b7 02b7 fiu_mem_start 2 start-rd; Flow C 0x3369 seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 02b8 02b8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2bd seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02bd 0x02bd seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02b9 02b9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 02ba 02ba fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 02b4 0x02b4 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 02bb 02bb fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2bc fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02bc 02bc ioc_tvbs 1 typ+fiu; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 02bd 02bd typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 02be 02be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a5 seq_br_type 1 Branch True seq_branch_adr 02a5 0x02a5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02bf 02bf seq_br_type 3 Unconditional Branch; Flow J 0x27f seq_branch_adr 027f 0x027f 02c0 02c0 fiu_mem_start 2 start-rd; Flow C 0x3345 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02c1 02c1 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c2 02c2 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c3 02c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2ce fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ce 0x02ce seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 02c4 02c4 fiu_load_oreg 1 hold_oreg; Flow C 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335a 0x335a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 02c5 02c5 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c6 02c6 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c7 02c7 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c8 02c8 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c9 02c9 fiu_mem_start 2 start-rd; Flow J 0x3455 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3455 0x3455 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 02ca 02ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d1 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 02d1 0x02d1 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 02cb 02cb seq_br_type 2 Push (branch address); Flow J 0x2cc seq_branch_adr 02c3 0x02c3 02cc 02cc fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 02cd 02cd ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02ce 02ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 02cf 02cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a8 seq_br_type 1 Branch True seq_branch_adr 02a8 0x02a8 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02d0 02d0 seq_br_type 3 Unconditional Branch; Flow J 0x2af seq_branch_adr 02af 0x02af 02d1 02d1 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d2 02d2 ioc_fiubs 2 typ typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02d3 02d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d4 02d4 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 02d5 0x02d5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 02d5 02d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 02d6 02d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2df seq_br_type 1 Branch True seq_branch_adr 02df 0x02df seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 02d7 02d7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 02d8 02d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2da seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 02da 0x02da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 02d9 02d9 fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02da 02da fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 02db 02db fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dc 02dc ioc_fiubs 2 typ ; Flow J 0x2dd seq_br_type 2 Push (branch address) seq_branch_adr 02d6 0x02d6 typ_a_adr 02 GP02 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dd 02dd fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 23 VR02:03 val_frame 2 02de 02de ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02df 02df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 02e0 02e0 seq_br_type 3 Unconditional Branch; Flow J 0x2c3 seq_branch_adr 02c3 0x02c3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02e1 02e1 ioc_tvbs 2 fiu+val; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 02e2 0x02e2 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 02e2 02e2 fiu_mem_start 2 start-rd; Flow J 0x2e3 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0309 0x0309 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 2 val_rand a PASS_B_HIGH 02e3 02e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_random 06 Pop_stack+? val_c_adr 3c GP03 val_c_source 0 FIU_BUS 02e4 02e4 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e5 02e5 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x302 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0302 0x0302 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 02e6 02e6 seq_br_type 0 Branch False; Flow J cc=False 0x304 seq_branch_adr 0304 0x0304 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 02e7 02e7 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e8 02e8 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2eb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 02eb 0x02eb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 02e9 02e9 ioc_fiubs 0 fiu ; Flow J cc=False 0x300 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 13 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 02ea 02ea seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 02eb 02eb fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 02ec 02ec fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02ed 02ed <default> 02ee 02ee fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x300 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0300 0x0300 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 02ef 02ef ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2f6 seq_br_type 1 Branch True seq_branch_adr 02f6 0x02f6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02f0 02f0 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 02f1 02f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f5 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 02f5 0x02f5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f2 02f2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 25 VR05:05 val_frame 5 02f3 02f3 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 02f4 02f4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 02f5 02f5 fiu_load_var 1 hold_var; Flow J 0x2eb fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02eb 0x02eb val_a_adr 05 GP05 02f6 02f6 ioc_fiubs 0 fiu ; Flow J cc=True 0x2fb ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02fb 0x02fb seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 25 VR05:05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 02f7 02f7 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f8 02f8 ioc_load_wdr 0 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 02f9 02f9 fiu_mem_start 3 start-wr; Flow J 0x2fa ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 02fa 02fa ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x6b4 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 06b4 0x06b4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 03 GP03 02fb 02fb fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 02fc 02fc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 02fd 02fd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x2f7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02f7 0x02f7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 02fe 02fe fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc 02ff 02ff seq_br_type 3 Unconditional Branch; Flow J 0x2f7 seq_branch_adr 02f7 0x02f7 0300 0300 ioc_adrbs 1 val typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0301 0301 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2e6 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02e6 0x02e6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0302 0302 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0303 0303 fiu_mem_start 2 start-rd; Flow J 0x2e6 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02e6 0x02e6 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 0 PASS_A 0304 0304 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0305 0305 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0306 0306 seq_br_type 1 Branch True; Flow J cc=True 0x308 seq_branch_adr 0308 0x0308 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0307 0307 seq_br_type 3 Unconditional Branch; Flow J 0x304 seq_branch_adr 0304 0x0304 seq_en_micro 0 seq_random 06 Pop_stack+? 0308 0308 fiu_mem_start 2 start-rd; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0309 0x0309 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0309 0309 seq_br_type 7 Unconditional Call; Flow C 0x32a3 seq_branch_adr 32a3 0x32a3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 030a ; -------------------------------------------------------------------------------------- 030a ; 0x00b7 Action Make_Self 030a ; -------------------------------------------------------------------------------------- 030a MACRO_Action_Make_Self: 030a 030a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030b 030b seq_br_type 3 Unconditional Branch; Flow J 0x314 seq_branch_adr 0314 0x0314 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 030c ; -------------------------------------------------------------------------------------- 030c ; 0x00b6 Action Make_Scope 030c ; -------------------------------------------------------------------------------------- 030c MACRO_Action_Make_Scope: 030c 030c dispatch_brk_class 8 ; Flow J 0x312 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0312 0x0312 seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030d 030d <halt> ; Flow R 030e ; -------------------------------------------------------------------------------------- 030e ; 0x00b5 Action Make_Parent 030e ; -------------------------------------------------------------------------------------- 030e MACRO_Action_Make_Parent: 030e 030e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR04:0e val_frame 4 030f 030f ioc_tvbs 2 fiu+val typ_a_adr 38 TR1b:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b 0310 0310 fiu_mem_start 2 start-rd; Flow J cc=True 0x312 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0312 0x0312 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 0311 0311 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0312 0312 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME 0313 0313 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0314 0314 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x316 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0316 0x0316 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_latch 1 typ_a_adr 27 TR12:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0315 0315 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR12:08 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0316 0316 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR02:0a typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0317 0317 <halt> ; Flow R 0318 ; -------------------------------------------------------------------------------------- 0318 ; 0x00b4 Action Name_Partner 0318 ; -------------------------------------------------------------------------------------- 0318 MACRO_Action_Name_Partner: 0318 0318 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0318 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM 0319 0319 ioc_fiubs 0 fiu ; Flow J cc=False 0x320 seq_br_type 0 Branch False seq_branch_adr 0320 0x0320 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 031a 031a fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_frame 7 031b 031b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031c 031c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 031d 031d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x321 seq_br_type 1 Branch True seq_branch_adr 0321 0x0321 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 031e 031e fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x31a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 031a 0x031a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031f 031f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0320 0320 fiu_mem_start 2 start-rd; Flow J 0x31d ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 031d 0x031d typ_a_adr 39 TR02:19 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0321 0321 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0322 ; -------------------------------------------------------------------------------------- 0322 ; 0x00b8 Action Set_Priority 0322 ; -------------------------------------------------------------------------------------- 0322 MACRO_Action_Set_Priority: 0322 0322 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0322 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR06:01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0323 0323 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x327 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0327 0x0327 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_frame 5 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 0324 0324 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0325 0325 seq_en_micro 0 0326 0326 fiu_len_fill_lit 42 zero-fill 0x2; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0327 0327 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_b_adr 01 GP01 0328 0328 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x326c fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_frame 5 0329 0329 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_b_adr 16 CSA/VAL_BUS 032a 032a ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 032b 032b seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 032c 032c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 032d 032d fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 032e 032e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 032f 032f ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0330 0330 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0331 0331 seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 0332 0332 ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0333 0333 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0334 0334 ioc_fiubs 1 val ; Flow J cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR06:01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 0335 0335 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0336 0336 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0337 0337 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0338 0338 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0339 0339 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1b A_OR_B val_b_adr 20 VR02:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 033a 033a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 033b 033b fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 033c 033c ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 033d 033d seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 033e 033e seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 033f 033f ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0340 0340 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0341 0341 <halt> ; Flow R 0342 ; -------------------------------------------------------------------------------------- 0342 ; 0x00b3 Action Increase_Priority 0342 ; -------------------------------------------------------------------------------------- 0342 MACRO_Action_Increase_Priority: 0342 0342 dispatch_brk_class 4 ; Flow C 0x326a dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0342 seq_br_type 7 Unconditional Call seq_branch_adr 326a 0x326a 0343 0343 <halt> ; Flow R 0344 ; -------------------------------------------------------------------------------------- 0344 ; 0x00b9 Action Get_Priority 0344 ; -------------------------------------------------------------------------------------- 0344 MACRO_Action_Get_Priority: 0344 0344 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0344 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0345 0345 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0346 0346 fiu_load_tar 1 hold_tar; Flow J 0x347 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 32c3 0x32c3 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0347 0347 ioc_load_wdr 0 ; Flow J cc=True 0x526 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_frame 8 0348 0348 fiu_mem_start 3 start-wr; Flow J 0x32fc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0349 0349 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 034a 034a fiu_load_tar 1 hold_tar; Flow J cc=True 0x32c3 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32c3 0x32c3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 034b 034b ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 2e VR04:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 034c 034c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 034d 034d ioc_fiubs 2 typ ; Flow J cc=True 0x526 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 3b TR02:1b typ_frame 2 val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 8 034e 034e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3a3a ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3a3a 0x3a3a seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 034f 034f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0350 0350 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0351 0351 ioc_tvbs 5 seq+seq; Flow J cc=False 0x366 seq_br_type 0 Branch False seq_branch_adr 0366 0x0366 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0352 0352 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x354 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0354 0x0354 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 0353 0353 seq_br_type 1 Branch True; Flow J cc=True 0x359 seq_branch_adr 0359 0x0359 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 val_c_adr 3d GP02 0354 0354 seq_b_timing 0 Early Condition; Flow J cc=True 0x367 seq_br_type 1 Branch True seq_branch_adr 0367 0x0367 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0355 0355 fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_rand a PASS_B_HIGH 0356 0356 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0357 0x0357 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0357 0357 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0358 0358 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x359 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0359 0x0359 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0359 0359 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x365 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0365 0x0365 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 23 TR01:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 typ_frame 1 val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 035a 035a fiu_load_tar 1 hold_tar; Flow C cc=True 0x35d fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 035d 0x035d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 035b 035b fiu_mem_start 3 start-wr; Flow J 0x35c ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 035c 035c ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 035d 035d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x363 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0363 0x0363 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 035e 035e seq_br_type 0 Branch False; Flow J cc=False 0x367 seq_branch_adr 0367 0x0367 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 035f 035f seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 seq_en_micro 0 0360 0360 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0361 0361 seq_b_timing 1 Latch Condition; Flow J cc=False 0x352 seq_br_type 0 Branch False seq_branch_adr 0352 0x0352 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0362 0362 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0363 0363 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 31 TR12:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0364 0364 ioc_load_wdr 0 ; Flow J 0x365 seq_br_type 3 Unconditional Branch seq_branch_adr 0365 0x0365 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 0365 0365 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0366 0366 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36b fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 036b 0x036b typ_a_adr 20 TR05:00 typ_b_adr 03 GP03 typ_frame 5 0367 0367 seq_br_type 2 Push (branch address); Flow J 0x368 seq_branch_adr 069b 0x069b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0368 0368 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 2e TR12:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 24 VR04:04 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0369 0369 fiu_mem_start 2 start-rd; Flow J 0x3711 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 036a 036a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 20 TR02:00 typ_frame 2 036b 036b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 036c 036c seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 036d 036d seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 036e 036e fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 11 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A 036f 036f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x372 seq_br_type 1 Branch True seq_branch_adr 0372 0x0372 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 31 TR12:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0370 0370 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0371 0371 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 2e TR02:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0372 0372 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x374 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0374 0x0374 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR06:01 val_frame 6 0373 0373 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3371 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0374 0374 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_frame 2 0375 0375 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3371 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0376 0376 ioc_tvbs 5 seq+seq; Flow J 0x56b seq_br_type 3 Unconditional Branch seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0377 0377 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR02:18 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0378 0378 fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0379 0379 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x37e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 037e 0x037e typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 037a 037a <default> 037b 037b fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 037c 037c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 037d 037d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 037e 037e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 037f 037f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x37e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 037e 0x037e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 0380 ; -------------------------------------------------------------------------------------- 0380 ; Comes from: 0380 ; 36fb C from color 0x0000 0380 ; 36fd C from color 0x0000 0380 ; 36ff C from color 0x36f5 0380 ; -------------------------------------------------------------------------------------- 0380 0380 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_frame 4 val_rand a PASS_B_HIGH 0381 0381 ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0382 0382 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 0383 0383 ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 0384 0384 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0385 0385 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0386 0386 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0387 0387 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x393 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0393 0x0393 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0388 0388 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 0389 0389 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 038a 038a fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x38e fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 038e 0x038e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 038b 038b seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 038c 038c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 038d 038d ioc_fiubs 0 fiu seq_en_micro 0 038e 038e fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x396 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0396 0x0396 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 038f 038f fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x395 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0395 0x0395 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0390 0390 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x38a seq_br_type 1 Branch True seq_branch_adr 038a 0x038a seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0391 0391 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0392 0392 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0393 0393 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0394 0394 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0395 0395 seq_br_type 3 Unconditional Branch; Flow J 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0396 ; -------------------------------------------------------------------------------------- 0396 ; Comes from: 0396 ; 038e C #0x0 from color 0x0000 0396 ; -------------------------------------------------------------------------------------- 0396 0396 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 0397 0397 fiu_load_tar 1 hold_tar; Flow J 0x39b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 039b 0x039b typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 0398 0398 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 0399 0399 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3a2 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 03a2 0x03a2 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 039a 039a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 039b 039b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 039c 039c fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 039d 0x039d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 039d 039d fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 039e 039e <default> 039f 039f fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a0 03a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03a1 03a1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03a2 03a2 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 03a3 0x03a3 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03a3 03a3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x3ab fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 03ab 0x03ab seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS 03a4 03a4 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x3aa fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 03aa 0x03aa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 03a5 03a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 06 Pop_stack+? typ_a_adr 02 GP02 typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 02 GP02 03a6 03a6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03a7 03a7 <default> 03a8 03a8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a9 03a9 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03aa 03aa fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR06:11 val_frame 6 03ab 03ab ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32b0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32b0 0x32b0 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e 03ac 03ac seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03ad ; -------------------------------------------------------------------------------------- 03ad ; Comes from: 03ad ; 3729 C from color 0x0000 03ad ; 372b C from color 0x0000 03ad ; -------------------------------------------------------------------------------------- 03ad 03ad fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 03ae 03ae ioc_fiubs 1 val ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 03af 03af ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 03b0 03b0 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03b1 03b1 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03b2 03b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3be fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 03be 0x03be seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03b3 03b3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 03b4 03b4 seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03b5 03b5 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03b9 0x03b9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03b6 03b6 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 03b7 03b7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 03b8 03b8 ioc_fiubs 0 fiu seq_en_micro 0 03b9 03b9 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x3c0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 03c0 0x03c0 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 03ba 03ba fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x470 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0470 0x0470 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 03bb 03bb ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x3b5 seq_br_type 1 Branch True seq_branch_adr 03b5 0x03b5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03bc 03bc fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bd 03bd seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03be 03be fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bf 03bf seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03c0 ; -------------------------------------------------------------------------------------- 03c0 ; Comes from: 03c0 ; 03b9 C #0x0 from color 0x0000 03c0 ; -------------------------------------------------------------------------------------- 03c0 03c0 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 03c1 03c1 fiu_load_tar 1 hold_tar; Flow J 0x3c4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 03c4 0x03c4 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 03c2 03c2 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c3 03c3 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c4 03c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 03c5 03c5 fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 03c6 0x03c6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 03c6 03c6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03c7 03c7 <default> 03c8 03c8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03c9 03c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03ca 03ca fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03cb 03cb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3a GP05 03cc 03cc seq_b_timing 1 Latch Condition; Flow C cc=True 0x3cf seq_br_type 5 Call True seq_branch_adr 03cf 0x03cf typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03cd 03cd fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x3d1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 03d1 0x03d1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03ce 03ce ioc_fiubs 2 typ ; Flow J 0x3d8 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03cf 03cf ioc_fiubs 2 typ typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03d0 03d0 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 03d1 ; -------------------------------------------------------------------------------------- 03d1 ; Comes from: 03d1 ; 03cd C False from color 0x0000 03d1 ; -------------------------------------------------------------------------------------- 03d1 03d1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d2 03d2 ioc_load_wdr 0 typ_b_adr 03 GP03 03d3 03d3 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 03d4 03d4 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03d5 03d5 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d6 03d6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 03d7 0x03d7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 03d7 03d7 seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 03d8 03d8 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d9 03d9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 03da 03da fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 03db 03db fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x409 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0409 0x0409 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 03dc 03dc fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x408 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0408 0x0408 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03dd 03dd ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 03de 03de fiu_load_tar 1 hold_tar; Flow J cc=False 0x3e1 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03e1 0x03e1 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 03df 03df seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 03e0 03e0 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 03e1 03e1 ioc_tvbs 2 fiu+val; Flow J cc=True 0x40c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 040c 0x040c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03e2 03e2 fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 03e3 03e3 seq_b_timing 0 Early Condition; Flow J cc=False 0x3de seq_br_type 0 Branch False seq_branch_adr 03de 0x03de seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 03e4 03e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 02 GP02 03e5 03e5 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 03e6 03e6 seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 val_a_adr 2f VR02:0f val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03e7 03e7 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 03e8 03e8 fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03e9 03e9 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3ec seq_br_type 0 Branch False seq_branch_adr 03ec 0x03ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ea 03ea seq_br_type 7 Unconditional Call; Flow C 0x33ba seq_branch_adr 33ba 0x33ba 03eb 03eb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ec 03ec fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 03ed 03ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 03ee 03ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 03ef 03ef fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP seq_random 3e ? typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03f0 03f0 seq_br_type 7 Unconditional Call; Flow C 0x410 seq_branch_adr 0410 0x0410 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 03f1 03f1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_random 39 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 03f2 03f2 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3fe fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 0 Branch False seq_branch_adr 03fe 0x03fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 03f3 03f3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x400 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 03f4 03f4 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 03f5 03f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x40a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 040a 0x040a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03f6 03f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x3f8 seq_br_type f Unconditional Case Call seq_branch_adr 03f8 0x03f8 seq_en_micro 0 03f7 03f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 03f8 ; -------------------------------------------------------------------------------------- 03f8 ; Comes from: 03f8 ; 03f6 C #0x0 from color 0x03f0 03f8 ; -------------------------------------------------------------------------------------- 03f8 03f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03f9 03f9 seq_br_type 3 Unconditional Branch; Flow J 0x3fc seq_branch_adr 03fc 0x03fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 03fa 03fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a1d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a1d 0x3a1d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fb 03fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3a1d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3a1d 0x3a1d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fc 03fc seq_br_type 1 Branch True; Flow J cc=True 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03fd 03fd seq_br_type 3 Unconditional Branch; Flow J 0x32ac seq_branch_adr 32ac 0x32ac 03fe 03fe fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3ff fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 03f4 0x03f4 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 03ff 03ff ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2f TR12:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 0400 0400 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0401 0401 ioc_load_wdr 0 ; Flow J 0x405 seq_br_type 3 Unconditional Branch seq_branch_adr 0405 0x0405 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0402 0402 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0403 0403 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x405 seq_br_type 0 Branch False seq_branch_adr 0405 0x0405 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0404 0404 fiu_load_tar 1 hold_tar; Flow R cc=False ; Flow J cc=True 0x3f5 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0405 0405 ioc_adrbs 3 seq ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0406 0406 ioc_fiubs 2 typ ; Flow J cc=True 0x402 seq_br_type 1 Branch True seq_branch_adr 0402 0x0402 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0407 0407 seq_br_type 3 Unconditional Branch; Flow J 0x402 seq_branch_adr 0402 0x0402 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 0408 0408 ioc_tvbs 2 fiu+val; Flow J 0x3e4 seq_br_type 3 Unconditional Branch seq_branch_adr 03e4 0x03e4 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0409 ; -------------------------------------------------------------------------------------- 0409 ; Comes from: 0409 ; 03db C True from color 0x0000 0409 ; -------------------------------------------------------------------------------------- 0409 0409 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 040a ; -------------------------------------------------------------------------------------- 040a ; Comes from: 040a ; 03f5 C True from color 0x03f0 040a ; -------------------------------------------------------------------------------------- 040a 040a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 040b 0x040b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 040b 040b seq_br_type a Unconditional Return; Flow R typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 040c 040c fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 1 INC_LOOP_COUNTER 040d 040d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 040e 040e fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x40d ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 040d 0x040d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 040f 040f seq_br_type 3 Unconditional Branch; Flow J 0x3e6 seq_branch_adr 03e6 0x03e6 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0410 ; -------------------------------------------------------------------------------------- 0410 ; Comes from: 0410 ; 03f0 C from color 0x03f0 0410 ; -------------------------------------------------------------------------------------- 0410 0410 ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0411 0411 seq_br_type a Unconditional Return; Flow R typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0412 0412 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_b_adr 08 GP08 0413 0413 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x414 fiu_mem_start 3 start-wr fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0417 0x0417 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR08:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0414 0414 ioc_load_wdr 0 ; Flow J cc=True 0x416 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0416 0x0416 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 0415 0415 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0416 0416 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0417 0417 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42c fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 042c 0x042c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 0418 0418 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0419 0419 seq_br_type 3 Unconditional Branch; Flow J 0x41b seq_branch_adr 041b 0x041b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 041a 041a seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 041b 041b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 13 LOOP_REG typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 13 LOOP_REG 041c 041c ioc_tvbs 2 fiu+val; Flow J cc=True 0x41a seq_br_type 1 Branch True seq_branch_adr 041a 0x041a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 041d 041d seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 05 GP05 val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 041e 041e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 041f 041f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0420 0420 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR12:18 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0421 0421 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 0422 0422 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 02 GP02 0423 0423 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 05 GP05 val_b_adr 08 GP08 0424 0424 fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 0425 0425 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 08 GP08 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0426 0426 seq_br_type 2 Push (branch address); Flow J 0x427 seq_branch_adr 042d 0x042d val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0427 0427 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6b4 seq_br_type 0 Branch False seq_branch_adr 06b4 0x06b4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0428 0428 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0429 0429 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 042a 042a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR11:0f typ_frame 11 042b 042b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a1d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a1d 0x3a1d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 042c 042c ioc_tvbs 2 fiu+val; Flow J 0x41d seq_br_type 3 Unconditional Branch seq_branch_adr 041d 0x041d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 042d 042d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 042e 042e seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 042f 042f fiu_mem_start 2 start-rd; Flow C cc=False 0x49e ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 049e 0x049e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0430 0430 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x46a seq_br_type 1 Branch True seq_branch_adr 046a 0x046a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 08 GP08 0431 0431 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x432 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 044b 0x044b seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0432 0432 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 1e A_AND_B typ_b_adr 21 TR07:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0433 0433 fiu_tivi_src c mar_0xc; Flow J cc=True 0x436 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0436 0x0436 0434 0434 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame e val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0435 0435 fiu_mem_start 2 start-rd; Flow J 0x43c ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 043c 0x043c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 0436 0436 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 0437 0437 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0438 0438 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x49c fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 049c 0x049c seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0439 0439 fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 043a 043a fiu_mem_start 2 start-rd; Flow J cc=False 0x43c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 043c 0x043c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 043b 043b seq_br_type 3 Unconditional Branch; Flow J 0x49c seq_branch_adr 049c 0x049c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 043c 043c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x46e fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 046e 0x046e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 20 VR02:00 val_frame 2 043d 043d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 043e 043e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 043f 043f fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0440 0440 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22c5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22c5 0x22c5 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0441 0441 ioc_fiubs 1 val ; Flow C 0x22c5 seq_br_type 7 Unconditional Call seq_branch_adr 22c5 0x22c5 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 0442 0442 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0443 0443 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 0444 0444 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 0445 0445 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 0446 0446 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0447 0447 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0448 0448 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0449 0449 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 044a 044a seq_br_type 3 Unconditional Branch; Flow J 0x450 seq_branch_adr 0450 0x0450 044b 044b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 044c 044c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 044d 044d fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 044e 044e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 044f 044f ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0450 0450 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x456 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0456 0x0456 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0451 0451 <default> 0452 0452 ioc_load_wdr 0 ; Flow J cc=True 0x4a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04a7 0x04a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 0453 0453 fiu_mem_start 3 start-wr; Flow C cc=True 0x460 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0460 0x0460 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP 0454 0454 <default> 0455 0455 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x451 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0451 0x0451 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0456 0456 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 0457 0457 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 02 GP02 typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN 0458 0458 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 0459 0459 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 02 GP02 val_a_adr 01 GP01 val_b_adr 02 GP02 045a 045a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR01:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 045b 045b ioc_load_wdr 0 ; Flow J 0x45c seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 05 GP05 045c 045c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 3e VR11:1e val_frame 11 045d 045d fiu_mem_start 3 start-wr; Flow J cc=True 0x461 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0461 0x0461 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 045e 045e ioc_load_wdr 0 ; Flow C 0x3371 seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 045f 045f fiu_mem_start 2 start-rd; Flow J 0x4a0 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0460 0460 seq_br_type 3 Unconditional Branch; Flow J 0x2a82 seq_branch_adr 2a82 0x2a82 0461 0461 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 0462 0462 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 2a TR02:0a typ_b_adr 20 TR02:00 typ_frame 2 0463 0463 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3371 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0464 0464 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR02:04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0465 0465 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A 0466 0466 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x469 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0469 0x0469 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 07 GP07 typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 0467 0467 ioc_fiubs 1 val ; Flow C 0x56b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b typ_a_adr 3e TR17:1e typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0468 0468 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 0469 ; -------------------------------------------------------------------------------------- 0469 ; Comes from: 0469 ; 0466 C True from color 0x0000 0469 ; -------------------------------------------------------------------------------------- 0469 0469 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 3e TR17:1e typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 046a 046a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_random 02 ? typ_a_adr 20 TR05:00 typ_csa_cntl 1 START_POP_DOWN typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 046b 046b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 046c 046c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 046d 046d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 046e 046e fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 046f 046f seq_br_type 7 Unconditional Call; Flow C 0x32a3 seq_branch_adr 32a3 0x32a3 0470 0470 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0471 0471 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x472 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0483 0x0483 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0472 0472 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 0473 0473 fiu_mem_start 2 start-rd; Flow J cc=False 0x4a6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 0474 0474 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0475 0475 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0476 0476 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 0477 0477 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0478 0478 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22c5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22c5 0x22c5 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0479 0479 ioc_fiubs 1 val ; Flow C 0x22c5 seq_br_type 7 Unconditional Call seq_branch_adr 22c5 0x22c5 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 047a 047a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 047b 047b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_b_adr 39 VR02:19 val_frame 2 047c 047c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 047d 047d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 047e 047e fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x4a6 fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 047f 047f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0480 0480 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0481 0481 ioc_fiubs 1 val ; Flow J cc=False 0x489 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0489 0x0489 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 0482 0482 seq_br_type 3 Unconditional Branch; Flow J 0x48d seq_branch_adr 048d 0x048d 0483 0483 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0484 0484 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 0485 0485 seq_en_micro 0 0486 0486 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 0487 0487 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 0488 0488 ioc_fiubs 0 fiu ; Flow J cc=True 0x48d ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 048d 0x048d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0489 0489 seq_br_type 3 Unconditional Branch; Flow J 0x48b seq_branch_adr 048b 0x048b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 048a 048a <default> 048b 048b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 13 LOOP_REG typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame f typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_b_adr 13 LOOP_REG 048c 048c seq_br_type 1 Branch True; Flow J cc=True 0x48a seq_branch_adr 048a 0x048a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 048d 048d fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 048e 048e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 02 GP02 val_a_adr 20 VR02:00 val_b_adr 02 GP02 val_frame 2 048f 048f fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 0490 0490 ioc_load_wdr 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0491 0491 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0492 0x0492 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0492 0492 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0493 0493 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0494 0494 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0495 0495 seq_br_type 4 Call False; Flow C cc=False 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_frame e 0496 0496 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 0497 0497 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 7 0498 0498 seq_br_type 5 Call True; Flow C cc=True 0x32ac seq_branch_adr 32ac 0x32ac seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 09 GP09 0499 0499 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 049a 049a fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049b 049b seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049c 049c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049d 049d seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049e 049e fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 049f 049f ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 04a0 04a0 <default> 04a1 04a1 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 04a2 04a2 fiu_mem_start 3 start-wr typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 04a3 04a3 ioc_load_wdr 0 04a4 04a4 fiu_tivi_src c mar_0xc; Flow C 0x3b71 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 04a5 04a5 seq_br_type a Unconditional Return; Flow R 04a6 04a6 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 04a7 04a7 seq_br_type 7 Unconditional Call; Flow C 0x49a seq_branch_adr 049a 0x049a 04a8 ; -------------------------------------------------------------------------------------- 04a8 ; 0x03c7 Complete_Type Access,By_Defining 04a8 ; -------------------------------------------------------------------------------------- 04a8 MACRO_Complete_Type_Access,By_Defining: 04a8 04a8 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04a8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04a9 04a9 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04aa 04aa fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 3d TR07:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 04ab 04ab fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x4ac fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32a7 0x32a7 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 2a TR09:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ac 04ac fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x3277 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ad 04ad fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a5 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 04ae 04ae fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x4af ; Flow J cc=#0x0 0x4af fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 04af 0x04af seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 04af 04af seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b0 04b0 fiu_load_tar 1 hold_tar; Flow J 0x4b3 fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04b3 0x04b3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b1 04b1 fiu_load_var 1 hold_var; Flow J 0x4cc fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04cc 0x04cc typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b2 04b2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b3 04b3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x4b4 ; Flow J cc=#0x0 0x4b8 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 04b8 0x04b8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04b4 04b4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04b5 04b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_random 02 ? typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04b6 04b6 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04b7 04b7 ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 04b8 04b8 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04b9 04b9 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04ba 04ba ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04bb 04bb seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 04bc 04bc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bd 04bd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04be 04be seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bf 04bf seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 04c0 04c0 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c1 04c1 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c2 04c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c3 04c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c4 04c4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c5 04c5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c6 04c6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c7 04c7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c8 04c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 0 PASS_A 04c9 04c9 fiu_fill_mode_src 0 ; Flow C 0x34fb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fb 0x34fb seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 04ca 04ca ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cb 04cb ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04cc 04cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x4cf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 04cf 0x04cf seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 04cd 04cd fiu_fill_mode_src 0 ; Flow C 0x34fb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fb 0x34fb seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04ce 04ce ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cf ; -------------------------------------------------------------------------------------- 04cf ; Comes from: 04cf ; 04cc C True from color 0x0000 04cf ; -------------------------------------------------------------------------------------- 04cf 04cf seq_br_type a Unconditional Return; Flow R typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 04d0 04d0 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x4d4 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 04d4 0x04d4 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04d1 04d1 fiu_mem_start a start_continue_if_false; Flow C cc=True 0x32a5 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04d2 04d2 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 04d3 04d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 04d4 04d4 seq_br_type 3 Unconditional Branch; Flow J 0x4d0 seq_branch_adr 04d0 0x04d0 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 04d5 04d5 <halt> ; Flow R 04d6 ; -------------------------------------------------------------------------------------- 04d6 ; 0x03c6 Complete_Type Access,By_Renaming 04d6 ; -------------------------------------------------------------------------------------- 04d6 MACRO_Complete_Type_Access,By_Renaming: 04d6 04d6 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 04d6 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04d7 04d7 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04d8 04d8 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04d9 04d9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04da 04da fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 04db 04db fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04dc 04dc fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04dd 04dd fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04de 04de fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04df 04df fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 04e0 04e0 fiu_mem_start 3 start-wr; Flow C cc=True 0x32a7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 04e1 04e1 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04e2 04e2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04e3 04e3 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 04e4 ; -------------------------------------------------------------------------------------- 04e4 ; 0x03c5 Complete_Type Access,By_Constraining 04e4 ; -------------------------------------------------------------------------------------- 04e4 MACRO_Complete_Type_Access,By_Constraining: 04e4 04e4 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04e4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04e5 04e5 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e6 04e6 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04e7 04e7 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04e8 04e8 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e9 04e9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04ea 04ea fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04eb 04eb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04ec 04ec fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04ed 04ed fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 04ee 04ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 val_c_adr 3e GP01 04ef 04ef fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a7 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 04f0 04f0 ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x4f5 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 04f5 0x04f5 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 04f1 04f1 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 04f2 04f2 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04f3 04f3 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 04f4 04f4 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 04f5 ; -------------------------------------------------------------------------------------- 04f5 ; Comes from: 04f5 ; 04f0 C #0x0 from color 0x0000 04f5 ; -------------------------------------------------------------------------------------- 04f5 04f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f6 04f6 fiu_mem_start 2 start-rd; Flow J 0x4fd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 04fd 0x04fd typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 04f7 04f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f8 04f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f9 04f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04fa 04fa seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fb 04fb seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fc 04fc fiu_mem_start 2 start-rd; Flow J 0x509 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0509 0x0509 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 04fd 04fd <default> 04fe 04fe fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 04ff 04ff ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0500 0500 fiu_mem_start 2 start-rd; Flow J 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3242 0x3242 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0501 0501 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 0502 0502 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0503 0x0503 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 01 GP01 0503 0503 fiu_mem_start 2 start-rd; Flow C 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3242 0x3242 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0504 0504 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 0505 0505 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 0506 0506 seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0507 0507 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0508 0x0508 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 0508 0508 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 0509 0509 <default> 050a 050a fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x501 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0501 0x0501 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 050b 050b fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 050c 050c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 050d 050d seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 050e ; -------------------------------------------------------------------------------------- 050e ; 0x03c4 Complete_Type Access,By_Component_Completion 050e ; -------------------------------------------------------------------------------------- 050e MACRO_Complete_Type_Access,By_Component_Completion: 050e 050e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 050e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 050f 050f fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0510 0510 fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0511 0511 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x4d3 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04d3 0x04d3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0512 0512 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 39 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0513 0513 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3277 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0514 0514 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x516 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0516 0x0516 seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0515 0515 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 0516 ; -------------------------------------------------------------------------------------- 0516 ; Comes from: 0516 ; 0514 C #0x0 from color 0x0000 0516 ; -------------------------------------------------------------------------------------- 0516 0516 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0517 0517 ioc_tvbs 1 typ+fiu; Flow J 0x51a seq_br_type 3 Unconditional Branch seq_branch_adr 051a 0x051a val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0518 0518 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0519 0519 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 051a 051a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x51f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 051f 0x051f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 02 GP02 typ_b_adr 10 TOP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 051b 051b fiu_fill_mode_src 0 ; Flow C 0x34fb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fb 0x34fb seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 051c 051c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x526 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_a_adr 02 GP02 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA 051d 051d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 051e 051e ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle val_b_adr 02 GP02 051f 051f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0520 0520 fiu_mem_start 3 start-wr; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0521 0521 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 0522 ; -------------------------------------------------------------------------------------- 0522 ; 0x0000 Action Illegal,>R 0522 ; -------------------------------------------------------------------------------------- 0522 MACRO_Action_Illegal,>R: 0522 0522 dispatch_brk_class 0 ; Flow C cc=True 0x68d dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0522 seq_br_type 5 Call True seq_branch_adr 068d 0x068d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0523 0523 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32ab seq_br_type 1 Branch True seq_branch_adr 32ab 0x32ab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0524 0524 seq_br_type 3 Unconditional Branch; Flow J 0x526 seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0525 0525 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 typ_csa_cntl 2 PUSH_CSA 0526 ; -------------------------------------------------------------------------------------- 0526 ; 0x0008 Action Idle 0526 ; -------------------------------------------------------------------------------------- 0526 MACRO_Action_Idle: 0526 0526 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0526 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0527 0527 <halt> ; Flow R 0528 ; -------------------------------------------------------------------------------------- 0528 ; 0x00c4 Action Make_Default 0528 ; -------------------------------------------------------------------------------------- 0528 MACRO_Action_Make_Default: 0528 0528 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0528 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 37 TR07:17 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0529 ; -------------------------------------------------------------------------------------- 0529 ; Comes from: 0529 ; 052d C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 052f C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0531 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0533 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0535 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0537 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 053a C from color MACRO_Pop_Control_Pop_Count_7 0529 ; -------------------------------------------------------------------------------------- 0529 0529 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 052a 0x052a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 052a 052a seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 052b 0x052b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 10 052b 052b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x525 seq_br_type 9 Return False seq_branch_adr 0525 0x0525 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 18 052c ; -------------------------------------------------------------------------------------- 052c ; 0x00d7 Pop_Control Pop_Count_7 052c ; -------------------------------------------------------------------------------------- 052c MACRO_Pop_Control_Pop_Count_7: 052c 052c dispatch_brk_class 3 ; Flow J cc=False 0x52e dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 052c seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 052e MACRO_Pop_Control_Pop_Count_6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052d 052d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 052e ; -------------------------------------------------------------------------------------- 052e ; 0x00d6 Pop_Control Pop_Count_6 052e ; -------------------------------------------------------------------------------------- 052e MACRO_Pop_Control_Pop_Count_6: 052e 052e dispatch_brk_class 3 ; Flow J cc=False 0x530 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 052e seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0530 MACRO_Pop_Control_Pop_Count_5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052f 052f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0530 ; -------------------------------------------------------------------------------------- 0530 ; 0x00d5 Pop_Control Pop_Count_5 0530 ; -------------------------------------------------------------------------------------- 0530 MACRO_Pop_Control_Pop_Count_5: 0530 0530 dispatch_brk_class 3 ; Flow J cc=False 0x532 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 0530 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0532 MACRO_Pop_Control_Pop_Count_4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0531 0531 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0532 ; -------------------------------------------------------------------------------------- 0532 ; 0x00d4 Pop_Control Pop_Count_4 0532 ; -------------------------------------------------------------------------------------- 0532 MACRO_Pop_Control_Pop_Count_4: 0532 0532 dispatch_brk_class 3 ; Flow J cc=False 0x534 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 0532 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0534 MACRO_Pop_Control_Pop_Count_3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0533 0533 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0534 ; -------------------------------------------------------------------------------------- 0534 ; 0x00d3 Pop_Control Pop_Count_3 0534 ; -------------------------------------------------------------------------------------- 0534 MACRO_Pop_Control_Pop_Count_3: 0534 0534 dispatch_brk_class 3 ; Flow J cc=False 0x536 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0534 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0536 MACRO_Pop_Control_Pop_Count_2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0535 0535 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0536 ; -------------------------------------------------------------------------------------- 0536 ; 0x00d2 Pop_Control Pop_Count_2 0536 ; -------------------------------------------------------------------------------------- 0536 MACRO_Pop_Control_Pop_Count_2: 0536 0536 dispatch_brk_class 3 ; Flow J cc=False 0x538 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0536 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0538 MACRO_Pop_Control_Pop_Count_1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0537 0537 seq_br_type 5 Call True; Flow C cc=True 0x529 seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0538 ; -------------------------------------------------------------------------------------- 0538 ; 0x00d1 Pop_Control Pop_Count_1 0538 ; -------------------------------------------------------------------------------------- 0538 MACRO_Pop_Control_Pop_Count_1: 0538 0538 dispatch_brk_class 3 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0538 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0539 0x0539 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0539 0539 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053a 0x053a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 11 TOP + 1 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 053a 053a seq_br_type 7 Unconditional Call; Flow C 0x529 seq_branch_adr 0529 0x0529 053b 053b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 053c ; -------------------------------------------------------------------------------------- 053c ; 0x00d0 Action Swap_Control 053c ; -------------------------------------------------------------------------------------- 053c MACRO_Action_Swap_Control: 053c 053c dispatch_brk_class 3 ; Flow J cc=True 0x53f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 053c ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 053f 0x053f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 053d 053d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053e 0x053e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 053e 053e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 053f 053f seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 typ_c_adr 2f TOP val_c_adr 2f TOP 0540 ; -------------------------------------------------------------------------------------- 0540 ; 0x00cd Action Spare6_Action 0540 ; -------------------------------------------------------------------------------------- 0540 MACRO_Action_Spare6_Action: 0540 0540 dispatch_brk_class 3 ; Flow J cc=True 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0540 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 val_b_adr 10 TOP 0541 0541 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0542 0x0542 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0542 0542 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0543 0543 <halt> ; Flow R 0544 ; -------------------------------------------------------------------------------------- 0544 ; 0x00cf Action Mark_Auxiliary 0544 ; -------------------------------------------------------------------------------------- 0544 MACRO_Action_Mark_Auxiliary: 0544 0544 dispatch_brk_class 3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0544 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR02:16 val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0545 0545 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_alu_func 1b A_OR_B typ_b_adr 21 TR02:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0546 0546 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x54c fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 054c 0x054c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0547 0547 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 19 X_XOR_B typ_b_adr 31 TR11:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0548 0548 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0549 0x0549 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_frame 2 0549 0549 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 22 TR02:02 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 054a 054a fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 054b 054b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 054c 054c seq_br_type 3 Unconditional Branch; Flow J 0x548 seq_branch_adr 0548 0x0548 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR07:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 054d 054d <halt> ; Flow R 054e ; -------------------------------------------------------------------------------------- 054e ; 0x00ce Action Pop_Auxiliary 054e ; -------------------------------------------------------------------------------------- 054e MACRO_Action_Pop_Auxiliary: 054e 054e dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 054e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 054f 054f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 2 0550 0550 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x555 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0555 0x0555 typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0551 0551 ioc_load_wdr 0 ; Flow J cc=True 0x552 ; Flow J cc=#0x0 0x552 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0552 0x0552 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0552 0552 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0553 0553 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0554 0554 ioc_load_wdr 0 ; Flow J 0x552 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0552 0x0552 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 0555 0555 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0556 0x0556 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0556 0556 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0557 0557 <halt> ; Flow R 0558 ; -------------------------------------------------------------------------------------- 0558 ; 0x00c9 Action Pop_Auxiliary_Loop 0558 ; -------------------------------------------------------------------------------------- 0558 MACRO_Action_Pop_Auxiliary_Loop: 0558 0558 dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0558 fiu_len_fill_lit 64 zero-fill 0x24 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 10 TOP typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 0559 0559 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055a ; -------------------------------------------------------------------------------------- 055a ; 0x00c8 Action Pop_Auxiliary_Range 055a ; -------------------------------------------------------------------------------------- 055a MACRO_Action_Pop_Auxiliary_Range: 055a 055a dispatch_brk_class 3 ; Flow C cc=False 0x32a5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 055a fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 34 VR06:14 val_frame 6 055b 055b fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 055c 0x055c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 1f TOP - 1 typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055c 055c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU 055d 055d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 055e ; -------------------------------------------------------------------------------------- 055e ; 0x00ba Action Initiate_Delay 055e ; -------------------------------------------------------------------------------------- 055e MACRO_Action_Initiate_Delay: 055e 055e dispatch_brk_class 3 ; Flow J cc=False 0x563 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 055e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type 0 Branch False seq_branch_adr 0563 0x0563 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 1d ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 055f 055f seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d seq_random 05 ? 0560 0560 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0561 0561 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x562 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 28 VR05:08 val_frame 5 0562 0562 ioc_tvbs 2 fiu+val; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0563 0563 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0564 ; -------------------------------------------------------------------------------------- 0564 ; Comes from: 0564 ; 0591 C from color 0x058d 0564 ; 05c2 C from color 0x05a7 0564 ; 05e7 C True from color 0x05db 0564 ; -------------------------------------------------------------------------------------- 0564 0564 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0565 0565 seq_en_micro 0 0566 0566 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0567 0567 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x3651 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3651 0x3651 seq_en_micro 0 val_c_adr 00 VR17:1f val_c_source 0 FIU_BUS val_frame 17 0568 0568 fiu_load_var 1 hold_var; Flow C cc=True 0x2a82 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 0569 0569 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 056a 0x056a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056a 056a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056b 056b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x599 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0599 0x0599 seq_en_micro 0 typ_c_adr 18 TR17:07 typ_c_source 0 FIU_BUS typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR17:07 val_c_mux_sel 2 ALU val_frame 17 056c 056c fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 056d 056d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 056e 056e fiu_len_fill_lit 71 zero-fill 0x31 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 07 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 23 VR17:03 val_frame 17 056f 056f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 07 fiu_rdata_src 0 rotator seq_en_micro 0 0570 0570 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x62e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0571 0571 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 0572 0572 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0573 0573 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR17:02 typ_frame 17 val_b_adr 22 VR17:02 val_frame 17 0574 0574 seq_br_type 0 Branch False; Flow J cc=False 0x58c seq_branch_adr 058c 0x058c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 0575 0575 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0576 0576 seq_en_micro 0 0577 0577 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0578 0578 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x58c seq_br_type 0 Branch False seq_branch_adr 058c 0x058c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0579 0579 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 057a 057a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 057b 057b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 057c 057c fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x581 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 057d 057d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x596 seq_br_type 1 Branch True seq_branch_adr 0596 0x0596 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 057e 057e fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 057f 057f fiu_mem_start 2 start-rd; Flow J cc=False 0x581 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0580 0580 fiu_load_tar 1 hold_tar; Flow J 0x57b fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 057b 0x057b seq_en_micro 0 typ_b_adr 24 TR17:04 typ_frame 17 0581 0581 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0582 0582 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_frame 17 0583 0583 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0584 0584 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0585 0585 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0586 0586 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_frame 17 0587 0587 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0588 0588 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0589 0589 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 058a 058a fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 058b ; -------------------------------------------------------------------------------------- 058b ; Comes from: 058b ; 368d C from color 0x0200 058b ; -------------------------------------------------------------------------------------- 058b 058b seq_br_type 1 Branch True; Flow J cc=True 0x575 seq_branch_adr 0575 0x0575 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 058c 058c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 058d 058d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 058e 058e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 058f 058f ioc_fiubs 2 typ ; Flow C cc=True 0x2a82 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR17:01 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 0590 0590 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 0591 0591 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 0592 0592 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 0593 0593 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 0594 ; -------------------------------------------------------------------------------------- 0594 ; Comes from: 0594 ; 0589 C False from color 0x0588 0594 ; 0590 C False from color 0x058d 0594 ; -------------------------------------------------------------------------------------- 0594 0594 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 0595 0595 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0596 0596 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0597 0597 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 0 PASS_A typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 0598 0598 seq_br_type 3 Unconditional Branch; Flow J 0x57e seq_branch_adr 057e 0x057e seq_en_micro 0 0599 ; -------------------------------------------------------------------------------------- 0599 ; Comes from: 0599 ; 056b C from color 0x0000 0599 ; -------------------------------------------------------------------------------------- 0599 0599 ioc_fiubs 1 val ; Flow C cc=True 0x5a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 05a4 0x05a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 21 VR17:01 val_alu_func 1e A_AND_B val_b_adr 3a VR17:1a val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 059a 059a seq_en_micro 0 val_a_adr 23 VR17:03 val_b_adr 39 VR17:19 val_frame 17 val_rand c START_MULTIPLY 059b 059b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 1 ALU >> 16 val_frame 17 val_m_b_src 2 Bits 32…47 059c 059c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 059d 059d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 059e 059e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 059f 059f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 05a0 05a0 seq_br_type 7 Unconditional Call; Flow C 0x3651 seq_branch_adr 3651 0x3651 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_rand e PRODUCT_LEFT_32 05a1 05a1 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 05a2 05a2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a3 05a3 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x5a6 seq_branch_adr 05a6 0x05a6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1d A_AND_NOT_B val_b_adr 3c VR17:1c val_frame 17 05a4 05a4 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 05a5 0x05a5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 21 VR17:01 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 05a5 05a5 seq_en_micro 0 seq_random 06 Pop_stack+? 05a6 05a6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3c VR17:1c val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a7 ; -------------------------------------------------------------------------------------- 05a7 ; Comes from: 05a7 ; 02f0 C from color 0x0000 05a7 ; 035f C from color 0x0000 05a7 ; 3701 C from color 0x36f5 05a7 ; 372c C from color 0x0000 05a7 ; 38b4 C from color 0x38b3 05a7 ; 3a9f C from color 0x0000 05a7 ; 3ac9 C from color 0x0000 05a7 ; 3acd C from color 0x0000 05a7 ; -------------------------------------------------------------------------------------- 05a7 05a7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 05a8 05a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 05a9 05a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 05aa 05aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x5bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 05bb 0x05bb seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 05ab 05ab fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 05ac 05ac seq_br_type 2 Push (branch address); Flow J 0x5ad seq_branch_adr 05b8 0x05b8 seq_en_micro 0 05ad 05ad seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 05ae 05ae seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 27 VR04:07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 05af 05af ioc_fiubs 2 typ ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 05b0 05b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 05b1 05b1 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b2 05b2 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 39 TR09:19 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b3 05b3 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 05b4 05b4 ioc_adrbs 2 typ ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 05b5 05b5 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 05b6 05b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 05b7 05b7 fiu_mem_start 2 start-rd; Flow J 0x3711 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 05b8 05b8 ioc_adrbs 1 val ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05b9 05b9 fiu_mem_start 2 start-rd; Flow J cc=False 0x5da ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05ba 05ba ioc_fiubs 1 val ; Flow J 0x5a9 seq_br_type 3 Unconditional Branch seq_branch_adr 05a9 0x05a9 seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 val_a_adr 06 GP06 05bb 05bb seq_br_type 0 Branch False; Flow J cc=False 0x5da seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05bc 05bc fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05bd 05bd seq_en_micro 0 05be 05be fiu_tivi_src 3 tar_frame; Flow C cc=False 0x62e ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05bf 05bf fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05c0 05c0 seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 20 TR17:00 typ_b_adr 23 TR17:03 typ_frame 17 05c1 05c1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x5c5 seq_br_type 0 Branch False seq_branch_adr 05c5 0x05c5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c2 05c2 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 05c3 05c3 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 05c4 05c4 seq_br_type 3 Unconditional Branch; Flow J 0x5d2 seq_branch_adr 05d2 0x05d2 seq_en_micro 0 05c5 05c5 seq_br_type 1 Branch True; Flow J cc=True 0x5d2 seq_branch_adr 05d2 0x05d2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05c6 05c6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 05c7 05c7 fiu_mem_start 11 start_tag_query; Flow J 0x5bd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 05bd 0x05bd seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 23 VR04:03 val_frame 4 05c8 05c8 ioc_load_wdr 0 ; Flow C cc=True 0x2a82 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 36 TR17:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c9 05c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x5da fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 24 TR17:04 typ_frame 17 val_a_adr 26 VR17:06 val_frame 17 05ca 05ca fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05cb 05cb fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05cc 05cc seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 24 TR17:04 typ_frame 17 05cd 05cd fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 1a TR17:05 typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1a VR17:05 val_frame 17 05ce 05ce fiu_mem_start e start_physical_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED 05cf 05cf ioc_load_wdr 0 ; Flow J 0x5d2 seq_br_type 3 Unconditional Branch seq_branch_adr 05d2 0x05d2 seq_en_micro 0 typ_b_adr 25 TR17:05 typ_frame 17 val_b_adr 25 VR17:05 val_frame 17 05d0 ; -------------------------------------------------------------------------------------- 05d0 ; Comes from: 05d0 ; 05ca C from color 0x05a7 05d0 ; 05d2 C from color 0x05a7 05d0 ; -------------------------------------------------------------------------------------- 05d0 05d0 seq_en_micro 0 05d1 05d1 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d2 05d2 fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05d3 05d3 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 3e VR17:1e val_frame 17 05d4 05d4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 23 TR17:03 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 37 VR17:17 val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d5 05d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 05d6 05d6 fiu_len_fill_lit 71 zero-fill 0x31 fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_source 0 FIU_BUS val_frame 17 05d7 05d7 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 21 TR17:01 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05d8 05d8 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 05d9 05d9 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 05da 05da fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? typ_b_adr 04 GP04 val_b_adr 04 GP04 05db ; -------------------------------------------------------------------------------------- 05db ; Comes from: 05db ; 0108 C from color ME_GP_TIME 05db ; -------------------------------------------------------------------------------------- 05db 05db seq_br_type 0 Branch False; Flow J cc=False 0x5e4 seq_branch_adr 05e4 0x05e4 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05dc 05dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5e5 seq_br_type 1 Branch True seq_branch_adr 05e5 0x05e5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 0 PASS_A val_frame 17 05dd ; -------------------------------------------------------------------------------------- 05dd ; Comes from: 05dd ; 0592 C from color 0x058d 05dd ; 05c3 C from color 0x05a7 05dd ; -------------------------------------------------------------------------------------- 05dd 05dd seq_br_type 1 Branch True; Flow J cc=True 0x5df seq_branch_adr 05df 0x05df seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR17:1b val_frame 17 05de 05de fiu_load_var 1 hold_var; Flow J 0x5e0 fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 05e0 0x05e0 seq_en_micro 0 val_b_adr 3f VR17:1f val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05df 05df fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 3b VR17:1b val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05e0 05e0 ioc_random e enable delay timer; Flow J cc=True 0x5e2 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 05e2 0x05e2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 05e1 05e1 fiu_load_var 1 hold_var; Flow J 0x364b fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 364b 0x364b seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e2 05e2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05e3 05e3 fiu_load_var 1 hold_var; Flow J 0x364b fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 364b 0x364b seq_en_micro 0 val_b_adr 23 VR17:03 val_frame 17 05e4 05e4 fiu_load_var 1 hold_var; Flow J 0x364b fiu_tivi_src 1 tar_val ioc_random f disable delay timer seq_br_type 3 Unconditional Branch seq_branch_adr 364b 0x364b seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e5 05e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_c_adr 1c TR17:03 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e6 05e6 seq_en_micro 0 05e7 05e7 ioc_fiubs 2 typ ; Flow C cc=True 0x564 ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 0564 0x0564 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 05e8 05e8 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e9 05e9 seq_en_micro 0 05ea 05ea ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 05eb 05eb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ec 05ec fiu_len_fill_lit 60 zero-fill 0x20 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ed 05ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 05ee 05ee fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 37 TR17:17 typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05ef 05ef seq_en_micro 0 05f0 05f0 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x62e ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f1 05f1 ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 05f2 05f2 seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05f3 05f3 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05f4 05f4 seq_b_timing 1 Latch Condition; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05f5 05f5 seq_br_type 3 Unconditional Branch; Flow J 0x5ee seq_branch_adr 05ee 0x05ee seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 05f6 05f6 fiu_mem_start 2 start-rd; Flow J 0x5f7 ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 05ff 0x05ff seq_en_micro 0 seq_random 02 ? typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 37 TR17:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05f7 05f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 05f8 05f8 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f9 05f9 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 05fa 05fa ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 03 GP03 typ_frame 1 val_b_adr 03 GP03 05fb 05fb fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05fc 05fc ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 0f GP0f 05fd 05fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x69b seq_br_type 4 Call False seq_branch_adr 069b 0x069b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05fe 05fe seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05ff 05ff fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0600 0600 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0601 0601 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x62e fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0602 0602 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0603 0603 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0604 0604 fiu_mem_start 3 start-wr; Flow J cc=True 0x623 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0623 0x0623 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0605 0605 ioc_fiubs 2 typ ; Flow C 0x210 ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0606 0606 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x621 seq_br_type 1 Branch True seq_branch_adr 0621 0x0621 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 35 VR02:15 val_frame 2 0607 0607 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0608 0608 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 0609 0609 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 060a 060a fiu_mem_start 2 start-rd; Flow J 0x60b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 060b 0x060b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 060b 060b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 060c 060c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x611 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0611 0x0611 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 060d 060d fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x613 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0613 0x0613 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 060e 060e ioc_tvbs 2 fiu+val; Flow J cc=True 0x617 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0617 0x0617 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 060f 060f fiu_mem_start 3 start-wr; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0610 0610 ioc_load_wdr 0 ; Flow J 0x61b seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 0611 0611 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0612 0612 ioc_load_wdr 0 ; Flow J 0x61b ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0613 0613 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0614 0614 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 0615 0615 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0616 0616 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0617 0617 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0618 0618 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 0619 0619 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 061a 061a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 061b 061b fiu_mem_start 2 start-rd; Flow C 0x2abd ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2abd 0x2abd seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 061c 061c fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 061d 061d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x627 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0627 0x0627 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 061e 061e fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 061f 061f ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0620 0620 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0621 0621 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x622 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 0622 0622 ioc_tvbs 2 fiu+val; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0623 0623 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 0624 0624 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0625 0625 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0626 0626 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x603 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0603 0x0603 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0627 ; -------------------------------------------------------------------------------------- 0627 ; Comes from: 0627 ; 061d C True from color 0x0000 0627 ; -------------------------------------------------------------------------------------- 0627 0627 ioc_adrbs 1 val ; Flow C 0x3b71 seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0628 0628 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0629 0629 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 062a ; -------------------------------------------------------------------------------------- 062a ; Comes from: 062a ; 05f1 C from color 0x05ec 062a ; 05fc C from color 0x05fb 062a ; -------------------------------------------------------------------------------------- 062a 062a fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 062b 062b seq_en_micro 0 062c 062c seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062d 062d seq_br_type 3 Unconditional Branch; Flow J 0x6bd seq_branch_adr 06bd 0x06bd seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 062e ; -------------------------------------------------------------------------------------- 062e ; Comes from: 062e ; 0570 C False from color 0x0000 062e ; 05be C False from color 0x05a7 062e ; 05f0 C False from color 0x05ec 062e ; 0601 C False from color 0x05fb 062e ; -------------------------------------------------------------------------------------- 062e 062e seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062f 062f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x632 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 0632 0x0632 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0630 0630 ioc_fiubs 0 fiu typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0631 0631 seq_br_type 3 Unconditional Branch; Flow J 0x632 seq_branch_adr 0632 0x0632 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0632 0632 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 0633 0633 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x634 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0637 0x0637 seq_int_reads 6 CONTROL TOP 0634 0634 fiu_mem_start 2 start-rd; Flow C 0x3340 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3340 0x3340 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0635 0635 fiu_load_var 1 hold_var; Flow J cc=True 0x636 ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0636 0636 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0652 0x0652 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? 0637 0637 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 0638 0638 seq_br_type 2 Push (branch address); Flow J 0x639 seq_branch_adr 0637 0x0637 0639 0639 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0652 0x0652 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 063a 063a fiu_load_oreg 1 hold_oreg; Flow C 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335a 0x335a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 063b 063b fiu_load_var 1 hold_var; Flow J cc=True 0x63c ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063c 063c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063d 063d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063e 063e ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 063f 063f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x640 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0640 0x0640 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0640 0640 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0641 0641 ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0642 0642 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0643 0643 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0644 0x0644 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR08:0c typ_frame 8 val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0644 0644 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 42 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 0645 0645 ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0646 0646 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 0647 0647 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 0648 0648 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA 0649 0649 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x64b fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 064b 0x064b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064a 064a fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064b 064b fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 064c 064c fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064d 064d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x64e fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0646 0x0646 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064e 064e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 064f 064f ioc_fiubs 0 fiu ; Flow C 0x3a3e seq_br_type 7 Unconditional Call seq_branch_adr 3a3e 0x3a3e typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0650 0650 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 0651 0651 ioc_fiubs 0 fiu ; Flow J 0x3a3e seq_br_type 3 Unconditional Branch seq_branch_adr 3a3e 0x3a3e val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0652 0652 ioc_tvbs 1 typ+fiu val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0653 0653 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 0654 0654 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x656 seq_br_type 1 Branch True seq_branch_adr 0656 0x0656 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_frame 2 0655 0655 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x632 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0632 0x0632 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0656 0656 ioc_fiubs 2 typ ; Flow J cc=False 0x661 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 24 TR02:04 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0657 0657 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x3ad9 seq_br_type 4 Call False seq_branch_adr 3ad9 0x3ad9 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 24 TR02:04 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A 0658 0658 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x65c fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 065c 0x065c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 25 VR05:05 val_frame 5 0659 0659 ioc_tvbs 2 fiu+val; Flow J 0x65a seq_br_type 2 Push (branch address) seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065a 065a fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3371 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 065b 065b seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 065c 065c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 065d 065d ioc_tvbs 1 typ+fiu; Flow J cc=False 0x661 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 065e 065e seq_br_type 2 Push (branch address); Flow J 0x65f seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065f 065f fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3371 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0660 0660 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0661 0661 seq_br_type 7 Unconditional Call; Flow C 0x32b1 seq_branch_adr 32b1 0x32b1 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0662 0662 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0663 0663 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0664 0664 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 29 TR09:09 typ_frame 9 val_b_adr 39 VR02:19 val_frame 2 0665 0665 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 0666 0666 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0667 0667 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0668 0668 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_b_adr 0f GP0f 0669 0669 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 066a 066a fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x68a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 066b 066b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 066c 066c fiu_load_tar 1 hold_tar; Flow J cc=False 0x68a fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 066d 066d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x68a fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 066e 066e seq_br_type 0 Branch False; Flow J cc=False 0x68a seq_branch_adr 068a 0x068a seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 066f 066f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x674 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0674 0x0674 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 0670 0670 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x676 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0676 0x0676 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0671 0671 ioc_tvbs 2 fiu+val; Flow J cc=True 0x67a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 067a 0x067a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 0672 0672 fiu_mem_start 3 start-wr; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0673 0673 ioc_load_wdr 0 ; Flow J 0x67e seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e seq_random 02 ? 0674 0674 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val val_b_adr 39 VR02:19 val_frame 2 0675 0675 ioc_load_wdr 0 ; Flow J 0x67e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e val_b_adr 39 VR02:19 val_frame 2 0676 0676 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 0677 0677 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val 0678 0678 ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0679 0679 seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067a 067a fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 067b 067b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 067c 067c ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 067d 067d seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067e 067e fiu_mem_start 2 start-rd; Flow C 0x2abd ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2abd 0x2abd typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 067f 067f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 0680 0680 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x687 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0687 0x0687 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0681 0681 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0682 0682 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0683 0683 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0684 0684 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x685 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 2 Push (branch address) seq_branch_adr 0662 0x0662 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 0685 0685 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0686 0686 fiu_mem_start 3 start-wr; Flow J 0x3b4a ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0687 ; -------------------------------------------------------------------------------------- 0687 ; Comes from: 0687 ; 0680 C True from color 0x066a 0687 ; -------------------------------------------------------------------------------------- 0687 0687 ioc_adrbs 1 val ; Flow C 0x3b71 seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0688 0688 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0689 0689 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 068a 068a fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 068b 068b fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 068c 068c seq_br_type 3 Unconditional Branch; Flow J 0x680 seq_branch_adr 0680 0x0680 068d ; -------------------------------------------------------------------------------------- 068d ; Comes from: 068d ; 0340 C from color 0x033e 068d ; 05f3 C from color 0x05ec 068d ; 05fe C from color 0x05fb 068d ; 39ae C False from color 0x39ae 068d ; 39b0 C False from color 0x39ae 068d ; 3b6b C from color 0x0ba9 068d ; -------------------------------------------------------------------------------------- 068d 068d seq_br_type 7 Unconditional Call; Flow C 0x6a3 seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 068e 068e seq_b_timing 1 Latch Condition; Flow C cc=True 0x722 seq_br_type 5 Call True seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 068f 068f ioc_adrbs 2 typ ioc_random 14 clear cpu running seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0690 0690 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0691 0691 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0692 0692 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0693 0693 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0694 0694 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0695 0695 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0696 0696 ioc_fiubs 1 val seq_en_micro 0 0697 0697 ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0698 0698 seq_b_timing 1 Latch Condition; Flow C cc=False 0x72b seq_br_type 4 Call False seq_branch_adr 072b 0x072b seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0699 0699 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 069a 069a seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 069b ; -------------------------------------------------------------------------------------- 069b ; Comes from: 069b ; 042d C True from color 0x0000 069b ; 05f2 C True from color 0x05ec 069b ; 05fd C False from color 0x05fb 069b ; 3919 C True from color 0x0000 069b ; 3949 C True from color 0x0913 069b ; 3ae2 C from color 0x0000 069b ; -------------------------------------------------------------------------------------- 069b 069b seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d seq_en_micro 0 069c 069c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069d 069d fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x69e fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 06a1 0x06a1 seq_en_micro 0 069e 069e ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069f 069f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3371 seq_br_type 1 Branch True seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 06a0 06a0 seq_br_type 3 Unconditional Branch; Flow J 0x72e seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 06a1 06a1 ioc_adrbs 3 seq ; Flow C 0x6b7 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 06a2 06a2 seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 06a3 ; -------------------------------------------------------------------------------------- 06a3 ; Comes from: 06a3 ; 068d C from color 0x0000 06a3 ; 0697 C #0x0 from color 0x0695 06a3 ; 069e C #0x0 from color 0x0698 06a3 ; -------------------------------------------------------------------------------------- 06a3 06a3 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a4 0x06a4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a4 06a4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a5 0x06a5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a5 06a5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a6 0x06a6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a6 06a6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a7 0x06a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a7 06a7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a8 0x06a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a8 06a8 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a9 0x06a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a9 06a9 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06aa 0x06aa seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06aa 06aa seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ab 0x06ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ab 06ab seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ac 0x06ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ac 06ac seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ad 0x06ad seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ad 06ad seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ae 0x06ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ae 06ae seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06af 0x06af seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06af 06af seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b0 0x06b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b0 06b0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b1 0x06b1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b1 06b1 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b2 0x06b2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b2 06b2 seq_br_type a Unconditional Return; Flow R seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b3 06b3 seq_br_type a Unconditional Return; Flow R seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 seq_latch 1 06b4 ; -------------------------------------------------------------------------------------- 06b4 ; Comes from: 06b4 ; 3662 C from color 0x365e 06b4 ; 367e C from color 0x0200 06b4 ; 397b C from color 0x3972 06b4 ; 3994 C from color 0x398b 06b4 ; 3a28 C from color 0x3a28 06b4 ; -------------------------------------------------------------------------------------- 06b4 06b4 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b5 06b5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 06b6 06b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06b7 ; -------------------------------------------------------------------------------------- 06b7 ; Comes from: 06b7 ; 0699 C from color 0x0698 06b7 ; 06a1 C from color 0x06a1 06b7 ; 374c C from color 0x0000 06b7 ; 375c C from color 0x0000 06b7 ; 3788 C from color 0x0000 06b7 ; 3978 C from color 0x3972 06b7 ; 3b82 C from color 0x3b49 06b7 ; -------------------------------------------------------------------------------------- 06b7 06b7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b8 06b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 13 LOOP_REG typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06b9 06b9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06ba 06ba ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06bb 06bb fiu_tivi_src c mar_0xc; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 06bc 0x06bc seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 06bc 06bc seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06bd ; -------------------------------------------------------------------------------------- 06bd ; Comes from: 06bd ; 2efb C from color 0x2ee5 06bd ; 2eff C from color 0x2ee5 06bd ; 3a17 C from color 0x0000 06bd ; -------------------------------------------------------------------------------------- 06bd 06bd fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06be 06be fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06bf 06bf seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 06c0 ; -------------------------------------------------------------------------------------- 06c0 ; Comes from: 06c0 ; 0332 C from color 0x0000 06c0 ; 033f C from color 0x033e 06c0 ; 074d C from color 0x0203 06c0 ; 075e C from color 0x0000 06c0 ; -------------------------------------------------------------------------------------- 06c0 06c0 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06c1 06c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 13 LOOP_REG val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06c2 06c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c3 06c3 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06c4 06c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 13 LOOP_REG val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 06c5 06c5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06c6 06c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c7 06c7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 06c8 06c8 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06c9 0x06c9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06c9 06c9 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06ca 06ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 06cb 06cb ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 06cc 06cc fiu_tivi_src c mar_0xc; Flow C cc=False 0x20d ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06cd 06cd seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06ce 06ce seq_en_micro 0 06cf ; -------------------------------------------------------------------------------------- 06cf ; Comes from: 06cf ; 3709 C from color 0x0000 06cf ; 38bc C from color 0x38b3 06cf ; 38cb C from color 0x38b3 06cf ; 3a9c C from color 0x0000 06cf ; 3ac7 C from color 0x0000 06cf ; -------------------------------------------------------------------------------------- 06cf 06cf fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06d0 06d0 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR04:05 typ_frame 4 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 06d1 06d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 06d2 06d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x6e8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 06e8 0x06e8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06d3 06d3 fiu_mem_start 3 start-wr; Flow C 0x3b4e ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b4e 0x3b4e seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 06d4 06d4 seq_br_type 2 Push (branch address); Flow J 0x6d5 seq_branch_adr 06e0 0x06e0 seq_en_micro 0 06d5 06d5 seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 06d6 06d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 28 VR04:08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 06d7 06d7 ioc_fiubs 2 typ ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06d8 06d8 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 06d9 06d9 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06da 06da fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR09:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06db 06db ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 06dc 06dc ioc_adrbs 2 typ ; Flow C cc=False 0x20d seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 06dd 06dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 06de 06de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 06df 06df fiu_mem_start 2 start-rd; Flow J 0x3711 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 06e0 06e0 ioc_adrbs 1 val ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand a PASS_B_HIGH 06e1 06e1 fiu_mem_start 2 start-rd; Flow J cc=False 0x6e5 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 06e5 0x06e5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 06e2 06e2 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 06 GP06 06e3 06e3 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06e4 06e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x6d1 seq_br_type 1 Branch True seq_branch_adr 06d1 0x06d1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06e5 06e5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? 06e6 ; -------------------------------------------------------------------------------------- 06e6 ; Comes from: 06e6 ; 06e8 C from color 0x06d2 06e6 ; 06ed C from color 0x06d2 06e6 ; 0702 C from color 0x0000 06e6 ; -------------------------------------------------------------------------------------- 06e6 06e6 seq_en_micro 0 06e7 06e7 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 06e8 06e8 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 06e9 06e9 fiu_mem_start d start_physical_rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 06ea 06ea fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 06eb 06eb seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06ec ; -------------------------------------------------------------------------------------- 06ec ; Comes from: 06ec ; 3696 C from color 0x05a7 06ec ; -------------------------------------------------------------------------------------- 06ec 06ec seq_br_type 0 Branch False; Flow J cc=False 0x6f8 seq_branch_adr 06f8 0x06f8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 32 TR02:12 typ_frame 2 06ed 06ed fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 06ee 06ee fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 06ef 06ef ioc_fiubs 2 typ ; Flow J cc=False 0x6f5 seq_br_type 0 Branch False seq_branch_adr 06f5 0x06f5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 25 TR04:05 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 06f0 06f0 seq_br_type 7 Unconditional Call; Flow C 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 06f1 06f1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x6f8 seq_br_type 0 Branch False seq_branch_adr 06f8 0x06f8 seq_en_micro 0 06f2 06f2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06f3 0x06f3 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 2c TR04:0c typ_frame 4 val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f3 06f3 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f4 06f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06f5 06f5 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 06f6 0x06f6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f6 06f6 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f7 06f7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 06f8 06f8 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 typ_b_adr 25 TR04:05 typ_frame 4 06f9 06f9 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06fa 0x06fa seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06fa 06fa fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 val_a_adr 3d VR04:1d val_frame 4 06fb 06fb seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_en_micro 0 06fc ; -------------------------------------------------------------------------------------- 06fc ; Comes from: 06fc ; 06f8 C from color 0x06d2 06fc ; 06fa C from color 0x06d2 06fc ; -------------------------------------------------------------------------------------- 06fc 06fc seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fd 06fd fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fe 06fe fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06ff 06ff seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0700 0700 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 0701 0701 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0702 0x0702 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0702 0702 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 26 TR04:06 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0703 0703 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0704 0704 seq_br_type 0 Branch False; Flow J cc=False 0x706 seq_branch_adr 0706 0x0706 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_b_adr 25 TR04:05 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 0705 0705 seq_br_type 3 Unconditional Branch; Flow J 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0706 0706 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0707 0707 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 0708 0708 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 0 PASS_A val_b_adr 3a VR04:1a val_frame 4 0709 0709 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 070a 070a seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 070b ; -------------------------------------------------------------------------------------- 070b ; Comes from: 070b ; 06f0 C from color 0x06d2 070b ; -------------------------------------------------------------------------------------- 070b 070b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 070c 070c fiu_load_var 1 hold_var; Flow J cc=False 0x710 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0710 0x0710 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 19 TR04:06 typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_b_adr 29 VR04:09 val_frame 4 070d 070d seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 070e 070e fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 070f 070f seq_en_micro 0 0710 0710 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x716 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0716 0x0716 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 0711 0711 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0712 0712 ioc_fiubs 0 fiu ; Flow J cc=True 0x70b seq_br_type 1 Branch True seq_branch_adr 070b 0x070b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 25 TR04:05 typ_b_adr 26 TR04:06 typ_c_adr 1b TR04:04 typ_c_source 0 FIU_BUS typ_frame 4 0713 0713 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_c_adr 13 VR04:0c val_frame 4 0714 0714 fiu_mem_start e start_physical_wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR04:04 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR04:0d typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED 0715 0715 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 2c TR04:0c typ_frame 4 val_b_adr 2c VR04:0c val_frame 4 0716 0716 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0717 0717 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0718 0718 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 04 GP04 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0719 0719 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 071a 071a seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 071b 071b fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 30 GP0f val_c_source 0 FIU_BUS 071c 071c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 071d 071d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 071e 071e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 071f 071f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 14 ZEROS 0720 0720 seq_br_type 7 Unconditional Call; Flow C 0x707 seq_branch_adr 0707 0x0707 seq_en_micro 0 0721 0721 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0722 ; -------------------------------------------------------------------------------------- 0722 ; Comes from: 0722 ; 069a C from color 0x0698 0722 ; 06a2 C from color 0x06a1 0722 ; 074e C from color 0x0203 0722 ; -------------------------------------------------------------------------------------- 0722 0722 fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 2 typ ioc_random 13 set cpu running seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0723 0723 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x727 seq_br_type 1 Branch True seq_branch_adr 0727 0x0727 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 0724 0724 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0725 0725 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 0726 0726 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0727 0727 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0728 0728 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 0729 0729 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 072a 072a fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072b ; -------------------------------------------------------------------------------------- 072b ; Comes from: 072b ; 0698 C False from color 0x0698 072b ; -------------------------------------------------------------------------------------- 072b 072b fiu_mem_start 2 start-rd; Flow C 0x3392 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_random 14 clear cpu running ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 072c 072c seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 072d 072d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072e 072e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072f ; -------------------------------------------------------------------------------------- 072f ; Comes from: 072f ; 0725 C from color 0x0000 072f ; 0729 C from color 0x0000 072f ; -------------------------------------------------------------------------------------- 072f 072f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 25 TR08:05 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 0730 0730 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0731 0731 fiu_fill_mode_src 0 ; Flow J cc=True 0x733 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0733 0x0733 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 0732 0732 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 0733 0733 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 0734 0734 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x736 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0736 0x0736 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 23 VR02:03 val_frame 2 0735 0735 seq_b_timing 0 Early Condition; Flow J cc=True 0x736 ; Flow J cc=#0x0 0x0 seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0736 0736 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 0737 0737 seq_br_type 3 Unconditional Branch; Flow J 0x734 seq_branch_adr 0734 0x0734 seq_en_micro 0 0738 ; -------------------------------------------------------------------------------------- 0738 ; Comes from: 0738 ; 0724 C True from color 0x0000 0738 ; 0728 C True from color 0x0000 0738 ; 072c C True from color 0x0000 0738 ; -------------------------------------------------------------------------------------- 0738 0738 seq_br_type 7 Unconditional Call; Flow C 0x33ba seq_branch_adr 33ba 0x33ba seq_en_micro 0 seq_random 02 ? 0739 0739 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 073a 073a fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR06:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 073b 073b fiu_mem_start 3 start-wr; Flow J 0x74f seq_br_type 3 Unconditional Branch seq_branch_adr 074f 0x074f seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 28 VR08:08 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 073c 073c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 073d 073d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 073e 073e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 073f 073f seq_br_type 1 Branch True; Flow J cc=True 0x742 seq_branch_adr 0742 0x0742 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 5 DEC_A_MINUS_B val_b_adr 26 VR05:06 val_frame 5 0740 0740 seq_b_timing 0 Early Condition; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0741 0741 fiu_mem_start 2 start-rd; Flow J 0x744 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0744 0x0744 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0742 0742 seq_b_timing 0 Early Condition; Flow J cc=False 0x749 seq_br_type 0 Branch False seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0743 0743 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1 A_PLUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0744 0744 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 0745 0745 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0746 0746 ioc_load_wdr 0 ; Flow J 0x747 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 075d 0x075d seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0747 0747 seq_br_type 0 Branch False; Flow J cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0748 0748 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x756 seq_br_type 8 Return True seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0749 0749 seq_b_timing 1 Latch Condition; Flow C cc=False 0x756 seq_br_type 4 Call False seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 074a 074a seq_br_type 2 Push (branch address); Flow J 0x74b seq_branch_adr 074d 0x074d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 074b 074b fiu_load_tar 1 hold_tar; Flow J cc=True 0x338e fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 338e 0x338e seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 074c 074c ioc_random c enable slice timer; Flow J 0x72e seq_br_type 3 Unconditional Branch seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 074d 074d ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 074e 074e seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 074f 074f ioc_load_wdr 0 ; Flow J 0x750 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 074a 0x074a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f 0750 0750 seq_br_type 4 Call False; Flow C cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0751 0751 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x731 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 0752 0752 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x731 seq_br_type 0 Branch False seq_branch_adr 0731 0x0731 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 34 TR08:14 typ_frame 8 0753 0753 fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP 0754 0754 fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0755 0755 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x731 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0756 ; -------------------------------------------------------------------------------------- 0756 ; Comes from: 0756 ; 0749 C False from color 0x0000 0756 ; -------------------------------------------------------------------------------------- 0756 0756 seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d seq_en_micro 0 0757 0757 fiu_mem_start 2 start-rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 0758 0758 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0759 0759 ioc_tvbs 2 fiu+val; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 075a 0x075a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 075a 075a seq_en_micro 0 seq_random 06 Pop_stack+? 075b 075b fiu_load_tar 1 hold_tar; Flow J 0x75c fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 0717 0x0717 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 075c 075c ioc_adrbs 3 seq ; Flow J 0x338e ioc_random a clear slice event seq_br_type 3 Unconditional Branch seq_branch_adr 338e 0x338e seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 075d 075d fiu_load_tar 1 hold_tar; Flow C 0x338e fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_br_type 7 Unconditional Call seq_branch_adr 338e 0x338e seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL 075e 075e ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 075f 075f seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0760 0760 seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0761 0761 seq_br_type 2 Push (branch address); Flow J 0x762 seq_branch_adr 074d 0x074d seq_en_micro 0 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0762 0762 seq_br_type 3 Unconditional Branch; Flow J 0x74b seq_branch_adr 074b 0x074b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 0763 0763 fiu_load_tar 1 hold_tar; Flow C 0x364f fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 364f 0x364f seq_en_micro 0 typ_b_adr 3b TR12:1b typ_frame 12 0764 0764 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0765 0765 ioc_random c enable slice timer seq_en_micro 0 val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0766 0766 seq_br_type 3 Unconditional Branch; Flow J 0x329f seq_branch_adr 329f 0x329f seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0767 0767 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 19 VR04:06 val_c_source 0 FIU_BUS val_frame 4 0768 0768 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0769 0769 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 076a 076a fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR04:02 val_c_mux_sel 2 ALU val_frame 4 076b 076b seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 4 076c 076c ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_frame d val_c_adr 3c GP03 val_c_source 0 FIU_BUS 076d 076d seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 076e 076e seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 076f 076f seq_b_timing 0 Early Condition; Flow J cc=False 0x76d seq_br_type 0 Branch False seq_branch_adr 076d 0x076d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0770 0770 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 11 TR0d:0e typ_c_source 0 FIU_BUS typ_frame d val_a_adr 22 VR04:02 val_frame 4 0771 0771 seq_en_micro 0 typ_a_adr 26 TR0d:06 typ_alu_func 0 PASS_A typ_c_adr 17 TR0d:08 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 27 VR0d:07 val_alu_func 0 PASS_A val_c_adr 17 VR0d:08 val_c_mux_sel 2 ALU val_frame d 0772 0772 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 2b TR0d:0b typ_alu_func 0 PASS_A typ_c_adr 10 TR0d:0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2b VR0d:0b val_alu_func 0 PASS_A val_c_adr 10 VR0d:0f val_c_mux_sel 2 ALU val_frame d 0773 0773 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0774 0774 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 27 VR04:07 val_alu_func 0 PASS_A val_c_adr 18 VR04:07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0775 0775 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 28 VR04:08 val_alu_func 0 PASS_A val_c_adr 17 VR04:08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0776 0776 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0777 0777 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_random 02 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 25 VR04:05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0778 0778 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 26 VR04:06 val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 0779 0779 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x77c seq_br_type 1 Branch True seq_branch_adr 077c 0x077c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3b TR05:1b typ_frame 5 077a 077a fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 077b 077b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 077c 077c fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 077d 077d fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 077e 077e fiu_fill_mode_src 0 ; Flow J 0x77f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0782 0x0782 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 077f 077f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x791 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0780 0780 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 06 Pop_stack+? typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0781 0781 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 0782 0782 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0783 0783 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0784 0784 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 0785 0785 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0786 0786 <default> 0787 0787 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x78b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 078b 0x078b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0788 0788 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 0789 0789 <default> 078a 078a ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 078b 078b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 078c 078c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1a PASS_B 078d 078d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 078e 078e fiu_fill_mode_src 0 ; Flow J cc=False 0x791 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 078f 078f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0790 0790 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0791 0791 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0792 0792 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0793 0793 fiu_load_var 1 hold_var; Flow J 0x790 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0790 0x0790 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0794 0794 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 2b VR04:0b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 0795 0795 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 0796 0796 ioc_fiubs 2 typ typ_a_adr 2b TR04:0b typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0797 0797 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0798 0x0798 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 0798 0798 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0799 0799 seq_br_type 3 Unconditional Branch; Flow J 0x79b seq_branch_adr 079b 0x079b seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3d VR02:1d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 079a 079a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7a2 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07a2 0x07a2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 14 ZEROS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 079b 079b seq_br_type 1 Branch True; Flow J cc=True 0x79a seq_branch_adr 079a 0x079a seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 26 VR06:06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 079c 079c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x79a fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 079a 0x079a seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 079d 079d fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x79e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 079c 0x079c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 25 TR08:05 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 079e 079e fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 079f 079f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x7a1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 07a1 0x07a1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 07a0 07a0 ioc_tvbs 3 fiu+fiu; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 07a1 07a1 ioc_tvbs 3 fiu+fiu; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 07a2 07a2 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07a3 07a3 fiu_load_var 1 hold_var; Flow C 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 07ab 0x07ab seq_en_micro 0 typ_a_adr 37 TR04:17 typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07a4 07a4 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_frame 5 val_alu_func 1a PASS_B val_b_adr 37 VR04:17 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a5 07a5 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 0 PASS_A typ_frame 4 val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 07a6 07a6 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_frame 6 val_alu_func 1a PASS_B val_b_adr 38 VR04:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a7 07a7 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 08 TR04:17 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 14 ZEROS val_c_adr 08 VR04:17 val_c_source 0 FIU_BUS val_frame 4 07a8 07a8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR05:1e val_frame 5 07a9 07a9 fiu_fill_mode_src 0 ; Flow C 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 07b1 0x07b1 seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 07aa 07aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 07 TR04:18 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_c_adr 07 VR04:18 val_c_source 0 FIU_BUS val_frame 4 07ab ; -------------------------------------------------------------------------------------- 07ab ; Comes from: 07ab ; 07a3 C from color 0x07a3 07ab ; 07a4 C True from color 0x07a3 07ab ; 07a5 C True from color 0x07a3 07ab ; 07a6 C True from color 0x07a3 07ab ; -------------------------------------------------------------------------------------- 07ab 07ab fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 07ac 0x07ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 07ac 07ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07ad 07ad fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 07ae 07ae fiu_fill_mode_src 0 ; Flow C cc=True 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 07b1 0x07b1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 07af 07af fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 07b0 07b0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x7ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 07ab 0x07ab seq_en_micro 0 val_a_adr 03 GP03 val_b_adr 39 VR02:19 val_frame 2 07b1 ; -------------------------------------------------------------------------------------- 07b1 ; Comes from: 07b1 ; 07a9 C from color 0x07a3 07b1 ; 07ae C True from color 0x07ab 07b1 ; -------------------------------------------------------------------------------------- 07b1 07b1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 07b2 07b2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07b3 07b3 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07b4 ; -------------------------------------------------------------------------------------- 07b4 ; Comes from: 07b4 ; 0693 C from color 0x0693 07b4 ; 06b4 C from color 0x0000 07b4 ; 06bd C from color 0x062d 07b4 ; 06e9 C from color 0x06d2 07b4 ; 0757 C from color 0x0203 07b4 ; -------------------------------------------------------------------------------------- 07b4 07b4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 07b5 07b5 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 07b6 ; -------------------------------------------------------------------------------------- 07b6 ; Comes from: 07b6 ; 05ad C from color 0x05a7 07b6 ; 06d5 C from color 0x06d2 07b6 ; 361c C from color 0x0000 07b6 ; 3b69 C from color 0x0ba9 07b6 ; -------------------------------------------------------------------------------------- 07b6 07b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7b5 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07b5 0x07b5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07b7 07b7 seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 07b8 07b8 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 15 ? typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS 07b9 07b9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 21 TR02:01 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 07ba 07ba fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x7dd fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 07dd 0x07dd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_c_adr 34 GP0b val_frame 2 07bb 07bb seq_en_micro 0 typ_c_adr 32 GP0d val_c_adr 32 GP0d 07bc 07bc fiu_len_fill_lit 6f zero-fill 0x2f; Flow J cc=False 0x7bf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07bf 0x07bf seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c 07bd 07bd fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x364f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 364f 0x364f seq_en_micro 0 val_a_adr 0c GP0c val_b_adr 3c VR12:1c val_frame 12 07be 07be fiu_mem_start 3 start-wr seq_en_micro 0 07bf 07bf fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07c0 07c0 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0e GP0e val_b_adr 0e GP0e 07c1 07c1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_random 06 Pop_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07c2 07c2 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07c3 07c3 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 22 VR02:02 val_frame 2 07c4 07c4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR 07c5 07c5 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 07c6 07c6 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 07c7 07c7 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 07c8 07c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 07c9 07c9 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 05 GP05 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 05 GP05 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07ca 07ca fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 07cb 07cb fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 07cc 07cc fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 07cd 07cd fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 09 GP09 07ce 07ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x7d0 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d0 0x07d0 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 5b ? typ_a_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 07cf 07cf fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d0 07d0 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=False 0x7d2 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d2 0x07d2 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 21 VR0d:01 val_frame d 07d1 07d1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d2 07d2 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 0a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 17 LOOP_COUNTER val_b_adr 20 VR0d:00 val_frame d 07d3 07d3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0b GP0b val_b_adr 22 VR0d:02 val_frame d 07d4 07d4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR0d:03 val_frame d 07d5 07d5 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 07d6 07d6 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 24 TR02:04 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR02:04 val_frame 2 07d7 07d7 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07d8 07d8 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0b GP0b 07d9 07d9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR12:14 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 07da 07da fiu_mem_start a start_continue_if_false; Flow J cc=True 0x7dc ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07dc 0x07dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 14 BOT - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 07db 07db fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7db ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07db 0x07db seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 15 BOT typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 15 BOT val_rand 2 DEC_LOOP_COUNTER 07dc 07dc seq_br_type a Unconditional Return; Flow R seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 07dd 07dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 39 VR02:19 val_frame 2 07de 07de fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07df 07df fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e0 07e0 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e1 07e1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e2 07e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 07e3 07e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e4 07e4 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e5 07e5 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e6 07e6 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION 07e7 07e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x7bc fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 07bc 0x07bc seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07e8 07e8 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 07e9 07e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7e8 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07e8 0x07e8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ea 07ea fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7ed seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07ed 0x07ed seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_frame 3 typ_mar_cntl 6 INCREMENT_MAR 07eb 07eb ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ec 07ec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x80f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 080f 0x080f seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ed 07ed fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 07ee 07ee fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ef 07ef fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 25 TR02:05 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07f0 07f0 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 6 INCREMENT_MAR 07f1 07f1 fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 07f2 07f2 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 07f3 07f3 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07f4 07f4 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 07f5 07f5 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 07f6 07f6 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 07f7 07f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 07f8 07f8 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 07f9 07f9 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 07fa 07fa fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 07fb 07fb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 55 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 07fc 07fc fiu_len_fill_lit 4a zero-fill 0xa fiu_mem_start 4 continue fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07fd 07fd fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 07fe 07fe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 07ff 07ff fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0800 0800 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_mux_sel 2 ALU val_frame d 0801 0801 ioc_adrbs 1 val ; Flow J cc=True 0x802 ; Flow J cc=#0x0 0x802 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0802 0x0802 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_lex_adr 2 seq_random 14 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0802 0802 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0803 0803 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0804 0804 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0805 0805 seq_br_type 3 Unconditional Branch; Flow J 0x804 seq_branch_adr 0804 0x0804 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? 0806 0806 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 22 TR02:02 typ_b_adr 21 TR02:01 typ_c_adr 1b TR02:04 typ_frame 2 val_b_adr 25 VR02:05 val_c_adr 1b VR02:04 val_frame 2 0807 0807 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR11:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 11 val_rand a PASS_B_HIGH 0808 0808 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80c ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080c 0x080c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0e GP0e 0809 0809 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80b ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080b 0x080b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080a 080a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x80a ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 080a 0x080a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080b 080b fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080c 080c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080d 080d fiu_len_fill_lit 59 zero-fill 0x19 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 0d GP0d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 080e 080e fiu_len_fill_lit 49 zero-fill 0x9; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 1 ALU >> 16 080f ; -------------------------------------------------------------------------------------- 080f ; Comes from: 080f ; 07ec C from color 0x07e8 080f ; -------------------------------------------------------------------------------------- 080f 080f fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0810 0810 seq_en_micro 0 0811 0811 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x816 seq_br_type 1 Branch True seq_branch_adr 0816 0x0816 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0812 0812 fiu_mem_start 3 start-wr; Flow C 0x3651 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3651 0x3651 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0813 0813 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl b LOAD_MAR_DATA 0814 0814 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0815 0815 fiu_tivi_src 4 fiu_var; Flow R cc=True ; Flow J cc=False 0x211 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_b_adr 39 VR03:19 val_frame 3 0816 0816 fiu_mem_start 5 start_rd_if_true; Flow R cc=False ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0817 0x0817 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0817 0817 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0818 0x0818 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0818 0818 fiu_tivi_src 2 tar_fiu; Flow J 0x812 ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0812 0x0812 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0819 0819 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 081a 081a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 16 stage data register ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 081b 081b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20b fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b val_b_adr 0b GP0b 081c 081c fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 34 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 081d 081d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x81e ; Flow J cc=#0x0 0x81f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 081f 0x081f seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR00:05 val_a_adr 0b GP0b 081e 081e seq_br_type 7 Unconditional Call; Flow C 0x20c seq_branch_adr 020c 0x020c seq_en_micro 0 081f 081f seq_br_type 3 Unconditional Branch; Flow J 0x825 seq_branch_adr 0825 0x0825 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0820 0820 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x846 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0846 0x0846 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0821 0821 fiu_len_fill_lit 57 zero-fill 0x17; Flow J 0x871 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0871 0x0871 seq_en_micro 0 0822 0822 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x85d fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 085d 0x085d seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0823 0823 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x865 fiu_load_mdr 1 hold_mdr fiu_mem_start f start_physical_tag_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0865 0x0865 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0824 0824 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x86c fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 086c 0x086c seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0825 0825 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 1e TR19:01 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0826 0826 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 1e VR19:01 val_c_source 0 FIU_BUS val_frame 19 0827 0827 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x20c fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0828 0828 fiu_len_fill_lit 7c zero-fill 0x3c fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 1c TR19:03 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1c VR19:03 val_c_source 0 FIU_BUS val_frame 19 0829 0829 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 34 GP0b val_c_source 0 FIU_BUS 082a 082a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 1d TR19:02 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 23 VR19:03 val_alu_func 6 A_MINUS_B val_b_adr 0b GP0b val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 082b 082b fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 082c 082c seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 082d 082d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 082e 082e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x211 fiu_mem_start 4 continue fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_c_adr 3f GP00 082f 082f ioc_load_wdr 0 ; Flow J cc=True 0x830 ; Flow J cc=#0x0 0x830 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0830 0x0830 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0830 0830 fiu_vmux_sel 1 fill value; Flow J 0x834 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0834 0x0834 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 23 VR19:03 val_c_adr 1d VR19:02 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 0831 0831 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0832 0832 fiu_mem_start 11 start_tag_query; Flow J 0x836 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0836 0x0836 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR19:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame 19 0833 0833 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0834 0834 seq_en_micro 0 val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0835 0835 ioc_fiubs 2 typ ; Flow J 0x83e seq_br_type 3 Unconditional Branch seq_branch_adr 083e 0x083e seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0836 0836 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x834 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0834 0x0834 seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0837 0837 seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0838 0838 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x211 ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0839 0839 ioc_adrbs 1 val ; Flow C cc=True 0x2a82 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 083a 083a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 083b 083b fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 083c 083c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083d 083d ioc_fiubs 2 typ ; Flow J cc=True 0x839 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0839 0x0839 seq_en_micro 0 typ_a_adr 21 TR05:01 typ_b_adr 05 GP05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083e 083e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 083f 083f fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0840 0840 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0841 0841 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3711 seq_br_type 1 Branch True seq_branch_adr 3711 0x3711 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 2 0842 0842 seq_br_type 4 Call False; Flow C cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0843 0843 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3711 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3711 0x3711 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0844 0844 seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3e VR04:1e val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0845 0845 fiu_mem_start 2 start-rd; Flow J 0x3711 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0846 0846 fiu_load_oreg 1 hold_oreg fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 12 0847 0847 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x20c fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0848 0848 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20c fiu_mem_start 13 start_available_query fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 0849 0849 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20c fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR10:01 typ_frame 10 084a 084a seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 084b 084b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 084c 084c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 084d 084d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_frame 6 084e 084e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 31 VR02:11 val_frame 2 084f 084f fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0850 0850 fiu_tivi_src 2 tar_fiu; Flow C 0x8a5 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 08a5 0x08a5 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0851 0851 ioc_adrbs 1 val ; Flow C cc=True 0x2a82 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 0852 0852 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0853 0853 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0854 0854 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0855 0855 ioc_load_wdr 0 ; Flow J cc=False 0x851 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0851 0x0851 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 0856 0856 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0b GP0b val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0857 0857 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0858 0858 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b 0859 0859 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 32 VR02:12 val_frame 2 085a 085a fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 14 clear cpu running seq_en_micro 0 val_a_adr 14 ZEROS 085b 085b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 085c 085c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 085d 085d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_rand e CHECK_CLASS_SYSTEM_B 085e 085e ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 3a TR02:1a typ_frame 2 085f 085f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 13 LOOP_REG val_rand 1 INC_LOOP_COUNTER 0860 0860 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x85d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 085d 0x085d seq_en_micro 0 typ_a_adr 0b GP0b 0861 0861 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 typ_c_adr 34 GP0b 0862 0862 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0863 0863 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_b_adr 0b GP0b typ_frame 10 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0864 0864 fiu_tivi_src 4 fiu_var; Flow J 0x859 ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0859 0x0859 seq_en_micro 0 val_a_adr 0b GP0b val_c_adr 34 GP0b 0865 0865 fiu_mem_start 15 setup_tag_read fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0866 0866 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x868 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 0868 0x0868 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0867 0867 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x861 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs a fiu+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0868 0868 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x867 fiu_load_tar 1 hold_tar fiu_mem_start 15 setup_tag_read fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0867 0x0867 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 0869 0869 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 086a 086a fiu_mem_start f start_physical_tag_rd seq_en_micro 0 086b 086b fiu_mem_start 15 setup_tag_read; Flow J 0x867 seq_br_type 3 Unconditional Branch seq_branch_adr 0867 0x0867 seq_en_micro 0 086c 086c seq_br_type 3 Unconditional Branch; Flow J 0x86f seq_branch_adr 086f 0x086f seq_en_micro 0 086d 086d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 7 INC_A typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 0b GP0b 086e 086e ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x861 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 086f 086f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0870 0870 fiu_tivi_src c mar_0xc; Flow J 0x86d ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address seq_br_type 3 Unconditional Branch seq_branch_adr 086d 0x086d seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_rand d SET_PASS_PRIVACY_BIT 0871 0871 fiu_len_fill_lit 57 zero-fill 0x17 fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 32 TR02:12 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0872 0872 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20c seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_frame 3 0873 0873 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0874 0874 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 0875 0875 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0876 0876 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0877 0877 fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0878 0878 seq_b_timing 1 Latch Condition; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 05 VR03:1a val_c_mux_sel 2 ALU val_frame 3 0879 0879 ioc_fiubs 1 val ; Flow C 0xb90 seq_br_type 7 Unconditional Call seq_branch_adr 0b90 0x0b90 seq_en_micro 0 typ_c_adr 1b TR1b:04 typ_c_mux_sel 0 ALU typ_frame 1b typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR1b:04 val_c_mux_sel 2 ALU val_frame 1b val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 087a 087a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 087b 087b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 087c 087c ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 087d 087d typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 087e 087e typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 087f 087f typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 0880 0880 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0881 0881 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0882 0882 fiu_mem_start 2 start-rd; Flow J 0x3711 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0883 0883 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 14 ZEROS typ_b_adr 1e TOP - 2 typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 20 VR06:00 val_frame 6 0884 0884 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x888 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0888 0x0888 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0885 0885 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0886 0886 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x88c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 088c 0x088c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0887 0887 fiu_fill_mode_src 0 ; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0888 0888 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0889 0889 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 088a 088a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 088b 088b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088c 088c fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 088d 088d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088e 088e fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 33 VR03:13 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 3 088f 088f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR05:01 val_frame 5 0890 0890 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3e TR03:1e typ_alu_func 7 INC_A typ_c_adr 01 TR03:1e typ_c_mux_sel 0 ALU typ_frame 3 0891 0891 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 0892 0892 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR05:1b val_frame 5 0893 0893 ioc_load_wdr 0 ; Flow J cc=True 0x89c ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 089c 0x089c typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0894 0894 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0895 0895 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x211 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 0896 0896 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 0897 0897 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 05 GP05 0898 0898 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0899 0899 ioc_random 1e write ioc memory and increment address seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 06 GP06 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 089a 089a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 06 GP06 089b 089b ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x898 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0898 0x0898 seq_en_micro 0 089c 089c fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3f GP00 val_frame 3 val_rand c START_MULTIPLY 089d 089d seq_en_micro 0 typ_c_adr 3f GP00 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 089e 089e fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 089f 089f fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 05 GP05 08a0 08a0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address seq_en_micro 0 08a1 08a1 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a2 08a2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a3 08a3 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a4 08a4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 08a5 ; -------------------------------------------------------------------------------------- 08a5 ; Comes from: 08a5 ; 0850 C from color 0x0820 08a5 ; -------------------------------------------------------------------------------------- 08a5 08a5 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 08a6 08a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 08a7 08a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34cb fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 34cb 0x34cb seq_en_micro 0 08a8 08a8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 08 GP08 val_b_adr 08 GP08 08a9 08a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 08aa 08aa fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_frame 2 08ab 08ab fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 val_a_adr 3a VR08:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 08ac 08ac seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 08ad 08ad fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3f VR02:1f val_frame 2 08ae 08ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 33 TR09:13 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 9 typ_rand c WRITE_OUTER_FRAME 08af 08af fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_c_adr 13 VR0d:0c val_c_mux_sel 2 ALU val_frame d 08b0 08b0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 12 VR0d:0d val_c_source 0 FIU_BUS val_frame d 08b1 08b1 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 2d VR0d:0d val_alu_func 7 INC_A val_c_adr 12 VR0d:0d val_c_mux_sel 2 ALU val_frame d 08b2 08b2 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_mux_sel 2 ALU 08b3 08b3 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 08b4 08b4 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08b5 08b5 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08b6 08b6 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08b7 08b7 seq_br_type 0 Branch False; Flow J cc=False 0x8c4 seq_branch_adr 08c4 0x08c4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 08b8 08b8 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08b9 08b9 fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ba 08ba fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08bb 08bb fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08bc 08bc fiu_mem_start f start_physical_tag_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08bd 08bd fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08be 08be fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08bf 08bf fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 13 VR0d:0c val_c_source 0 FIU_BUS val_frame d 08c0 08c0 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08c1 08c1 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c0 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08c0 0x08c0 seq_en_micro 0 08c2 08c2 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 08c3 08c3 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c4 08c4 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8b5 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08b5 0x08b5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08c5 08c5 seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08c6 08c6 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR08:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 2c VR0d:0c val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame d 08c7 08c7 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c8 08c8 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08c9 08c9 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08ca 08ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 12 TR0d:0d typ_c_source 0 FIU_BUS typ_frame d 08cb 08cb seq_br_type 0 Branch False; Flow J cc=False 0x8d9 seq_branch_adr 08d9 0x08d9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08cc 08cc fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08cd 08cd fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ce 08ce fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08cf 08cf fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08d0 08d0 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08d1 08d1 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08d2 08d2 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x20d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08d3 08d3 fiu_mem_start e start_physical_wr fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 2c VR0d:0c val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame d 08d4 08d4 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 08d5 08d5 fiu_mem_start e start_physical_wr; Flow J cc=True 0x8d4 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08d4 0x08d4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08d6 08d6 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x8d3 fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08d3 0x08d3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 39 VR08:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 08d7 08d7 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 08d8 08d8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08d9 08d9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c9 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08c9 0x08c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08da 08da seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08db 08db fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2c VR0d:0c val_frame d 08dc 08dc fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 11 VR0d:0e val_c_source 0 FIU_BUS val_frame d 08dd 08dd seq_en_micro 0 val_a_adr 23 VR08:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 08de 08de fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_frame d val_a_adr 33 VR05:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 08df 08df fiu_mem_start 13 start_available_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 08e0 08e0 seq_en_micro 0 08e1 08e1 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 08e2 08e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 08e3 08e3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 04 GP04 08e4 08e4 ioc_load_wdr 0 ; Flow J cc=False 0x8df ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08df 0x08df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 08e5 08e5 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 08e6 ; -------------------------------------------------------------------------------------- 08e6 ; Comes from: 08e6 ; 08c5 C from color 0x0127 08e6 ; 08da C from color 0x0127 08e6 ; -------------------------------------------------------------------------------------- 08e6 08e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 08e7 08e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 08e8 08e8 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 08e9 08e9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ea 08ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ec seq_br_type 1 Branch True seq_branch_adr 08ec 0x08ec seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08eb 08eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ec 08ec fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ed 08ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ef seq_br_type 1 Branch True seq_branch_adr 08ef 0x08ef seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08ee 08ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ef 08ef fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f0 08f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f2 seq_br_type 1 Branch True seq_branch_adr 08f2 0x08f2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f1 08f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f2 08f2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f3 08f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f5 seq_br_type 1 Branch True seq_branch_adr 08f5 0x08f5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f4 08f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f5 08f5 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 08f6 08f6 fiu_mem_start 18 acknowledge_refresh; Flow C 0x3649 fiu_tivi_src c mar_0xc ioc_random 1 load transfer address seq_br_type 7 Unconditional Call seq_branch_adr 3649 0x3649 seq_en_micro 0 seq_random 0a ? typ_b_adr 33 TR02:13 typ_frame 2 08f7 08f7 ioc_random 1c read ioc memory and increment address seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 30 VR02:10 val_frame 2 08f8 08f8 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08f9 08f9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 seq_random 55 ? typ_c_adr 0c TR03:13 typ_c_source 0 FIU_BUS typ_frame 3 val_c_adr 0c VR03:13 val_c_source 0 FIU_BUS val_frame 3 08fa 08fa fiu_mem_start 13 start_available_query ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08fb 08fb seq_en_micro 0 08fc 08fc fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3a VR11:1a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 08fd 08fd fiu_mem_start 17 scavenger_write; Flow J cc=False 0x8fc fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fc 0x08fc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_b_adr 22 VR07:02 val_frame 7 val_rand 2 DEC_LOOP_COUNTER 08fe 08fe fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x8fb ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fb 0x08fb seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08ff 08ff fiu_tivi_src 8 type_var; Flow C 0x2a82 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a82 0x2a82 seq_en_micro 0 typ_b_adr 33 TR09:13 typ_frame 9 typ_mar_cntl 4 RESTORE_MAR 0900 0900 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0b VR03:14 val_c_source 0 FIU_BUS val_frame 3 0901 0901 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0a VR03:15 val_c_source 0 FIU_BUS val_frame 3 0902 0902 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 09 VR03:16 val_c_source 0 FIU_BUS val_frame 3 0903 0903 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb51 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b51 0x0b51 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0904 0904 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0905 0905 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_b_adr 1f TOP - 1 0906 0906 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0907 0907 ioc_fiubs 1 val ; Flow C cc=False 0x32aa ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2f VR12:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 12 0908 0908 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0909 0909 ioc_fiubs 0 fiu typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 090a 090a fiu_mem_start 2 start-rd; Flow C cc=True 0x326c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 090b 090b typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 090c 090c fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a5 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 090d 090d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 090e 090e fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x90b ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 090b 0x090b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 090f 090f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 03 GP03 val_rand a PASS_B_HIGH 0910 0910 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 0f Load_control_top+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 1 START_POP_DOWN typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0911 0911 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 04 GP04 0912 0912 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0913 0913 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0914 0914 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0915 0915 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x916 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32ac 0x32ac typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0916 0916 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x393d fiu_offs_lit 45 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 393d 0x393d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 0917 0917 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0918 0918 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0919 0919 ioc_adrbs 1 val ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 091a 091a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x91e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 091e 0x091e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 091b 091b <default> 091c 091c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 091d 091d ioc_load_wdr 0 ; Flow J 0x94d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 094d 0x094d 091e 091e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 091f 091f <halt> ; Flow R 0920 ; -------------------------------------------------------------------------------------- 0920 ; 0x020d Execute Module,Elaborate 0920 ; -------------------------------------------------------------------------------------- 0920 MACRO_Execute_Module,Elaborate: 0920 0920 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0920 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0921 0921 fiu_mem_start 4 continue; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 0922 0922 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0923 0923 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0924 0924 fiu_mem_start 3 start-wr; Flow C cc=True 0x32a9 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0925 0925 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 0926 0926 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0927 0927 <halt> ; Flow R 0928 ; -------------------------------------------------------------------------------------- 0928 ; 0x0206 Execute Module,Check_Elaborated 0928 ; -------------------------------------------------------------------------------------- 0928 MACRO_Execute_Module,Check_Elaborated: 0928 0928 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0928 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 0929 0929 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 092a 0x092a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 092a 092a fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x3277 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 092b 092b fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092c 092c fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092d 092d ioc_load_wdr 0 ; Flow J 0x926 seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 typ_b_adr 01 GP01 val_b_adr 01 GP01 092e ; -------------------------------------------------------------------------------------- 092e ; 0x020f Execute Module,Activate 092e ; -------------------------------------------------------------------------------------- 092e MACRO_Execute_Module,Activate: 092e 092e dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 092e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 092f 092f fiu_tivi_src c mar_0xc; Flow C cc=False 0x3277 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 0930 0930 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0931 0931 seq_br_type 7 Unconditional Call; Flow C 0x393d seq_branch_adr 393d 0x393d seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 0932 ; -------------------------------------------------------------------------------------- 0932 ; 0x020e Execute Module,Augment_Imports 0932 ; -------------------------------------------------------------------------------------- 0932 MACRO_Execute_Module,Augment_Imports: 0932 0932 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0932 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0933 0933 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0934 0934 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0935 0935 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x936 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 093a 0x093a typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0936 0936 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x943 fiu_load_tar 1 hold_tar fiu_offs_lit 2c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0943 0x0943 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0937 0937 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0938 0938 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0939 0939 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 093a 093a ioc_fiubs 1 val ; Flow C cc=True 0x32aa seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1d A_AND_NOT_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 093b 093b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x940 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0940 0x0940 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 093c 093c typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093d 093d fiu_mem_start 3 start-wr; Flow J cc=True 0x949 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0949 0x0949 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 093e 093e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093f 093f fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x93c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 093c 0x093c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0940 0940 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_csa_cntl 1 START_POP_DOWN val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0941 0941 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE 0942 0942 ioc_load_wdr 0 ; Flow J 0x926 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 val_b_adr 01 GP01 0943 0943 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0944 0944 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0945 0945 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0946 0946 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0xb51 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b51 0x0b51 typ_a_adr 10 TOP 0947 0947 fiu_tivi_src c mar_0xc; Flow J 0x3307 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3307 0x3307 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_rand c WRITE_OUTER_FRAME val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0948 0948 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0949 0949 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 094a 094a seq_br_type 3 Unconditional Branch; Flow J 0x32a5 seq_branch_adr 32a5 0x32a5 094b 094b <halt> ; Flow R 094c ; -------------------------------------------------------------------------------------- 094c ; 0x0209 Execute Task,Abort 094c ; -------------------------------------------------------------------------------------- 094c MACRO_Execute_Task,Abort: 094c 094c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094c typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU 094d 094d seq_br_type 7 Unconditional Call; Flow C 0x3a3a seq_branch_adr 3a3a 0x3a3a val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 094e ; -------------------------------------------------------------------------------------- 094e ; 0x0208 Execute Task,Abort_Multiple 094e ; -------------------------------------------------------------------------------------- 094e MACRO_Execute_Task,Abort_Multiple: 094e 094e dispatch_brk_class 8 ; Flow J 0x326a dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094e seq_br_type 3 Unconditional Branch seq_branch_adr 326a 0x326a typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 094f 094f <halt> ; Flow R 0950 ; -------------------------------------------------------------------------------------- 0950 ; 0x020c Execute Module,Is_Callable 0950 ; -------------------------------------------------------------------------------------- 0950 MACRO_Execute_Module,Is_Callable: 0950 0950 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0950 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0951 0951 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x958 seq_br_type 1 Branch True seq_branch_adr 0958 0x0958 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_frame 2 0952 0952 fiu_load_tar 1 hold_tar; Flow J cc=False 0x959 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0959 0x0959 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0953 0953 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_rand 2 DEC_LOOP_COUNTER 0954 0954 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x956 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0956 0x0956 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0955 0955 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x957 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0956 0956 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0957 0957 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0958 0958 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0959 0959 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 095a 095a fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 095b 095b fiu_load_tar 1 hold_tar; Flow J 0x953 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0953 0x0953 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 095c 095c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 095d 095d ioc_tvbs 1 typ+fiu; Flow J 0x950 seq_br_type 3 Unconditional Branch seq_branch_adr 0950 MACRO_Execute_Module,Is_Callable typ_a_adr 24 TR00:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 095e ; -------------------------------------------------------------------------------------- 095e ; 0x020b Execute Module,Is_Terminated 095e ; -------------------------------------------------------------------------------------- 095e MACRO_Execute_Module,Is_Terminated: 095e 095e dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 095e fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 095f 095f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x963 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0963 0x0963 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0960 0960 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0961 0x0961 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0961 0961 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 0962 0962 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x958 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0958 0x0958 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0963 0963 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0964 0964 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x958 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0958 0x0958 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0965 0965 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x960 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0960 0x0960 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0966 ; -------------------------------------------------------------------------------------- 0966 ; 0x0205 QQUnknown InMicrocode 0966 ; -------------------------------------------------------------------------------------- 0966 MACRO_0966_QQUnknown_InMicrocode: 0966 0966 dispatch_brk_class 0 ; Flow J cc=False 0x96b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0966 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 096b 0x096b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0967 0967 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x969 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0969 0x0969 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0968 0968 fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0969 0969 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 096a 096a fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 096b 096b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x96f seq_br_type 0 Branch False seq_branch_adr 096f 0x096f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU 096c 096c seq_br_type 1 Branch True; Flow J cc=True 0x96e seq_branch_adr 096e 0x096e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame a 096d 096d seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 096e 096e fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 096f 096f fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0970 ; -------------------------------------------------------------------------------------- 0970 ; 0x020a Execute Module,Get_Name 0970 ; -------------------------------------------------------------------------------------- 0970 MACRO_Execute_Module,Get_Name: 0970 0970 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0970 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0971 0x0971 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL 0971 0971 typ_c_adr 2f TOP 0972 0972 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x32a5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0973 0973 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x975 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0975 0x0975 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0974 0974 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0975 0975 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0976 0976 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0977 0977 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0978 0978 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x97a fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 097a 0x097a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0979 0979 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 097a 097a seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 097b 097b fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 097c 097c seq_br_type 3 Unconditional Branch; Flow J 0x978 seq_branch_adr 0978 0x0978 097d 097d <halt> ; Flow R 097e ; -------------------------------------------------------------------------------------- 097e ; 0x02c7 Declare_Variable Any 097e ; -------------------------------------------------------------------------------------- 097e MACRO_Declare_Variable_Any: 097e 097e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 097e fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 097f 097f fiu_fill_mode_src 0 ; Flow J cc=True 0x3162 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3162 MACRO_Declare_Variable_Discrete seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0980 0980 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x981 ; Flow J cc=#0x0 0x981 seq_br_type b Case False seq_branch_adr 0981 0x0981 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0981 0981 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0982 0982 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0983 0983 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0984 0984 seq_br_type 3 Unconditional Branch; Flow J 0xaec seq_branch_adr 0aec MACRO_Declare_Variable_Package 0985 0985 seq_br_type 3 Unconditional Branch; Flow J 0xaf0 seq_branch_adr 0af0 MACRO_Declare_Variable_Task 0986 0986 seq_br_type 3 Unconditional Branch; Flow J 0x1328 seq_branch_adr 1328 MACRO_Declare_Variable_Array 0987 0987 seq_br_type 3 Unconditional Branch; Flow J 0x1328 seq_branch_adr 1328 MACRO_Declare_Variable_Array 0988 0988 seq_br_type 3 Unconditional Branch; Flow J 0x1328 seq_branch_adr 1328 MACRO_Declare_Variable_Array 0989 0989 seq_br_type 3 Unconditional Branch; Flow J 0x1ee2 seq_branch_adr 1ee2 MACRO_Declare_Variable_Record 098a 098a seq_br_type 3 Unconditional Branch; Flow J 0x12d2 seq_branch_adr 12d2 MACRO_Declare_Variable_Variant_Record 098b 098b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 098c 098c seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 098d 098d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 098e ; -------------------------------------------------------------------------------------- 098e ; 0x02c6 Declare_Variable Any,Visible 098e ; -------------------------------------------------------------------------------------- 098e MACRO_Declare_Variable_Any,Visible: 098e 098e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 098e fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 098f 098f fiu_fill_mode_src 0 ; Flow J cc=True 0x3160 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3160 MACRO_Declare_Variable_Discrete,Visible seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0990 0990 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x991 ; Flow J cc=#0x0 0x991 seq_br_type b Case False seq_branch_adr 0991 0x0991 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0991 0991 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0992 0992 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0993 0993 seq_br_type 3 Unconditional Branch; Flow J 0x30ca seq_branch_adr 30ca MACRO_Declare_Variable_Float,Visible 0994 0994 seq_br_type 3 Unconditional Branch; Flow J 0xaf6 seq_branch_adr 0af6 MACRO_Declare_Variable_Package,Visible 0995 0995 seq_br_type 3 Unconditional Branch; Flow J 0xafc seq_branch_adr 0afc MACRO_Declare_Variable_Task,Visible 0996 0996 seq_br_type 3 Unconditional Branch; Flow J 0x133a seq_branch_adr 133a MACRO_Declare_Variable_Array,Visible 0997 0997 seq_br_type 3 Unconditional Branch; Flow J 0x133a seq_branch_adr 133a MACRO_Declare_Variable_Array,Visible 0998 0998 seq_br_type 3 Unconditional Branch; Flow J 0x133a seq_branch_adr 133a MACRO_Declare_Variable_Array,Visible 0999 0999 seq_br_type 3 Unconditional Branch; Flow J 0x1ed4 seq_branch_adr 1ed4 MACRO_Declare_Variable_Record,Visible 099a 099a seq_br_type 3 Unconditional Branch; Flow J 0x12c6 seq_branch_adr 12c6 MACRO_Declare_Variable_Variant_Record,Visible 099b 099b seq_br_type 4 Call False; Flow C cc=False 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 099c 099c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 099d 099d seq_br_type 4 Call False; Flow C cc=False 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 099e 099e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 099f 099f <halt> ; Flow R 09a0 ; -------------------------------------------------------------------------------------- 09a0 ; 0x012f Execute Any,Equal 09a0 ; -------------------------------------------------------------------------------------- 09a0 MACRO_Execute_Any,Equal: 09a0 09a0 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09a0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09a1 09a1 fiu_fill_mode_src 0 ; Flow J cc=True 0x2f9a fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2f9a MACRO_Execute_Discrete,Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09a2 09a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9a3 ; Flow J cc=#0x0 0x9a3 seq_br_type b Case False seq_branch_adr 09a3 0x09a3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09a3 09a3 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09a4 09a4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09a5 09a5 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09a6 09a6 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09a7 09a7 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09a8 09a8 seq_br_type 3 Unconditional Branch; Flow J 0x1b42 seq_branch_adr 1b42 MACRO_Execute_Array,Equal 09a9 09a9 seq_br_type 3 Unconditional Branch; Flow J 0x1818 seq_branch_adr 1818 MACRO_Execute_Vector,Equal 09aa 09aa seq_br_type 3 Unconditional Branch; Flow J 0x1436 seq_branch_adr 1436 MACRO_Execute_Matrix,Equal 09ab 09ab seq_br_type 3 Unconditional Branch; Flow J 0x17ee seq_branch_adr 17ee MACRO_Execute_Record,Equal 09ac 09ac seq_br_type 3 Unconditional Branch; Flow J 0x1742 seq_branch_adr 1742 MACRO_Execute_Variant_Record,Equal 09ad 09ad fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09ae 09ae seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09af 09af fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b0 ; -------------------------------------------------------------------------------------- 09b0 ; 0x012e Execute Any,Not_Equal 09b0 ; -------------------------------------------------------------------------------------- 09b0 MACRO_Execute_Any,Not_Equal: 09b0 09b0 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09b0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09b1 09b1 fiu_fill_mode_src 0 ; Flow J cc=True 0x2f9e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2f9e MACRO_Execute_Discrete,Not_Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09b2 09b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9b3 ; Flow J cc=#0x0 0x9b3 seq_br_type b Case False seq_branch_adr 09b3 0x09b3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09b3 09b3 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09b4 09b4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09b5 09b5 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b6 09b6 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09b7 09b7 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 09b8 09b8 seq_br_type 3 Unconditional Branch; Flow J 0x1b42 seq_branch_adr 1b42 MACRO_Execute_Array,Equal 09b9 09b9 seq_br_type 3 Unconditional Branch; Flow J 0x1818 seq_branch_adr 1818 MACRO_Execute_Vector,Equal 09ba 09ba seq_br_type 3 Unconditional Branch; Flow J 0x1436 seq_branch_adr 1436 MACRO_Execute_Matrix,Equal 09bb 09bb seq_br_type 3 Unconditional Branch; Flow J 0x17ee seq_branch_adr 17ee MACRO_Execute_Record,Equal 09bc 09bc seq_br_type 3 Unconditional Branch; Flow J 0x1742 seq_branch_adr 1742 MACRO_Execute_Variant_Record,Equal 09bd 09bd fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09be 09be seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09bf 09bf fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09c0 ; -------------------------------------------------------------------------------------- 09c0 ; 0x012d Execute Any,Address 09c0 ; -------------------------------------------------------------------------------------- 09c0 MACRO_Execute_Any,Address: 09c0 09c0 dispatch_brk_class 8 ; Flow J cc=False 0x9c4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09c0 seq_br_type 0 Branch False seq_branch_adr 09c4 0x09c4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 09c1 09c1 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c5 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 09c5 0x09c5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 09c2 09c2 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c6 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 09c6 0x09c6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 09c3 09c3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09c4 09c4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09c5 09c5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c6 09c6 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c7 09c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 09c8 ; -------------------------------------------------------------------------------------- 09c8 ; 0x0116 Execute Any,Address_Of_Type 09c8 ; -------------------------------------------------------------------------------------- 09c8 MACRO_Execute_Any,Address_Of_Type: 09c8 09c8 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09c8 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09c9 09c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09ca ; -------------------------------------------------------------------------------------- 09ca ; 0x012c Execute Any,Size 09ca ; -------------------------------------------------------------------------------------- 09ca MACRO_Execute_Any,Size: 09ca 09ca dispatch_brk_class 8 ; Flow J cc=False 0x9cf dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09ca fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 09cf 0x09cf seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 09cb 09cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 09cc 09cc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09cd 0x09cd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09cd 09cd fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09ce 0x09ce seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL 09ce 09ce seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 seq_random 02 ? 09cf 09cf ioc_fiubs 0 fiu ; Flow J cc=True 0x9f2 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 09f2 0x09f2 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 09d0 09d0 fiu_load_tar 1 hold_tar; Flow J cc=False 0x9d3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09d3 0x09d3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 09d1 09d1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09d2 0x09d2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09d2 09d2 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 seq_random 02 ? 09d3 09d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 09d4 09d4 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x9e3 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 09e3 0x09e3 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 09d5 09d5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9d8 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09d8 0x09d8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 09d6 09d6 fiu_fill_mode_src 0 ; Flow C cc=False 0x9df fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09df 0x09df typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09d7 09d7 seq_br_type 3 Unconditional Branch; Flow J 0x9db seq_branch_adr 09db 0x09db seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09d8 09d8 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09d9 09d9 fiu_fill_mode_src 0 ; Flow C cc=False 0x9df fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09df 0x09df typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09da 09da seq_br_type 3 Unconditional Branch; Flow J 0x9db seq_branch_adr 09db 0x09db seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09db 09db seq_b_timing 1 Latch Condition; Flow J cc=True 0x9de seq_br_type 1 Branch True seq_branch_adr 09de 0x09de seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 09dc 09dc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 09dd 09dd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 09de 09de fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x9ea ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 09ea 0x09ea seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B 09df ; -------------------------------------------------------------------------------------- 09df ; Comes from: 09df ; 09d6 C False from color MACRO_Execute_Any,Size 09df ; 09d9 C False from color MACRO_Execute_Any,Size 09df ; -------------------------------------------------------------------------------------- 09df 09df fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9e1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09e1 0x09e1 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 09e0 09e0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e1 09e1 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09e2 09e2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e3 09e3 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 09e4 09e4 fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09e5 09e5 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x9e8 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09e8 0x09e8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 09e6 09e6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09e7 09e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09e8 09e8 fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 09e9 0x09e9 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09e9 09e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 38 VR13:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 13 09ea 09ea fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 09eb 09eb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x9f0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09f0 0x09f0 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09ec 09ec fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9ee seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09ee 0x09ee seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 09ed 09ed fiu_fill_mode_src 0 ; Flow J 0x9ea fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ea 0x09ea typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 09ee 09ee fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09ef 09ef fiu_fill_mode_src 0 ; Flow J 0x9ea fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ea 0x09ea typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 09f0 09f0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 09f1 09f1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f2 09f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9cc seq_br_type 1 Branch True seq_branch_adr 09cc 0x09cc seq_cond_sel 00 VAL.ALU_ZERO(late) val_b_adr 10 TOP val_rand a PASS_B_HIGH 09f3 09f3 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 09f4 09f4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f5 09f5 <halt> ; Flow R 09f6 ; -------------------------------------------------------------------------------------- 09f6 ; 0x012a Execute Any,Change_Utility 09f6 ; -------------------------------------------------------------------------------------- 09f6 MACRO_Execute_Any,Change_Utility: 09f6 09f6 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09f6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09f7 09f7 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 09f8 09f8 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=False 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 09f9 09f9 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 09fa 09fa fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a5 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 09fb 09fb ioc_load_wdr 0 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 1f TOP - 1 09fc 09fc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 09fd 09fd <halt> ; Flow R 09fe ; -------------------------------------------------------------------------------------- 09fe ; 0x0129 Execute Any,Make_Visible 09fe ; -------------------------------------------------------------------------------------- 09fe MACRO_Execute_Any,Make_Visible: 09fe 09fe dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09fe seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 09ff 09ff fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a00 0x0a00 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a00 0a00 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a01 0x0a01 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a01 0a01 ioc_tvbs 2 fiu+val; Flow C 0x32a5 seq_br_type 7 Unconditional Call seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 0a02 ; -------------------------------------------------------------------------------------- 0a02 ; 0x0128 QQUnknown InMicrocode 0a02 ; -------------------------------------------------------------------------------------- 0a02 MACRO_0a02_QQUnknown_InMicrocode: 0a02 0a02 dispatch_brk_class 0 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a02 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a03 0x0a03 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a03 0a03 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a04 ; -------------------------------------------------------------------------------------- 0a04 ; 0x0124 Execute Any,Is_Constrained 0a04 ; -------------------------------------------------------------------------------------- 0a04 MACRO_Execute_Any,Is_Constrained: 0a04 0a04 dispatch_brk_class 8 ; Flow J cc=True 0xa07 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a04 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0a07 0x0a07 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame b 0a05 0a05 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0a06 0x0a06 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0a06 0a06 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a07 0a07 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a08 0x0a08 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a08 0a08 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a09 0a09 <halt> ; Flow R 0a0a ; -------------------------------------------------------------------------------------- 0a0a ; 0x0112 Execute Any,Make_Constrained 0a0a ; -------------------------------------------------------------------------------------- 0a0a MACRO_Execute_Any,Make_Constrained: 0a0a 0a0a dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0a0b 0x0a0b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL 0a0b 0a0b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0a0c ; -------------------------------------------------------------------------------------- 0a0c ; 0x0123 Execute Any,Make_Aligned 0a0c ; -------------------------------------------------------------------------------------- 0a0c MACRO_Execute_Any,Make_Aligned: 0a0c 0a0c dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0a0d 0a0d ioc_tvbs 5 seq+seq; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS 0a0e 0a0e fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x32a5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a0f 0a0f ioc_load_wdr 0 ; Flow J cc=False 0x9c7 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 09c7 0x09c7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 0a10 0a10 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a11 0a11 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 0a12 0a12 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 0a13 0a13 <halt> ; Flow R 0a14 ; -------------------------------------------------------------------------------------- 0a14 ; 0x0122 Execute Any,Make_Root_Type 0a14 ; -------------------------------------------------------------------------------------- 0a14 MACRO_Execute_Any,Make_Root_Type: 0a14 0a14 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a14 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR09:00 val_frame 9 0a15 0a15 seq_br_type 4 Call False; Flow C cc=False 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 39 VR02:19 val_frame 2 0a16 0a16 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x3277 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a17 0a17 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0a18 0x0a18 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS 0a18 0a18 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0xa1a ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0a1a 0x0a1a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0a19 0a19 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a1a 0a1a <default> 0a1b 0a1b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 0a1c 0a1c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 0a1d 0a1d seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a1e ; -------------------------------------------------------------------------------------- 0a1e ; 0x0121 Execute Any,Is_Default 0a1e ; -------------------------------------------------------------------------------------- 0a1e MACRO_Execute_Any,Is_Default: 0a1e 0a1e dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a1e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a1f 0x0a1f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0a1f 0a1f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xa1d ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 0a1d 0x0a1d seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a20 ; -------------------------------------------------------------------------------------- 0a20 ; 0x0120 Execute Any,Is_Value 0a20 ; -------------------------------------------------------------------------------------- 0a20 MACRO_Execute_Any,Is_Value: 0a20 0a20 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a20 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a21 0a21 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a22 ; -------------------------------------------------------------------------------------- 0a22 ; 0x011f Execute Any,Is_Scalar 0a22 ; -------------------------------------------------------------------------------------- 0a22 MACRO_Execute_Any,Is_Scalar: 0a22 0a22 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a22 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a23 0a23 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 34 VR05:14 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0a24 ; -------------------------------------------------------------------------------------- 0a24 ; 0x011e Execute Any,Convert 0a24 ; -------------------------------------------------------------------------------------- 0a24 MACRO_Execute_Any,Convert: 0a24 0a24 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a24 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a25 0a25 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fec MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a26 0a26 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa27 ; Flow J cc=#0x0 0xa27 seq_br_type b Case False seq_branch_adr 0a27 0x0a27 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a27 0a27 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a28 0a28 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a29 0a29 seq_br_type 3 Unconditional Branch; Flow J 0x28ce seq_branch_adr 28ce MACRO_Execute_Float,Convert 0a2a 0a2a seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a2b 0a2b seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a2c 0a2c seq_br_type 3 Unconditional Branch; Flow J 0x1bd4 seq_branch_adr 1bd4 MACRO_Execute_Array,Convert 0a2d 0a2d seq_br_type 3 Unconditional Branch; Flow J 0x1a56 seq_branch_adr 1a56 MACRO_Execute_Vector,Convert 0a2e 0a2e seq_br_type 3 Unconditional Branch; Flow J 0x1550 seq_branch_adr 1550 MACRO_Execute_Matrix,Convert 0a2f 0a2f seq_br_type 3 Unconditional Branch; Flow J 0x1802 seq_branch_adr 1802 MACRO_Execute_Record,Convert 0a30 0a30 seq_br_type 3 Unconditional Branch; Flow J 0x179c seq_branch_adr 179c MACRO_Execute_Variant_Record,Convert 0a31 0a31 seq_br_type 0 Branch False; Flow J cc=False 0x1af1 seq_branch_adr 1af1 0x1af1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a32 0a32 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b09 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a33 0a33 seq_br_type 0 Branch False; Flow J cc=False 0xc31 seq_branch_adr 0c31 0x0c31 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a34 0a34 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc49 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a35 0a35 <halt> ; Flow R 0a36 ; -------------------------------------------------------------------------------------- 0a36 ; 0x011d Execute Any,Convert_To_Formal 0a36 ; -------------------------------------------------------------------------------------- 0a36 MACRO_Execute_Any,Convert_To_Formal: 0a36 0a36 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a36 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a37 0a37 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fec MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a38 0a38 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa39 ; Flow J cc=#0x0 0xa39 seq_br_type b Case False seq_branch_adr 0a39 0x0a39 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a39 0a39 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a3a 0a3a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a3b 0a3b seq_br_type 3 Unconditional Branch; Flow J 0x28ce seq_branch_adr 28ce MACRO_Execute_Float,Convert 0a3c 0a3c seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a3d 0a3d seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a3e 0a3e seq_br_type 3 Unconditional Branch; Flow J 0x1c3a seq_branch_adr 1c3a MACRO_Execute_Array,Convert_To_Formal 0a3f 0a3f seq_br_type 3 Unconditional Branch; Flow J 0x1a96 seq_branch_adr 1a96 MACRO_Execute_Vector,Convert_To_Formal 0a40 0a40 seq_br_type 3 Unconditional Branch; Flow J 0x15c6 seq_branch_adr 15c6 MACRO_Execute_Matrix,Convert_To_Formal 0a41 0a41 seq_br_type 3 Unconditional Branch; Flow J 0x1802 seq_branch_adr 1802 MACRO_Execute_Record,Convert 0a42 0a42 seq_br_type 3 Unconditional Branch; Flow J 0x179c seq_branch_adr 179c MACRO_Execute_Variant_Record,Convert 0a43 0a43 seq_br_type 0 Branch False; Flow J cc=False 0x1af1 seq_branch_adr 1af1 0x1af1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a44 0a44 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b09 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a45 0a45 seq_br_type 0 Branch False; Flow J cc=False 0xc31 seq_branch_adr 0c31 0x0c31 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a46 0a46 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc49 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a47 0a47 <halt> ; Flow R 0a48 ; -------------------------------------------------------------------------------------- 0a48 ; 0x011c Execute Any,Convert_Unchecked 0a48 ; -------------------------------------------------------------------------------------- 0a48 MACRO_Execute_Any,Convert_Unchecked: 0a48 0a48 dispatch_brk_class 4 ; Flow C cc=False 0xa4d dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0a48 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0a4d 0x0a4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a49 0a49 fiu_load_tar 1 hold_tar; Flow J cc=True 0xa4b fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0a4b 0x0a4b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 3 0a4a 0a4a fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a4b 0x0a4b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 11 TOP + 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 0a4b 0a4b ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a5 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 0a4c 0a4c seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0a4d 0a4d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0xa50 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0a50 0x0a50 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0a4e 0a4e fiu_tivi_src 4 fiu_var; Flow J cc=True 0xa4f ; Flow J cc=#0x0 0xa61 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0a61 0x0a61 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 7 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a4f 0a4f seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a50 ; -------------------------------------------------------------------------------------- 0a50 ; Comes from: 0a50 ; 0a4d C #0x0 from color MACRO_Execute_Any,Convert_Unchecked 0a50 ; -------------------------------------------------------------------------------------- 0a50 0a50 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a51 0a51 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa58 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a58 0x0a58 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a52 0a52 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a53 0a53 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a54 0a54 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a55 0a55 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5a fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5a 0x0a5a typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a56 0a56 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5b fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5b 0x0a5b typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a57 0a57 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5c 0x0a5c typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a58 0a58 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0a59 0a59 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=True ; Flow J cc=False 0xa6d fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0a6d 0x0a6d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5a 0a5a fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0a5b 0a5b fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 34 VR07:14 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 0a5c 0a5c fiu_mem_start 2 start-rd; Flow C cc=True 0x32a5 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5d 0a5d fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a5e 0a5e fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0a5f 0a5f fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 06 Pop_stack+? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 0a60 0a60 seq_b_timing 0 Early Condition; Flow J cc=True 0xa61 ; Flow J cc=#0x0 0xa61 seq_br_type b Case False seq_branch_adr 0a61 0x0a61 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0a61 0a61 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa6b seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a6b 0x0a6b seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a62 0a62 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa69 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a69 0x0a69 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a63 0a63 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a64 0a64 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a65 0a65 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a66 0a66 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa61 seq_br_type 8 Return True seq_branch_adr 0a61 0x0a61 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a67 0a67 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa61 seq_br_type 8 Return True seq_branch_adr 0a61 0x0a61 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a68 0a68 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa61 seq_br_type 8 Return True seq_branch_adr 0a61 0x0a61 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a69 0a69 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xa6b ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a6b 0x0a6b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 0a6a 0a6a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a6b 0a6b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 0a6c 0x0a6c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 28 TR09:08 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0a6c 0a6c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0a6d 0a6d seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0a6e ; -------------------------------------------------------------------------------------- 0a6e ; 0x011b Execute Any,In_Type 0a6e ; -------------------------------------------------------------------------------------- 0a6e MACRO_Execute_Any,In_Type: 0a6e 0a6e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a6e dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a6f 0a6f fiu_fill_mode_src 0 ; Flow J cc=True 0x2fe8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fe8 MACRO_Execute_Discrete,In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a70 0a70 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa71 ; Flow J cc=#0x0 0xa71 seq_br_type b Case False seq_branch_adr 0a71 0x0a71 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a71 0a71 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a72 0a72 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a73 0a73 seq_br_type 3 Unconditional Branch; Flow J 0x28f2 seq_branch_adr 28f2 MACRO_Execute_Float,In_Type 0a74 0a74 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa7e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a7e 0x0a7e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a75 0a75 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa7e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a7e 0x0a7e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a76 0a76 seq_br_type 3 Unconditional Branch; Flow J 0x1ba4 seq_branch_adr 1ba4 MACRO_Execute_Array,In_Type 0a77 0a77 seq_br_type 3 Unconditional Branch; Flow J 0x1a9e seq_branch_adr 1a9e MACRO_Execute_Vector,In_Type 0a78 0a78 seq_br_type 3 Unconditional Branch; Flow J 0x14ae seq_branch_adr 14ae MACRO_Execute_Matrix,In_Type 0a79 0a79 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa7e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a7e 0x0a7e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7a 0a7a seq_br_type 3 Unconditional Branch; Flow J 0x17ae seq_branch_adr 17ae MACRO_Execute_Variant_Record,In_Type 0a7b 0a7b fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1afb fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1afb 0x1afb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7c 0a7c seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a7d 0a7d fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc3b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3b 0x0c3b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7e 0a7e ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a7f 0a7f fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a80 0a80 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a81 0a81 <halt> ; Flow R 0a82 ; -------------------------------------------------------------------------------------- 0a82 ; 0x011a Execute Any,Not_In_Type 0a82 ; -------------------------------------------------------------------------------------- 0a82 MACRO_Execute_Any,Not_In_Type: 0a82 0a82 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a82 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a83 0a83 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fea fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fea MACRO_Execute_Discrete,Not_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a84 0a84 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa85 ; Flow J cc=#0x0 0xa85 seq_br_type b Case False seq_branch_adr 0a85 0x0a85 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a85 0a85 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a86 0a86 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a87 0a87 seq_br_type 3 Unconditional Branch; Flow J 0x28f4 seq_branch_adr 28f4 MACRO_Execute_Float,Not_In_Type 0a88 0a88 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa92 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a92 0x0a92 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a89 0a89 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa92 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a92 0x0a92 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8a 0a8a seq_br_type 3 Unconditional Branch; Flow J 0x1bb2 seq_branch_adr 1bb2 MACRO_Execute_Array,Not_In_Type 0a8b 0a8b seq_br_type 3 Unconditional Branch; Flow J 0x1aac seq_branch_adr 1aac MACRO_Execute_Vector,Not_In_Type 0a8c 0a8c seq_br_type 3 Unconditional Branch; Flow J 0x14b2 seq_branch_adr 14b2 MACRO_Execute_Matrix,Not_In_Type 0a8d 0a8d fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa92 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a92 0x0a92 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8e 0a8e seq_br_type 3 Unconditional Branch; Flow J 0x17b2 seq_branch_adr 17b2 MACRO_Execute_Variant_Record,Not_In_Type 0a8f 0a8f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1b01 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b01 0x1b01 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a90 0a90 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a91 0a91 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc41 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c41 0x0c41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a92 0a92 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a93 0a93 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a94 0a94 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a95 0a95 <halt> ; Flow R 0a96 ; -------------------------------------------------------------------------------------- 0a96 ; 0x0119 Execute Any,Check_In_Formal_Type 0a96 ; -------------------------------------------------------------------------------------- 0a96 MACRO_Execute_Any,Check_In_Formal_Type: 0a96 0a96 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a96 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a97 0a97 fiu_fill_mode_src 0 ; Flow J cc=True 0x2ff8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2ff8 MACRO_Execute_Discrete,Check_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a98 0a98 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa99 ; Flow J cc=#0x0 0xa99 seq_br_type b Case False seq_branch_adr 0a99 0x0a99 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a99 0a99 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0a9a 0a9a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a9b 0a9b seq_br_type 3 Unconditional Branch; Flow J 0x28f8 seq_branch_adr 28f8 MACRO_Execute_Float,Check_In_Type 0a9c 0a9c fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa6 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa6 0x0aa6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0a9d 0a9d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa6 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa6 0x0aa6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0a9e 0a9e seq_br_type 3 Unconditional Branch; Flow J 0x1bc0 seq_branch_adr 1bc0 MACRO_Execute_Array,Check_In_Type 0a9f 0a9f seq_br_type 3 Unconditional Branch; Flow J 0x1ab4 seq_branch_adr 1ab4 MACRO_Execute_Vector,Check_In_Type 0aa0 0aa0 seq_br_type 3 Unconditional Branch; Flow J 0x14b6 seq_branch_adr 14b6 MACRO_Execute_Matrix,Check_In_Type 0aa1 0aa1 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa6 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa6 0x0aa6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa2 0aa2 seq_br_type 3 Unconditional Branch; Flow J 0x17bc seq_branch_adr 17bc MACRO_Execute_Variant_Record,Check_In_Formal_Type 0aa3 0aa3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b07 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b07 0x1b07 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa4 0aa4 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0aa5 0aa5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc47 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c47 0x0c47 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa6 0aa6 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aa7 0aa7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0aa8 ; -------------------------------------------------------------------------------------- 0aa8 ; 0x0118 Execute Any,Write_Unchecked 0aa8 ; -------------------------------------------------------------------------------------- 0aa8 MACRO_Execute_Any,Write_Unchecked: 0aa8 0aa8 dispatch_brk_class 2 ; Flow J cc=False 0x1d46 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0aa8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0aa9 0aa9 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a5 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aaa 0aaa seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xaad seq_br_type 0 Branch False seq_branch_adr 0aad 0x0aad seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 1f TOP - 1 typ_frame 4 0aab 0aab fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE 0aac 0aac seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 0aad 0aad fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR05:01 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0aae 0aae fiu_fill_mode_src 0 ; Flow J cc=False 0xab0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ab0 0x0ab0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 0aaf 0aaf fiu_fill_mode_src 0 ; Flow J 0xab3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ab3 0x0ab3 typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 0ab0 0ab0 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ab1 0ab1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ab2 0ab2 fiu_load_var 1 hold_var; Flow J 0xab3 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ab3 0x0ab3 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ab3 0ab3 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ab4 0ab4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0ab5 0ab5 <halt> ; Flow R 0ab6 ; -------------------------------------------------------------------------------------- 0ab6 ; 0x0117 Execute Any,Structure_Query 0ab6 ; -------------------------------------------------------------------------------------- 0ab6 MACRO_Execute_Any,Structure_Query: 0ab6 0ab6 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ab6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ab7 0ab7 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0xab9 fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0ab9 0x0ab9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl 6 INCREMENT_MAR 0ab8 0ab8 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 0ab9 ; -------------------------------------------------------------------------------------- 0ab9 ; Comes from: 0ab9 ; 0ab7 C #0x0 from color MACRO_Execute_Any,Structure_Query 0ab9 ; -------------------------------------------------------------------------------------- 0ab9 0ab9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0aba 0aba fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abb 0abb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abc 0abc fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0abd 0abd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_rand b CARRY IN = Q BIT FROM VAL 0abe 0abe seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 0abf 0abf seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac0 0ac0 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0ac1 0ac1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0xacb fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac2 0ac2 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xacc seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acc 0x0acc seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0ac3 0ac3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac4 0ac4 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3277 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0ac5 0ac5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac6 0ac6 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xac9 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0ac9 0x0ac9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac7 0ac7 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xac9 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0ac9 0x0ac9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac8 0ac8 fiu_mem_start 4 continue; Flow R cc=True ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0ac9 0x0ac9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac9 0ac9 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0aca 0aca fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0acb 0acb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR05:09 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0acc 0acc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0acd 0acd fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ace 0ace fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0xadd fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0add 0x0add seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR05:04 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0acf 0acf fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0ad0 0ad0 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xad5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ad5 0x0ad5 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ad1 0ad1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad2 0ad2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad3 0ad3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad4 0ad4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR05:0a val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0ad5 0ad5 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0xad1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ad1 0x0ad1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0ad6 0ad6 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ad7 0ad7 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xad1 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ad1 0x0ad1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0ad8 0ad8 typ_rand e CHECK_CLASS_SYSTEM_B val_rand 2 DEC_LOOP_COUNTER 0ad9 0ad9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2a82 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0ada 0ada seq_br_type 1 Branch True; Flow J cc=True 0xad7 seq_branch_adr 0ad7 0x0ad7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 0adb 0adb fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0adc 0adc ioc_tvbs 1 typ+fiu; Flow J 0xad3 seq_br_type 3 Unconditional Branch seq_branch_adr 0ad3 0x0ad3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0add ; -------------------------------------------------------------------------------------- 0add ; Comes from: 0add ; 0ace C True from color 0x0ac2 0add ; -------------------------------------------------------------------------------------- 0add 0add ioc_tvbs 3 fiu+fiu; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ade 0ade fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 0adf 0adf <halt> ; Flow R 0ae0 ; -------------------------------------------------------------------------------------- 0ae0 ; 0x0126 Execute Any,Has_Default_Initialization 0ae0 ; -------------------------------------------------------------------------------------- 0ae0 MACRO_Execute_Any,Has_Default_Initialization: 0ae0 0ae0 dispatch_brk_class 8 ; Flow J cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae1 0ae1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d 0ae2 0ae2 fiu_fill_mode_src 0 ; Flow J cc=False 0x32a5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 0ae3 0ae3 ioc_load_wdr 0 ; Flow J 0x9c7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 09c7 0x09c7 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ae4 ; -------------------------------------------------------------------------------------- 0ae4 ; 0x0111 Execute Any,Has_Repeated_Initialization 0ae4 ; -------------------------------------------------------------------------------------- 0ae4 MACRO_Execute_Any,Has_Repeated_Initialization: 0ae4 0ae4 dispatch_brk_class 8 ; Flow J cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae5 0ae5 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xae2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d seq_br_type 3 Unconditional Branch seq_branch_adr 0ae2 0x0ae2 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 ; 0x0110 Execute Any,Is_Initialization_Repeated 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 MACRO_Execute_Any,Is_Initialization_Repeated: 0ae6 0ae6 dispatch_brk_class 8 ; Flow J cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ae7 0ae7 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True ; Flow J cc=False 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 ; 0x012b Execute Any,Spare14 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 MACRO_Execute_Any,Spare14: 0ae8 0ae8 dispatch_brk_class 8 ; Flow J cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ae9 0ae9 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x32a5 fiu_offs_lit 3b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aea 0aea fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0aeb 0aeb <halt> ; Flow R 0aec ; -------------------------------------------------------------------------------------- 0aec ; 0x0387 Declare_Variable Package 0aec ; -------------------------------------------------------------------------------------- 0aec MACRO_Declare_Variable_Package: 0aec 0aec dispatch_brk_class 4 ; Flow J 0xaed dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0aec fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b49 0x0b49 seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0aed 0aed fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0aee 0aee ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3277 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0aef 0aef fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xb5d fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0b5d 0x0b5d typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 0af0 ; -------------------------------------------------------------------------------------- 0af0 ; 0x036f Declare_Variable Task 0af0 ; -------------------------------------------------------------------------------------- 0af0 MACRO_Declare_Variable_Task: 0af0 0af0 dispatch_brk_class 4 ; Flow J 0xaf1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af1 0af1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af2 0af2 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af3 0af3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0af4 0af4 seq_br_type 3 Unconditional Branch; Flow J 0xb5d seq_branch_adr 0b5d 0x0b5d typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0af5 0af5 <halt> ; Flow R 0af6 ; -------------------------------------------------------------------------------------- 0af6 ; 0x0386 Declare_Variable Package,Visible 0af6 ; -------------------------------------------------------------------------------------- 0af6 MACRO_Declare_Variable_Package,Visible: 0af6 0af6 dispatch_brk_class 4 ; Flow J 0xaf7 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b49 0x0b49 seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af7 0af7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR18:00 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af8 0af8 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3277 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af9 0af9 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5d fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0afa 0afa seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 0afb 0afb <halt> ; Flow R 0afc ; -------------------------------------------------------------------------------------- 0afc ; 0x036e Declare_Variable Task,Visible 0afc ; -------------------------------------------------------------------------------------- 0afc MACRO_Declare_Variable_Task,Visible: 0afc 0afc dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0afc fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0afd 0afd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xafe fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0afe 0afe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x32a8 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0aff 0aff fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 0b00 0b00 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0b01 0b01 seq_br_type 3 Unconditional Branch; Flow J 0xb5d seq_branch_adr 0b5d 0x0b5d typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b02 ; -------------------------------------------------------------------------------------- 0b02 ; 0x036d Declare_Variable Task,On_Processor 0b02 ; -------------------------------------------------------------------------------------- 0b02 MACRO_Declare_Variable_Task,On_Processor: 0b02 0b02 dispatch_brk_class 4 ; Flow C cc=True 0x326c dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b02 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b03 0b03 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b04 0b04 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b05 0b05 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb06 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b06 0b06 fiu_load_var 1 hold_var; Flow J 0xb5d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0b5d 0x0b5d typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b07 0b07 <halt> ; Flow R 0b08 ; -------------------------------------------------------------------------------------- 0b08 ; 0x036c Declare_Variable Task,Visible,On_Processor 0b08 ; -------------------------------------------------------------------------------------- 0b08 MACRO_Declare_Variable_Task,Visible,On_Processor: 0b08 0b08 dispatch_brk_class 4 ; Flow C cc=True 0x326c dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b08 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b09 0b09 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b0a 0b0a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b0b 0b0b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb0c fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b0c 0b0c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b0d 0b0d seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 typ_csa_cntl 3 POP_CSA 0b0e ; -------------------------------------------------------------------------------------- 0b0e ; 0x036b Declare_Variable Task,As_Component 0b0e ; -------------------------------------------------------------------------------------- 0b0e MACRO_Declare_Variable_Task,As_Component: 0b0e 0b0e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b0e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0b0f 0b0f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb10 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b10 0b10 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b11 0b11 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x32a9 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame c 0b12 0b12 fiu_load_var 1 hold_var; Flow C 0xb1d fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b1d 0x0b1d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b13 0b13 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5d fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 08 GP08 val_alu_func 1a PASS_B 0b14 0b14 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 0b15 0b15 <halt> ; Flow R 0b16 ; -------------------------------------------------------------------------------------- 0b16 ; 0x036a Declare_Variable Task,On_Processor,As_Component 0b16 ; -------------------------------------------------------------------------------------- 0b16 MACRO_Declare_Variable_Task,On_Processor,As_Component: 0b16 0b16 dispatch_brk_class 4 ; Flow C cc=True 0x326c dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b16 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b17 0b17 ioc_fiubs 1 val ; Flow J cc=True 0x32a9 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame c 0b18 0b18 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b19 0b19 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb1a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b1a 0b1a fiu_load_var 1 hold_var; Flow C 0xb1d fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 0b1d 0x0b1d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b1b 0b1b fiu_load_var 1 hold_var; Flow J cc=True 0xb5d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 1a PASS_B 0b1c 0b1c seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 0b1d 0b1d fiu_mem_start a start_continue_if_false; Flow J cc=False 0xb1f ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0b1f 0x0b1f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b1e 0b1e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b1f 0b1f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0b20 0b20 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b21 0b21 <halt> ; Flow R 0b22 ; -------------------------------------------------------------------------------------- 0b22 ; 0x0385 Declare_Variable Package,On_Processor 0b22 ; -------------------------------------------------------------------------------------- 0b22 MACRO_Declare_Variable_Package,On_Processor: 0b22 0b22 dispatch_brk_class 4 ; Flow C cc=True 0x326c dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b22 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b23 0b23 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b24 0b24 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb25 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b49 0x0b49 seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b25 0b25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b26 0b26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b27 0b27 seq_br_type 3 Unconditional Branch; Flow J 0x3277 seq_branch_adr 3277 0x3277 0b28 ; -------------------------------------------------------------------------------------- 0b28 ; 0x0384 Declare_Variable Package,Visible,On_Processor 0b28 ; -------------------------------------------------------------------------------------- 0b28 MACRO_Declare_Variable_Package,Visible,On_Processor: 0b28 0b28 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b28 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0b29 0b29 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x326c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b2a 0b2a ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b2b 0b2b fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb2c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b49 0x0b49 seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b2c 0b2c fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b2d 0b2d fiu_load_var 1 hold_var; Flow J cc=True 0xb5d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5d 0x0b5d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b2e 0b2e seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 0b2f 0b2f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 10 TOP 0b30 0b30 ioc_adrbs 1 val ; Flow C 0xb69 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b69 0x0b69 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b31 0b31 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0b32 0b32 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b33 0b33 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 0b34 0b34 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0xb35 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0b4c 0x0b4c typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 0b35 0b35 ioc_adrbs 1 val ; Flow R cc=False ; Flow J cc=True 0xb49 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0b49 0x0b49 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0b36 0b36 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_frame 2 0b37 0b37 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b38 0b38 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b39 0b39 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0b3a 0b3a fiu_mem_start 4 continue; Flow C cc=False 0x326c ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0b3b 0b3b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0b3c 0b3c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 25 VR11:05 val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 11 0b3d 0b3d ioc_load_wdr 0 ; Flow C cc=True 0x32a5 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1d val_b_adr 16 CSA/VAL_BUS 0b3e 0b3e ioc_fiubs 0 fiu ; Flow C cc=True 0xb48 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b48 0x0b48 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 10 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 0b3f 0b3f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 0b40 0b40 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b41 0b41 fiu_load_var 1 hold_var; Flow C 0xb5d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b5d 0x0b5d typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_a_adr 02 GP02 val_c_adr 2e TOP + 1 0b42 0b42 fiu_tivi_src c mar_0xc; Flow J cc=True 0xb46 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b46 0x0b46 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 16 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b43 0b43 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 0b44 0b44 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 16 CSA/VAL_BUS typ_frame 1b val_a_adr 24 VR11:04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 11 0b45 0b45 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0b46 0b46 seq_br_type 1 Branch True; Flow J cc=True 0x38e2 seq_branch_adr 38e2 0x38e2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 0b47 0b47 seq_br_type 3 Unconditional Branch; Flow J 0x38e2 seq_branch_adr 38e2 0x38e2 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 0b48 0b48 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 16 0b49 0b49 fiu_tivi_src c mar_0xc; Flow C 0x32ff ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32ff 0x32ff val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4a 0b4a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x38e2 seq_br_type 0 Branch False seq_branch_adr 38e2 0x38e2 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b4b 0b4b fiu_mem_start 2 start-rd; Flow J 0xb4f ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b4f 0x0b4f seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b4c 0b4c fiu_tivi_src c mar_0xc; Flow C 0x32fe ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fe 0x32fe val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4d 0b4d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x38e2 seq_br_type 0 Branch False seq_branch_adr 38e2 0x38e2 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b4e 0b4e fiu_mem_start 2 start-rd; Flow J 0xb4f ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b4f 0x0b4f seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b4f 0b4f seq_br_type 2 Push (branch address); Flow J 0xb50 seq_branch_adr 0b47 0x0b47 0b50 0b50 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x38e2 seq_br_type 9 Return False seq_branch_adr 38e2 0x38e2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 0b51 ; -------------------------------------------------------------------------------------- 0b51 ; Comes from: 0b51 ; 0903 C from color 0x0903 0b51 ; -------------------------------------------------------------------------------------- 0b51 0b51 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb72 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b72 0x0b72 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b52 0b52 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb59 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b59 0x0b59 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b53 0b53 ioc_fiubs 1 val ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b54 0b54 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b55 0b55 fiu_tivi_src c mar_0xc; Flow C 0xb7b ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7b 0x0b7b seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b56 0b56 fiu_load_var 1 hold_var; Flow J cc=True 0xb54 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b54 0x0b54 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b57 0b57 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5a fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b5a 0x0b5a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl a LOAD_MAR_IMPORT 0b58 0b58 seq_br_type 3 Unconditional Branch; Flow J 0xb51 seq_branch_adr 0b51 0x0b51 seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b59 0b59 fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x32a1 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b5a 0b5a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b5b 0b5b fiu_load_var 1 hold_var; Flow C 0xb76 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b76 0x0b76 seq_en_micro 0 0b5c 0b5c ioc_adrbs 1 val ; Flow J 0x3417 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3417 0x3417 seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b5d 0b5d fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb72 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b72 0x0b72 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b5e 0b5e fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb65 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b65 0x0b65 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b5f 0b5f ioc_fiubs 1 val ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b60 0b60 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b61 0b61 fiu_tivi_src c mar_0xc; Flow C 0xb7b ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7b 0x0b7b seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b62 0b62 fiu_load_var 1 hold_var; Flow J cc=True 0xb60 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b60 0x0b60 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b63 0b63 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb66 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b66 0x0b66 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0b64 0b64 seq_br_type 3 Unconditional Branch; Flow J 0xb5d seq_branch_adr 0b5d 0x0b5d seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b65 0b65 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x32a1 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b66 0b66 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b67 0b67 fiu_load_var 1 hold_var; Flow C 0xb76 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b76 0x0b76 seq_en_micro 0 0b68 0b68 ioc_adrbs 1 val ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b69 0b69 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b6a 0b6a fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb72 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 0b72 0x0b72 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b6b 0b6b ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0b6c 0b6c ioc_adrbs 1 val ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 0 PASS_A 0b6d 0b6d seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a1 seq_br_type 9 Return False seq_branch_adr 32a1 0x32a1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0b6e 0b6e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0b6f 0b6f fiu_len_fill_lit 55 zero-fill 0x15; Flow C cc=False 0x32c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 19 X_XOR_B val_b_adr 10 TOP 0b70 0b70 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b71 0b71 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR08:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 8 0b72 ; -------------------------------------------------------------------------------------- 0b72 ; Comes from: 0b72 ; 0b51 C from color 0x0000 0b72 ; 0b5d C from color 0x0000 0b72 ; 0b6a C from color 0x0000 0b72 ; -------------------------------------------------------------------------------------- 0b72 0b72 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM 0b73 0b73 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0b74 0b74 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 35 VR09:15 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 0b75 0b75 fiu_len_fill_lit 55 zero-fill 0x15; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0f GP0f 0b76 ; -------------------------------------------------------------------------------------- 0b76 ; Comes from: 0b76 ; 0b5b C from color 0x0000 0b76 ; 0b67 C from color 0x0000 0b76 ; -------------------------------------------------------------------------------------- 0b76 0b76 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0b77 0b77 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 0b78 0b78 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b79 0b79 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0b7a 0b7a fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0e GP0e 0b7b ; -------------------------------------------------------------------------------------- 0b7b ; Comes from: 0b7b ; 0b55 C from color 0x0000 0b7b ; 0b61 C from color 0x0000 0b7b ; -------------------------------------------------------------------------------------- 0b7b 0b7b seq_br_type 7 Unconditional Call; Flow C 0xb83 seq_branch_adr 0b83 0x0b83 seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b7c 0b7c fiu_tivi_src c mar_0xc; Flow J cc=True 0xb80 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b80 0x0b80 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 5 0b7d 0b7d fiu_tivi_src c mar_0xc; Flow C 0xb83 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b83 0x0b83 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b7e 0b7e fiu_tivi_src c mar_0xc; Flow C 0xb83 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b83 0x0b83 seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b7f 0b7f fiu_tivi_src c mar_0xc; Flow C 0xb83 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b83 0x0b83 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0b80 0b80 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 0b81 0x0b81 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_a_adr 0b GP0b val_alu_func 19 X_XOR_B val_b_adr 0c GP0c 0b81 0b81 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0b82 0x0b82 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 6 A_MINUS_B typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 0b GP0b 0b82 0b82 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0b83 ; -------------------------------------------------------------------------------------- 0b83 ; Comes from: 0b83 ; 0b7b C from color 0x0b7b 0b83 ; 0b7d C from color 0x0b7b 0b83 ; 0b7e C from color 0x0b7b 0b83 ; 0b7f C from color 0x0b7b 0b83 ; -------------------------------------------------------------------------------------- 0b83 0b83 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 0b84 0b84 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0b85 0b85 seq_b_timing 0 Early Condition; Flow J cc=True 0xb89 seq_br_type 1 Branch True seq_branch_adr 0b89 0x0b89 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b86 0b86 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b87 0b87 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 12 start_lru_query fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 val_rand 2 DEC_LOOP_COUNTER 0b88 0b88 seq_b_timing 0 Early Condition; Flow J cc=False 0xb86 seq_br_type 0 Branch False seq_branch_adr 0b86 0x0b86 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b89 0b89 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b8a 0b8a fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0b8b 0b8b fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 0b8c 0b8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b8d 0b8d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0c GP0c 0b8e 0b8e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 0f GP0f typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0f GP0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b8f 0b8f <halt> ; Flow R 0b90 ; -------------------------------------------------------------------------------------- 0b90 ; Comes from: 0b90 ; 0879 C from color 0x0821 0b90 ; -------------------------------------------------------------------------------------- 0b90 0b90 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2d TR1d:0d typ_frame 1d val_c_adr 04 VR0d:1b val_c_source 0 FIU_BUS val_frame d 0b91 0b91 fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 09 TR0d:16 typ_c_mux_sel 0 ALU typ_frame d 0b92 0b92 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 34 VR02:14 val_frame 2 0b93 0b93 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xba2 seq_br_type 1 Branch True seq_branch_adr 0ba2 0x0ba2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0b94 0b94 ioc_fiubs 1 val ; Flow C 0x2a82 seq_br_type 7 Unconditional Call seq_branch_adr 2a82 0x2a82 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 3b VR0d:1b val_frame d 0b95 0b95 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b96 0b96 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 26 TR05:06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0b97 0b97 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b98 0b98 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_c_adr 02 TR0d:1d typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b99 0b99 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 0a TR0d:15 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 01 GP01 val_b_adr 01 GP01 0b9a 0b9a fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xba1 fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ba1 0x0ba1 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b9b 0b9b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 12 TR1d:0d typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_frame 5 0b9c 0b9c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR08:1a val_frame 8 0b9d 0b9d fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d 0b9e 0b9e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 0b9f 0b9f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 0a VR0d:15 val_c_source 0 FIU_BUS val_frame d 0ba0 0ba0 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 35 VR0d:15 val_alu_func 1c DEC_A val_c_adr 0a VR0d:15 val_c_mux_sel 2 ALU val_frame d 0ba1 0ba1 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0xba8 seq_br_type 8 Return True seq_branch_adr 0ba8 0x0ba8 seq_en_micro 0 val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 0ba2 0ba2 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 12 TR1d:0d typ_c_source 0 FIU_BUS typ_frame 1d val_a_adr 3b VR0d:1b val_frame d 0ba3 0ba3 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 3e VR05:1e val_frame 5 0ba4 0ba4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ba5 0ba5 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl 6 INCREMENT_MAR 0ba6 0ba6 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 3d TR0d:1d typ_frame d val_b_adr 39 VR02:19 val_frame 2 0ba7 0ba7 fiu_tivi_src 8 type_var; Flow C 0x2a82 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a82 0x2a82 seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d typ_mar_cntl 5 RESTORE_MAR_REFRESH 0ba8 0ba8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0ba9 ; -------------------------------------------------------------------------------------- 0ba9 ; Comes from: 0ba9 ; 013a C from color 0x0000 0ba9 ; 361b C True from color 0x0000 0ba9 ; -------------------------------------------------------------------------------------- 0ba9 0ba9 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xbab fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bab 0x0bab seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 14 ZEROS typ_c_adr 0d TR0d:12 typ_frame d val_a_adr 24 VR09:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 9 0baa 0baa fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR12:10 typ_frame 12 0bab 0bab fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 38 TR0d:18 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0bac 0bac fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xbad ; Flow J cc=#0x0 0xbb0 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0bb0 0x0bb0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 34 TR0d:14 typ_c_adr 0f TR0d:10 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 0f VR0d:10 val_c_mux_sel 2 ALU val_frame d 0bad 0bad ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 0a TR0d:15 typ_c_mux_sel 0 ALU typ_frame d val_b_adr 0f GP0f val_c_adr 0d VR0d:12 val_frame d 0bae 0bae seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xbb4 seq_br_type 0 Branch False seq_branch_adr 0bb4 0x0bb4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d 0baf 0baf fiu_len_fill_lit 4a zero-fill 0xa; Flow J 0xbd2 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bd2 0x0bd2 seq_en_micro 0 typ_c_adr 04 TR0d:1b typ_c_source 0 FIU_BUS typ_frame d 0bb0 0bb0 fiu_mem_start 3 start-wr; Flow J 0xbad ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bad 0x0bad seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb1 0bb1 fiu_mem_start 3 start-wr; Flow J 0xbad ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bad 0x0bad seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb2 0bb2 fiu_mem_start 3 start-wr; Flow J 0xbad ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bad 0x0bad seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bb3 0bb3 fiu_mem_start 3 start-wr; Flow J 0xbad ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bad 0x0bad seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bb4 0bb4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbd0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd0 0x0bd0 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bb5 0bb5 fiu_tivi_src 1 tar_val; Flow J cc=False 0xbbc ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0bbc 0x0bbc seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bb6 0bb6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bb7 0bb7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xbd0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0bd0 0x0bd0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bb8 0bb8 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc3 0x0bc3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d 0bb9 0bb9 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xbbd fiu_mem_start 3 start-wr fiu_offs_lit 40 seq_br_type 1 Branch True seq_branch_adr 0bbd 0x0bbd seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR0d:13 typ_alu_func 1c DEC_A typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 33 VR0d:13 val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bba 0bba fiu_mem_start 8 start_wr_if_false; Flow J 0xbbb fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbb 0x0bbb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbb 0bbb ioc_load_wdr 0 ; Flow J 0xbd0 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd0 0x0bd0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bbc 0bbc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbd 0bbd fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xbd0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0bd0 0x0bd0 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bbe 0bbe fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc3 0x0bc3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame d 0bbf 0bbf fiu_mem_start 3 start-wr; Flow J cc=True 0xbc1 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0bc1 0x0bc1 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bc0 0bc0 fiu_mem_start 8 start_wr_if_false; Flow J 0xbbb fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbb 0x0bbb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_b_adr 34 TR0d:14 typ_frame d val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bc1 0bc1 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bc2 0bc2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbb5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bb5 0x0bb5 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bc3 0bc3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xbd0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd0 0x0bd0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bc4 0bc4 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS 0bc5 0bc5 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bc6 0bc6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bc7 0bc7 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bc8 0bc8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bc9 0bc9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bca 0bca seq_b_timing 0 Early Condition; Flow J cc=True 0xbcb ; Flow J cc=#0x0 0xbcb seq_br_type b Case False seq_branch_adr 0bcb 0x0bcb seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bcb 0bcb fiu_mem_start 3 start-wr; Flow J 0xbcf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bcf 0x0bcf seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bcc 0bcc fiu_mem_start 3 start-wr; Flow J 0xbcf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bcf 0x0bcf seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bcd 0bcd fiu_mem_start 3 start-wr; Flow J 0xbcf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bcf 0x0bcf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bce 0bce fiu_mem_start 3 start-wr; Flow J 0xbcf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bcf 0x0bcf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bcf 0bcf ioc_load_wdr 0 ; Flow J 0xbd0 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd0 0x0bd0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0bd0 0bd0 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0bd1 0x0bd1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bd1 0bd1 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0bd2 0bd2 fiu_tivi_src 1 tar_val; Flow C 0xbe8 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0be8 0x0be8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bd3 0bd3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0bd4 0bd4 seq_en_micro 0 0bd5 0bd5 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xbe5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0be5 0x0be5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0bd6 0bd6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbdd fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bdd 0x0bdd seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 03 VR0d:1c val_c_source 0 FIU_BUS val_frame d 0bd7 0bd7 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xc02 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0c02 0x0c02 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR0d:1d val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame d 0bd8 0bd8 seq_en_micro 0 0bd9 0bd9 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xbe5 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be5 0x0be5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0bda 0bda fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 03 VR0d:1c val_c_mux_sel 2 ALU val_frame d 0bdb 0bdb fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0xbe5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be5 0x0be5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bdc 0bdc fiu_mem_start 2 start-rd; Flow J cc=False 0xbe5 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 0be5 0x0be5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bdd 0bdd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe5 seq_br_type 1 Branch True seq_branch_adr 0be5 0x0be5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR0d:1b typ_alu_func 1c DEC_A typ_c_adr 04 TR0d:1b typ_c_mux_sel 0 ALU typ_frame d 0bde 0bde ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xbe5 seq_br_type 0 Branch False seq_branch_adr 0be5 0x0be5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bdf 0bdf fiu_tivi_src c mar_0xc; Flow C 0xbe8 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0be8 0x0be8 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be0 0be0 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR0d:1a val_alu_func 1 A_PLUS_B val_b_adr 3d VR0d:1d val_frame d 0be1 0be1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe5 seq_br_type 1 Branch True seq_branch_adr 0be5 0x0be5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 3d VR0d:1d val_alu_func 6 A_MINUS_B val_b_adr 3a VR0d:1a val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be2 0be2 seq_br_type 0 Branch False; Flow J cc=False 0xbe5 seq_branch_adr 0be5 0x0be5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0be3 0be3 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0xbd7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd7 0x0bd7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 0be4 0be4 fiu_mem_start 2 start-rd; Flow J cc=True 0xbdd ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 0bdd 0x0bdd seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0be5 0be5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0be6 0be6 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0be7 0be7 seq_br_type 3 Unconditional Branch; Flow J 0xc02 seq_branch_adr 0c02 0x0c02 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 3d TR0d:1d typ_alu_func 7 INC_A typ_c_adr 02 TR0d:1d typ_c_mux_sel 0 ALU typ_frame d 0be8 0be8 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 0be9 0be9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbec fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0bec 0x0bec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bea 0bea fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0beb 0beb ioc_load_wdr 0 ; Flow J 0xc02 seq_br_type 3 Unconditional Branch seq_branch_adr 0c02 0x0c02 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bec 0bec seq_b_timing 0 Early Condition; Flow J cc=False 0xbf1 seq_br_type 0 Branch False seq_branch_adr 0bf1 0x0bf1 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 0bed 0bed fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0bee 0x0bee seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bee 0bee fiu_mem_start 3 start-wr ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bef 0bef ioc_tvbs 1 typ+fiu; Flow J cc=True 0xc01 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c01 0x0c01 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 01 TR0d:1e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0bf0 0bf0 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False ; Flow J cc=True 0xbf5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf5 0x0bf5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 3e TR0d:1e typ_frame d 0bf1 0bf1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0bf2 0x0bf2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bf2 0bf2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bf3 0bf3 ioc_tvbs 2 fiu+val; Flow J cc=True 0xc01 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c01 0x0c01 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 01 VR0d:1e val_c_mux_sel 2 ALU val_frame d 0bf4 0bf4 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf5 0x0bf5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 3e VR0d:1e val_frame d 0bf5 0bf5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bf6 0bf6 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_b_adr 0f GP0f 0bf7 0bf7 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bf8 0bf8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bf9 0bf9 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bfa 0bfa fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bfb 0bfb fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bfc 0bfc seq_b_timing 0 Early Condition; Flow J cc=True 0xbfd ; Flow J cc=#0x0 0xbfd seq_br_type b Case False seq_branch_adr 0bfd 0x0bfd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bfd 0bfd fiu_mem_start 3 start-wr; Flow J 0xc01 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c01 0x0c01 seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bfe 0bfe fiu_mem_start 3 start-wr; Flow J 0xc01 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c01 0x0c01 seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bff 0bff fiu_mem_start 3 start-wr; Flow J 0xc01 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c01 0x0c01 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0c00 0c00 fiu_mem_start 3 start-wr; Flow J 0xc01 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c01 0x0c01 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0c01 0c01 ioc_load_wdr 0 ; Flow J 0xc02 seq_br_type 3 Unconditional Branch seq_branch_adr 0c02 0x0c02 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0f GP0f val_b_adr 0f GP0f 0c02 0c02 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0c03 0x0c03 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0c03 0c03 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0c04 ; -------------------------------------------------------------------------------------- 0c04 ; 0x021f Execute Heap_Access,Equal 0c04 ; -------------------------------------------------------------------------------------- 0c04 MACRO_Execute_Heap_Access,Equal: 0c04 0c04 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c04 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c05 0c05 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0c06 ; -------------------------------------------------------------------------------------- 0c06 ; 0x021e Execute Heap_Access,Maximum 0c06 ; -------------------------------------------------------------------------------------- 0c06 MACRO_Execute_Heap_Access,Maximum: 0c06 0c06 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c06 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c07 0c07 <halt> ; Flow R 0c08 ; -------------------------------------------------------------------------------------- 0c08 ; 0x021d Execute Heap_Access,Is_Null 0c08 ; -------------------------------------------------------------------------------------- 0c08 MACRO_Execute_Heap_Access,Is_Null: 0c08 0c08 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c08 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c09 0c09 <halt> ; Flow R 0c0a ; -------------------------------------------------------------------------------------- 0c0a ; 0x021c Execute Heap_Access,Not_Null 0c0a ; -------------------------------------------------------------------------------------- 0c0a MACRO_Execute_Heap_Access,Not_Null: 0c0a 0c0a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c0b 0c0b <halt> ; Flow R 0c0c ; -------------------------------------------------------------------------------------- 0c0c ; 0x021b Execute Heap_Access,Set_Null 0c0c ; -------------------------------------------------------------------------------------- 0c0c MACRO_Execute_Heap_Access,Set_Null: 0c0c 0c0c dispatch_brk_class 8 ; Flow J cc=True 0xc10 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0c fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c10 0x0c10 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_lit 2 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c0d 0c0d fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a5 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c0e 0c0e fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 0c0f 0c0f ioc_load_wdr 0 ; Flow J 0xc05 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0c05 0x0c05 val_b_adr 39 VR02:19 val_frame 2 0c10 0c10 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3277 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 0c11 0c11 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0xc13 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c13 0x0c13 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 0c12 0c12 fiu_fill_mode_src 0 ; Flow J 0xc16 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c16 0x0c16 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0c13 0c13 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c14 0c14 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c15 0c15 fiu_load_var 1 hold_var; Flow J 0xc16 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c16 0x0c16 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c16 0c16 ioc_load_wdr 0 ; Flow J 0xc05 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c05 0x0c05 0c17 0c17 <halt> ; Flow R 0c18 ; -------------------------------------------------------------------------------------- 0c18 ; 0x021a Execute Heap_Access,Element_Type 0c18 ; -------------------------------------------------------------------------------------- 0c18 MACRO_Execute_Heap_Access,Element_Type: 0c18 0c18 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c18 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 0c19 0c19 fiu_load_tar 1 hold_tar; Flow J cc=False 0xc1c fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c1c 0x0c1c seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 0c1a 0c1a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 0c1b 0c1b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 0c1c 0c1c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c1d 0x0c1d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c1d 0c1d seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 seq_random 02 ? 0c1e ; -------------------------------------------------------------------------------------- 0c1e ; 0x0219 Execute Heap_Access,All_Read 0c1e ; -------------------------------------------------------------------------------------- 0c1e MACRO_Execute_Heap_Access,All_Read: 0c1e 0c1e dispatch_brk_class 8 ; Flow C cc=True 0x326f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c1e dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 0c1f 0c1f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc25 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c25 0x0c25 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c20 0c20 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c21 0c21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc23 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c23 0x0c23 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0c22 0c22 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc26 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c26 0x0c26 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c23 0c23 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c24 0c24 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc26 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c26 0x0c26 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c25 0c25 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c26 0c26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0c27 0x0c27 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c27 0c27 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c28 ; -------------------------------------------------------------------------------------- 0c28 ; 0x0218 Execute Heap_Access,All_Write 0c28 ; -------------------------------------------------------------------------------------- 0c28 MACRO_Execute_Heap_Access,All_Write: 0c28 0c28 dispatch_brk_class 2 ; Flow C cc=True 0x326f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c28 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c29 0c29 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0c2a 0c2a fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c2b 0c2b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 0c2c 0c2c fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 0c2d 0c2d <halt> ; Flow R 0c2e ; -------------------------------------------------------------------------------------- 0c2e ; 0x0217 Execute Heap_Access,All_Reference 0c2e ; -------------------------------------------------------------------------------------- 0c2e MACRO_Execute_Heap_Access,All_Reference: 0c2e 0c2e dispatch_brk_class 8 ; Flow C cc=True 0x326f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c2e dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c2f 0c2f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 0c30 ; -------------------------------------------------------------------------------------- 0c30 ; 0x0216 Execute Heap_Access,Convert 0c30 ; -------------------------------------------------------------------------------------- 0c30 MACRO_Execute_Heap_Access,Convert: 0c30 0c30 dispatch_brk_class 4 ; Flow J cc=True 0xc32 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c30 seq_br_type 1 Branch True seq_branch_adr 0c32 0x0c32 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0c31 0c31 seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c32 0c32 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc49 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c33 0c33 <halt> ; Flow R 0c34 ; -------------------------------------------------------------------------------------- 0c34 ; 0x0211 Execute Heap_Access,Convert_Reference 0c34 ; -------------------------------------------------------------------------------------- 0c34 MACRO_Execute_Heap_Access,Convert_Reference: 0c34 0c34 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c34 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c35 0c35 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 0c36 0c36 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0c37 0c37 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 0c38 0c38 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0c39 0x0c39 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c39 0c39 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_csa_cntl 3 POP_CSA 0c3a ; -------------------------------------------------------------------------------------- 0c3a ; 0x0215 Execute Heap_Access,In_Type 0c3a ; -------------------------------------------------------------------------------------- 0c3a MACRO_Execute_Heap_Access,In_Type: 0c3a 0c3a dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c3a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3b 0x0c3b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c3b 0c3b ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c3c 0c3c typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c3d 0c3d seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c3e 0c3e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c3f 0c3f <halt> ; Flow R 0c40 ; -------------------------------------------------------------------------------------- 0c40 ; 0x0214 Execute Heap_Access,Not_In_Type 0c40 ; -------------------------------------------------------------------------------------- 0c40 MACRO_Execute_Heap_Access,Not_In_Type: 0c40 0c40 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c40 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c41 0x0c41 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c41 0c41 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c42 0c42 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c43 0c43 seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c44 0c44 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c45 0c45 <halt> ; Flow R 0c46 ; -------------------------------------------------------------------------------------- 0c46 ; 0x0213 Execute Heap_Access,Check_In_Type 0c46 ; -------------------------------------------------------------------------------------- 0c46 MACRO_Execute_Heap_Access,Check_In_Type: 0c46 0c46 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c46 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c47 0x0c47 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0c47 0c47 seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c48 0c48 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c49 0c49 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0c4a 0c4a <default> 0c4b 0c4b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 0c4c 0c4c seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 0c4d 0c4d <halt> ; Flow R 0c4e ; -------------------------------------------------------------------------------------- 0c4e ; 0x0212 Execute Heap_Access,Address 0c4e ; -------------------------------------------------------------------------------------- 0c4e MACRO_Execute_Heap_Access,Address: 0c4e 0c4e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c4e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 0c4f 0c4f <halt> ; Flow R 0c50 ; -------------------------------------------------------------------------------------- 0c50 ; 0x0210 Execute Heap_Access,Get_Segment 0c50 ; -------------------------------------------------------------------------------------- 0c50 MACRO_Execute_Heap_Access,Get_Segment: 0c50 0c50 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c50 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0c51 0c51 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c52 ; -------------------------------------------------------------------------------------- 0c52 ; 0x0144 Execute Heap_Access,Get_Name 0c52 ; -------------------------------------------------------------------------------------- 0c52 MACRO_Execute_Heap_Access,Get_Name: 0c52 0c52 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c52 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0c53 0c53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c54 ; -------------------------------------------------------------------------------------- 0c54 ; 0x0148 Execute Heap_Access,Get_Offset 0c54 ; -------------------------------------------------------------------------------------- 0c54 MACRO_Execute_Heap_Access,Get_Offset: 0c54 0c54 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c54 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0c55 0c55 <halt> ; Flow R 0c56 ; -------------------------------------------------------------------------------------- 0c56 ; 0x0147 Execute Heap_Access,Construct_Segment 0c56 ; -------------------------------------------------------------------------------------- 0c56 MACRO_Execute_Heap_Access,Construct_Segment: 0c56 0c56 dispatch_brk_class 8 ; Flow C cc=True 0x32af dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c56 fiu_len_fill_lit 55 zero-fill 0x15 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32af 0x32af seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR08:01 val_frame 8 0c57 0c57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32af fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32af 0x32af seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 0c58 0c58 fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 30 TR0b:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c59 0c59 <halt> ; Flow R 0c5a ; -------------------------------------------------------------------------------------- 0c5a ; 0x0146 Execute Heap_Access,Hash 0c5a ; -------------------------------------------------------------------------------------- 0c5a MACRO_Execute_Heap_Access,Hash: 0c5a 0c5a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c5a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0c5b 0c5b ioc_tvbs 1 typ+fiu typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c5c 0c5c fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c5d 0x0c5d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0c5d 0c5d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c5e ; -------------------------------------------------------------------------------------- 0c5e ; 0x0145 Execute Heap_Access,Diana_Tree_Kind 0c5e ; -------------------------------------------------------------------------------------- 0c5e MACRO_Execute_Heap_Access,Diana_Tree_Kind: 0c5e 0c5e dispatch_brk_class 8 ; Flow J cc=True 0xc63 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c5e fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c63 0x0c63 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c5f 0c5f fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc61 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c61 0x0c61 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 0c60 0c60 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c61 0c61 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c62 0c62 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c63 0c63 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0c64 0c64 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a7 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c65 ; -------------------------------------------------------------------------------------- 0c65 ; Comes from: 0c65 ; 0c70 C from color MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci 0c65 ; 0c74 C from color MACRO_Execute_Discrete,Diana_Arity_For_Kind 0c65 ; 0c76 C from color MACRO_Execute_Discrete,Diana_Spare0 0c65 ; 0c78 C from color MACRO_Execute_Discrete,Diana_Spare2 0c65 ; -------------------------------------------------------------------------------------- 0c65 0c65 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x326c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326c 0x326c seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2b TR09:0b typ_frame 9 val_a_adr 05 GP05 0c66 0c66 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0xc67 ; Flow J cc=#0x0 0xc67 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0c67 0x0c67 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR06:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 35 VR06:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0c67 0c67 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c68 0c68 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c69 0c69 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6a 0c6a fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6b 0c6b fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6c 0c6c fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6d 0c6d fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6e 0c6e fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6f 0c6f <halt> ; Flow R 0c70 ; -------------------------------------------------------------------------------------- 0c70 ; 0x008f Execute Discrete,Diana_Map_Kind_To_Vci 0c70 ; -------------------------------------------------------------------------------------- 0c70 MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci: 0c70 0c70 dispatch_brk_class 8 ; Flow C 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c70 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c71 0c71 fiu_len_fill_lit 46 zero-fill 0x6; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0c72 0x0c72 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0c72 0c72 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0c73 0c73 <halt> ; Flow R 0c74 ; -------------------------------------------------------------------------------------- 0c74 ; 0x008e Execute Discrete,Diana_Arity_For_Kind 0c74 ; -------------------------------------------------------------------------------------- 0c74 MACRO_Execute_Discrete,Diana_Arity_For_Kind: 0c74 0c74 dispatch_brk_class 8 ; Flow C 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c74 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c75 0c75 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c76 ; -------------------------------------------------------------------------------------- 0c76 ; 0x008a Execute Discrete,Diana_Spare0 0c76 ; -------------------------------------------------------------------------------------- 0c76 MACRO_Execute_Discrete,Diana_Spare0: 0c76 0c76 dispatch_brk_class 8 ; Flow C 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c76 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c77 0c77 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c78 ; -------------------------------------------------------------------------------------- 0c78 ; 0x0087 Execute Discrete,Diana_Spare2 0c78 ; -------------------------------------------------------------------------------------- 0c78 MACRO_Execute_Discrete,Diana_Spare2: 0c78 0c78 dispatch_brk_class 8 ; Flow C 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c78 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c79 0c79 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c7a ; -------------------------------------------------------------------------------------- 0c7a ; 0x008d Execute Heap_Access,Diana_Allocate_Tree_Node 0c7a ; -------------------------------------------------------------------------------------- 0c7a MACRO_Execute_Heap_Access,Diana_Allocate_Tree_Node: 0c7a 0c7a dispatch_brk_class 8 ; Flow C 0xc65 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c7a fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 typ_a_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c7b 0c7b ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 12 0c7c 0c7c fiu_tivi_src c mar_0xc; Flow J 0xc7d ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0c85 0x0c85 typ_a_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 0c7d 0c7d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xc82 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c82 0x0c82 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR12:1e typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 0c7e 0c7e seq_b_timing 1 Latch Condition; Flow J cc=True 0xc81 seq_br_type 1 Branch True seq_branch_adr 0c81 0x0c81 seq_random 05 ? typ_a_adr 20 TR13:00 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c7f 0c7f fiu_mem_start 2 start-rd; Flow J cc=True 0x3594 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3594 0x3594 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR09:1f val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 9 0c80 0c80 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0c81 0c81 fiu_mem_start 2 start-rd; Flow J 0x3594 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3594 0x3594 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 33 VR05:13 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 0c82 0c82 fiu_len_fill_lit 4e zero-fill 0xe fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c83 0c83 fiu_fill_mode_src 0 ; Flow J cc=False 0x3594 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 0c84 0c84 seq_br_type 7 Unconditional Call; Flow C 0x3594 seq_branch_adr 3594 0x3594 val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 13 0c85 0c85 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3f TR12:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c86 0c86 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 val_b_adr 10 TOP 0c87 0c87 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0xc89 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c89 0x0c89 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c88 0c88 fiu_len_fill_lit 50 zero-fill 0x10 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0c89 0c89 fiu_fill_mode_src 0 ; Flow J cc=False 0xc8d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c8d 0x0c8d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0c8a 0c8a fiu_fill_mode_src 0 ; Flow J 0xc8b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c8b 0x0c8b typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c8b 0c8b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c8c 0c8c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0c8d 0c8d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 0c8e 0c8e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c8f 0c8f fiu_load_var 1 hold_var; Flow J 0xc8b fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8b 0x0c8b seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c90 ; -------------------------------------------------------------------------------------- 0c90 ; 0x008c Execute Heap_Access,Diana_Put_Node_On_Seq_Type 0c90 ; -------------------------------------------------------------------------------------- 0c90 MACRO_Execute_Heap_Access,Diana_Put_Node_On_Seq_Type: 0c90 0c90 dispatch_brk_class 8 ; Flow J cc=True 0x326f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c90 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326f 0x326f seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c91 0c91 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc93 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c93 0x0c93 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0c92 0c92 fiu_fill_mode_src 0 ; Flow J 0xc95 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c95 0x0c95 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c93 0c93 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c94 0c94 fiu_fill_mode_src 0 ; Flow J 0xc95 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c95 0x0c95 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c95 0c95 fiu_len_fill_lit 7c zero-fill 0x3c; Flow C 0xc65 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 0c65 0x0c65 val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c96 0c96 ioc_fiubs 2 typ ; Flow J cc=True 0xc9e ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c9e 0x0c9e seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR13:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 12 0c97 0c97 fiu_len_fill_lit 5a zero-fill 0x1a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0c98 0c98 fiu_fill_mode_src 0 ; Flow J cc=False 0xc9b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c9b 0x0c9b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 0c99 0c99 fiu_fill_mode_src 0 ; Flow J 0xc9a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c9a 0x0c9a typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c9a 0c9a ioc_load_wdr 0 ; Flow J 0xc8c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8c 0x0c8c typ_a_adr 2e TR0b:0e typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c9b 0c9b fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c9c 0c9c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c9d 0c9d fiu_load_var 1 hold_var; Flow J 0xc9a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c9a 0x0c9a seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c9e 0c9e fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c9f 0c9f fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca0 0ca0 fiu_fill_mode_src 0 ; Flow J cc=False 0xca4 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ca4 0x0ca4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 0ca1 0ca1 fiu_fill_mode_src 0 ; Flow J 0xca2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ca2 0x0ca2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0ca2 0ca2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 2a VR13:0a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0ca3 0ca3 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0xc98 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0c98 0x0c98 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca4 0ca4 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ca5 0ca5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ca6 0ca6 fiu_load_var 1 hold_var; Flow J 0xca2 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ca2 0x0ca2 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ca7 0ca7 <halt> ; Flow R 0ca8 ; -------------------------------------------------------------------------------------- 0ca8 ; 0x008b Execute Heap_Access,Diana_Seq_Type_Get_Head 0ca8 ; -------------------------------------------------------------------------------------- 0ca8 MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head: 0ca8 0ca8 dispatch_brk_class 8 ; Flow J cc=True 0xcb1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ca8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb1 0x0cb1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0ca9 0ca9 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0caa 0caa fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cab 0cab fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0cac 0x0cac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0cac 0cac fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0cad 0cad fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcaf seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0caf 0x0caf seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cae 0cae fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0caf 0caf fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cb0 0cb0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb1 0cb1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cb2 ; -------------------------------------------------------------------------------------- 0cb2 ; 0x0089 Execute Discrete,Diana_Spare1 0cb2 ; -------------------------------------------------------------------------------------- 0cb2 MACRO_Execute_Discrete,Diana_Spare1: 0cb2 0cb2 dispatch_brk_class 8 ; Flow J cc=True 0xcb7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cb2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 1e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb7 0x0cb7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0cb3 0cb3 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xcb6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb6 0x0cb6 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1e A_AND_B typ_b_adr 27 TR13:07 typ_frame 13 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand 9 PASS_A_HIGH 0cb4 0cb4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_b_adr 38 TR11:18 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0cb5 0cb5 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb6 0cb6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32ac ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32ac 0x32ac seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cb7 0cb7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0cb8 ; -------------------------------------------------------------------------------------- 0cb8 ; 0x0088 Execute Heap_Access,Diana_Spare2 0cb8 ; -------------------------------------------------------------------------------------- 0cb8 MACRO_Execute_Heap_Access,Diana_Spare2: 0cb8 0cb8 dispatch_brk_class 8 ; Flow J cc=True 0xcd1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0cb8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd1 0x0cd1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 0cb9 0cb9 fiu_mem_start 2 start-rd; Flow J cc=True 0xcd2 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd2 0x0cd2 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0cba 0cba typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0cbb 0cbb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cbc 0cbc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcc0 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0cc0 0x0cc0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cbd 0cbd fiu_load_tar 1 hold_tar; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cbe 0cbe fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cbf 0cbf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc5 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc5 0x0cc5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc0 0cc0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc5 0x0cc5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc1 0cc1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc5 0x0cc5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc2 0cc2 ioc_load_wdr 0 ; Flow J cc=True 0xcc5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc5 0x0cc5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_rand 1 INC_LOOP_COUNTER 0cc3 0cc3 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xcd3 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0cd3 0x0cd3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 0cc4 0cc4 seq_br_type 3 Unconditional Branch; Flow J 0xcbd seq_branch_adr 0cbd 0x0cbd 0cc5 0cc5 ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0cc6 0cc6 fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xcc8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc8 0x0cc8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0cc7 0cc7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0cc8 0cc8 ioc_fiubs 1 val ; Flow J cc=True 0xcca seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0cca 0x0cca typ_c_adr 20 TOP - 0x1 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0cc9 0cc9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cca 0cca fiu_mem_start 2 start-rd; Flow J cc=True 0xccb ; Flow J cc=#0x0 0xccb ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ccb 0x0ccb seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0ccb 0ccb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xccf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0ccf 0x0ccf 0ccc 0ccc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xccf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0ccf 0x0ccf 0ccd 0ccd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xccf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0ccf 0x0ccf 0cce 0cce fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xccf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0ccf 0x0ccf 0ccf 0ccf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 0cd0 0cd0 ioc_load_wdr 0 ; Flow J 0xc8c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8c 0x0c8c 0cd1 0cd1 fiu_load_var 1 hold_var; Flow J 0xcd4 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd4 0x0cd4 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0cd2 0cd2 fiu_load_var 1 hold_var; Flow J 0xcd4 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd4 0x0cd4 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1c DEC_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd3 0cd3 fiu_load_var 1 hold_var; Flow J 0xcd4 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0cd4 0x0cd4 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd4 0cd4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cd5 0cd5 <halt> ; Flow R 0cd6 ; -------------------------------------------------------------------------------------- 0cd6 ; 0x0142 Execute Heap_Access,Diana_Find_Permanent_Attribute 0cd6 ; -------------------------------------------------------------------------------------- 0cd6 MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute: 0cd6 0cd6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cd6 fiu_len_fill_lit 65 zero-fill 0x25 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 0cd7 0cd7 fiu_len_fill_lit 59 zero-fill 0x19; Flow J cc=True 0xce6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ce6 0x0ce6 typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2b VR13:0b val_frame 13 val_rand 9 PASS_A_HIGH 0cd8 0cd8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcda ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cda 0x0cda seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cd9 0cd9 fiu_fill_mode_src 0 ; Flow J 0xcdc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cdc 0x0cdc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cda 0cda fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cdb 0cdb fiu_fill_mode_src 0 ; Flow J 0xcdc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cdc 0x0cdc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cdc 0cdc ioc_fiubs 2 typ ; Flow J cc=True 0xce4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce4 0x0ce4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 0cdd 0cdd fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xce7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce7 0x0ce7 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR06:17 typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA 0cde 0cde fiu_mem_start a start_continue_if_false; Flow J cc=False 0xce1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ce1 0x0ce1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0cdf 0cdf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce0 0ce0 seq_br_type 3 Unconditional Branch; Flow J 0xcdc seq_branch_adr 0cdc 0x0cdc typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce1 0ce1 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ce2 0ce2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce3 0ce3 seq_br_type 3 Unconditional Branch; Flow J 0xcdc seq_branch_adr 0cdc 0x0cdc typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce4 0ce4 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0ce5 0x0ce5 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ce5 0ce5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce6 0ce6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce7 0ce7 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0ce8 0ce8 seq_br_type 1 Branch True; Flow J cc=True 0xcdd seq_branch_adr 0cdd 0x0cdd seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 29 TR06:09 typ_frame 6 0ce9 0ce9 seq_br_type 7 Unconditional Call; Flow C 0x32c3 seq_branch_adr 32c3 0x32c3 0cea ; -------------------------------------------------------------------------------------- 0cea ; 0x0143 Execute Heap_Access,Adaptive_Balanced_Tree_Lookup 0cea ; -------------------------------------------------------------------------------------- 0cea MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup: 0cea 0cea dispatch_brk_class 8 ; Flow C 0x32fc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cea fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0ceb 0ceb fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 0cec 0cec fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 0ced 0ced fiu_mem_start 4 continue; Flow J 0xcee ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0d01 0x0d01 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0cee 0cee fiu_mem_start 4 continue; Flow J cc=True 0xd00 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d00 0x0d00 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0cef 0cef fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0cf0 0cf0 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_frame 5 0cf1 0cf1 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf2 0cf2 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0xcf4 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cf4 0x0cf4 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0cf3 0cf3 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xd00 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d00 0x0d00 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf4 0cf4 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcfe seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cfe 0x0cfe seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cf5 0cf5 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf6 0x0cf6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0cf6 0cf6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcfa seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cfa 0x0cfa seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR 0cf7 0cf7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf3 0x0cf3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cf8 0cf8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf3 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf3 0x0cf3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cf9 0cf9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0cfa 0cfa fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cfb 0cfb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf3 0x0cf3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfc 0cfc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf3 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf3 0x0cf3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfd 0cfd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0cfe 0cfe fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cff 0cff fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0xcf6 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf6 0x0cf6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d00 0d00 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d01 0d01 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0d02 0d02 seq_br_type 2 Push (branch address); Flow J 0xd03 seq_branch_adr 0d01 0x0d01 0d03 0d03 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xcf6 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 0cf6 0x0cf6 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d04 0d04 seq_br_type 7 Unconditional Call; Flow C 0x32c3 seq_branch_adr 32c3 0x32c3 0d05 0d05 <halt> ; Flow R 0d06 ; -------------------------------------------------------------------------------------- 0d06 ; 0x01be Execute Vector,Hash 0d06 ; -------------------------------------------------------------------------------------- 0d06 MACRO_Execute_Vector,Hash: 0d06 0d06 dispatch_brk_class 8 ; Flow J cc=False 0xd0c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0d06 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 0d0c 0x0d0c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0d07 0d07 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd09 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d09 0x0d09 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d08 0d08 fiu_fill_mode_src 0 ; Flow J 0xd0b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0b 0x0d0b 0d09 0d09 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d0a 0d0a fiu_fill_mode_src 0 ; Flow J 0xd0b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0b 0x0d0b 0d0b 0d0b fiu_len_fill_lit 7c zero-fill 0x3c; Flow J 0xd0e fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d0e 0x0d0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d0c 0d0c fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0d0d 0d0d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xd0e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0e 0x0d0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d0e 0d0e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xd1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d1f 0x0d1f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 0d0f 0d0f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0d10 0d10 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1b 0x0d1b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d11 0d11 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d12 0d12 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1d 0x0d1d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d13 0d13 fiu_fill_mode_src 0 ; Flow J 0xd14 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d14 0x0d14 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d14 0d14 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d15 0d15 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d16 0d16 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d17 0d17 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 14 ZEROS val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d18 0d18 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 0d19 0x0d19 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0d19 0d19 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0d1a 0x0d1a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0d1a 0d1a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d1b 0d1b fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d1c 0d1c fiu_fill_mode_src 0 ; Flow J 0xd12 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d12 0x0d12 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d1d 0d1d fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d1e 0d1e fiu_fill_mode_src 0 ; Flow J 0xd14 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d14 0x0d14 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d1f 0d1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA 0d20 0d20 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd24 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d24 0x0d24 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0d21 0d21 fiu_fill_mode_src 0 ; Flow J 0xd22 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d22 0x0d22 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d22 0d22 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d23 0d23 ioc_tvbs 1 typ+fiu; Flow J 0xd15 seq_br_type 3 Unconditional Branch seq_branch_adr 0d15 0x0d15 val_a_adr 3f VR05:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d24 0d24 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d25 0d25 fiu_fill_mode_src 0 ; Flow J 0xd22 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d22 0x0d22 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d26 0d26 ioc_load_wdr 0 ; Flow J 0xe1e seq_br_type 3 Unconditional Branch seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 0d27 0d27 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0d28 ; -------------------------------------------------------------------------------------- 0d28 ; Comes from: 0d28 ; 0d2e C from color 0x0000 0d28 ; 0d7d C from color 0x0000 0d28 ; 0d84 C from color 0x0000 0d28 ; 0ddc C from color 0x0000 0d28 ; 0de2 C from color 0x0000 0d28 ; 0de8 C from color 0x0de6 0d28 ; 0e4e C from color 0x0e4a 0d28 ; 0e68 C from color 0x0d34 0d28 ; 0e80 C from color 0x0e7f 0d28 ; 0e83 C from color 0x0e82 0d28 ; 0e9f C from color 0x0000 0d28 ; 0ebd C from color 0x0000 0d28 ; 0edc C from color 0x0000 0d28 ; -------------------------------------------------------------------------------------- 0d28 0d28 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0d29 ; -------------------------------------------------------------------------------------- 0d29 ; Comes from: 0d29 ; 0767 C from color 0x0767 0d29 ; 0769 C from color 0x0767 0d29 ; 0776 C from color 0x0767 0d29 ; 0d64 C from color 0x0d34 0d29 ; 0d66 C from color 0x0d34 0d29 ; 0d9f C from color 0x0d9f 0d29 ; 0da4 C from color 0x0d9f 0d29 ; 0db3 C from color 0x0db1 0d29 ; 0db5 C from color 0x0db1 0d29 ; 0dba C from color 0x0db1 0d29 ; 0dd8 C from color 0x0dd8 0d29 ; 0de6 C from color 0x0de6 0d29 ; 0df8 C from color 0x0df8 0d29 ; 0e1f C from color 0x0e1f 0d29 ; 0e22 C from color 0x0e22 0d29 ; 0e37 C from color 0x0e37 0d29 ; 0e4a C from color 0x0e4a 0d29 ; 0e53 C from color 0x0e53 0d29 ; 0e54 C from color 0x0e53 0d29 ; 0e57 C from color 0x0e57 0d29 ; 0e78 C from color 0x0e78 0d29 ; 0e7f C from color 0x0e7f 0d29 ; 0e82 C from color 0x0e82 0d29 ; 0e9b C from color 0x0e9b 0d29 ; 3b6d C from color 0x0ba9 0d29 ; 3b75 C from color 0x3b75 0d29 ; -------------------------------------------------------------------------------------- 0d29 0d29 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd2b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d2b 0x0d2b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0d2a 0d2a fiu_fill_mode_src 0 ; Flow J 0xd2d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d2d 0x0d2d typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d2b 0d2b fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d2c 0d2c fiu_fill_mode_src 0 ; Flow J 0xd2d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d2d 0x0d2d typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d2d 0d2d fiu_len_fill_lit 75 zero-fill 0x35; Flow J 0xd2e fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d2e 0x0d2e seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 0d2e 0d2e fiu_load_oreg 1 hold_oreg; Flow C 0xd28 fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d2f 0d2f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd32 fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d32 0x0d32 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d30 0d30 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d31 0d31 fiu_mem_start 15 setup_tag_read; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d32 0d32 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d33 0d33 fiu_mem_start 15 setup_tag_read; Flow R cc=True ; Flow J cc=False 0xe1e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d34 0d34 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd36 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d36 0x0d36 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d35 0d35 fiu_fill_mode_src 0 ; Flow J 0xd39 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d39 0x0d39 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0d36 0d36 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d37 0d37 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0d38 0d38 fiu_load_var 1 hold_var; Flow J 0xd39 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d39 0x0d39 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0d39 0d39 ioc_load_wdr 0 ; Flow J 0xd73 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d73 0x0d73 0d3a 0d3a fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d3b 0d3b fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_a_adr 3e VR09:1e val_b_adr 1f TOP - 1 val_frame 9 0d3c 0d3c ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0d3d 0d3d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd27 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0d3e 0d3e seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 0d3f 0d3f seq_b_timing 1 Latch Condition; Flow J cc=False 0xd41 seq_br_type 0 Branch False seq_branch_adr 0d41 0x0d41 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d40 0d40 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d41 0d41 fiu_mem_start 11 start_tag_query seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 1e A_AND_B typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0d42 0d42 seq_b_timing 0 Early Condition; Flow J cc=True 0xd47 seq_br_type 1 Branch True seq_branch_adr 0d47 0x0d47 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0d43 0d43 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 0d44 0d44 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d45 0d45 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d46 0d46 ioc_load_wdr 0 seq_en_micro 0 0d47 0d47 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start e start_physical_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d48 0d48 fiu_mem_start 4 continue; Flow J cc=False 0xd48 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d48 0x0d48 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0d49 0d49 seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d4a 0d4a fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d4b 0d4b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 0d4c 0d4c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d4d 0d4d ioc_load_wdr 0 ; Flow J 0xd27 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 0d4e 0d4e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d4f 0d4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 2c VR12:0c val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 0d50 0d50 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xd53 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d53 0x0d53 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_b_adr 10 TOP 0d51 0d51 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0d52 0d52 seq_b_timing 1 Latch Condition; Flow J cc=True 0xd27 seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d53 0d53 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34f1 fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d54 0d54 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20d fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0d55 0d55 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xd56 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d26 0x0d26 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0d56 0d56 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0xd27 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0d27 0x0d27 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0d57 0d57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xe00 fiu_load_tar 1 hold_tar fiu_mem_start 10 start_physical_tag_wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0e00 0x0e00 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 4 0d58 0d58 ioc_load_wdr 0 seq_en_micro 0 0d59 0d59 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0d5a 0d5a fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d5b 0d5b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 02 GP02 0d5c 0d5c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d5d 0d5d ioc_load_wdr 0 ; Flow J 0xe1e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 0d5e 0d5e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0d5f 0d5f fiu_load_var 1 hold_var; Flow J cc=True 0xd62 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d62 0x0d62 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0d60 0d60 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd61 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d61 0d61 ioc_load_wdr 0 ; Flow J 0x34d8 seq_br_type 3 Unconditional Branch seq_branch_adr 34d8 0x34d8 seq_en_micro 0 0d62 0d62 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xd60 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d60 0x0d60 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0d63 0d63 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd26 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d26 0x0d26 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d64 0d64 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0d65 0d65 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d66 0d66 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0d67 0d67 fiu_mem_start 2 start-rd; Flow J 0xd69 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d69 0x0d69 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0d68 0d68 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0d69 0d69 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0d6a 0d6a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl 6 INCREMENT_MAR 0d6b 0d6b fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0d6c 0d6c ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0d6d 0d6d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0d6e 0d6e fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 0 PASS_A 0d6f 0d6f fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d70 0d70 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 0d71 0d71 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0d72 0d72 ioc_load_wdr 0 ; Flow J cc=False 0xd68 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d68 0x0d68 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 val_b_adr 04 GP04 0d73 0d73 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0d74 0d74 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d75 0d75 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd7b ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0d7b 0x0d7b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0d76 0d76 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd7b ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d7b 0x0d7b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0d77 0d77 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd79 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0d79 0x0d79 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0d78 0d78 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 21 TR10:01 typ_frame 10 0d79 0d79 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 15 setup_tag_read fiu_offs_lit 38 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d7a 0d7a fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0xd7c fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d7c 0x0d7c seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0d7b 0d7b fiu_len_fill_lit 4c zero-fill 0xc fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0d7c 0d7c fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 15 setup_tag_read fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0d7d 0d7d fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd28 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d7e 0d7e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 0d7f 0d7f ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 0d80 0d80 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0d81 0d81 fiu_len_fill_lit 4c zero-fill 0xc fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 5 0d82 0d82 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d83 0d83 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 18 NOT_A_AND_B val_b_adr 25 VR05:05 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0d84 0d84 fiu_mem_start 11 start_tag_query; Flow C 0xd28 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 0d85 0d85 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xd9d fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0d9d 0x0d9d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0d86 0d86 ioc_tvbs 2 fiu+val; Flow J cc=True 0xd27 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0d87 0d87 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 0d88 0d88 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d89 0d89 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0d8a 0d8a ioc_load_wdr 0 seq_en_micro 0 val_b_adr 01 GP01 0d8b 0d8b fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0d8c 0d8c fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d8d 0d8d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 06 GP06 0d8e 0d8e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d8f 0d8f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0d90 0d90 fiu_mem_start d start_physical_rd; Flow C 0xd93 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d93 0x0d93 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0d91 0d91 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d92 0d92 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0d93 ; -------------------------------------------------------------------------------------- 0d93 ; Comes from: 0d93 ; 0d90 C from color 0x0000 0d93 ; 0dac C from color 0x0d9f 0d93 ; 0dc0 C from color 0x0db1 0d93 ; -------------------------------------------------------------------------------------- 0d93 0d93 fiu_mem_start 4 continue seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 0d94 0d94 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0d95 0d95 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0d96 0d96 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0d97 0d97 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0d98 0d98 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 0 PASS_A 0d99 0d99 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 0d9a 0d9a fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0d9b 0d9b fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 0d9c 0d9c ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0xd92 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 0d92 0x0d92 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0d9d 0d9d seq_b_timing 1 Latch Condition; Flow C cc=False 0x3493 seq_br_type 4 Call False seq_branch_adr 3493 0x3493 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0d9e 0d9e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d9f 0d9f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0da0 0da0 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xda8 fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0da8 0x0da8 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0da1 0da1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xda8 seq_br_type 1 Branch True seq_branch_adr 0da8 0x0da8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 val_rand 1 INC_LOOP_COUNTER 0da2 0da2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xda8 seq_br_type 1 Branch True seq_branch_adr 0da8 0x0da8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0da3 0da3 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 0da4 0da4 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0da5 0da5 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xda9 fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0da9 0x0da9 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0da6 0da6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xda8 seq_br_type 1 Branch True seq_branch_adr 0da8 0x0da8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 0da7 0da7 seq_br_type 1 Branch True; Flow J cc=True 0xdaf seq_branch_adr 0daf 0x0daf seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0da8 0da8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0da9 0da9 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 13 0daa 0daa fiu_load_var 1 hold_var; Flow J cc=True 0xda8 fiu_tivi_src 3 tar_frame seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0da8 0x0da8 seq_en_micro 0 val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0dab 0dab ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0dac 0dac fiu_mem_start d start_physical_rd; Flow C 0xd93 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0d93 0x0d93 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0dad 0dad fiu_mem_start 11 start_tag_query; Flow C 0x3493 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 3493 0x3493 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR 0dae 0dae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0daf 0daf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0db0 0db0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xdab fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0dab 0x0dab seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 22 VR13:02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0db1 0db1 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_en_micro 0 0db2 0db2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xdc1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 0 Branch False seq_branch_adr 0dc1 0x0dc1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0db3 0db3 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0db4 0db4 seq_b_timing 1 Latch Condition; Flow J cc=False 0xdb1 seq_br_type 0 Branch False seq_branch_adr 0db1 0x0db1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand 1 INC_LOOP_COUNTER 0db5 0db5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0db6 0db6 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xdbc fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0dbc 0x0dbc seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0db7 0db7 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0db8 0db8 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 0db9 0db9 seq_b_timing 1 Latch Condition; Flow J cc=True 0xdb3 seq_br_type 1 Branch True seq_branch_adr 0db3 0x0db3 seq_en_micro 0 0dba 0dba fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0dbb 0dbb fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0dbc 0dbc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xdbf seq_br_type 5 Call True seq_branch_adr 0dbf 0x0dbf seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0dbd 0dbd fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0dbe 0dbe ioc_load_wdr 0 ; Flow J 0xdc0 seq_br_type 3 Unconditional Branch seq_branch_adr 0dc0 0x0dc0 seq_en_micro 0 val_b_adr 01 GP01 0dbf ; -------------------------------------------------------------------------------------- 0dbf ; Comes from: 0dbf ; 0dbc C True from color 0x0db1 0dbf ; -------------------------------------------------------------------------------------- 0dbf 0dbf seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0dc0 0dc0 fiu_mem_start d start_physical_rd; Flow C 0xd93 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d93 0x0d93 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0dc1 0dc1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 17 LOOP_COUNTER typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0dc2 0dc2 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0dc3 0dc3 fiu_tivi_src 3 tar_frame; Flow J cc=False 0xdc9 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dc9 0x0dc9 seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0dc4 0dc4 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dc5 0dc5 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A 0dc6 0dc6 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd27 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame d 0dc7 0dc7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32c3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c3 0x32c3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dc8 0dc8 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xd26 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d26 0x0d26 seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0dc9 0dc9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dca 0dca fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dcb 0dcb fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xd27 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0dcc 0dcc fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0dcd 0dcd fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0xd26 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d26 0x0d26 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0dce 0dce fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe1e fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_frame 2 0dcf 0dcf fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xdd0 ; Flow J cc=#0x0 0xdd0 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0dd0 0x0dd0 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0dd0 0dd0 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xdd2 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0dd2 0x0dd2 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0dd1 0dd1 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xdd2 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0dd2 0x0dd2 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0dd2 0dd2 ioc_load_wdr 0 ; Flow C 0x34d7 seq_br_type 7 Unconditional Call seq_branch_adr 34d7 0x34d7 seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dd3 0dd3 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34cc fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34cc 0x34cc seq_en_micro 0 0dd4 0dd4 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0dd5 0dd5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dd6 0dd6 fiu_load_var 1 hold_var; Flow J cc=True 0xe1e fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0dd7 0dd7 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd26 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d26 0x0d26 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0dd8 0dd8 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0dd9 0dd9 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0dda 0dda fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ddb 0ddb fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0ddc 0ddc fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd28 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 0ddd 0ddd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0dde 0dde fiu_fill_mode_src 0 ; Flow J cc=True 0xe1e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0ddf 0ddf ioc_load_wdr 0 ; Flow J 0xe1e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 0de0 0de0 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0de1 0de1 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0de2 0de2 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd28 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_frame 2 0de3 0de3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0de4 0de4 fiu_fill_mode_src 0 ; Flow J cc=True 0xe1e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0de5 0de5 ioc_load_wdr 0 ; Flow J 0xe1e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e1e 0x0e1e seq_en_micro 0 0de6 0de6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0de7 0de7 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0de8 0de8 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd28 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0de9 0de9 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0dea 0dea fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0deb 0deb fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0dec 0dec ioc_load_wdr 0 ; Flow J 0xd27 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 0ded 0ded fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR05:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0dee 0dee fiu_load_var 1 hold_var; Flow J cc=True 0xd27 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0def 0def ioc_tvbs 1 typ+fiu; Flow J cc=True 0xdf2 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0df2 0x0df2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 33 VR13:13 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0df0 0df0 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR13:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0df1 0df1 ioc_fiubs 2 typ ; Flow J 0xd27 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0df2 0df2 ioc_fiubs 2 typ ; Flow J cc=True 0xd27 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0df3 0df3 ioc_fiubs 2 typ ; Flow J cc=True 0xd27 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0df4 0df4 ioc_fiubs 2 typ ; Flow J 0xd27 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0df5 0df5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0df6 0df6 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0df7 0df7 ioc_load_wdr 0 ; Flow J 0xd27 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 0df8 0df8 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0df9 0df9 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0dfa 0dfa fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dfb 0dfb fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0dfc 0dfc fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xe1e ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0dfd 0dfd fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0dfe 0dfe fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xdff fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d26 0x0d26 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0dff 0dff fiu_mem_start 10 start_physical_tag_wr; Flow R cc=False ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0e00 0x0e00 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e00 0e00 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e01 0e01 fiu_mem_start 11 start_tag_query; Flow C 0x34f1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0e02 0e02 ioc_tvbs 8 typ+mem; Flow J cc=True 0xe0e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e0e 0x0e0e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0e03 0e03 fiu_mem_start d start_physical_rd; Flow J cc=False 0xe0e fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e0e 0x0e0e seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0e04 0e04 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0e05 0e05 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e06 0e06 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe09 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e09 0x0e09 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A 0e07 0e07 fiu_fill_mode_src 0 ; Flow J cc=False 0xe0e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e0e 0x0e0e seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0e08 0e08 fiu_fill_mode_src 0 ; Flow J cc=True 0xe09 ; Flow J cc=#0x0 0xe0a fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e0a 0x0e0a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_frame d val_b_adr 28 VR0d:08 val_frame d 0e09 0e09 fiu_fill_mode_src 0 ; Flow J cc=False 0xe0e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e0e 0x0e0e seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_frame d val_b_adr 2f VR0d:0f val_frame d 0e0a 0e0a seq_b_timing 0 Early Condition; Flow J cc=True 0xe0b ; Flow J cc=#0x0 0xe0c seq_br_type b Case False seq_branch_adr 0e0c 0x0e0c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0e0b 0e0b seq_br_type 3 Unconditional Branch; Flow J 0xe0e seq_branch_adr 0e0e 0x0e0e seq_en_micro 0 0e0c 0e0c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0e0d 0e0d ioc_fiubs 1 val ; Flow C 0x368f seq_br_type 7 Unconditional Call seq_branch_adr 368f 0x368f seq_en_micro 0 val_a_adr 23 VR04:03 val_alu_func 1a PASS_B val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0e0e 0e0e fiu_load_var 1 hold_var; Flow C 0x34fa fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0e0f 0e0f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e10 0e10 fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e11 0e11 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e12 0e12 fiu_load_var 1 hold_var; Flow J cc=True 0xe1e fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e13 0e13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xe1e fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0e14 0e14 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e15 0e15 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xe16 ; Flow J cc=#0x0 0xe16 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e16 0x0e16 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e16 0e16 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe18 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e18 0x0e18 seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0e17 0e17 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe18 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e18 0x0e18 seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0e18 0e18 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3e GP01 typ_frame 12 0e19 0e19 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start f start_physical_tag_rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0e1a 0e1a fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e1b 0e1b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e1c 0e1c fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x34d8 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 34d8 0x34d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_frame 12 0e1d 0e1d ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 0e1e 0e1e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0e1f 0e1f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e20 0e20 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e21 0e21 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e22 0e22 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e23 0e23 fiu_mem_start 15 setup_tag_read; Flow C 0xe25 seq_br_type 7 Unconditional Call seq_branch_adr 0e25 0x0e25 seq_en_micro 0 0e24 0e24 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e25 ; -------------------------------------------------------------------------------------- 0e25 ; Comes from: 0e25 ; 0e23 C from color 0x0e22 0e25 ; 0e29 C from color 0x0000 0e25 ; -------------------------------------------------------------------------------------- 0e25 0e25 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe27 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e27 0x0e27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0e26 0e26 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 8 Return True seq_branch_adr 0e27 0x0e27 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e27 0e27 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 14 ZEROS val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e28 0e28 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e29 0e29 fiu_mem_start 15 setup_tag_read; Flow C 0xe25 seq_br_type 7 Unconditional Call seq_branch_adr 0e25 0x0e25 seq_en_micro 0 0e2a 0e2a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd27 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_frame 2 0e2b 0e2b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 0e2c 0e2c ioc_load_wdr 0 ; Flow J 0xd27 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 0e2d 0e2d fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e2e 0e2e fiu_load_var 1 hold_var; Flow J cc=True 0xe1e fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e2f 0e2f ioc_fiubs 0 fiu ; Flow J cc=True 0xe31 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e31 0x0e31 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e30 0e30 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e31 0e31 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd26 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d26 0x0d26 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e32 0e32 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e33 0e33 fiu_load_var 1 hold_var; Flow J cc=True 0xe1e fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e1e 0x0e1e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e34 0e34 ioc_fiubs 0 fiu ; Flow J cc=True 0xe36 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e36 0x0e36 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e35 0e35 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e36 0e36 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd26 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d26 0x0d26 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 18 NOT_A_AND_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e37 0e37 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e38 0e38 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e39 0e39 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32c3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c3 0x32c3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3e VR03:1e val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 3 0e3a 0e3a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e3b 0x0e3b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0e3b 0e3b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e3c 0x0e3c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL 0e3c 0e3c seq_br_type 3 Unconditional Branch; Flow J 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0e3d 0e3d fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e3e 0e3e fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32c3 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 32c3 0x32c3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e3f 0e3f fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e40 0e40 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 10 TOP 0e41 0e41 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x326c fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2c VR0d:0c val_frame d 0e42 0e42 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0e43 0e43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x326c fiu_load_mdr 1 hold_mdr fiu_offs_lit 27 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2d VR0d:0d val_frame d 0e44 0e44 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_op_sel 3 insert seq_en_micro 0 0e45 0e45 fiu_mem_start f start_physical_tag_rd; Flow C cc=False 0x32a5 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0e46 0e46 fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x32a5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 15 setup_tag_read fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 0e47 0e47 fiu_len_fill_lit 75 zero-fill 0x35 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e48 0e48 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e49 0e49 fiu_fill_mode_src 0 ; Flow J 0xd34 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d34 0x0d34 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0e4a 0e4a fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e4b 0e4b fiu_mem_start 12 start_lru_query fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e4c 0e4c seq_br_type 3 Unconditional Branch; Flow J 0xe4e seq_branch_adr 0e4e 0x0e4e seq_en_micro 0 0e4d 0e4d fiu_tivi_src 8 type_var; Flow C 0xfd0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0fd0 0x0fd0 seq_en_micro 0 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e4e 0e4e fiu_mem_start 13 start_available_query; Flow C 0xd28 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e4f 0e4f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xe4d ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0e4d 0x0e4d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e50 0e50 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR0d:0d val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame d 0e51 0e51 seq_en_micro 0 val_a_adr 2c VR0d:0c val_b_adr 2d VR0d:0d val_frame d val_rand c START_MULTIPLY 0e52 0e52 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0e53 0e53 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP 0e54 0e54 fiu_load_oreg 1 hold_oreg; Flow C 0xd29 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e55 0e55 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 7 fiu_frame ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_frame d val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0e56 0e56 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0e57 0e57 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 22 TR08:02 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP 0e58 0e58 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src b type_frame fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e59 0e59 ioc_fiubs 1 val ; Flow C cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 0e5a 0e5a ioc_adrbs 1 val ioc_fiubs 1 val typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_rand a PASS_B_HIGH 0e5b 0e5b seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0xe5d seq_br_type f Unconditional Case Call seq_branch_adr 0e5d 0x0e5d seq_en_micro 0 typ_csa_cntl 3 POP_CSA 0e5c 0e5c seq_br_type 3 Unconditional Branch; Flow J 0xd27 seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0e5d ; -------------------------------------------------------------------------------------- 0e5d ; Comes from: 0e5d ; 0e5b C #0x0 from color 0x0e59 0e5d ; -------------------------------------------------------------------------------------- 0e5d 0e5d fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0xe60 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e60 0x0e60 seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e5e 0e5e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0e5f 0e5f fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xe63 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e63 0x0e63 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0e60 0e60 seq_en_micro 0 0e61 0e61 fiu_fill_mode_src 0 ; Flow J cc=False 0xe6d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0e6d 0x0e6d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0e62 0e62 fiu_load_oreg 1 hold_oreg; Flow J 0x3424 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3424 0x3424 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 0e63 0e63 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR07:12 val_frame 7 0e64 0e64 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0xe67 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0e67 0x0e67 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0e65 0e65 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xe6d seq_br_type 0 Branch False seq_branch_adr 0e6d 0x0e6d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0e66 0e66 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xe60 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e60 0x0e60 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e67 0e67 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xe6c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e6c 0x0e6c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 0e68 0e68 fiu_mem_start 2 start-rd; Flow C 0xd28 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 0e69 0e69 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0e6a 0e6a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 02 GP02 typ_frame d 0e6b 0e6b ioc_load_wdr 0 ; Flow J 0xe6c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e6c 0x0e6c seq_en_micro 0 0e6c 0e6c fiu_mem_start 2 start-rd; Flow J 0x3459 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3459 0x3459 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 0e6d 0e6d fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x32a5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A 0e6e 0e6e fiu_len_fill_lit 7c zero-fill 0x3c; Flow C cc=False 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0e6f 0e6f fiu_fill_mode_src 0 ; Flow J 0xd34 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d34 0x0d34 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0e70 0e70 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e71 0e71 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e72 0e72 ioc_load_wdr 0 ; Flow C cc=False 0x32c3 seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 2e VR12:0e val_alu_func 1d A_AND_NOT_B val_frame 12 0e73 0e73 fiu_mem_start d start_physical_rd; Flow C cc=True 0x32c3 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c3 0x32c3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_frame 11 0e74 0e74 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xe76 seq_br_type 1 Branch True seq_branch_adr 0e76 0x0e76 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0e75 0e75 fiu_mem_start d start_physical_rd; Flow C cc=False 0x32c3 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0e76 0e76 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0e77 0e77 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0xd27 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e78 0e78 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e79 0e79 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e7a 0e7a ioc_fiubs 1 val ; Flow C cc=False 0x32c3 seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 0e7b 0e7b fiu_mem_start d start_physical_rd; Flow C cc=True 0x32c3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c3 0x32c3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 33 TR12:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2c VR11:0c val_alu_func 1e A_AND_B val_frame 11 0e7c 0e7c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xe7e seq_br_type 1 Branch True seq_branch_adr 0e7e 0x0e7e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0e7d 0e7d fiu_mem_start d start_physical_rd; Flow C cc=False 0x32c3 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0e7e 0e7e fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e7f 0e7f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e80 0e80 fiu_mem_start 2 start-rd; Flow C 0xd28 seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0e81 0e81 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e82 0e82 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e83 0e83 fiu_mem_start 3 start-wr; Flow C 0xd28 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 seq_random 02 ? typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0e84 0e84 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e85 0e85 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0e86 0e86 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0e87 0e87 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0e88 0e88 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e89 0e89 fiu_mem_start 4 continue seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0e8a 0e8a fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0e8b 0e8b fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0e8c 0e8c ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0e8d 0e8d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0e8e 0e8e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e8f 0e8f fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0e90 0e90 fiu_mem_start 4 continue; Flow J cc=True 0xd27 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e91 0e91 fiu_mem_start 4 continue; Flow J cc=True 0xd27 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e92 0e92 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd27 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e93 0e93 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd27 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0e94 0e94 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0xe89 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e89 0x0e89 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0e95 0e95 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0e96 0e96 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e97 0e97 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xd27 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0d27 0x0d27 seq_en_micro 0 val_a_adr 2d VR0d:0d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame d 0e98 0e98 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 17 LOOP_COUNTER val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0e99 0e99 fiu_mem_start 12 start_lru_query; Flow J cc=True 0xe98 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0e98 0x0e98 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0e9a 0e9a seq_br_type 3 Unconditional Branch; Flow J 0xd27 seq_branch_adr 0d27 0x0d27 seq_en_micro 0 0e9b 0e9b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e9c 0e9c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0e9d 0e9d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd27 seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0e9e 0e9e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd27 seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 29 TR04:09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0e9f 0e9f fiu_mem_start 2 start-rd; Flow C 0xd28 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0ea0 0ea0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ea1 0ea1 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xec0 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ec0 0x0ec0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_mar_cntl f LOAD_MAR_RESERVED 0ea2 0ea2 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xec4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ec4 0x0ec4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0ea3 0ea3 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xec2 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 0ec2 0x0ec2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR06:1f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0ea4 0ea4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xea1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0ea1 0x0ea1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_frame 12 0ea5 0ea5 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xea1 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ea1 0x0ea1 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 0ea6 0ea6 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xeb3 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0eb3 0x0eb3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 0ea7 0ea7 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xeb3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0eb3 0x0eb3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 30 VR11:10 val_frame 11 0ea8 0ea8 fiu_mem_start 11 start_tag_query; Flow C 0x34f1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0ea9 0ea9 ioc_tvbs 8 typ+mem; Flow J cc=True 0xeb3 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0eb3 0x0eb3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0eaa 0eaa fiu_mem_start d start_physical_rd; Flow J cc=False 0xeb2 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0eb2 0x0eb2 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0eab 0eab fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0eac 0eac fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 1 0ead 0ead ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 0eae 0eae fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0xeb3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0eb3 0x0eb3 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 15 NOT_B typ_b_adr 05 GP05 0eaf 0eaf fiu_fill_mode_src 0 ; Flow J cc=True 0xea1 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0eb0 0eb0 seq_b_timing 0 Early Condition; Flow J cc=True 0xeb1 ; Flow J cc=#0x0 0xeb1 seq_br_type b Case False seq_branch_adr 0eb1 0x0eb1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0eb1 0eb1 seq_br_type 3 Unconditional Branch; Flow J 0xea1 seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 0eb2 0eb2 seq_en_micro 0 0eb3 0eb3 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1b A_OR_B val_b_adr 3f VR08:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 0eb4 0eb4 ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 01 GP01 0eb5 0eb5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0eb6 0eb6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 0eb7 0eb7 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0eb8 0eb8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 02 GP02 val_frame 2 0eb9 0eb9 seq_b_timing 1 Latch Condition; Flow J cc=True 0xea1 seq_br_type 1 Branch True seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 0eba 0eba fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0ebb 0ebb fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 0ebc 0ebc seq_br_type 1 Branch True; Flow J cc=True 0xea1 seq_branch_adr 0ea1 0x0ea1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 val_c_adr 3c GP03 0ebd 0ebd fiu_mem_start 3 start-wr; Flow C 0xd28 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 0ebe 0ebe fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ebf 0ebf ioc_load_wdr 0 ; Flow J 0xea1 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR07:06 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 0ec0 0ec0 ioc_load_wdr 0 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 16 TR04:09 typ_c_mux_sel 0 ALU typ_frame 4 val_b_adr 04 GP04 0ec1 0ec1 fiu_mem_start 3 start-wr; Flow J cc=True 0xd27 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d27 0x0d27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0ec2 0ec2 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR07:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 0ec3 0ec3 seq_br_type 3 Unconditional Branch; Flow J 0xea1 seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 31 TR05:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 0ec4 0ec4 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 0ec5 0ec5 seq_br_type 3 Unconditional Branch; Flow J 0xea1 seq_branch_adr 0ea1 0x0ea1 seq_en_micro 0 0ec6 0ec6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ec7 0ec7 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 0e VR03:11 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ec8 0ec8 fiu_mem_start 3 start-wr; Flow C cc=False 0x211 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 37 TR08:17 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0ec9 0ec9 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 0eca 0eca seq_br_type 3 Unconditional Branch; Flow J 0xd27 seq_branch_adr 0d27 0x0d27 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 0ecb 0ecb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR03:10 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 3 0ecc 0ecc seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0ecd 0ecd seq_br_type 7 Unconditional Call; Flow C 0x213 seq_branch_adr 0213 0x0213 seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 08 VR03:17 val_c_mux_sel 2 ALU val_frame 3 0ece 0ece seq_br_type 7 Unconditional Call; Flow C 0x212 seq_branch_adr 0212 0x0212 seq_en_micro 0 0ecf 0ecf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 0d TR03:12 typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed0 0ed0 fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 2a VR0c:0a val_frame c 0ed1 0ed1 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed2 0ed2 ioc_load_wdr 0 ; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0ed3 0ed3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20d ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0ed4 0ed4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR04:04 val_alu_func 0 PASS_A val_c_adr 1b VR04:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed5 0ed5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR04:1e val_alu_func 0 PASS_A val_c_adr 01 VR04:1e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ed6 0ed6 fiu_mem_start 11 start_tag_query; Flow C 0x34f1 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0ed7 0ed7 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_mem_start 2 start-rd fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0ed8 0ed8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 0ed9 0ed9 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=False ; Flow J cc=True 0x326c fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR12:0e val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0eda 0eda fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR1b:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 1b 0edb 0edb fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0edc 0edc fiu_mem_start 2 start-rd; Flow C 0xd28 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d28 0x0d28 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 38 VR06:18 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 6 0edd 0edd fiu_mem_start 3 start-wr seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 34 VR11:14 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0ede 0ede fiu_mem_start 4 continue ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 2a TR1d:0a typ_frame 1d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0edf 0edf fiu_mem_start 4 continue; Flow J cc=False 0xedf ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0edf 0x0edf seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 13 LOOP_REG typ_mar_cntl 6 INCREMENT_MAR typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_b_adr 13 LOOP_REG val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 0ee0 0ee0 ioc_load_wdr 0 ; Flow J 0xd27 seq_br_type 3 Unconditional Branch seq_branch_adr 0d27 0x0d27 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 0ee1 0ee1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 36 VR04:16 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0ee2 0ee2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 36 TR04:16 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ee3 0ee3 ioc_fiubs 1 val ; Flow C cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 0ee4 0ee4 seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0ee5 0ee5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 13 LOOP_REG typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ee6 0ee6 seq_br_type 7 Unconditional Call; Flow C 0x3651 seq_branch_adr 3651 0x3651 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 34 VR04:14 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0ee7 0ee7 typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR03:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0ee8 0ee8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2c VR06:0c val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 6 0ee9 0ee9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0eea 0eea fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0eeb 0eeb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 00 TR04:1f typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 00 VR04:1f val_c_source 0 FIU_BUS val_frame 4 0eec 0eec seq_br_type 3 Unconditional Branch; Flow J 0x326a seq_branch_adr 326a 0x326a 0eed 0eed fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2a TR12:0a typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 0eee 0eee fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xef3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ef3 0x0ef3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 0eef 0eef fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20d fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 0ef0 0ef0 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 0ef1 0ef1 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xef2 ; Flow J cc=#0x0 0xf0f fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0f0f 0x0f0f seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0ef2 0ef2 fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0xef3 ; Flow J cc=#0x0 0xef5 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ef5 0x0ef5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0ef3 0ef3 seq_b_timing 0 Early Condition; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0ef4 0ef4 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 0ef5 0ef5 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0ef6 0ef6 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0ef7 0ef7 fiu_load_var 1 hold_var; Flow J 0xf08 fiu_tivi_src b type_frame ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f08 0x0f08 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0ef8 0ef8 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf60 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f60 0x0f60 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0ef9 0ef9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xefa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 2 Push (branch address) seq_branch_adr 0fc9 0x0fc9 seq_en_micro 0 val_c_adr 30 GP0f 0efa ; -------------------------------------------------------------------------------------- 0efa ; Comes from: 0efa ; 34a3 C from color 0x349b 0efa ; -------------------------------------------------------------------------------------- 0efa 0efa fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xf06 fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f06 0x0f06 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 2 0efb 0efb fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xefc ; Flow J cc=#0x0 0xefc fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0efc 0x0efc seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR02:1d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0efc 0efc fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xefe fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0efe 0x0efe seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0efd 0efd fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xefe fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0efe 0x0efe seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 0efe 0efe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_b_adr 0f GP0f val_frame 3 0eff 0eff fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xf01 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0f01 0x0f01 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 21 VR11:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 0f00 0f00 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 0f01 0f01 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 0f02 0f02 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f03 0f03 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0f04 0x0f04 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0f04 0f04 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f05 0f05 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34cc fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34cc 0x34cc seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_b_adr 0d GP0d typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 0f GP0f val_b_adr 0d GP0d 0f06 0f06 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0f07 0f07 fiu_mem_start 3 start-wr; Flow J 0x3b59 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b59 0x3b59 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 0f08 0f08 fiu_load_tar 1 hold_tar; Flow C cc=False 0x20d fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0f09 0f09 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c0 0x32c0 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_c_adr 30 GP0f 0f0a 0f0a seq_br_type 0 Branch False; Flow J cc=False 0x32c0 seq_branch_adr 32c0 0x32c0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 0f0b 0f0b fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f0c 0f0c ioc_tvbs 8 typ+mem; Flow C cc=True 0x32c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32c0 0x32c0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f0d 0f0d fiu_mem_start 10 start_physical_tag_wr; Flow J 0xf0e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0fc9 0x0fc9 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f0e 0f0e ioc_load_wdr 0 ; Flow J 0x34d8 seq_br_type 3 Unconditional Branch seq_branch_adr 34d8 0x34d8 seq_en_micro 0 val_b_adr 0f GP0f 0f0f 0f0f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f10 0f10 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf17 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f17 0x0f17 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f11 0f11 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf2a fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f2a 0x0f2a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f12 0f12 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf33 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f33 0x0f33 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f13 0f13 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf3d fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f3d 0x0f3d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f14 0f14 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf55 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f55 0x0f55 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f15 0f15 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0xf5d fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f5d 0x0f5d seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_frame d 0f16 0f16 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f17 0f17 fiu_load_var 1 hold_var; Flow C cc=False 0xf62 fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f62 0x0f62 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f18 0f18 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f19 0f19 fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0xf23 fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f23 0x0f23 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f1a 0f1a ioc_fiubs 0 fiu ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0f1b 0f1b fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f1c 0f1c fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf21 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f21 0x0f21 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f1d 0f1d fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xfa0 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa0 0x0fa0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f1e 0f1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfa0 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa0 0x0fa0 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 0e GP0e typ_frame 12 val_a_adr 31 VR04:11 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 4 0f1f 0f1f fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf7a fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7a 0x0f7a seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 0f20 0f20 seq_br_type 3 Unconditional Branch; Flow J 0xfa0 seq_branch_adr 0fa0 0x0fa0 seq_en_micro 0 0f21 0f21 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x327a fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 327a 0x327a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 29 VR12:09 val_frame 12 0f22 0f22 fiu_mem_start 11 start_tag_query; Flow J 0xf7a ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7a 0x0f7a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_c_adr 34 GP0b 0f23 0f23 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfa0 seq_br_type 1 Branch True seq_branch_adr 0fa0 0x0fa0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 0f24 0f24 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfad fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fad 0x0fad seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f25 0f25 ioc_tvbs 3 fiu+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f26 0f26 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf21 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f21 0x0f21 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f27 0f27 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 0f28 0f28 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf7a seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7a 0x0f7a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f29 0f29 seq_br_type 3 Unconditional Branch; Flow J 0xf9c seq_branch_adr 0f9c 0x0f9c seq_en_micro 0 0f2a 0f2a fiu_load_var 1 hold_var; Flow C cc=False 0xf6b fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f6b 0x0f6b seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f2b 0f2b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f2c 0f2c ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfa0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fa0 0x0fa0 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f2d 0f2d seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 2c TR12:0c typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 0f2e 0f2e fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f2f 0f2f fiu_len_fill_lit 14 sign-fill 0x14; Flow J cc=False 0xf31 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f31 0x0f31 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f30 0f30 seq_br_type 3 Unconditional Branch; Flow J 0xf9c seq_branch_adr 0f9c 0x0f9c seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f31 0f31 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x3299 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3299 0x3299 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f32 0f32 fiu_mem_start 11 start_tag_query; Flow J 0xf7a ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7a 0x0f7a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 0f33 0f33 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f34 0f34 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d 0f35 0f35 fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 7 INC_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f36 0f36 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xfad seq_br_type 0 Branch False seq_branch_adr 0fad 0x0fad seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2d TR12:0d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0f37 0f37 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f38 0f38 fiu_tivi_src 2 tar_fiu; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR01:02 typ_frame 1 val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0f39 0f39 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfa0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa0 0x0fa0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f3a 0f3a ioc_fiubs 0 fiu ; Flow C cc=True 0x329c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329c 0x329c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f3b 0f3b fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A val_a_adr 0b GP0b val_b_adr 0f GP0f 0f3c 0f3c fiu_mem_start 11 start_tag_query; Flow J 0xf7a ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0f7a 0x0f7a seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0f3d 0f3d fiu_load_var 1 hold_var; Flow C cc=False 0xf6b fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f6b 0x0f6b seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f3e 0f3e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f3f 0f3f ioc_tvbs 1 typ+fiu; Flow J cc=False 0xf46 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f46 0x0f46 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0f40 0f40 fiu_vmux_sel 1 fill value; Flow C 0x210 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f41 0f41 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 0f42 0f42 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf44 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f44 0x0f44 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b 0f43 0f43 seq_br_type 3 Unconditional Branch; Flow J 0xf9c seq_branch_adr 0f9c 0x0f9c seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f44 0f44 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329a seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 0f45 0f45 fiu_mem_start 11 start_tag_query; Flow J 0xf7a seq_br_type 3 Unconditional Branch seq_branch_adr 0f7a 0x0f7a seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0f46 0f46 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf41 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 0f41 0x0f41 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f47 0f47 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfad seq_br_type 0 Branch False seq_branch_adr 0fad 0x0fad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f48 0f48 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfb3 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fb3 0x0fb3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3a VR05:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f49 0f49 fiu_mem_start 2 start-rd; Flow C 0xfcf fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0fcf 0x0fcf seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0f4a 0f4a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_en_micro 0 0f4b 0f4b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xfad fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fad 0x0fad seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0f4c 0f4c fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0f4d 0f4d fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0xfcf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0fcf 0x0fcf seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0c GP0c 0f4e 0f4e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR0d:00 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 0f4f 0f4f seq_en_micro 0 val_a_adr 3f VR06:1f val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 0f50 0f50 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f51 0f51 ioc_load_wdr 0 ; Flow J cc=True 0xf9c ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0f9c 0x0f9c seq_en_micro 0 typ_b_adr 0c GP0c typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f52 0f52 seq_en_micro 0 typ_c_adr 33 GP0c val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 33 VR02:13 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f53 0f53 fiu_mem_start 11 start_tag_query; Flow J cc=True 0xf7a seq_br_type 1 Branch True seq_branch_adr 0f7a 0x0f7a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 0f54 0f54 seq_br_type 7 Unconditional Call; Flow C 0x32b4 seq_branch_adr 32b4 0x32b4 seq_en_micro 0 0f55 0f55 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f56 0f56 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 20 VR0d:00 val_frame d val_rand a PASS_B_HIGH 0f57 0f57 ioc_fiubs 0 fiu ; Flow J cc=True 0xfa1 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0fa1 0x0fa1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0f58 0f58 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfad fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fad 0x0fad seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 0f59 0f59 fiu_tivi_src c mar_0xc; Flow J cc=True 0xf5c ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f5c 0x0f5c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 25 TR00:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f5a 0f5a ioc_tvbs 2 fiu+val; Flow J cc=False 0xfb4 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fb4 0x0fb4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 0e GP0e val_alu_func 1e A_AND_B val_b_adr 32 VR06:12 val_frame 6 0f5b 0f5b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f5c 0f5c fiu_mem_start 11 start_tag_query; Flow J 0xf7a ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0f7a 0x0f7a seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f5d 0f5d ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xfb4 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fb4 0x0fb4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0f5e 0f5e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xf60 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f60 0x0f60 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 3e VR09:1e val_frame 9 0f5f 0f5f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfb4 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fb4 0x0fb4 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame d 0f60 0f60 fiu_mem_start 2 start-rd; Flow C 0xfcf seq_br_type 7 Unconditional Call seq_branch_adr 0fcf 0x0fcf seq_en_micro 0 0f61 0f61 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0f62 ; -------------------------------------------------------------------------------------- 0f62 ; Comes from: 0f62 ; 0f17 C False from color 0x0ef8 0f62 ; -------------------------------------------------------------------------------------- 0f62 0f62 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf6c fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0f6c 0x0f6c seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f63 0f63 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f64 0f64 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0f65 0f65 fiu_mem_start 2 start-rd ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f66 0f66 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf64 seq_br_type 1 Branch True seq_branch_adr 0f64 0x0f64 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f67 0f67 fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame c val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f68 0f68 ioc_fiubs 2 typ ; Flow C cc=True 0x329f ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329f 0x329f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 0f69 0f69 seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c 0f6a 0f6a ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x329f seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 329f 0x329f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f6b ; -------------------------------------------------------------------------------------- 0f6b ; Comes from: 0f6b ; 0f2a C False from color 0x0ef8 0f6b ; 0f3d C False from color 0x0ef8 0f6b ; -------------------------------------------------------------------------------------- 0f6b 0f6b fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf63 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f63 0x0f63 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f6c 0f6c fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c val_rand 9 PASS_A_HIGH 0f6d 0f6d ioc_fiubs 0 fiu ; Flow J cc=True 0xf6f ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f6f 0x0f6f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f6e 0f6e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xf63 seq_br_type 0 Branch False seq_branch_adr 0f63 0x0f63 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR0c:04 typ_frame c 0f6f 0f6f fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf63 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f63 0x0f63 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR13:0e typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_c_adr 32 GP0d typ_frame 13 val_a_adr 20 VR0d:00 val_frame d 0f70 0f70 ioc_fiubs 0 fiu ; Flow J cc=True 0xf78 seq_br_type 1 Branch True seq_branch_adr 0f78 0x0f78 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1e A_AND_B typ_b_adr 26 TR0c:06 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame c 0f71 0f71 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf63 seq_br_type 1 Branch True seq_branch_adr 0f63 0x0f63 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_c_adr 1a VR0c:05 val_frame c 0f72 0f72 fiu_load_var 1 hold_var; Flow J cc=True 0xf63 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f63 0x0f63 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 2 0f73 0f73 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf63 seq_br_type 1 Branch True seq_branch_adr 0f63 0x0f63 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_frame 2 val_a_adr 2d VR0c:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f74 0f74 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 26 TR0c:06 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame c 0f75 0f75 ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 2d TR13:0d typ_b_adr 0d GP0d typ_frame 13 val_b_adr 25 VR0c:05 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame c 0f76 0f76 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x364f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random d disable slice timer seq_br_type 7 Unconditional Call seq_branch_adr 364f 0x364f seq_en_micro 0 typ_a_adr 3c TR12:1c typ_frame 12 val_a_adr 21 VR02:01 val_alu_func 1b A_OR_B val_b_adr 0b GP0b val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0f77 0f77 ioc_random c enable slice timer; Flow J 0xf63 seq_br_type 3 Unconditional Branch seq_branch_adr 0f63 0x0f63 seq_en_micro 0 0f78 0f78 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 30 TR07:10 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 1a VR0c:05 val_frame c 0f79 0f79 ioc_load_wdr 0 ; Flow J 0xf63 seq_br_type 3 Unconditional Branch seq_branch_adr 0f63 0x0f63 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 25 VR0c:05 val_frame c 0f7a 0f7a fiu_len_fill_lit 4c zero-fill 0xc; Flow C 0x34f2 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 34f2 0x34f2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_frame d val_b_adr 20 VR0d:00 val_frame d 0f7b 0f7b ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0f7c 0f7c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame d 0f7d 0f7d fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32c0 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32c0 0x32c0 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A val_a_adr 25 VR05:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 5 0f7e 0f7e seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 0f7f 0f7f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xf97 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f97 0x0f97 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0f80 0f80 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 0f81 0f81 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 0f82 0f82 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 72 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0f83 0f83 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 0f84 0f84 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0f85 0f85 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0f86 0f86 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 0f87 0f87 fiu_mem_start 15 setup_tag_read; Flow C 0x210 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame d val_a_adr 0c GP0c 0f88 0f88 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0f89 0f89 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f8a 0f8a fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34cb fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34cb 0x34cb seq_en_micro 0 val_b_adr 0e GP0e 0f8b 0f8b fiu_load_var 1 hold_var; Flow J cc=True 0xf92 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0f92 0x0f92 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0f8c 0f8c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e 0f8d 0f8d fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 0f8e 0f8e fiu_load_tar 1 hold_tar; Flow J cc=True 0xfc9 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fc9 0x0fc9 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0b GP0b val_b_adr 0b GP0b 0f8f 0f8f fiu_mem_start e start_physical_wr; Flow J cc=False 0xf94 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f94 0x0f94 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0f90 0f90 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 0f91 0f91 fiu_mem_start e start_physical_wr; Flow J 0xf94 seq_br_type 3 Unconditional Branch seq_branch_adr 0f94 0x0f94 seq_en_micro 0 0f92 0f92 fiu_load_tar 1 hold_tar; Flow J cc=True 0xfc9 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0fc9 0x0fc9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e val_b_adr 0e GP0e 0f93 0f93 fiu_mem_start e start_physical_wr; Flow J cc=True 0xf90 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f90 0x0f90 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 0f94 0f94 fiu_mem_start 4 continue; Flow J cc=False 0xf94 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f94 0x0f94 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 0f95 0f95 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfc9 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fc9 0x0fc9 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 0f96 0f96 fiu_mem_start e start_physical_wr; Flow J 0xf94 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0f94 0x0f94 seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f97 0f97 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 0f98 0f98 seq_br_type 7 Unconditional Call; Flow C 0xfd0 seq_branch_adr 0fd0 0x0fd0 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 0f99 0f99 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfc9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fc9 0x0fc9 seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame d val_a_adr 25 VR0d:05 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame d 0f9a 0f9a fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xfc9 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 0 Branch False seq_branch_adr 0fc9 0x0fc9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR0d:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 0f9b 0f9b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xf7d fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f7d 0x0f7d seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0f9c 0f9c fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f9d 0f9d ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0f9e 0f9e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 0f GP0f 0f9f 0f9f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfa1 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fa1 0x0fa1 seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 0fa0 0fa0 fiu_mem_start 2 start-rd; Flow J 0xfa1 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fa1 0x0fa1 seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0fa1 0fa1 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ac ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fa2 0fa2 seq_br_type 0 Branch False; Flow J cc=False 0xfb4 seq_branch_adr 0fb4 0x0fb4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fa3 0fa3 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x34f3 seq_br_type 7 Unconditional Call seq_branch_adr 34f3 0x34f3 seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 0fa4 0fa4 ioc_load_wdr 0 ; Flow J cc=True 0xef9 ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ef9 0x0ef9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fa5 0fa5 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xfb4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fb4 0x0fb4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0fa6 0fa6 seq_br_type 3 Unconditional Branch; Flow J 0xfa7 seq_branch_adr 0fa7 0x0fa7 seq_en_micro 0 0fa7 0fa7 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x32b4 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32b4 0x32b4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl 4 RESTORE_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 20 VR0d:00 val_frame d 0fa8 0fa8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfab fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fab 0x0fab seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d 0fa9 0fa9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xf7d fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f7d 0x0f7d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0faa 0faa seq_br_type 3 Unconditional Branch; Flow J 0xfc9 seq_branch_adr 0fc9 0x0fc9 seq_en_micro 0 0fab 0fab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfc9 seq_br_type 1 Branch True seq_branch_adr 0fc9 0x0fc9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_a_adr 3c TR07:1c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 33 VR02:13 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 2 0fac 0fac seq_br_type 7 Unconditional Call; Flow C 0x32b4 seq_branch_adr 32b4 0x32b4 seq_en_micro 0 0fad 0fad fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 11 start_tag_query fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME 0fae 0fae fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ac ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0faf 0faf seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 0fb0 0fb0 fiu_load_var 1 hold_var; Flow J cc=False 0xfb5 fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fb5 0x0fb5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 0fb1 0fb1 ioc_load_wdr 0 ; Flow J cc=True 0xef9 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0ef9 0x0ef9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fb2 0fb2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0fb3 0fb3 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ac ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fb4 0fb4 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0fb5 0fb5 seq_br_type 7 Unconditional Call; Flow C 0xfb8 seq_branch_adr 0fb8 0x0fb8 seq_en_micro 0 0fb6 0fb6 seq_b_timing 1 Latch Condition; Flow J cc=False 0xfc9 seq_br_type 0 Branch False seq_branch_adr 0fc9 0x0fc9 seq_en_micro 0 0fb7 0fb7 seq_br_type 3 Unconditional Branch; Flow J 0xfa7 seq_branch_adr 0fa7 0x0fa7 seq_en_micro 0 0fb8 ; -------------------------------------------------------------------------------------- 0fb8 ; Comes from: 0fb8 ; 0fb5 C from color 0x0ef8 0fb8 ; 34a7 C False from color 0x349b 0fb8 ; -------------------------------------------------------------------------------------- 0fb8 0fb8 fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fb9 0fb9 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0fba 0x0fba seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0fba 0fba seq_br_type 7 Unconditional Call; Flow C 0x3622 seq_branch_adr 3622 0x3622 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fbb 0fbb fiu_mem_start 2 start-rd; Flow C 0xfcf ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0fcf 0x0fcf seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fbc 0fbc ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0fbd 0fbd fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fbe 0fbe fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0xfc1 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fc1 0x0fc1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 5 0fbf 0fbf fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 0fc0 0fc0 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 0fc1 0fc1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfc2 ; Flow J cc=#0x0 0xfc3 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0fc3 0x0fc3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0fc2 0fc2 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0fc3 0fc3 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0fc4 0fc4 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc5 0fc5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc6 0fc6 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0fc7 0fc7 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362a fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362a 0x362a seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_mar_cntl 1 RESTORE_RDR val_b_adr 0c GP0c 0fc8 0fc8 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 0fc9 0fc9 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xfc8 fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_offs_lit 27 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fc8 0x0fc8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0fca 0fca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfcb ; Flow J cc=#0x0 0xfcb fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start b start_last_cmd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0fcb 0x0fcb seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 23 VR0d:03 val_frame d 0fcb 0fcb fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fcc 0fcc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0fcd 0fcd fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fce 0fce fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fcf ; -------------------------------------------------------------------------------------- 0fcf ; Comes from: 0fcf ; 0f49 C from color 0x0ef8 0fcf ; 0f4d C from color 0x0ef8 0fcf ; 0f60 C from color 0x0ef8 0fcf ; 0fbb C from color 0x0fb9 0fcf ; -------------------------------------------------------------------------------------- 0fcf 0fcf seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0fd0 ; -------------------------------------------------------------------------------------- 0fd0 ; Comes from: 0fd0 ; 0e4d C from color 0x0e4a 0fd0 ; 0f98 C from color 0x0ef8 0fd0 ; 33d7 C from color 0x0f05 0fd0 ; 3642 C from color 0x3635 0fd0 ; -------------------------------------------------------------------------------------- 0fd0 0fd0 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 0fd1 0fd1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0fd2 0fd2 fiu_vmux_sel 1 fill value; Flow C cc=True 0x2a82 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0fd3 0fd3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0fd4 0fd4 fiu_fill_mode_src 0 ; Flow J cc=False 0xfdb fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fdb 0x0fdb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 0fd5 0fd5 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fd6 0fd6 fiu_mem_start 15 setup_tag_read seq_en_micro 0 0fd7 0fd7 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0fd8 0fd8 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xfdf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0fdf 0x0fdf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 5 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0fd9 0fd9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0fda 0fda fiu_mem_start 12 start_lru_query; Flow J 0xfd4 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fd4 0x0fd4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0fdb 0fdb fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0xfd6 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fd6 0x0fd6 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fdc 0fdc fiu_mem_start 15 setup_tag_read seq_en_micro 0 0fdd 0fdd fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0fde 0fde fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0xfd9 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fd9 0x0fd9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0fdf 0fdf fiu_tivi_src 4 fiu_var; Flow J cc=True 0xfe1 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0fe1 0x0fe1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 0fe0 0fe0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfe2 seq_br_type 1 Branch True seq_branch_adr 0fe2 0x0fe2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 0fe1 0fe1 fiu_fill_mode_src 0 ; Flow J 0xfe2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 3 Unconditional Branch seq_branch_adr 0fe2 0x0fe2 seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0fe2 0fe2 fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 4 0fe3 0fe3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame d val_alu_func 13 ONES val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 0fe4 0fe4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 2d VR12:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 0fe5 0fe5 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 06 TR03:19 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl f LOAD_MAR_RESERVED 0fe6 0fe6 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x1040 fiu_load_var 1 hold_var fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1040 0x1040 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR typ_rand d SET_PASS_PRIVACY_BIT 0fe7 0fe7 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0xfec fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fec 0x0fec seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 3 SPARE_0x03 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fe8 0fe8 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xfe9 ; Flow J cc=#0x0 0x1001 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1001 0x1001 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_c_adr 32 GP0d 0fe9 0fe9 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 0fea 0fea fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0xfe8 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fe8 0x0fe8 seq_en_micro 0 val_b_adr 0d GP0d 0feb 0feb fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xfe8 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fe8 0x0fe8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fec 0fec fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0xff2 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ff2 0x0ff2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 0fed 0fed fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0fee 0fee fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0fef 0fef ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 28 LOOP_COUNTER typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 0ff0 0ff0 seq_br_type 7 Unconditional Call; Flow C 0x34d8 seq_branch_adr 34d8 0x34d8 seq_en_micro 0 0ff1 0ff1 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0ff2 0ff2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xff4 seq_br_type 1 Branch True seq_branch_adr 0ff4 0x0ff4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_b_adr 0c GP0c val_rand a PASS_B_HIGH 0ff3 0ff3 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x104c fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 104c 0x104c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_a_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 0b GP0b val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0ff4 0ff4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0ff5 0ff5 seq_b_timing 0 Early Condition; Flow J cc=True 0xffc seq_br_type 1 Branch True seq_branch_adr 0ffc 0x0ffc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 0ff6 0ff6 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0ff7 0ff7 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0ff8 0ff8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0ff9 0ff9 fiu_mem_start 12 start_lru_query; Flow J cc=False 0xff5 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0ff5 0x0ff5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 0ffa 0ffa seq_b_timing 0 Early Condition; Flow J cc=True 0x1000 seq_br_type 1 Branch True seq_branch_adr 1000 0x1000 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 0ffb 0ffb fiu_mem_start 12 start_lru_query; Flow J 0xffa seq_br_type 3 Unconditional Branch seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 0ffc 0ffc fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0ffd 0ffd fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 0ffe 0ffe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0fff 0fff fiu_tivi_src 4 fiu_var; Flow J cc=False 0xff3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ff3 0x0ff3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 1000 1000 fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 1001 1001 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1002 1002 fiu_tivi_src 4 fiu_var; Flow J 0x1009 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1009 0x1009 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d val_alu_func 18 NOT_A_AND_B val_b_adr 30 VR11:10 val_frame 11 1003 1003 fiu_mem_start 11 start_tag_query; Flow J 0x1030 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1030 0x1030 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1004 1004 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1005 1005 fiu_mem_start 11 start_tag_query; Flow J 0x1038 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1038 0x1038 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1006 1006 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1007 1007 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1008 1008 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1009 1009 fiu_mem_start 11 start_tag_query; Flow C 0x34f1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 100a 100a fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1004 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 100b 100b ioc_adrbs 2 typ ; Flow J cc=True 0x1004 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 100c 100c fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1013 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1013 0x1013 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 3b TR02:1b typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0d GP0d 100d 100d fiu_mem_start d start_physical_rd; Flow J cc=False 0x1011 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1011 0x1011 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 100e 100e fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 100f 100f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1004 seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 1010 1010 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1004 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1011 1011 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1004 seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1012 1012 fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1013 1013 seq_br_type 1 Branch True; Flow J cc=True 0x1015 seq_branch_adr 1015 0x1015 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 3c VR06:1c val_frame 6 1014 1014 seq_br_type 3 Unconditional Branch; Flow J 0x1012 seq_branch_adr 1012 0x1012 seq_en_micro 0 typ_c_adr 32 GP0d 1015 1015 fiu_mem_start d start_physical_rd; Flow J cc=True 0x1027 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1027 0x1027 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 1016 1016 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1025 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1025 0x1025 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1017 1017 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 1 1018 1018 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_alu_func 13 ONES val_rand 9 PASS_A_HIGH 1019 1019 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1023 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1023 0x1023 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 15 NOT_B typ_b_adr 0d GP0d 101a 101a fiu_fill_mode_src 0 ; Flow J cc=False 0x101d fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 101d 0x101d seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 101b 101b fiu_fill_mode_src 0 ; Flow J cc=True 0x101c ; Flow J cc=#0x0 0x101c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 101c 0x101c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 101c 101c seq_b_timing 0 Early Condition; Flow J cc=True 0x101d ; Flow J cc=#0x0 0x1025 seq_br_type b Case False seq_branch_adr 1025 0x1025 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 101d 101d fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 101e 101e fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x1004 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 101f 101f seq_br_type 0 Branch False; Flow J cc=False 0x1004 seq_branch_adr 1004 0x1004 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 1020 1020 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1021 1021 ioc_load_wdr 0 ; Flow C 0x34d8 seq_br_type 7 Unconditional Call seq_branch_adr 34d8 0x34d8 seq_en_micro 0 typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 1022 1022 ioc_load_wdr 0 ; Flow J 0x1004 seq_br_type 3 Unconditional Branch seq_branch_adr 1004 0x1004 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1023 1023 fiu_fill_mode_src 0 ; Flow J cc=False 0x1004 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_c_adr 32 GP0d typ_frame d val_b_adr 2f VR0d:0f val_c_adr 32 GP0d val_frame d 1024 1024 seq_b_timing 0 Early Condition; Flow J cc=True 0x1025 ; Flow J cc=#0x0 0x1025 seq_br_type b Case False seq_branch_adr 1025 0x1025 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1025 1025 fiu_mem_start f start_physical_tag_rd; Flow J 0xfe6 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1026 1026 ioc_load_wdr 0 ; Flow J 0x1004 seq_br_type 3 Unconditional Branch seq_branch_adr 1004 0x1004 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1027 1027 fiu_mem_start d start_physical_rd seq_en_micro 0 1028 1028 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1025 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1025 0x1025 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1029 1029 fiu_len_fill_lit 07 sign-fill 0x7 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 102a 102a fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS 102b 102b fiu_fill_mode_src 0 ; Flow J cc=True 0x1023 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1023 0x1023 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 102c 102c fiu_fill_mode_src 0 ; Flow J cc=True 0x102d ; Flow J cc=#0x0 0x102e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 102e 0x102e seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 102d 102d fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 102e 102e seq_b_timing 0 Early Condition; Flow J cc=True 0x102f ; Flow J cc=#0x0 0x1025 seq_br_type b Case False seq_branch_adr 1025 0x1025 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 102f 102f fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1030 1030 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1004 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d 1031 1031 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 1032 1032 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1004 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 1033 1033 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 1034 1034 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1004 seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_en_micro 0 1035 1035 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 2a TR09:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 1036 1036 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1004 seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1037 1037 fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1038 1038 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1004 seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 11 1039 1039 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 103a 103a fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1004 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1004 0x1004 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 103b 103b fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 103c 103c seq_b_timing 1 Latch Condition; Flow J cc=True 0x1004 seq_br_type 1 Branch True seq_branch_adr 1004 0x1004 seq_en_micro 0 103d 103d ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 103e 103e seq_br_type 1 Branch True; Flow J cc=True 0x1004 seq_branch_adr 1004 0x1004 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 103f 103f fiu_mem_start f start_physical_tag_rd; Flow J 0xfed ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0fed 0x0fed seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1040 1040 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1041 1041 fiu_len_fill_lit 46 zero-fill 0x6 fiu_mem_start 2 start-rd fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR03:19 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA 1042 1042 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x1049 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1049 0x1049 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_frame 12 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR04:02 val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 1043 1043 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1044 1044 fiu_mem_start 2 start-rd; Flow C 0x107a ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 107a 0x107a seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_frame 4 1045 1045 fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1046 1046 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 1047 1047 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 1048 1048 seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 1049 1049 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0xfeb ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0feb 0x0feb seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 39 VR03:19 val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_frame 3 104a 104a fiu_mem_start 15 setup_tag_read seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 104b 104b fiu_mem_start 15 setup_tag_read; Flow J 0xfeb seq_br_type 3 Unconditional Branch seq_branch_adr 0feb 0x0feb seq_en_micro 0 typ_c_adr 30 GP0f val_c_adr 30 GP0f 104c ; -------------------------------------------------------------------------------------- 104c ; Comes from: 104c ; 33d9 C True from color 0x0f05 104c ; 33fc C from color 0x0000 104c ; -------------------------------------------------------------------------------------- 104c 104c fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x106d fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 106d 0x106d seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 104d 104d fiu_mem_start 15 setup_tag_read; Flow J 0x104e seq_br_type 2 Push (branch address) seq_branch_adr 1064 0x1064 seq_en_micro 0 104e 104e fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1052 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1052 0x1052 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 104f 104f fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x106d fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 106d 0x106d seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1050 1050 fiu_mem_start 15 setup_tag_read; Flow J 0x1051 seq_br_type 2 Push (branch address) seq_branch_adr 1065 0x1065 seq_en_micro 0 1051 1051 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1052 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1052 0x1052 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1052 1052 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1053 ; Flow J cc=#0x0 0x1054 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1054 0x1054 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_frame 12 1053 1053 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1054 1054 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1055 1055 fiu_mem_start 11 start_tag_query; Flow J 0x105c ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105c 0x105c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1056 1056 fiu_mem_start 11 start_tag_query; Flow J 0x105c ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105c 0x105c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1057 1057 fiu_mem_start 11 start_tag_query; Flow J 0x105c ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105c 0x105c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1058 1058 fiu_mem_start 11 start_tag_query; Flow J 0x105c ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105c 0x105c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1059 1059 fiu_mem_start 11 start_tag_query; Flow J 0x105c ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 105c 0x105c seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 105a 105a ioc_adrbs 1 val ; Flow J 0x3626 seq_br_type 3 Unconditional Branch seq_branch_adr 3626 0x3626 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 105b 105b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 105c 105c fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 105d 105d fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1063 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1063 0x1063 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 105e 105e fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 105f 105f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1 A_PLUS_B val_b_adr 0b GP0b 1060 1060 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x1063 seq_br_type 0 Branch False seq_branch_adr 1063 0x1063 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 1061 1061 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1063 seq_br_type 1 Branch True seq_branch_adr 1063 0x1063 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1062 1062 ioc_adrbs 1 val ; Flow J 0x3627 seq_br_type 3 Unconditional Branch seq_branch_adr 3627 0x3627 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1063 1063 ioc_adrbs 1 val ; Flow J 0x3626 seq_br_type 3 Unconditional Branch seq_branch_adr 3626 0x3626 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1064 1064 fiu_mem_start 2 start-rd; Flow J 0x1066 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1066 0x1066 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR02:11 val_frame 2 1065 1065 fiu_mem_start 2 start-rd; Flow J 0x1066 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1066 0x1066 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR02:19 val_frame 2 1066 1066 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 1067 1067 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1068 1068 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 1069 1069 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x106c seq_br_type 1 Branch True seq_branch_adr 106c 0x106c seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0b GP0b val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 106a 106a fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 106b 106b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_b_adr 0c GP0c 106c 106c fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362a fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362a 0x362a seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 106d ; -------------------------------------------------------------------------------------- 106d ; Comes from: 106d ; 104c C True from color 0x0fd0 106d ; 104f C True from color 0x0fd0 106d ; -------------------------------------------------------------------------------------- 106d 106d fiu_mem_start 15 setup_tag_read; Flow J cc=True 0x107b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 107b 0x107b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 10 NOT_A typ_c_adr 34 GP0b val_c_adr 34 GP0b 106e 106e ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 106f 106f ioc_fiubs 1 val ; Flow C 0x368f seq_br_type 7 Unconditional Call seq_branch_adr 368f 0x368f seq_en_micro 0 val_a_adr 23 VR04:03 val_c_adr 1c VR04:03 val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1070 1070 seq_br_type 0 Branch False; Flow J cc=False 0x1072 seq_branch_adr 1072 0x1072 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 1071 1071 fiu_mem_start f start_physical_tag_rd; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 1072 1072 fiu_mem_start 11 start_tag_query; Flow J cc=True 0x1076 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1076 0x1076 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 1073 1073 seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 1074 1074 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 1075 1075 fiu_mem_start f start_physical_tag_rd; Flow R cc=True ; Flow J cc=False 0x1077 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 1077 0x1077 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1076 1076 fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED 1077 1077 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 1078 1078 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 2 1079 1079 seq_br_type 7 Unconditional Call; Flow C 0x34d8 seq_branch_adr 34d8 0x34d8 seq_en_micro 0 107a ; -------------------------------------------------------------------------------------- 107a ; Comes from: 107a ; 1044 C from color 0x0fd0 107a ; -------------------------------------------------------------------------------------- 107a 107a seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 107b 107b fiu_tivi_src 8 type_var; Flow C cc=True 0x2a82 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 0b GP0b 107c 107c fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 107d 107d seq_en_micro 0 107e 107e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 107f 107f fiu_mem_start f start_physical_tag_rd; Flow C 0x34fa fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1080 1080 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1081 1081 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1085 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1085 0x1085 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 1082 1082 fiu_mem_start 12 start_lru_query; Flow J cc=True 0x107e fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 107e 0x107e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 1083 1083 seq_br_type 1 Branch True; Flow J cc=True 0x107e seq_branch_adr 107e 0x107e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 1084 1084 ioc_tvbs 2 fiu+val; Flow J 0x107e seq_br_type 3 Unconditional Branch seq_branch_adr 107e 0x107e seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1085 1085 fiu_load_var 1 hold_var; Flow J cc=True 0x1088 fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1088 0x1088 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 1086 1086 seq_br_type 1 Branch True; Flow J cc=True 0x1088 seq_branch_adr 1088 0x1088 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 1087 1087 ioc_tvbs 2 fiu+val; Flow J 0x1088 seq_br_type 3 Unconditional Branch seq_branch_adr 1088 0x1088 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1088 1088 fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f 1089 1089 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x108b fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 108b 0x108b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS 108a 108a fiu_mem_start 3 start-wr; Flow J 0x3b59 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b59 0x3b59 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 108b 108b fiu_mem_start 3 start-wr; Flow C 0x211 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0211 0x0211 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 0b GP0b 108c ; -------------------------------------------------------------------------------------- 108c ; 0x03bf Declare_Variable Access 108c ; -------------------------------------------------------------------------------------- 108c MACRO_Declare_Variable_Access: 108c 108c dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 108c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR10:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 108d 108d <halt> ; Flow R 108e ; -------------------------------------------------------------------------------------- 108e ; 0x03be Declare_Variable Access,Visible 108e ; -------------------------------------------------------------------------------------- 108e MACRO_Declare_Variable_Access,Visible: 108e 108e dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 108e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 108f 108f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR07:1e typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1090 ; -------------------------------------------------------------------------------------- 1090 ; 0x03bd Declare_Variable Access,Duplicate 1090 ; -------------------------------------------------------------------------------------- 1090 MACRO_Declare_Variable_Access,Duplicate: 1090 1090 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1090 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1091 1091 <halt> ; Flow R 1092 ; -------------------------------------------------------------------------------------- 1092 ; 0x039f Declare_Variable Heap_Access 1092 ; -------------------------------------------------------------------------------------- 1092 MACRO_Declare_Variable_Heap_Access: 1092 1092 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1092 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR18:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1093 1093 <halt> ; Flow R 1094 ; -------------------------------------------------------------------------------------- 1094 ; 0x039e Declare_Variable Heap_Access,Visible 1094 ; -------------------------------------------------------------------------------------- 1094 MACRO_Declare_Variable_Heap_Access,Visible: 1094 1094 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1094 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 1095 1095 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR11:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1096 ; -------------------------------------------------------------------------------------- 1096 ; 0x039d Declare_Variable Heap_Access,Duplicate 1096 ; -------------------------------------------------------------------------------------- 1096 MACRO_Declare_Variable_Heap_Access,Duplicate: 1096 1096 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1096 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1097 ; -------------------------------------------------------------------------------------- 1097 ; Comes from: 1097 ; 10a6 C from color MACRO_Declare_Variable_Access,By_Allocation 1097 ; 10fe C from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 1097 ; 11e2 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 1097 ; 1240 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 1097 ; -------------------------------------------------------------------------------------- 1097 1097 <default> 1098 1098 fiu_load_tar 1 hold_tar; Flow J 0x109b fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 109b 0x109b typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1099 ; -------------------------------------------------------------------------------------- 1099 ; Comes from: 1099 ; 10ae C from color 0x10a8 1099 ; 1106 C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 1099 ; 11ea C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 1099 ; 1248 C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 1099 ; -------------------------------------------------------------------------------------- 1099 1099 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 109a 109a fiu_load_tar 1 hold_tar; Flow J 0x109b fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 109b 0x109b typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 109b 109b ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 01 GP01 109c 109c fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 109d 0x109d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 109d 109d seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 109e ; -------------------------------------------------------------------------------------- 109e ; Comes from: 109e ; 10aa C from color 0x10a8 109e ; 1102 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 109e ; 11e6 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 109e ; 1244 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 109e ; -------------------------------------------------------------------------------------- 109e 109e <default> 109f 109f fiu_load_tar 1 hold_tar; Flow J 0x10a2 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10a2 0x10a2 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10a0 ; -------------------------------------------------------------------------------------- 10a0 ; Comes from: 10a0 ; 10b2 C from color 0x10a8 10a0 ; 110a C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 10a0 ; 11ee C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 10a0 ; 124c C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 10a0 ; -------------------------------------------------------------------------------------- 10a0 10a0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 10a1 10a1 fiu_load_tar 1 hold_tar; Flow J 0x10a2 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10a2 0x10a2 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10a2 10a2 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 10a3 10a3 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 10a4 0x10a4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10a4 10a4 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 10a5 10a5 <halt> ; Flow R 10a6 ; -------------------------------------------------------------------------------------- 10a6 ; 0x03bc Declare_Variable Access,By_Allocation 10a6 ; -------------------------------------------------------------------------------------- 10a6 MACRO_Declare_Variable_Access,By_Allocation: 10a6 10a6 dispatch_brk_class 4 ; Flow C 0x1097 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10a6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1097 0x1097 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10a7 10a7 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b6 0x10b6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10a8 10a8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d1 0x10d1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10a9 10a9 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 10aa ; -------------------------------------------------------------------------------------- 10aa ; 0x039c Declare_Variable Heap_Access,By_Allocation 10aa ; -------------------------------------------------------------------------------------- 10aa MACRO_Declare_Variable_Heap_Access,By_Allocation: 10aa 10aa dispatch_brk_class 4 ; Flow C 0x109e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10aa fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109e 0x109e typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10ab 10ab fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b6 0x10b6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10ac 10ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d1 0x10d1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10ad 10ad seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 10ae ; -------------------------------------------------------------------------------------- 10ae ; 0x03bb Declare_Variable Access,Visible,By_Allocation 10ae ; -------------------------------------------------------------------------------------- 10ae MACRO_Declare_Variable_Access,Visible,By_Allocation: 10ae 10ae dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10ae fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10af 10af fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b6 0x10b6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10b0 10b0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d1 0x10d1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10b1 10b1 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 10b2 ; -------------------------------------------------------------------------------------- 10b2 ; 0x039b Declare_Variable Heap_Access,Visible,By_Allocation 10b2 ; -------------------------------------------------------------------------------------- 10b2 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation: 10b2 10b2 dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10b2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10b3 10b3 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10b6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10b6 0x10b6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10b4 10b4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 10d1 0x10d1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10b5 10b5 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 10b6 ; -------------------------------------------------------------------------------------- 10b6 ; Comes from: 10b6 ; 10a7 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation 10b6 ; -------------------------------------------------------------------------------------- 10b6 10b6 seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10b7 10b7 seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10b8 10b8 seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10b9 10b9 seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10ba 10ba seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10bb 10bb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10bc 10bc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10bd 10bd seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10be 10be seq_br_type 3 Unconditional Branch; Flow J 0x10c6 seq_branch_adr 10c6 0x10c6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10bf 10bf seq_br_type 3 Unconditional Branch; Flow J 0x10ca seq_branch_adr 10ca 0x10ca val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c0 10c0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c1 10c1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c2 10c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10c3 10c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10c6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c6 0x10c6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR05:00 typ_b_adr 01 GP01 typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c4 10c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10c6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c6 0x10c6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2f TR11:0f typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c5 10c5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10c6 0x10c6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2e TR11:0e typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10c6 10c6 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10c7 10c7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 10c8 0x10c8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 10c8 10c8 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 10c9 10c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10ca 10ca ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 10cb 10cb fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10cc 10cc seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 10cd 10cd typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 10ce 10ce ioc_fiubs 2 typ typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_source 0 FIU_BUS 10cf 10cf seq_br_type 7 Unconditional Call; Flow C 0x29b3 seq_branch_adr 29b3 0x29b3 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10d0 10d0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10d1 10d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x10d3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10d3 0x10d3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 10d2 10d2 seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 10d3 ; -------------------------------------------------------------------------------------- 10d3 ; Comes from: 10d3 ; 10d1 C #0x0 from color 0x10a8 10d3 ; -------------------------------------------------------------------------------------- 10d3 10d3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10d4 10d4 ioc_fiubs 0 fiu ; Flow R cc=False ; Flow J cc=True 0x10db seq_br_type 9 Return False seq_branch_adr 10db 0x10db seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 10d5 10d5 ioc_fiubs 2 typ ; Flow J 0x10ef seq_br_type 3 Unconditional Branch seq_branch_adr 10ef 0x10ef seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 27 TR09:07 typ_frame 9 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 10d6 10d6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 10d7 10d7 <default> 10d8 10d8 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10d9 10d9 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 10da 10da seq_br_type 3 Unconditional Branch; Flow J 0x10f0 seq_branch_adr 10f0 0x10f0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 10db 10db fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x10e0 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 10e0 0x10e0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10dc 10dc fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10dd 10dd val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 10de 10de fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10df 10df seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 10e0 10e0 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10e1 10e1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 10e2 10e2 fiu_fill_mode_src 0 ; Flow J cc=False 0x10ec fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 10ec 0x10ec seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 10e3 10e3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 10e4 10e4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 10e5 10e5 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 10e6 0x10e6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 10e6 10e6 seq_b_timing 1 Latch Condition; Flow J cc=True 0x10e9 seq_br_type 1 Branch True seq_branch_adr 10e9 0x10e9 10e7 10e7 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 10e8 10e8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10e9 10e9 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x118a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 118a 0x118a typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 10ea 10ea ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 10eb 10eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10ec 10ec fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 10ed 10ed fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 10ee 10ee fiu_load_var 1 hold_var; Flow J 0x10e4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 10e4 0x10e4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 10ef 10ef typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 10f0 10f0 ioc_fiubs 0 fiu ; Flow J cc=False 0x10f3 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 10f3 0x10f3 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 10f1 10f1 ioc_fiubs 2 typ ; Flow C 0x2254 seq_br_type 7 Unconditional Call seq_branch_adr 2254 0x2254 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10f2 10f2 ioc_fiubs 2 typ ; Flow C cc=True 0x10fc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 10fc 0x10fc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 10f3 10f3 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 10f4 0x10f4 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 10f4 10f4 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10f5 10f5 ioc_fiubs 2 typ ; Flow C 0x2226 seq_br_type 7 Unconditional Call seq_branch_adr 2226 0x2226 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10f6 10f6 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 10f7 0x10f7 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_source 0 FIU_BUS 10f7 10f7 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 10f8 10f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2246 seq_br_type 5 Call True seq_branch_adr 2246 0x2246 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 04 GP04 10f9 10f9 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 10fa 0x10fa seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL 10fa 10fa seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 10fb 10fb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10fc ; -------------------------------------------------------------------------------------- 10fc ; Comes from: 10fc ; 10f2 C True from color 0x10d5 10fc ; -------------------------------------------------------------------------------------- 10fc 10fc seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 10fd 10fd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 10fe ; -------------------------------------------------------------------------------------- 10fe ; 0x03b6 Declare_Variable Access,By_Allocation,With_Value 10fe ; -------------------------------------------------------------------------------------- 10fe MACRO_Declare_Variable_Access,By_Allocation,With_Value: 10fe 10fe dispatch_brk_class 4 ; Flow C 0x1097 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10fe fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1097 0x1097 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10ff 10ff fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110d fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110d 0x110d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1100 1100 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1101 1101 <halt> ; Flow R 1102 ; -------------------------------------------------------------------------------------- 1102 ; 0x0396 Declare_Variable Heap_Access,By_Allocation,With_Value 1102 ; -------------------------------------------------------------------------------------- 1102 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value: 1102 1102 dispatch_brk_class 4 ; Flow C 0x109e dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1102 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109e 0x109e typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1103 1103 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110d fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110d 0x110d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1104 1104 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1105 1105 <halt> ; Flow R 1106 ; -------------------------------------------------------------------------------------- 1106 ; 0x03b5 Declare_Variable Access,Visible,By_Allocation,With_Value 1106 ; -------------------------------------------------------------------------------------- 1106 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value: 1106 1106 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1106 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 1107 1107 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110d fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110d 0x110d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1108 1108 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1109 1109 <halt> ; Flow R 110a ; -------------------------------------------------------------------------------------- 110a ; 0x0395 Declare_Variable Heap_Access,Visible,By_Allocation,With_Value 110a ; -------------------------------------------------------------------------------------- 110a MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value: 110a 110a dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 110a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 110b 110b fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x110d fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 110d 0x110d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 110c 110c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 110d ; -------------------------------------------------------------------------------------- 110d ; Comes from: 110d ; 10ff C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 110d ; 1103 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 110d ; 1107 C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 110d ; 110b C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 110d ; -------------------------------------------------------------------------------------- 110d 110d ioc_fiubs 1 val ; Flow J 0x1121 seq_br_type 3 Unconditional Branch seq_branch_adr 1121 0x1121 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 110e 110e ioc_fiubs 1 val ; Flow J 0x112f seq_br_type 3 Unconditional Branch seq_branch_adr 112f 0x112f typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 110f 110f seq_br_type 3 Unconditional Branch; Flow J 0x113d seq_branch_adr 113d 0x113d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1110 1110 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1111 1111 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1112 1112 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1113 1113 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1114 1114 seq_br_type 3 Unconditional Branch; Flow J 0x1147 seq_branch_adr 1147 0x1147 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 1115 1115 seq_br_type 3 Unconditional Branch; Flow J 0x1158 seq_branch_adr 1158 0x1158 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 1116 1116 ioc_fiubs 0 fiu ; Flow J 0x115f seq_br_type 3 Unconditional Branch seq_branch_adr 115f 0x115f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1117 1117 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1118 1118 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1119 1119 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 111a 111a seq_br_type 3 Unconditional Branch; Flow J 0x116f seq_branch_adr 116f 0x116f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH 111b 111b ioc_fiubs 1 val ; Flow J 0x11b2 seq_br_type 3 Unconditional Branch seq_branch_adr 11b2 0x11b2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 11 111c 111c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 111d 111d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand a PASS_B_HIGH 111e 111e fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 111f 111f seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1120 1120 seq_br_type 3 Unconditional Branch; Flow J 0x11b2 seq_branch_adr 11b2 0x11b2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 1121 1121 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x112b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 112b 0x112b seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1122 1122 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1123 1123 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1124 1124 fiu_fill_mode_src 0 ; Flow J cc=False 0x1128 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1128 0x1128 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1125 1125 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1126 1126 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1127 1127 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1128 1128 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1129 1129 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 112a 112a fiu_mem_start 4 continue; Flow J 0x1126 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1126 0x1126 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 112b 112b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 112c 112c <default> 112d 112d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 112e 112e seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 112f 112f ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 1130 1130 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1134 seq_br_type 1 Branch True seq_branch_adr 1134 0x1134 typ_c_adr 3c GP03 val_c_adr 3c GP03 1131 1131 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1136 seq_br_type 1 Branch True seq_branch_adr 1136 0x1136 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1132 1132 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1133 1133 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1124 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1124 0x1124 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1134 1134 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1136 seq_br_type 1 Branch True seq_branch_adr 1136 0x1136 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 1135 1135 seq_br_type 1 Branch True; Flow J cc=True 0x1132 seq_branch_adr 1132 0x1132 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1136 1136 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1137 1137 seq_b_timing 1 Latch Condition; Flow J cc=True 0x113a seq_br_type 1 Branch True seq_branch_adr 113a 0x113a 1138 1138 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1139 1139 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 113a 113a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3276 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 113b 113b seq_br_type 5 Call True; Flow C cc=True 0x326c seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 113c 113c seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 113d 113d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1140 seq_br_type 1 Branch True seq_branch_adr 1140 0x1140 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 113e 113e seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 113f 113f seq_b_timing 1 Latch Condition; Flow J cc=False 0x1142 seq_br_type 0 Branch False seq_branch_adr 1142 0x1142 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1140 1140 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1141 1141 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1124 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1124 0x1124 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1142 1142 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1143 1143 <default> 1144 1144 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3273 seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1145 1145 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a 1146 1146 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1147 1147 seq_b_timing 1 Latch Condition; Flow J cc=True 0x114a seq_br_type 1 Branch True seq_branch_adr 114a 0x114a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1148 1148 seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1149 1149 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1142 seq_br_type 0 Branch False seq_branch_adr 1142 0x1142 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 114a 114a fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 114b 114b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_b_adr 02 GP02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 114c 114c fiu_fill_mode_src 0 ; Flow J cc=False 0x1150 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1150 0x1150 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 114d 114d fiu_fill_mode_src 0 ; Flow C cc=True 0x1154 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1154 0x1154 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 114e 114e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 114f 114f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1150 1150 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1151 1151 fiu_fill_mode_src 0 ; Flow C cc=True 0x1154 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1154 0x1154 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1152 1152 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR 1153 1153 ioc_load_wdr 0 ; Flow J 0x114f ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 114f 0x114f val_b_adr 04 GP04 1154 ; -------------------------------------------------------------------------------------- 1154 ; Comes from: 1154 ; 114d C True from color 0x110d 1154 ; 1151 C True from color 0x110d 1154 ; -------------------------------------------------------------------------------------- 1154 1154 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32af ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1155 1155 fiu_fill_mode_src 0 ; Flow J cc=False 0x1157 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1157 0x1157 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1156 1156 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1157 1157 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1158 1158 ioc_fiubs 0 fiu ; Flow C cc=False 0x115e seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 115e 0x115e typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1159 1159 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 115a 115a ioc_fiubs 1 val ; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 115b 115b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 115c 115c seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 115d 115d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 115e ; -------------------------------------------------------------------------------------- 115e ; Comes from: 115e ; 1158 C False from color 0x1115 115e ; -------------------------------------------------------------------------------------- 115e 115e fiu_mem_start 2 start-rd; Flow J 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 115f 115f fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1168 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1168 0x1168 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1160 1160 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1161 1161 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x1169 seq_br_type f Unconditional Case Call seq_branch_adr 1169 0x1169 seq_en_micro 0 1162 1162 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1163 1163 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1164 1164 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1165 1165 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1166 1166 ioc_load_wdr 0 ; Flow C 0x1eec ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1167 1167 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1168 ; -------------------------------------------------------------------------------------- 1168 ; Comes from: 1168 ; 115f C False from color 0x1116 1168 ; -------------------------------------------------------------------------------------- 1168 1168 fiu_mem_start 2 start-rd; Flow J 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1169 ; -------------------------------------------------------------------------------------- 1169 ; Comes from: 1169 ; 1161 C #0x0 from color 0x1116 1169 ; -------------------------------------------------------------------------------------- 1169 1169 seq_br_type 3 Unconditional Branch; Flow J 0x116d seq_branch_adr 116d 0x116d typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 116a 116a fiu_load_oreg 1 hold_oreg; Flow C 0x24e3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 24e3 0x24e3 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 116b 116b seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 116c 0x116c 116c 116c seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 116d 116d ioc_fiubs 2 typ ; Flow C 0x2456 seq_br_type 7 Unconditional Call seq_branch_adr 2456 0x2456 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 01 GP01 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 116e 116e seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 116f 116f ioc_tvbs 1 typ+fiu; Flow C cc=False 0x11b1 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11b1 0x11b1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1170 1170 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1171 1171 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x1198 seq_br_type f Unconditional Case Call seq_branch_adr 1198 0x1198 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 1172 1172 fiu_load_var 1 hold_var; Flow J cc=True 0x1178 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1178 0x1178 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 05 GP05 typ_b_adr 01 GP01 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1173 1173 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1174 1174 seq_br_type 1 Branch True; Flow J cc=True 0x1194 seq_branch_adr 1194 0x1194 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 1175 1175 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1176 1176 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1194 seq_br_type 1 Branch True seq_branch_adr 1194 0x1194 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 1177 1177 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1178 1178 fiu_load_var 1 hold_var; Flow J cc=True 0x117c fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 117c 0x117c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 1179 1179 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 117a 117a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 117b 117b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 117c 117c val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 117d 117d fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 117e 117e fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 05 GP05 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 117f 117f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 1180 1180 fiu_fill_mode_src 0 ; Flow J cc=True 0x1184 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1184 0x1184 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1181 1181 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 1182 1182 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1183 1183 fiu_load_var 1 hold_var; Flow J 0x1185 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1185 0x1185 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1184 1184 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1185 1185 ioc_load_wdr 0 ; Flow J cc=True 0x118f ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 118f 0x118f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1186 1186 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x118a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 118a 0x118a typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1187 1187 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1188 1188 seq_br_type 1 Branch True; Flow J cc=True 0x1191 seq_branch_adr 1191 0x1191 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 1189 1189 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 118a ; -------------------------------------------------------------------------------------- 118a ; Comes from: 118a ; 10e9 C from color 0x10d4 118a ; -------------------------------------------------------------------------------------- 118a 118a fiu_fill_mode_src 0 ; Flow J cc=True 0x118e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 118e 0x118e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 39 GP06 val_c_source 0 FIU_BUS 118b 118b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 118c 118c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 30 GP0f typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 118d 118d fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 118e 118e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 118f 118f typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1190 1190 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 1191 1191 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1192 1192 ioc_fiubs 1 val ; Flow C 0x228a seq_br_type 7 Unconditional Call seq_branch_adr 228a 0x228a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1193 1193 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1194 1194 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1195 1195 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1197 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1197 0x1197 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1196 1196 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eec fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1197 1197 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1198 ; -------------------------------------------------------------------------------------- 1198 ; Comes from: 1198 ; 1171 C #0x0 from color 0x111a 1198 ; -------------------------------------------------------------------------------------- 1198 1198 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x119a fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 119a 0x119a typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1199 1199 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x11a0 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11a0 0x11a0 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 119a 119a fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 119b 119b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 119c 119c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 119d 0x119d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 119d 119d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 119e 119e typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 119f 119f ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11a0 11a0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 11a1 11a1 fiu_fill_mode_src 0 ; Flow C 0x11a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 11a6 0x11a6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 11a2 11a2 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 11a3 11a3 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 11a4 0x11a4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 11a4 11a4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 11a5 11a5 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 11a6 ; -------------------------------------------------------------------------------------- 11a6 ; Comes from: 11a6 ; 11a1 C from color 0x1199 11a6 ; -------------------------------------------------------------------------------------- 11a6 11a6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11ae seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11ae 0x11ae seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 11a7 11a7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11a8 11a8 fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11a9 0x11a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11a9 11a9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 11aa 11aa fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11ac seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11ac 0x11ac seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11ab 11ab fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11ac 11ac fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11ad 11ad fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11ae 11ae fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11af 11af fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11b0 11b0 fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True ; Flow J cc=False 0x11a9 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11a9 0x11a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11b1 ; -------------------------------------------------------------------------------------- 11b1 ; Comes from: 11b1 ; 116f C False from color 0x111a 11b1 ; 11b2 C False from color 0x111b 11b1 ; -------------------------------------------------------------------------------------- 11b1 11b1 fiu_mem_start 2 start-rd; Flow J 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11b2 11b2 ioc_fiubs 2 typ ; Flow C cc=False 0x11b1 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11b1 0x11b1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 11b3 11b3 ioc_fiubs 2 typ ; Flow C cc=True 0x32a7 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11b4 11b4 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11c5 seq_br_type 1 Branch True seq_branch_adr 11c5 0x11c5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 11b5 11b5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1192 seq_br_type 1 Branch True seq_branch_adr 1192 0x1192 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 11b6 11b6 seq_br_type 7 Unconditional Call; Flow C 0x2294 seq_branch_adr 2294 0x2294 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11b7 11b7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11b9 seq_br_type 1 Branch True seq_branch_adr 11b9 0x11b9 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 11b8 11b8 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 11b9 11b9 ioc_fiubs 2 typ ; Flow C 0x2254 seq_br_type 7 Unconditional Call seq_branch_adr 2254 0x2254 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11ba 11ba seq_br_type 1 Branch True; Flow J cc=True 0x1194 seq_branch_adr 1194 0x1194 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 11bb 11bb seq_br_type 3 Unconditional Branch; Flow J 0x1194 seq_branch_adr 1194 0x1194 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 11bc 11bc ioc_fiubs 1 val ; Flow C 0x226b seq_br_type 7 Unconditional Call seq_branch_adr 226b 0x226b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 11bd 11bd seq_b_timing 1 Latch Condition; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11be 11be fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x11d4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 11d4 0x11d4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 11bf 11bf ioc_fiubs 2 typ ; Flow C cc=True 0x11df seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 11df 0x11df typ_a_adr 17 LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11c0 11c0 seq_br_type 4 Call False; Flow C cc=False 0x32a0 seq_branch_adr 32a0 0x32a0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11c1 11c1 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11c2 11c2 ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11c3 11c3 seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11c4 11c4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11c5 11c5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11bc seq_br_type 1 Branch True seq_branch_adr 11bc 0x11bc typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11c6 11c6 seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11c7 11c7 ioc_fiubs 2 typ ; Flow C cc=False 0x3270 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11c8 11c8 fiu_mem_start 2 start-rd; Flow C cc=True 0x11df ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 11df 0x11df seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11c9 11c9 <default> 11ca 11ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 11cb 11cb seq_br_type 4 Call False; Flow C cc=False 0x32a0 seq_branch_adr 32a0 0x32a0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11cc 11cc fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11cd 11cd ioc_fiubs 2 typ ; Flow C 0x2226 seq_br_type 7 Unconditional Call seq_branch_adr 2226 0x2226 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11ce 11ce fiu_load_tar 1 hold_tar; Flow J cc=True 0x11d1 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 11d1 0x11d1 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11cf 11cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eec fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11d0 11d0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11d1 11d1 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11d2 11d2 seq_br_type 7 Unconditional Call; Flow C 0x2246 seq_branch_adr 2246 0x2246 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11d3 11d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11d4 ; -------------------------------------------------------------------------------------- 11d4 ; Comes from: 11d4 ; 11be C from color 0x111b 11d4 ; -------------------------------------------------------------------------------------- 11d4 11d4 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x11d8 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 11d8 0x11d8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 11d5 11d5 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11d6 11d6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11d7 11d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x11da fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11da 0x11da seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11d8 11d8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11d9 11d9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11da 11da seq_br_type 0 Branch False; Flow J cc=False 0x11dc seq_branch_adr 11dc 0x11dc seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_rand c START_MULTIPLY 11db 11db seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 11dc 11dc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 11dd 11dd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 11de 11de seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 11df ; -------------------------------------------------------------------------------------- 11df ; Comes from: 11df ; 11bf C True from color 0x111b 11df ; 11c8 C True from color 0x111b 11df ; -------------------------------------------------------------------------------------- 11df 11df seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 11e0 11e0 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 11e1 11e1 <halt> ; Flow R 11e2 ; -------------------------------------------------------------------------------------- 11e2 ; 0x03b8 Declare_Variable Access,By_Allocation,With_Subtype 11e2 ; -------------------------------------------------------------------------------------- 11e2 MACRO_Declare_Variable_Access,By_Allocation,With_Subtype: 11e2 11e2 dispatch_brk_class 4 ; Flow C 0x1097 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 11e2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1097 0x1097 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 11e3 11e3 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f1 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f1 0x11f1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11e4 11e4 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 11e5 11e5 <halt> ; Flow R 11e6 ; -------------------------------------------------------------------------------------- 11e6 ; 0x0398 Declare_Variable Heap_Access,By_Allocation,With_Subtype 11e6 ; -------------------------------------------------------------------------------------- 11e6 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype: 11e6 11e6 dispatch_brk_class 4 ; Flow C 0x109e dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 11e6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109e 0x109e typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 11e7 11e7 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f1 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f1 0x11f1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11e8 11e8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 11e9 11e9 <halt> ; Flow R 11ea ; -------------------------------------------------------------------------------------- 11ea ; 0x03b7 Declare_Variable Access,Visible,By_Allocation,With_Subtype 11ea ; -------------------------------------------------------------------------------------- 11ea MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype: 11ea 11ea dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 11ea fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 11eb 11eb fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f1 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f1 0x11f1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11ec 11ec seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 11ed 11ed <halt> ; Flow R 11ee ; -------------------------------------------------------------------------------------- 11ee ; 0x0397 Declare_Variable Heap_Access,Visible,By_Allocation,With_Subtype 11ee ; -------------------------------------------------------------------------------------- 11ee MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype: 11ee 11ee dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 11ee fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 11ef 11ef fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x11f1 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 11f1 0x11f1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 11f0 11f0 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 11f1 ; -------------------------------------------------------------------------------------- 11f1 ; Comes from: 11f1 ; 11e3 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 11f1 ; 11e7 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 11f1 ; 11eb C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 11f1 ; 11ef C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 11f1 ; -------------------------------------------------------------------------------------- 11f1 11f1 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11f2 11f2 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11f3 11f3 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11f4 11f4 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11f5 11f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11f6 11f6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11f7 11f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11f8 11f8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11f9 11f9 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 11fa 11fa seq_br_type 3 Unconditional Branch; Flow J 0x1205 seq_branch_adr 1205 0x1205 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 11fb 11fb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11fc 11fc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11fd 11fd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 11fe 11fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x120c fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 120c 0x120c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_frame 2 11ff 11ff fiu_load_var 1 hold_var; Flow R cc=False ; Flow J cc=True 0x122a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 122a 0x122a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 11 1200 1200 fiu_mem_start 9 start_continue_if_true; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1201 0x1201 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR 1201 1201 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH 1202 1202 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1203 1203 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1204 1204 seq_br_type 3 Unconditional Branch; Flow J 0x122a seq_branch_adr 122a 0x122a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1205 1205 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1206 1206 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1207 1207 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1208 1208 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1209 1209 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 120a 120a fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 120b 120b seq_br_type 3 Unconditional Branch; Flow J 0x10cd seq_branch_adr 10cd 0x10cd seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 120c 120c fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 120d 120d fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 120e 120e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 120f 120f fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1210 1210 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1211 1211 fiu_load_var 1 hold_var; Flow J cc=True 0x1217 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1217 0x1217 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1212 1212 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1213 1213 ioc_fiubs 0 fiu ; Flow C cc=False 0x32aa ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 1214 1214 seq_br_type 2 Push (branch address); Flow J 0x1215 seq_branch_adr 329a 0x329a typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1215 1215 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x121c fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 121c 0x121c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 06 GP06 val_a_adr 03 GP03 1216 1216 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1217 1217 fiu_mem_start 2 start-rd; Flow C cc=False 0x32aa ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 1218 1218 seq_br_type 2 Push (branch address); Flow J 0x1219 seq_branch_adr 329a 0x329a val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1219 1219 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 121a 121a seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 121b 121b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x121d fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 121d 0x121d seq_en_micro 0 val_a_adr 03 GP03 121c 121c fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x121e fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 9 Return False seq_branch_adr 121e 0x121e seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 121d 121d seq_br_type 3 Unconditional Branch; Flow J 0x121e seq_branch_adr 121e 0x121e val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 121e 121e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3594 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A 121f 121f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1220 1220 fiu_fill_mode_src 0 ; Flow J cc=False 0x1227 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1227 0x1227 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1221 1221 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1222 1222 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 1223 1223 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1224 0x1224 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 1224 1224 seq_b_timing 1 Latch Condition; Flow J cc=True 0x10e9 seq_br_type 1 Branch True seq_branch_adr 10e9 0x10e9 1225 1225 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1226 1226 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1227 1227 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 1228 1228 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1229 1229 fiu_load_var 1 hold_var; Flow J 0x1222 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1222 0x1222 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 122a 122a fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 122b 122b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 122c 122c ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 122d 122d fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 122e 122e seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 122f 122f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1237 seq_br_type 1 Branch True seq_branch_adr 1237 0x1237 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 05 GP05 val_alu_func 0 PASS_A 1230 1230 seq_br_type 4 Call False; Flow C cc=False 0x32a0 seq_branch_adr 32a0 0x32a0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1231 1231 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1232 1232 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1233 1233 seq_br_type 7 Unconditional Call; Flow C 0x2226 seq_branch_adr 2226 0x2226 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1234 1234 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1235 0x1235 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1235 1235 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1236 1236 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1237 1237 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1238 1238 val_a_adr 04 GP04 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 1239 1239 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 123a 123a fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 123b 123b seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 123c 123c seq_br_type 7 Unconditional Call; Flow C 0x2226 seq_branch_adr 2226 0x2226 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 123d 123d seq_br_type 7 Unconditional Call; Flow C 0x2246 seq_branch_adr 2246 0x2246 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 123e 123e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 123f 123f <halt> ; Flow R 1240 ; -------------------------------------------------------------------------------------- 1240 ; 0x03ba Declare_Variable Access,By_Allocation,With_Constraint 1240 ; -------------------------------------------------------------------------------------- 1240 MACRO_Declare_Variable_Access,By_Allocation,With_Constraint: 1240 1240 dispatch_brk_class 4 ; Flow C 0x1097 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1240 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1097 0x1097 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1241 1241 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x124f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 124f 0x124f seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1242 1242 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 1243 1243 <halt> ; Flow R 1244 ; -------------------------------------------------------------------------------------- 1244 ; 0x039a Declare_Variable Heap_Access,By_Allocation,With_Constraint 1244 ; -------------------------------------------------------------------------------------- 1244 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint: 1244 1244 dispatch_brk_class 4 ; Flow C 0x109e dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1244 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 109e 0x109e typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1245 1245 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x124f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 124f 0x124f seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1246 1246 seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 1247 1247 <halt> ; Flow R 1248 ; -------------------------------------------------------------------------------------- 1248 ; 0x03b9 Declare_Variable Access,Visible,By_Allocation,With_Constraint 1248 ; -------------------------------------------------------------------------------------- 1248 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint: 1248 1248 dispatch_brk_class 4 ; Flow C 0x1099 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1248 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1099 0x1099 typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 1249 1249 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x124f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 124f 0x124f seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 124a 124a seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 124b 124b <halt> ; Flow R 124c ; -------------------------------------------------------------------------------------- 124c ; 0x0399 Declare_Variable Heap_Access,Visible,By_Allocation,With_Constraint 124c ; -------------------------------------------------------------------------------------- 124c MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint: 124c 124c dispatch_brk_class 4 ; Flow C 0x10a0 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 124c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10a0 0x10a0 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 124d 124d fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x124f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 124f 0x124f seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 124e 124e seq_br_type 7 Unconditional Call; Flow C 0x32aa seq_branch_adr 32aa 0x32aa 124f ; -------------------------------------------------------------------------------------- 124f ; Comes from: 124f ; 1241 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 124f ; 1245 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 124f ; 1249 C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 124f ; 124d C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 124f ; -------------------------------------------------------------------------------------- 124f 124f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1250 1250 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1251 1251 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1252 1252 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1253 1253 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1254 1254 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1255 1255 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1256 1256 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1257 1257 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 1258 1258 seq_br_type 3 Unconditional Branch; Flow J 0x125f seq_branch_adr 125f 0x125f 1259 1259 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125a 125a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125b 125b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 125c 125c fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x1279 ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 1279 0x1279 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 125d 125d fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x128c ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 128c 0x128c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 125e 125e seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_random 05 ? 125f 125f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1260 1260 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 1261 1261 seq_b_timing 0 Early Condition; Flow J cc=True 0x126c seq_br_type 1 Branch True seq_branch_adr 126c 0x126c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1262 1262 ioc_fiubs 1 val ; Flow J 0x1263 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 1266 0x1266 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1263 1263 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2480 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2480 0x2480 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR05:00 typ_c_adr 37 GP08 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 1264 1264 seq_br_type 1 Branch True; Flow J cc=True 0x2480 seq_branch_adr 2480 0x2480 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 1265 1265 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1266 1266 ioc_load_wdr 0 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1267 1267 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 1268 1268 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1269 1269 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2a2c seq_br_type 5 Call True seq_branch_adr 2a2c 0x2a2c seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 126a 126a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 126b 126b fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x126e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 126e 0x126e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 126c 126c fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 126d 126d fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x126e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 126e 0x126e seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 126e 126e fiu_fill_mode_src 0 ; Flow J cc=False 0x1270 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1270 0x1270 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_c_adr 39 GP06 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 126f 126f fiu_fill_mode_src 0 ; Flow J 0x1273 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1273 0x1273 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA 1270 1270 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 1271 1271 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1272 1272 fiu_load_var 1 hold_var; Flow J 0x1273 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1273 0x1273 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1273 1273 ioc_load_wdr 0 ; Flow C 0x1314 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1314 0x1314 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1274 1274 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1275 1275 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1276 1276 ioc_tvbs 2 fiu+val; Flow J 0x1277 seq_br_type 2 Push (branch address) seq_branch_adr 1278 0x1278 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN 1277 1277 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2a2c ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2a2c 0x2a2c seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1278 1278 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1279 1279 fiu_load_tar 1 hold_tar; Flow J cc=False 0x127b fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 127b 0x127b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 127a 127a seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 127b 127b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 127c 127c ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 127d 127d fiu_load_var 1 hold_var; Flow C cc=False 0x1284 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 1284 0x1284 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 127e 127e ioc_tvbs 1 typ+fiu; Flow J cc=False 0x1289 seq_br_type 0 Branch False seq_branch_adr 1289 0x1289 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 127f 127f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1280 1280 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1287 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1287 0x1287 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 1281 1281 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1282 1282 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1283 1283 seq_br_type 3 Unconditional Branch; Flow J 0x1287 seq_branch_adr 1287 0x1287 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1284 ; -------------------------------------------------------------------------------------- 1284 ; Comes from: 1284 ; 127d C False from color 0x10d4 1284 ; -------------------------------------------------------------------------------------- 1284 1284 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1285 0x1285 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1285 1285 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1286 1286 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1287 1287 fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1288 1288 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x10e2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 10e2 0x10e2 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1289 1289 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 128a 128a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 128b 128b seq_br_type 3 Unconditional Branch; Flow J 0x1287 seq_branch_adr 1287 0x1287 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 val_c_mux_sel 2 ALU 128c 128c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 128d 128d fiu_mem_start 4 continue typ_a_adr 2f TR09:0f typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 128e 128e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x12c3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 12c3 0x12c3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 128f 128f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1290 1290 ioc_tvbs 3 fiu+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1291 1291 ioc_fiubs 2 typ ; Flow C cc=True 0x12c5 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 12c5 0x12c5 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1292 1292 seq_br_type 4 Call False; Flow C cc=False 0x12c5 seq_branch_adr 12c5 0x12c5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 1293 1293 fiu_load_var 1 hold_var; Flow J cc=True 0x1297 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1297 0x1297 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1294 1294 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1295 1295 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1296 1296 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1297 1297 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1298 1298 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 1299 1299 fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 129a 129a fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 129b 129b fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 04 GP04 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 129c 129c ioc_fiubs 2 typ ; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 06 GP06 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 129d 129d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_b_adr 03 GP03 129e 129e ioc_tvbs 2 fiu+val; Flow J cc=True 0x12a5 seq_br_type 1 Branch True seq_branch_adr 12a5 0x12a5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 129f 129f fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val 12a0 12a0 fiu_load_var 1 hold_var; Flow C cc=False 0x32aa fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 12a1 12a1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12a2 12a2 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 12a3 12a3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 12a4 12a4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12ad fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12ad 0x12ad typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 12a5 12a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 12a6 12a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 12a7 12a7 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 12a8 12a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 12a9 12a9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x12ad seq_br_type 1 Branch True seq_branch_adr 12ad 0x12ad seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 12aa 12aa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12ab 12ab seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 12ac 12ac seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 12ad 12ad seq_b_timing 0 Early Condition; Flow C cc=False 0x12bd seq_br_type 4 Call False seq_branch_adr 12bd 0x12bd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12ae 12ae fiu_mem_start 2 start-rd; Flow C 0x3594 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3594 0x3594 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 12af 12af fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12be fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12be 0x12be typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 12b0 12b0 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 12b1 12b1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x12be fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12be 0x12be typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12b2 12b2 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12b3 12b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12be fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12be 0x12be typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12b4 12b4 ioc_load_wdr 0 ; Flow J cc=True 0x12b8 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 12b8 0x12b8 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12b5 12b5 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12b6 12b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12be fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12be 0x12be typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA 12b7 12b7 ioc_load_wdr 0 ; Flow J 0x12ba ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12ba 0x12ba 12b8 12b8 seq_br_type 1 Branch True; Flow J cc=True 0x12ba seq_branch_adr 12ba 0x12ba seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 12b9 12b9 seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 12ba 12ba ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12bb 12bb seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 12bc 12bc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 12bd ; -------------------------------------------------------------------------------------- 12bd ; Comes from: 12bd ; 12ad C False from color 0x125d 12bd ; -------------------------------------------------------------------------------------- 12bd 12bd seq_br_type a Unconditional Return; Flow R val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 8 12be ; -------------------------------------------------------------------------------------- 12be ; Comes from: 12be ; 12af C from color 0x125d 12be ; 12b1 C from color 0x125d 12be ; 12b3 C from color 0x125d 12be ; 12b6 C from color 0x125d 12be ; -------------------------------------------------------------------------------------- 12be 12be fiu_fill_mode_src 0 ; Flow J cc=False 0x12c0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12c0 0x12c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 12bf 12bf fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 12c0 12c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 12c1 12c1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12c2 12c2 fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12c3 ; -------------------------------------------------------------------------------------- 12c3 ; Comes from: 12c3 ; 128e C False from color 0x125d 12c3 ; -------------------------------------------------------------------------------------- 12c3 12c3 seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 12c4 12c4 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12c5 ; -------------------------------------------------------------------------------------- 12c5 ; Comes from: 12c5 ; 1291 C True from color 0x125d 12c5 ; 1292 C False from color 0x125d 12c5 ; -------------------------------------------------------------------------------------- 12c5 12c5 seq_b_timing 0 Early Condition; Flow R cc=False ; Flow J cc=True 0x3270 seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12c6 ; -------------------------------------------------------------------------------------- 12c6 ; 0x02fe Declare_Variable Variant_Record,Visible 12c6 ; -------------------------------------------------------------------------------------- 12c6 MACRO_Declare_Variable_Variant_Record,Visible: 12c6 12c6 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 12c6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 12c7 12c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12c8 12c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12cc fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 12cc 0x12cc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12c9 12c9 seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12ca 12ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12cb 12cb val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 12cc 12cc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 12cd 12cd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x12d0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 1 Branch True seq_branch_adr 12d0 0x12d0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12ce 12ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a0 seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 12cf 12cf seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 12d0 12d0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x29b3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 29b3 0x29b3 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 12d1 12d1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 12d2 ; -------------------------------------------------------------------------------------- 12d2 ; 0x02ff Declare_Variable Variant_Record 12d2 ; -------------------------------------------------------------------------------------- 12d2 MACRO_Declare_Variable_Variant_Record: 12d2 12d2 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 12d2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 12d3 12d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12c8 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 12c8 0x12c8 seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12d4 ; -------------------------------------------------------------------------------------- 12d4 ; 0x02fb Declare_Variable Variant_Record,Visible,With_Constraint 12d4 ; -------------------------------------------------------------------------------------- 12d4 MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint: 12d4 12d4 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 12d4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 12d5 12d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12d6 12d6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12da fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 12da 0x12da seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 12d7 12d7 seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 12d8 12d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 12d9 12d9 val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 12da 12da fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12db 12db fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x12de fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12de 0x12de seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 12dc 12dc fiu_load_var 1 hold_var; Flow J cc=False 0x12e3 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 12e3 0x12e3 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12dd 12dd fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x12e8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 12e8 0x12e8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12de 12de ioc_tvbs 2 fiu+val; Flow C cc=True 0x3273 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 12df 12df ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x12e1 seq_br_type 1 Branch True seq_branch_adr 12e1 0x12e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 12e0 12e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3273 seq_br_type 5 Call True seq_branch_adr 3273 0x3273 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 12e1 12e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2480 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2480 0x2480 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_b_adr 03 GP03 12e2 12e2 ioc_tvbs 2 fiu+val; Flow J cc=True 0x12e5 seq_br_type 1 Branch True seq_branch_adr 12e5 0x12e5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 12e3 12e3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a0 seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 12e4 12e4 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 12e5 12e5 seq_br_type 5 Call True; Flow C cc=True 0x2a2c seq_branch_adr 2a2c 0x2a2c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12e6 12e6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 12e7 12e7 fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x12e8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 12e8 0x12e8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12e8 12e8 fiu_fill_mode_src 0 ; Flow J cc=False 0x12ea fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12ea 0x12ea seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 12e9 12e9 fiu_fill_mode_src 0 ; Flow J 0x12ed fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 12ed 0x12ed typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 12ea 12ea fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 12eb 12eb fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12ec 12ec fiu_load_var 1 hold_var; Flow J 0x12ed fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12ed 0x12ed seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12ed 12ed ioc_load_wdr 0 ; Flow C 0x1314 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1314 0x1314 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 12ee 12ee fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x12f1 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 12f1 0x12f1 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 03 GP03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 03 GP03 12ef 12ef fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 12f0 12f0 ioc_tvbs 3 fiu+fiu; Flow C 0x2a2c seq_br_type 7 Unconditional Call seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 12f1 12f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12f6 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 12f6 0x12f6 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_b_adr 03 GP03 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 12f2 12f2 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12f3 12f3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL 12f4 12f4 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 12f5 12f5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 12f6 12f6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 21 VR02:01 val_frame 2 12f7 12f7 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x12ff fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 12ff 0x12ff typ_b_adr 2e TR08:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR06:02 val_frame 6 12f8 12f8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 12f9 12f9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_load_wdr 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 12fa 12fa ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12fb 12fb fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 12fc 12fc fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 12fd 12fd ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 12fe 12fe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 12ff 12ff fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1300 1300 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1301 1301 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1302 1302 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 1303 1303 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1304 1304 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 22 TR02:02 typ_b_adr 04 GP04 typ_frame 2 val_b_adr 04 GP04 1305 1305 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL 1306 1306 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 1307 1307 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 06 GP06 1308 1308 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1309 1309 <halt> ; Flow R 130a ; -------------------------------------------------------------------------------------- 130a ; 0x02fc Declare_Variable Variant_Record,With_Constraint 130a ; -------------------------------------------------------------------------------------- 130a MACRO_Declare_Variable_Variant_Record,With_Constraint: 130a 130a dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 130a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 130b 130b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12d6 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 12d6 0x12d6 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 130c ; -------------------------------------------------------------------------------------- 130c ; 0x02fd Declare_Variable Variant_Record,Duplicate 130c ; -------------------------------------------------------------------------------------- 130c MACRO_Declare_Variable_Variant_Record,Duplicate: 130c 130c dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 130c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 130d 130d fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 130e 130e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1311 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1311 0x1311 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 130f 130f seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1310 1310 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1311 1311 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1312 1312 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1313 1313 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1314 ; -------------------------------------------------------------------------------------- 1314 ; Comes from: 1314 ; 1273 C from color 0x0000 1314 ; 12ed C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 1314 ; -------------------------------------------------------------------------------------- 1314 1314 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 1315 1315 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 1316 0x1316 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1316 1316 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1317 1317 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1318 1318 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x131b fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 131b 0x131b seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1319 1319 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 131a 131a fiu_mem_start 2 start-rd seq_en_micro 0 131b 131b typ_c_adr 37 GP08 val_rand 2 DEC_LOOP_COUNTER 131c 131c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 131d 131d ioc_fiubs 0 fiu typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 36 GP09 val_c_source 0 FIU_BUS 131e 131e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 131f 131f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 08 GP08 1320 1320 fiu_fill_mode_src 0 ; Flow J cc=False 0x1322 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1322 0x1322 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 09 GP09 1321 1321 fiu_fill_mode_src 0 ; Flow J 0x1325 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1325 0x1325 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1322 1322 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1323 1323 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1324 1324 fiu_load_var 1 hold_var; Flow J 0x1325 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1325 0x1325 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1325 1325 ioc_load_wdr 0 ; Flow J cc=False 0x1317 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1317 0x1317 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1326 1326 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 1327 1327 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1328 ; -------------------------------------------------------------------------------------- 1328 ; 0x0337 Declare_Variable Array 1328 ; -------------------------------------------------------------------------------------- 1328 MACRO_Declare_Variable_Array: 1328 1328 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1328 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1329 1329 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1336 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1336 0x1336 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR0a:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 132a 132a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x132c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 132c 0x132c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 132b 132b fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1331 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1331 0x1331 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 1c ? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 132c 132c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x132d seq_br_type 2 Push (branch address) seq_branch_adr 1330 0x1330 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 132d 132d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1337 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1337 0x1337 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 132e 132e ioc_fiubs 2 typ ; Flow J cc=False 0x1331 seq_br_type 0 Branch False seq_branch_adr 1331 0x1331 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 132f 132f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a2c ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a2c 0x2a2c seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP 1330 1330 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1331 1331 ioc_fiubs 2 typ ; Flow J cc=True 0x1333 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1333 0x1333 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1332 1332 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 1333 1333 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1334 1334 seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 1335 1335 fiu_mem_start 2 start-rd; Flow J 0x1331 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1331 0x1331 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1336 1336 ioc_tvbs 2 fiu+val; Flow C 0x32a5 seq_br_type 7 Unconditional Call seq_branch_adr 32a5 0x32a5 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 1337 1337 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1338 1338 val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1339 1339 seq_br_type a Unconditional Return; Flow R val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 133a ; -------------------------------------------------------------------------------------- 133a ; 0x0336 Declare_Variable Array,Visible 133a ; -------------------------------------------------------------------------------------- 133a MACRO_Declare_Variable_Array,Visible: 133a 133a dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 133a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133b 133b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3277 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133c 133c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x132c fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 132c 0x132c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 133d 133d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1331 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1331 0x1331 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 133e ; -------------------------------------------------------------------------------------- 133e ; 0x0335 Declare_Variable Array,Duplicate 133e ; -------------------------------------------------------------------------------------- 133e MACRO_Declare_Variable_Array,Duplicate: 133e 133e dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 133e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133f 133f fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1340 1340 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1345 fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1345 0x1345 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1341 1341 seq_b_timing 1 Latch Condition; Flow C cc=True 0x136c seq_br_type 5 Call True seq_branch_adr 136c 0x136c 1342 1342 ioc_fiubs 2 typ ; Flow J cc=False 0x1331 seq_br_type 0 Branch False seq_branch_adr 1331 0x1331 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1343 1343 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1344 1344 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1345 1345 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x136c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 136c 0x136c typ_c_adr 39 GP06 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1346 1346 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1347 1347 fiu_len_fill_lit 4b zero-fill 0xb fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 1348 1348 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x134b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 134b 0x134b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1349 1349 fiu_fill_mode_src 0 ; Flow C cc=False 0x134e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 134e 0x134e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 134a 134a seq_br_type 3 Unconditional Branch; Flow J 0x1352 seq_branch_adr 1352 0x1352 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 134b 134b fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 134c 134c fiu_fill_mode_src 0 ; Flow C cc=False 0x134e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 134e 0x134e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 134d 134d seq_br_type 3 Unconditional Branch; Flow J 0x1352 seq_branch_adr 1352 0x1352 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 134e ; -------------------------------------------------------------------------------------- 134e ; Comes from: 134e ; 1349 C False from color 0x0000 134e ; 134c C False from color 0x0000 134e ; -------------------------------------------------------------------------------------- 134e 134e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1350 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1350 0x1350 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 134f 134f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1350 1350 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1351 1351 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1352 1352 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1356 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1356 0x1356 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1353 1353 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1354 1354 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1355 1355 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1356 1356 ioc_tvbs 1 typ+fiu; Flow J 0x1357 seq_br_type 2 Push (branch address) seq_branch_adr 135b 0x135b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1357 1357 ioc_fiubs 1 val ; Flow J cc=True 0x1359 seq_br_type 1 Branch True seq_branch_adr 1359 0x1359 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1358 1358 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1359 1359 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x135e seq_br_type 1 Branch True seq_branch_adr 135e 0x135e seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 135a 135a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x135e seq_br_type 1 Branch True seq_branch_adr 135e 0x135e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 135b 135b ioc_fiubs 2 typ ; Flow J cc=False 0x1335 seq_br_type 0 Branch False seq_branch_adr 1335 0x1335 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 135c 135c ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 135d 135d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 135e 135e fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 135f 135f ioc_fiubs 0 fiu typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1360 1360 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1363 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1363 0x1363 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1361 1361 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1362 1362 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1363 1363 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1367 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1367 0x1367 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1364 1364 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1365 1365 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1369 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1369 0x1369 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1366 1366 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x1360 seq_br_type 8 Return True seq_branch_adr 1360 0x1360 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1367 1367 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1368 1368 fiu_fill_mode_src 0 ; Flow J 0x1365 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1365 0x1365 1369 1369 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_b_adr 05 GP05 136a 136a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 136b 136b ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 136c ; -------------------------------------------------------------------------------------- 136c ; Comes from: 136c ; 1341 C True from color 0x0000 136c ; 1345 C True from color 0x0000 136c ; -------------------------------------------------------------------------------------- 136c 136c val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 136d 136d val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 136e 136e seq_br_type a Unconditional Return; Flow R val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 136f 136f <halt> ; Flow R 1370 ; -------------------------------------------------------------------------------------- 1370 ; 0x0334 Declare_Variable Array,With_Constraint 1370 ; -------------------------------------------------------------------------------------- 1370 MACRO_Declare_Variable_Array,With_Constraint: 1370 1370 dispatch_brk_class 4 ; Flow J 0x1371 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1370 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 3fff 0x3fff seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 21 TR0c:01 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1371 1371 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x139d fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 139d 0x139d seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1372 1372 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1373 1373 fiu_tivi_src 1 tar_val; Flow J cc=True 0x1392 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1392 0x1392 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 1374 1374 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3a GP05 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1375 1375 fiu_fill_mode_src 0 ; Flow J cc=True 0x1380 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1380 0x1380 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1376 1376 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1377 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 1378 0x1378 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1377 1377 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1383 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1383 0x1383 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 1378 1378 seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1379 1379 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 137a 137a fiu_fill_mode_src 0 ; Flow J cc=False 0x137d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 137d 0x137d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 137b 137b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 137c 137c ioc_load_wdr 0 ; Flow J 0x138f ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 138f 0x138f 137d 137d fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 137e 137e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 137f 137f fiu_load_var 1 hold_var; Flow J 0x137c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 137c 0x137c seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1380 1380 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1381 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 138f 0x138f typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1381 1381 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3270 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1382 1382 fiu_mem_start 2 start-rd; Flow C cc=False 0x3270 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 1383 1383 fiu_fill_mode_src 0 ; Flow J cc=False 0x138b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 138b 0x138b seq_en_micro 0 typ_a_adr 07 GP07 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1384 1384 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1385 1385 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1386 1386 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1387 0x1387 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1387 1387 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1388 1388 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1389 1389 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 138a 0x138a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 138a 138a seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 138b 138b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 138c 138c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 138d 138d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 138e 138e seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x1387 seq_br_type 8 Return True seq_branch_adr 1387 0x1387 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 138f 138f fiu_tivi_src 4 fiu_var; Flow C cc=True 0x139a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 139a 0x139a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1390 1390 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1391 0x1391 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1391 1391 ioc_fiubs 2 typ ; Flow C 0x329a seq_br_type 7 Unconditional Call seq_branch_adr 329a 0x329a typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1392 1392 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 1393 1393 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1394 1394 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1397 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1397 0x1397 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 1395 1395 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1374 seq_br_type 0 Branch False seq_branch_adr 1374 0x1374 1396 1396 ioc_fiubs 1 val ; Flow J 0x1374 seq_br_type 3 Unconditional Branch seq_branch_adr 1374 0x1374 seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 1397 ; -------------------------------------------------------------------------------------- 1397 ; Comes from: 1397 ; 1394 C True from color MACRO_Declare_Variable_Array,With_Constraint 1397 ; 13b7 C True from color MACRO_Declare_Variable_Array,With_Constraint 1397 ; -------------------------------------------------------------------------------------- 1397 1397 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1398 1398 seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1399 1399 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 139a ; -------------------------------------------------------------------------------------- 139a ; Comes from: 139a ; 138f C True from color MACRO_Declare_Variable_Array,With_Constraint 139a ; -------------------------------------------------------------------------------------- 139a 139a ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 139b 139b seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 139c 139c seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 139d 139d fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 139e 139e fiu_mem_start 4 continue; Flow J cc=True 0x13b5 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13b5 0x13b5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 139f 139f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13a0 13a0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x13e7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13e7 0x13e7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a1 13a1 fiu_fill_mode_src 0 ; Flow J cc=True 0x13a5 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13a5 0x13a5 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13a2 13a2 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a3 13a3 ioc_fiubs 1 val ; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 2b TR08:0b typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13a4 13a4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13a9 0x13a9 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13a5 13a5 typ_c_adr 3b GP04 val_c_adr 3b GP04 13a6 13a6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13a7 13a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3270 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2f TR09:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13a8 13a8 fiu_mem_start 2 start-rd; Flow C cc=False 0x3270 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13a9 13a9 fiu_fill_mode_src 0 ; Flow J cc=False 0x13b0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13b0 0x13b0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 13aa 13aa fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13ab 13ab ioc_load_wdr 0 ; Flow J cc=True 0x13bd ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13bd 0x13bd seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13ac 13ac seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13ad 13ad seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13ae 13ae seq_br_type 1 Branch True; Flow J cc=True 0x13bd seq_branch_adr 13bd 0x13bd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13af 13af seq_br_type 3 Unconditional Branch; Flow J 0x13bd seq_branch_adr 13bd 0x13bd val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 13b0 13b0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 13b1 13b1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 13b2 13b2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13b3 13b3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x13bd seq_br_type 1 Branch True seq_branch_adr 13bd 0x13bd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13b4 13b4 seq_br_type 3 Unconditional Branch; Flow J 0x13ad seq_branch_adr 13ad 0x13ad seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13b5 13b5 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 13b6 13b6 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 13b7 13b7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1397 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1397 0x1397 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 13b8 13b8 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x139f seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 139f 0x139f 13b9 13b9 fiu_mem_start 2 start-rd; Flow J 0x139f ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 139f 0x139f seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 13ba ; -------------------------------------------------------------------------------------- 13ba ; Comes from: 13ba ; 13e4 C True from color MACRO_Declare_Variable_Array,With_Constraint 13ba ; -------------------------------------------------------------------------------------- 13ba 13ba ioc_fiubs 1 val ; Flow R cc=False seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 13bb 0x13bb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13bb 13bb seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 13bc 13bc seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 13bd 13bd fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13be 13be fiu_fill_mode_src 0 ; Flow J cc=False 0x13c0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13c0 0x13c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 13bf 13bf fiu_fill_mode_src 0 ; Flow J 0x13c3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 13c3 0x13c3 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13c0 13c0 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13c1 13c1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 13c2 13c2 fiu_load_var 1 hold_var; Flow J 0x13c3 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13c3 0x13c3 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13c3 13c3 ioc_load_wdr 0 ; Flow J 0x13c4 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13c4 0x13c4 13c4 13c4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1c TOP - 4 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13c5 13c5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13c6 13c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13c7 13c7 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x13cc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13cc 0x13cc seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13c8 13c8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13c9 13c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value val_b_adr 1d TOP - 3 13ca 13ca ioc_fiubs 0 fiu ; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_frame 6 13cb 13cb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13ce fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13ce 0x13ce typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13cc 13cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3270 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13cd 13cd fiu_mem_start 2 start-rd; Flow C cc=False 0x3270 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13ce 13ce fiu_fill_mode_src 0 ; Flow J cc=False 0x13d5 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13d5 0x13d5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 13cf 13cf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13d0 13d0 ioc_load_wdr 0 ; Flow J cc=True 0x13db ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13db 0x13db seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 13d1 13d1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13d2 13d2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13d3 13d3 seq_br_type 1 Branch True; Flow J cc=True 0x13db seq_branch_adr 13db 0x13db seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13d4 13d4 seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 13d5 13d5 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13d6 13d6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 13d7 13d7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13d8 13d8 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13d9 13d9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x13db seq_br_type 1 Branch True seq_branch_adr 13db 0x13db seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 13da 13da seq_br_type 3 Unconditional Branch; Flow J 0x13d2 seq_branch_adr 13d2 0x13d2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13db 13db ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 6 13dc 13dc ioc_fiubs 2 typ ; Flow J cc=True 0x13e4 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 13e4 0x13e4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 0f GP0f typ_csa_cntl 7 FINISH_POP_DOWN 13dd 13dd fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 13de 13de fiu_fill_mode_src 0 ; Flow J cc=False 0x13e1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13e1 0x13e1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 13df 13df fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 13e0 13e0 ioc_load_wdr 0 ; Flow J 0x13e4 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13e4 0x13e4 13e1 13e1 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13e2 13e2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 7 13e3 13e3 fiu_load_var 1 hold_var; Flow J 0x13e0 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13e0 0x13e0 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13e4 13e4 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x13ba ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 13ba 0x13ba seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 13e5 13e5 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 13e6 0x13e6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13e6 13e6 ioc_fiubs 2 typ ; Flow C 0x329a seq_br_type 7 Unconditional Call seq_branch_adr 329a 0x329a typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 13e7 13e7 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 13e8 13e8 fiu_len_fill_lit 4d zero-fill 0xd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 13e9 13e9 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 13ea 13ea fiu_mem_start 2 start-rd; Flow C cc=False 0x329a ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 13eb 13eb ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13ec 13ec ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13ed 13ed seq_br_type 7 Unconditional Call; Flow C 0x140f seq_branch_adr 140f 0x140f typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 13ee 13ee ioc_fiubs 2 typ ; Flow J cc=True 0x1400 seq_br_type 1 Branch True seq_branch_adr 1400 0x1400 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 37 TR05:17 typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 13ef 13ef val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 13f0 13f0 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 13f1 13f1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13f2 13f2 ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13f3 13f3 seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 13f4 13f4 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x13f7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 13f7 0x13f7 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 13f5 13f5 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 13f6 13f6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 13f7 13f7 fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 13f8 13f8 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13f9 13f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x13fb fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 13fb 0x13fb seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 13fa 13fa seq_br_type 3 Unconditional Branch; Flow J 0x13fc seq_branch_adr 13fc 0x13fc val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 13fb 13fb seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 13fc 13fc fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 13fd 13fd fiu_fill_mode_src 0 ; Flow J cc=False 0x1407 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1407 0x1407 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 13fe 13fe fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 13ff 13ff ioc_load_wdr 0 ; Flow J cc=False 0x13f4 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13f4 0x13f4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1400 1400 ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1401 1401 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 1402 1402 fiu_tivi_src 4 fiu_var ioc_tvbs 2 fiu+val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f 1403 1403 seq_b_timing 1 Latch Condition; Flow C cc=True 0x140a seq_br_type 5 Call True seq_branch_adr 140a 0x140a typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1404 1404 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1405 0x1405 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1405 1405 ioc_fiubs 2 typ ; Flow C cc=True 0x32a0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1406 1406 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 1407 1407 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1408 1408 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1409 1409 fiu_load_var 1 hold_var; Flow J 0x13ff fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13ff 0x13ff seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 140a ; -------------------------------------------------------------------------------------- 140a ; Comes from: 140a ; 1403 C True from color MACRO_Declare_Variable_Array,With_Constraint 140a ; -------------------------------------------------------------------------------------- 140a 140a ioc_fiubs 1 val ; Flow J cc=True 0x140d seq_br_type 1 Branch True seq_branch_adr 140d 0x140d seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B 140b 140b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a0 seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 140c 140c seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 140d 140d ioc_fiubs 1 val ; Flow C 0x2a2c seq_br_type 7 Unconditional Call seq_branch_adr 2a2c 0x2a2c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 140e 140e seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 140f ; -------------------------------------------------------------------------------------- 140f ; Comes from: 140f ; 13ed C from color MACRO_Declare_Variable_Array,With_Constraint 140f ; -------------------------------------------------------------------------------------- 140f 140f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1410 1410 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1411 1411 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1412 1412 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 06 GP06 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1413 1413 seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3a GP05 val_frame 6 1414 1414 ioc_load_wdr 0 ; Flow J cc=True 0x1425 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1425 0x1425 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1415 1415 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1416 1416 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_c_adr 3b GP04 1417 1417 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3270 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 1418 1418 fiu_fill_mode_src 0 ; Flow J cc=False 0x1426 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1426 0x1426 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 1419 1419 fiu_fill_mode_src 0 ; Flow J cc=True 0x1429 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1429 0x1429 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 141a 141a ioc_load_wdr 0 ; Flow C cc=True 0x3270 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 141b 141b seq_br_type 0 Branch False; Flow J cc=False 0x1420 seq_branch_adr 1420 0x1420 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 141c 141c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 141d 141d fiu_fill_mode_src 0 ; Flow J cc=False 0x1431 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1431 0x1431 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 141e 141e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 141f 141f ioc_fiubs 2 typ ; Flow J 0x140f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 140f 0x140f typ_a_adr 04 GP04 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1420 1420 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1421 1421 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1422 1422 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1423 1423 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x141d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 141d 0x141d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1424 1424 seq_br_type 3 Unconditional Branch; Flow J 0x141d seq_branch_adr 141d 0x141d val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1425 1425 seq_br_type 3 Unconditional Branch; Flow J 0x1416 seq_branch_adr 1416 0x1416 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 37 TR05:17 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1426 1426 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1427 1427 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1428 1428 fiu_load_var 1 hold_var; Flow J cc=False 0x141a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 141a 0x141a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1429 1429 ioc_load_wdr 0 ; Flow C cc=True 0x3270 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 142a 142a seq_br_type 0 Branch False; Flow J cc=False 0x142c seq_branch_adr 142c 0x142c seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 142b 142b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 142c 142c seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 142d 142d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 142e 142e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 142f 142f seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1430 0x1430 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1430 1430 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1431 1431 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1432 1432 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1433 1433 fiu_load_var 1 hold_var; Flow J 0x141f fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 141f 0x141f seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1434 ; -------------------------------------------------------------------------------------- 1434 ; 0x0333 Declare_Variable Array,Visible,With_Constraint 1434 ; -------------------------------------------------------------------------------------- 1434 MACRO_Declare_Variable_Array,Visible,With_Constraint: 1434 1434 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1434 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 07 Push_stack+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 1435 1435 fiu_mem_start 2 start-rd; Flow J 0x1371 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1371 0x1371 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1436 ; -------------------------------------------------------------------------------------- 1436 ; 0x01ae Execute Matrix,Not_Equal 1436 ; 0x01af Execute Matrix,Equal 1436 ; -------------------------------------------------------------------------------------- 1436 MACRO_Execute_Matrix,Equal: 1436 MACRO_Execute_Matrix,Not_Equal: 1436 1436 dispatch_brk_class 8 ; Flow J cc=True 0x1438 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1436 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1438 0x1438 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1437 1437 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1438 1438 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1449 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1449 0x1449 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1439 1439 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 143a 143a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1441 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1441 0x1441 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 143b 143b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 143c 143c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 143d 143d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x143f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 143f 0x143f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 143e 143e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1445 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1445 0x1445 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 143f 143f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1440 1440 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1445 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1445 0x1445 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1441 1441 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3075 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1442 1442 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 1443 1443 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1444 1444 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1445 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1445 0x1445 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1445 1445 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1446 1446 seq_b_timing 1 Latch Condition; Flow J cc=True 0x144c seq_br_type 1 Branch True seq_branch_adr 144c 0x144c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1447 1447 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1448 1448 seq_br_type 3 Unconditional Branch; Flow J 0x144c seq_branch_adr 144c 0x144c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1449 1449 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 144a 144a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 144b 144b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x144c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 144c 0x144c typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 144c 144c fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x145d ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 145d 0x145d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 144d 144d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 144e 144e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1455 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1455 0x1455 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR07:14 val_frame 7 144f 144f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1450 1450 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 1451 1451 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1453 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1453 0x1453 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1452 1452 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1459 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1459 0x1459 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1453 1453 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1454 1454 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1459 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1459 0x1459 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1455 1455 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x3075 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1456 1456 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1457 1457 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1458 1458 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1459 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1459 0x1459 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1459 1459 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 145a 145a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1460 seq_br_type 1 Branch True seq_branch_adr 1460 0x1460 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 145b 145b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 145c 145c seq_br_type 3 Unconditional Branch; Flow J 0x1460 seq_branch_adr 1460 0x1460 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 145d 145d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 145e 145e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 145f 145f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1460 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1460 0x1460 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1460 1460 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1463 seq_br_type 1 Branch True seq_branch_adr 1463 0x1463 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1461 1461 ioc_fiubs 1 val ; Flow C cc=True 0x26fa seq_br_type 5 Call True seq_branch_adr 26fa 0x26fa seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 1462 1462 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1463 1463 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1462 seq_br_type 0 Branch False seq_branch_adr 1462 0x1462 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 04 GP04 val_alu_func 0 PASS_A 1464 1464 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1462 seq_br_type 0 Branch False seq_branch_adr 1462 0x1462 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 0 PASS_A val_alu_func 0 PASS_A 1465 1465 seq_br_type 3 Unconditional Branch; Flow J 0x1462 seq_branch_adr 1462 0x1462 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1466 ; -------------------------------------------------------------------------------------- 1466 ; 0x01ad Execute Matrix,First 1466 ; -------------------------------------------------------------------------------------- 1466 MACRO_Execute_Matrix,First: 1466 1466 dispatch_brk_class 8 ; Flow J cc=True 0x1470 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1466 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1470 0x1470 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1467 1467 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1475 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1475 0x1475 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 20 TR14:00 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1468 1468 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x146a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 146a 0x146a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1469 1469 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 146a 146a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 146b 146b fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 146c 146c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x146e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 146e 0x146e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 146d 146d fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32a7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 146e 146e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 146f 146f fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32a7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1470 1470 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1472 seq_br_type 1 Branch True seq_branch_adr 1472 0x1472 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1471 1471 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x146c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 146c 0x146c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 1472 1472 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1473 1473 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1c DEC_A 1474 1474 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1475 1475 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1476 1476 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1477 1477 <halt> ; Flow R 1478 ; -------------------------------------------------------------------------------------- 1478 ; 0x01ab Execute Matrix,Length 1478 ; -------------------------------------------------------------------------------------- 1478 MACRO_Execute_Matrix,Length: 1478 1478 dispatch_brk_class 8 ; Flow J cc=True 0x147f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1478 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 147f 0x147f seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1479 1479 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1482 seq_br_type 1 Branch True seq_branch_adr 1482 0x1482 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 147a 147a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 147b 147b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x147d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 147d 0x147d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 147c 147c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 147d 147d fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 147e 147e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 147f 147f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 1480 1480 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1482 seq_br_type 1 Branch True seq_branch_adr 1482 0x1482 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 1481 1481 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x147b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 147b 0x147b typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1482 1482 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1483 1483 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1484 ; -------------------------------------------------------------------------------------- 1484 ; Comes from: 1484 ; 14a0 C from color MACRO_Execute_Matrix,Last 1484 ; 14a2 C from color MACRO_Execute_Matrix,Bounds 1484 ; 14a6 C from color MACRO_Execute_Matrix,Reverse_Bounds 1484 ; -------------------------------------------------------------------------------------- 1484 1484 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1495 seq_br_type 1 Branch True seq_branch_adr 1495 0x1495 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1485 1485 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1497 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1497 0x1497 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1486 1486 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x148a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 148a 0x148a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1487 1487 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 1488 1488 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1489 1489 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x148e seq_br_type 8 Return True seq_branch_adr 148e 0x148e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 148a 148a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 148b 148b fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 148c 148c fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 148d 148d ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 148e 0x148e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 148e 148e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1490 seq_br_type 1 Branch True seq_branch_adr 1490 0x1490 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 148f 148f fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1491 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1491 0x1491 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1490 1490 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 1491 ; -------------------------------------------------------------------------------------- 1491 ; Comes from: 1491 ; 14cc C from color 0x0aa0 1491 ; 14d1 C from color 0x0aa0 1491 ; -------------------------------------------------------------------------------------- 1491 1491 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1493 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1493 0x1493 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1492 1492 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1493 1493 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1494 1494 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1495 1495 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 1496 1496 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1486 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1486 0x1486 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1497 1497 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 1498 1498 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1499 1499 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x149e fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 149e 0x149e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 149a 149a fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 149b 149b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x149d seq_br_type 1 Branch True seq_branch_adr 149d 0x149d seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 149c 149c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 149d 149d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 149e 149e ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 149f 149f <halt> ; Flow R 14a0 ; -------------------------------------------------------------------------------------- 14a0 ; 0x01ac Execute Matrix,Last 14a0 ; -------------------------------------------------------------------------------------- 14a0 MACRO_Execute_Matrix,Last: 14a0 14a0 dispatch_brk_class 8 ; Flow C 0x1484 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a0 seq_br_type 7 Unconditional Call seq_branch_adr 1484 0x1484 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a1 14a1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a2 ; -------------------------------------------------------------------------------------- 14a2 ; 0x01aa Execute Matrix,Bounds 14a2 ; -------------------------------------------------------------------------------------- 14a2 MACRO_Execute_Matrix,Bounds: 14a2 14a2 dispatch_brk_class 8 ; Flow C 0x1484 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a2 seq_br_type 7 Unconditional Call seq_branch_adr 1484 0x1484 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a3 14a3 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a4 14a4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14a5 14a5 <halt> ; Flow R 14a6 ; -------------------------------------------------------------------------------------- 14a6 ; 0x01a9 Execute Matrix,Reverse_Bounds 14a6 ; -------------------------------------------------------------------------------------- 14a6 MACRO_Execute_Matrix,Reverse_Bounds: 14a6 14a6 dispatch_brk_class 8 ; Flow C 0x1484 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14a6 seq_br_type 7 Unconditional Call seq_branch_adr 1484 0x1484 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14a7 14a7 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a8 14a8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14a9 14a9 <halt> ; Flow R 14aa ; -------------------------------------------------------------------------------------- 14aa ; 0x01a8 Execute Matrix,Element_Type 14aa ; -------------------------------------------------------------------------------------- 14aa MACRO_Execute_Matrix,Element_Type: 14aa 14aa dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 14aa fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 14ab 14ab typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 14ac 14ac fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 14ad 14ad <halt> ; Flow R 14ae ; -------------------------------------------------------------------------------------- 14ae ; 0x019d Execute Matrix,In_Type 14ae ; -------------------------------------------------------------------------------------- 14ae MACRO_Execute_Matrix,In_Type: 14ae 14ae dispatch_brk_class 8 ; Flow C cc=False 0x14ef dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14ae dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14ef 0x14ef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14af 14af fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ba fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ba 0x14ba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b0 14b0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14b1 14b1 <halt> ; Flow R 14b2 ; -------------------------------------------------------------------------------------- 14b2 ; 0x019c Execute Matrix,Not_In_Type 14b2 ; -------------------------------------------------------------------------------------- 14b2 MACRO_Execute_Matrix,Not_In_Type: 14b2 14b2 dispatch_brk_class 8 ; Flow C cc=False 0x14ef dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14b2 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14ef 0x14ef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14b3 14b3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ba fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ba 0x14ba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b4 14b4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 14b5 14b5 <halt> ; Flow R 14b6 ; -------------------------------------------------------------------------------------- 14b6 ; 0x019b Execute Matrix,Check_In_Type 14b6 ; -------------------------------------------------------------------------------------- 14b6 MACRO_Execute_Matrix,Check_In_Type: 14b6 14b6 dispatch_brk_class 8 ; Flow C cc=False 0x14ef dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14b6 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14ef 0x14ef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14b7 14b7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ba fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ba 0x14ba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b8 14b8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 14b9 0x14b9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 31 VR02:11 val_frame 2 14b9 14b9 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 14ba ; -------------------------------------------------------------------------------------- 14ba ; Comes from: 14ba ; 14af C from color 0x0a78 14ba ; 14b3 C from color 0x0a8c 14ba ; -------------------------------------------------------------------------------------- 14ba 14ba fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14e1 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14e1 0x14e1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 14bb 14bb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14c9 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14c9 0x14c9 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14bc 14bc <default> 14bd 14bd fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14be 14be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c8 seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14bf 14bf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14c3 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 14c3 0x14c3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14c0 14c0 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c1 14c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c2 14c2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 14c3 14c3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c8 seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 14c4 14c4 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 14c5 0x14c5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14c5 14c5 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14c6 14c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 14c7 14c7 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14c8 0x14c8 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 14c8 14c8 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 14c9 14c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x14d5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14d5 0x14d5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 14ca 14ca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c8 seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14cb 14cb seq_br_type 1 Branch True; Flow J cc=True 0x14cf seq_branch_adr 14cf 0x14cf seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14cc 14cc fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x1491 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1491 0x1491 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 14cd 14cd fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 14ce 14ce ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 14cf 14cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c8 seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 14d0 14d0 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 14d1 0x14d1 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14d1 14d1 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x1491 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1491 0x1491 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 14d2 14d2 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14d3 14d3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14d4 0x14d4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 14d4 14d4 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 14d5 ; -------------------------------------------------------------------------------------- 14d5 ; Comes from: 14d5 ; 14c9 C from color 0x0aa0 14d5 ; 14e6 C from color 0x0aa0 14d5 ; -------------------------------------------------------------------------------------- 14d5 14d5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14db seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14db 0x14db seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14d6 14d6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 14d7 14d7 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 14d8 14d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14de seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14de 0x14de seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14d9 14d9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 14da 14da fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 14db 14db fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14dc 14dc fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 14dd 14dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x14d8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 14d8 0x14d8 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 14de 14de fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14df 14df fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 14e0 14e0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 14e1 14e1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14e6 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14e6 0x14e6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14e2 14e2 <default> 14e3 14e3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14e4 14e4 fiu_load_var 1 hold_var; Flow J cc=True 0x14c8 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 14e5 14e5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x14e8 seq_br_type 3 Unconditional Branch seq_branch_adr 14e8 0x14e8 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14e6 14e6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x14d5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14d5 0x14d5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 14e7 14e7 fiu_load_var 1 hold_var; Flow J cc=True 0x14c8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14c8 0x14c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 14e8 14e8 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 14e9 14e9 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 14ea 14ea seq_br_type 0 Branch False; Flow J cc=False 0x14c8 seq_branch_adr 14c8 0x14c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 14eb 14eb fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 14ec 14ec ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 14ed 14ed seq_br_type 0 Branch False; Flow J cc=False 0x14c8 seq_branch_adr 14c8 0x14c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 14ee 14ee seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x14c8 seq_br_type 9 Return False seq_branch_adr 14c8 0x14c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 14ef ; -------------------------------------------------------------------------------------- 14ef ; Comes from: 14ef ; 14ae C False from color 0x0a78 14ef ; 14b2 C False from color 0x0a8c 14ef ; 14b6 C False from color 0x0aa0 14ef ; 1550 C False from color 0x0000 14ef ; 15c6 C False from color 0x0000 14ef ; -------------------------------------------------------------------------------------- 14ef 14ef fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 14f0 14f0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 14f1 14f1 seq_br_type a Unconditional Return; Flow R 14f2 ; -------------------------------------------------------------------------------------- 14f2 ; 0x01a4 Execute Matrix,Structure_Write 14f2 ; -------------------------------------------------------------------------------------- 14f2 MACRO_Execute_Matrix,Structure_Write: 14f2 14f2 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14f2 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14f3 14f3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0c 0x1e0c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14f4 ; -------------------------------------------------------------------------------------- 14f4 ; 0x01a6 Execute Matrix,Field_Write 14f4 ; -------------------------------------------------------------------------------------- 14f4 MACRO_Execute_Matrix,Field_Write: 14f4 14f4 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14f4 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 14f5 14f5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1503 fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1503 0x1503 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14f6 14f6 ioc_fiubs 1 val ; Flow J cc=False 0x14fd ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 14fd 0x14fd seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 14f7 14f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 14f8 14f8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14f9 14f9 seq_random 02 ? typ_csa_cntl 3 POP_CSA 14fa 14fa fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1500 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1500 0x1500 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 14fb 14fb fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 14fc 14fc seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 14fd 14fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 14fe 14fe seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 14ff 14ff seq_br_type 3 Unconditional Branch; Flow J 0x14f8 seq_branch_adr 14f8 0x14f8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1500 1500 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1501 1501 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1502 1502 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1503 1503 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x152f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 152f 0x152f typ_b_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1504 1504 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1500 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1500 0x1500 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1505 1505 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1506 1506 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1507 1507 <halt> ; Flow R 1508 ; -------------------------------------------------------------------------------------- 1508 ; 0x01a5 Execute Matrix,Field_Reference 1508 ; -------------------------------------------------------------------------------------- 1508 MACRO_Execute_Matrix,Field_Reference: 1508 1508 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1508 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 1509 1509 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1515 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1515 0x1515 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 150a 150a fiu_mem_start 2 start-rd; Flow J cc=False 0x150f ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 150f 0x150f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 150b 150b fiu_mem_start 4 continue; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 150c 150c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 150d 150d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1512 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1512 0x1512 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 150e 150e fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3270 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 150f 150f seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1510 1510 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1511 1511 fiu_mem_start 4 continue; Flow J 0x150c seq_br_type 3 Unconditional Branch seq_branch_adr 150c 0x150c seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1512 1512 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1513 1513 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1514 0x1514 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1514 1514 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1515 1515 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x152f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 152f 0x152f typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1516 1516 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1512 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1512 0x1512 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1517 1517 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3270 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1518 ; -------------------------------------------------------------------------------------- 1518 ; 0x01a7 Execute Matrix,Field_Read 1518 ; -------------------------------------------------------------------------------------- 1518 MACRO_Execute_Matrix,Field_Read: 1518 1518 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1518 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 1519 1519 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x152a fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 152a 0x152a typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 151a 151a fiu_mem_start 2 start-rd; Flow J cc=False 0x1523 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1523 0x1523 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 151b 151b fiu_mem_start 4 continue; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 151c 151c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 151d 151d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x152c fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 152c 0x152c seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 151e 151e fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x3270 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 151f 151f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1521 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1521 0x1521 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 1520 1520 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1526 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1526 0x1526 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1521 1521 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1522 1522 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1526 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1526 0x1526 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1523 1523 seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1524 1524 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1525 1525 fiu_mem_start 4 continue; Flow J 0x151c seq_br_type 3 Unconditional Branch seq_branch_adr 151c 0x151c seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1526 1526 seq_br_type 0 Branch False; Flow J cc=False 0x1529 seq_branch_adr 1529 0x1529 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 1527 1527 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1528 0x1528 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1528 1528 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1529 1529 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 152a 152a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x152f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 152f 0x152f typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 152b 152b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x151e fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 151e 0x151e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 152c 152c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 152d 152d seq_br_type 2 Push (branch address); Flow J 0x152e seq_branch_adr 151f 0x151f seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 152e 152e fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x3270 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 152f ; -------------------------------------------------------------------------------------- 152f ; Comes from: 152f ; 1503 C from color 0x0000 152f ; 1515 C from color 0x0000 152f ; 152a C from color 0x0000 152f ; -------------------------------------------------------------------------------------- 152f 152f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1540 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1540 0x1540 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1530 1530 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1531 1531 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1532 1532 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x153b ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 153b 0x153b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1533 1533 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1534 1534 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3270 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 1535 1535 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x153d fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 153d 0x153d seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1536 1536 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 1537 1537 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1538 1538 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1539 1539 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 153a 153a fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 153b 153b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3270 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 153c 153c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1536 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1536 0x1536 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 153d 153d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 153e 153e fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 153f 153f fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return typ_b_adr 21 TR05:01 typ_frame 5 1540 1540 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1541 1541 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1542 1542 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x154b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 154b 0x154b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1543 1543 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 1544 1544 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3270 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 7 1545 1545 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1546 1546 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1548 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1548 0x1548 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1547 1547 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x154f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 154f 0x154f seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1548 1548 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1549 1549 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 154a 154a fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x154f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 154f 0x154f seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 154b 154b fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 154c 154c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3270 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 154d 154d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1548 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 1548 0x1548 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 154e 154e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 154f 154f fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1550 ; -------------------------------------------------------------------------------------- 1550 ; 0x019f Execute Matrix,Convert 1550 ; -------------------------------------------------------------------------------------- 1550 MACRO_Execute_Matrix,Convert: 1550 1550 dispatch_brk_class 4 ; Flow C cc=False 0x14ef dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1550 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14ef 0x14ef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1551 1551 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1552 1552 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1577 seq_br_type 1 Branch True seq_branch_adr 1577 0x1577 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1553 1553 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1562 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1562 0x1562 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1554 1554 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1555 1555 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1556 1556 ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1557 1557 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1559 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1559 0x1559 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1558 1558 seq_br_type 1 Branch True; Flow J cc=True 0x155b seq_branch_adr 155b 0x155b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1559 1559 ioc_fiubs 2 typ ; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 155a 155a seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 02 GP02 val_alu_func 0 PASS_A 155b 155b fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 155c 155c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 155d 155d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x155f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 155f 0x155f seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 155e 155e ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 155f 155f seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 36 GP09 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1560 1560 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1561 1561 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1562 1562 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1567 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1567 0x1567 typ_a_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1563 1563 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 1564 1564 ioc_fiubs 1 val ; Flow J cc=True 0x1559 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1559 0x1559 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1565 1565 seq_br_type 1 Branch True; Flow J cc=True 0x155b seq_branch_adr 155b 0x155b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1566 1566 seq_br_type 3 Unconditional Branch; Flow J 0x1559 seq_branch_adr 1559 0x1559 1567 ; -------------------------------------------------------------------------------------- 1567 ; Comes from: 1567 ; 1562 C from color 0x0000 1567 ; 157d C from color 0x0000 1567 ; 15d3 C from color 0x0000 1567 ; -------------------------------------------------------------------------------------- 1567 1567 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x156f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 156f 0x156f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1568 1568 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 1569 1569 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 156a 156a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1572 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1572 0x1572 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 156b 156b fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 156c 156c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1574 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1574 0x1574 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 156d 156d fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 156e 156e fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 156f 156f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1570 1570 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 1571 1571 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x156a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 156a 0x156a typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1572 1572 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1573 1573 fiu_fill_mode_src 0 ; Flow J 0x156c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 156c 0x156c val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 1574 1574 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1575 1575 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1576 1576 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1577 1577 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x157d fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 157d 0x157d typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1578 1578 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 1579 1579 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 157a 157a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 157b 157b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1586 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1586 0x1586 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 157c 157c seq_br_type 3 Unconditional Branch; Flow J 0x157f seq_branch_adr 157f 0x157f 157d 157d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1567 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1567 0x1567 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 157e 157e fiu_load_var 1 hold_var; Flow J cc=True 0x1586 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1586 0x1586 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 157f 157f fiu_load_var 1 hold_var; Flow J cc=True 0x1585 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1585 0x1585 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1580 1580 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1581 1581 ioc_tvbs 1 typ+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1582 1582 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1583 1583 fiu_mem_start 2 start-rd; Flow J cc=True 0x15b1 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 15b1 0x15b1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 1584 1584 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1585 1585 fiu_mem_start 2 start-rd; Flow J 0x15b1 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 15b1 0x15b1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1586 1586 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1587 1587 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1588 1588 seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 1589 1589 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 158a 158a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1585 seq_br_type 1 Branch True seq_branch_adr 1585 0x1585 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 06 GP06 158b 158b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 158c 158c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 158d 158d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x15bb seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15bb 0x15bb val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 158e 158e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 158f 158f seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 1590 1590 ioc_fiubs 1 val ; Flow C cc=True 0x3277 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1591 1591 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1592 1592 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1594 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1594 0x1594 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1593 1593 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1594 1594 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 05 GP05 1595 1595 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1596 1596 fiu_fill_mode_src 0 ; Flow J cc=False 0x15a4 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a4 0x15a4 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 1597 1597 fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 1598 1598 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1599 1599 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 159a 159a fiu_fill_mode_src 0 ; Flow J cc=False 0x15a6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a6 0x15a6 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 07 GP07 159b 159b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 159c 159c ioc_load_wdr 0 ; Flow C cc=False 0x32aa ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 159d 159d fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 06 GP06 val_b_adr 06 GP06 159e 159e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 159f 159f fiu_fill_mode_src 0 ; Flow J cc=False 0x15a8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a8 0x15a8 seq_cond_sel 65 CROSS_WORD_FIELD~ 15a0 15a0 fiu_fill_mode_src 0 ; Flow J cc=False 0x15aa fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15aa 0x15aa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15a1 15a1 ioc_load_wdr 0 ; Flow C cc=False 0x329a ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 15a2 15a2 seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 15a3 15a3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15a4 15a4 fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 15a5 15a5 fiu_fill_mode_src 0 ; Flow J 0x1598 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1598 0x1598 typ_mar_cntl 6 INCREMENT_MAR 15a6 15a6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15a7 15a7 fiu_fill_mode_src 0 ; Flow J 0x159c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 159c 0x159c typ_mar_cntl 6 INCREMENT_MAR 15a8 15a8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15a9 15a9 fiu_fill_mode_src 0 ; Flow J cc=True 0x15a1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 15a1 0x15a1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 15aa 15aa ioc_load_wdr 0 ; Flow C cc=False 0x329a ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR08:0c val_frame 8 15ab 15ab fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 03 GP03 val_b_adr 03 GP03 15ac 15ac fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 15ad 15ad fiu_fill_mode_src 0 ; Flow J cc=False 0x15af fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15af 0x15af seq_cond_sel 65 CROSS_WORD_FIELD~ 15ae 15ae fiu_fill_mode_src 0 ; Flow J 0x15a1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15a1 0x15a1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15af 15af fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15b0 15b0 fiu_fill_mode_src 0 ; Flow J 0x15a1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 15a1 0x15a1 typ_mar_cntl 6 INCREMENT_MAR 15b1 15b1 seq_b_timing 1 Latch Condition; Flow J cc=True 0x15b9 seq_br_type 1 Branch True seq_branch_adr 15b9 0x15b9 15b2 15b2 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15b3 15b3 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 15b4 15b4 fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR02:01 val_frame 2 15b5 15b5 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 15b6 15b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 15b7 15b7 ioc_fiubs 2 typ ; Flow J 0x15b8 seq_br_type 2 Push (branch address) seq_branch_adr 1592 0x1592 typ_a_adr 03 GP03 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 15b8 15b8 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 15b9 15b9 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15ba 15ba fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x15c1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 15c1 0x15c1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 15bb 15bb fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15bc 15bc ioc_fiubs 2 typ ; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 05 GP05 typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 15bd 15bd seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 15be 15be fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x15c1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15c1 0x15c1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 15bf 15bf seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 15c0 15c0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 15c1 15c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x15c3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15c3 0x15c3 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15c2 15c2 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 15c3 15c3 ioc_fiubs 1 val ; Flow C cc=False 0x329a seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 15c4 15c4 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 15c5 15c5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 15c6 ; -------------------------------------------------------------------------------------- 15c6 ; 0x019e Execute Matrix,Convert_To_Formal 15c6 ; -------------------------------------------------------------------------------------- 15c6 MACRO_Execute_Matrix,Convert_To_Formal: 15c6 15c6 dispatch_brk_class 4 ; Flow C cc=False 0x14ef dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 15c6 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 14ef 0x14ef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 15c7 15c7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 15c8 15c8 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1577 seq_br_type 1 Branch True seq_branch_adr 1577 0x1577 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15c9 15c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x15d3 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15d3 0x15d3 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 15ca 15ca ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 15cb 15cb fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 15cc 15cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 15cd 15cd fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 15ce 15ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 15cf 15cf fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15d0 15d0 fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x155b ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 155b 0x155b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15d1 15d1 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 15d2 15d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x15e0 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e0 0x15e0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 15d3 15d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1567 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1567 0x1567 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 15d4 15d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 15d5 15d5 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 15d6 15d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 15d7 15d7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15d8 15d8 fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x155b ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 155b 0x155b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15d9 15d9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 15da 15da fiu_mem_start a start_continue_if_false; Flow J cc=False 0x15dd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15dd 0x15dd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 15db 15db fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 15dc 15dc fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x15e0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e0 0x15e0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 15dd 15dd fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15de 15de fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 15df 15df fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x15e0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15e0 0x15e0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 15e0 15e0 <default> 15e1 15e1 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 15e2 15e2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15e3 15e3 seq_br_type 3 Unconditional Branch; Flow J 0x155b seq_branch_adr 155b 0x155b 15e4 ; -------------------------------------------------------------------------------------- 15e4 ; 0x01a3 Execute Matrix,Subarray 15e4 ; -------------------------------------------------------------------------------------- 15e4 MACRO_Execute_Matrix,Subarray: 15e4 15e4 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 15e4 dispatch_uses_tos 1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 15e5 15e5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 15e6 15e6 ioc_fiubs 1 val ; Flow J cc=False 0x15ea ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 15ea 0x15ea seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 15e7 15e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 15e8 15e8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 15e9 15e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR08:0d typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 15ea 15ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 15eb 15eb seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 15ec 15ec seq_br_type 3 Unconditional Branch; Flow J 0x15e8 seq_branch_adr 15e8 0x15e8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 15ed 15ed <halt> ; Flow R 15ee ; -------------------------------------------------------------------------------------- 15ee ; 0x2c00-0x2cff Execute Variant_Record,Field_Read,Fixed,Direct,fieldnum 15ee ; -------------------------------------------------------------------------------------- 15ee MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum: 15ee 15ee dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 15ee dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 15ef 15ef fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x15f4 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 15f4 0x15f4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 15f0 15f0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x15f2 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15f2 0x15f2 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 15f1 15f1 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x15f6 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f6 0x15f6 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f2 15f2 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15f3 15f3 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x15f6 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f6 0x15f6 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f4 15f4 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 15f5 0x15f5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f5 15f5 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 15f6 15f6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 15f7 0x15f7 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15f7 15f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 15f8 ; -------------------------------------------------------------------------------------- 15f8 ; 0x2e00-0x2eff Execute Variant_Record,Field_Read,Variant,Direct,fieldnum 15f8 ; -------------------------------------------------------------------------------------- 15f8 MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum: 15f8 15f8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 15f8 dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_frame 4 15f9 15f9 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1602 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1602 0x1602 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 15fa 15fa fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 3d GP02 val_c_source 0 FIU_BUS 15fb 15fb fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=False 0x1605 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1605 0x1605 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 15fc 15fc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1600 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1600 0x1600 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 15fd 15fd fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 15fe 0x15fe seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 15fe 15fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 15ff 15ff seq_br_type 7 Unconditional Call; Flow C 0x3273 seq_branch_adr 3273 0x3273 seq_en_micro 0 1600 1600 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1601 1601 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x15fe fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 15fe 0x15fe seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1602 1602 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 4 continue fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1603 1603 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1604 1604 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x15fc fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15fc 0x15fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1605 1605 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x160e seq_br_type 0 Branch False seq_branch_adr 160e 0x160e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_c_lit 2 typ_frame 18 1606 1606 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x160a fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 160a 0x160a seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1607 1607 fiu_fill_mode_src 0 ; Flow J cc=True 0x15fe fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 15fe 0x15fe seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1608 1608 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1609 0x1609 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1609 1609 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 160a 160a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 160b 160b fiu_fill_mode_src 0 ; Flow J cc=True 0x15fe fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 15fe 0x15fe seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 160c 160c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 160d 0x160d seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 160d 160d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 160e 160e fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 160f 0x160f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 160f 160f fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1610 1610 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x15fe seq_br_type 1 Branch True seq_branch_adr 15fe 0x15fe seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1611 1611 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1612 0x1612 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1612 1612 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x161a fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 161a 0x161a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1613 1613 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 1614 1614 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1621 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1621 0x1621 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1615 1615 ioc_fiubs 1 val ; Flow C 0x1eec ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 03 GP03 1616 1616 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1617 1617 ioc_tvbs 2 fiu+val; Flow J 0x1618 seq_br_type 2 Push (branch address) seq_branch_adr 1616 0x1616 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1618 1618 ioc_fiubs 1 val ; Flow J cc=False 0x1eec ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1eec 0x1eec seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1619 1619 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 161a 161a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1614 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1614 0x1614 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 161b 161b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 161c 161c fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 161d 161d fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 161e 161e ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1620 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1620 0x1620 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 161f 161f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1620 1620 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1615 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1615 0x1615 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1621 1621 fiu_tivi_src c mar_0xc; Flow J cc=True 0x1617 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1617 0x1617 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1622 1622 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1623 1623 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a seq_en_micro 0 1624 ; -------------------------------------------------------------------------------------- 1624 ; 0x2800-0x28ff Execute Variant_Record,Field_Write,Fixed,Direct,fieldnum 1624 ; -------------------------------------------------------------------------------------- 1624 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum: 1624 1624 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1624 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1625 1625 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1626 ; -------------------------------------------------------------------------------------- 1626 ; 0x2900-0x29ff Execute Variant_Record,Field_Write,Fixed,Indirect,fieldnum 1626 ; -------------------------------------------------------------------------------------- 1626 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum: 1626 1626 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1626 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1627 1627 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1628 1628 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x162a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 162a 0x162a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1629 1629 fiu_fill_mode_src 0 ; Flow J 0x162c fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 162c 0x162c typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 162a 162a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 162b 162b fiu_fill_mode_src 0 ; Flow J 0x162c fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 162c 0x162c typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 162c 162c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d46 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 162d 162d seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 162e ; -------------------------------------------------------------------------------------- 162e ; 0x2a00-0x2aff Execute Variant_Record,Field_Write,Variant,Direct,fieldnum 162e ; -------------------------------------------------------------------------------------- 162e MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum: 162e 162e dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 162e dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 162f 162f fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 1630 1630 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1635 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1635 0x1635 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 1631 1631 fiu_len_fill_lit 47 zero-fill 0x7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1632 1632 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d46 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1633 1633 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1634 1634 seq_br_type 7 Unconditional Call; Flow C 0x3273 seq_branch_adr 3273 0x3273 seq_en_micro 0 1635 1635 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1636 1636 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x1632 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1632 0x1632 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1637 1637 <halt> ; Flow R 1638 ; -------------------------------------------------------------------------------------- 1638 ; 0x2b00-0x2bff Execute Variant_Record,Field_Write,Variant,Indirect,fieldnum 1638 ; -------------------------------------------------------------------------------------- 1638 MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum: 1638 1638 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1638 dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1639 1639 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 163a 163a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x163c ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 163c 0x163c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 163b 163b fiu_fill_mode_src 0 ; Flow J 0x163e fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 163e 0x163e typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 163c 163c fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 163d 163d fiu_fill_mode_src 0 ; Flow J 0x163e fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 163e 0x163e typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 163e 163e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1641 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1641 0x1641 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 163f 163f fiu_fill_mode_src 0 ; Flow J cc=True 0x1644 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1644 0x1644 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1640 1640 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1641 1641 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1642 1642 fiu_fill_mode_src 0 ; Flow J cc=True 0x1644 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1644 0x1644 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1643 1643 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1644 1644 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d46 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1645 1645 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1646 1646 seq_br_type 7 Unconditional Call; Flow C 0x3273 seq_branch_adr 3273 0x3273 seq_en_micro 0 1647 1647 <halt> ; Flow R 1648 ; -------------------------------------------------------------------------------------- 1648 ; 0x2400-0x24ff Execute Variant_Record,Field_Reference,Fixed,Direct,fieldnum 1648 ; -------------------------------------------------------------------------------------- 1648 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum: 1648 1648 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1648 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 1649 1649 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 164a ; -------------------------------------------------------------------------------------- 164a ; 0x2500-0x25ff Execute Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 164a ; -------------------------------------------------------------------------------------- 164a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum: 164a 164a dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 164a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 164b 164b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 164c 164c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x164e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 164e 0x164e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 164d 164d fiu_fill_mode_src 0 ; Flow J 0x1650 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1650 0x1650 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 164e 164e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 164f 164f fiu_fill_mode_src 0 ; Flow J 0x1650 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1650 0x1650 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1650 1650 fiu_load_var 1 hold_var; Flow C cc=True 0x32ac fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_b_adr 10 TOP 1651 1651 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1652 0x1652 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1652 1652 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1653 1653 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1654 1654 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x166c ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 166c 0x166c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1655 1655 <halt> ; Flow R 1656 ; -------------------------------------------------------------------------------------- 1656 ; 0x2600-0x26ff Execute Variant_Record,Field_Reference,Variant,Direct,fieldnum 1656 ; -------------------------------------------------------------------------------------- 1656 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum: 1656 1656 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1656 dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 1657 1657 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1658 1658 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x165a fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 165a 0x165a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1659 1659 fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x160e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 160e 0x160e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 165a 165a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 165b 165b fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x160e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 160e 0x160e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 165c ; -------------------------------------------------------------------------------------- 165c ; 0x2700-0x27ff Execute Variant_Record,Field_Reference,Variant,Indirect,fieldnum 165c ; -------------------------------------------------------------------------------------- 165c MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum: 165c 165c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 165c dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 165d 165d fiu_load_mdr 1 hold_mdr; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 165e 165e fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1660 fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1660 0x1660 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 165f 165f fiu_fill_mode_src 0 ; Flow J 0x1662 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1662 0x1662 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1660 1660 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1661 1661 fiu_fill_mode_src 0 ; Flow J 0x1662 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1662 0x1662 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1662 1662 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1665 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1665 0x1665 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1663 1663 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x1668 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1668 0x1668 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1664 1664 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1665 1665 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1666 1666 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x1668 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1668 0x1668 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1667 1667 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1668 1668 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1669 0x1669 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1669 1669 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 166a 166a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x167b seq_br_type 1 Branch True seq_branch_adr 167b 0x167b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 166b 166b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 166c 0x166c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 166c 166c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 166d 166d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x166f fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 166f 0x166f seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 166e 166e fiu_fill_mode_src 0 ; Flow J 0x1671 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1671 0x1671 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 166f 166f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1670 1670 fiu_fill_mode_src 0 ; Flow J 0x1671 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1671 0x1671 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1671 1671 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 1672 1672 fiu_load_tar 1 hold_tar; Flow J 0x1673 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 167a 0x167a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1673 1673 ioc_tvbs 2 fiu+val; Flow J cc=True 0x1eec seq_br_type 1 Branch True seq_branch_adr 1eec 0x1eec seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 1674 1674 seq_br_type 1 Branch True; Flow J cc=True 0x1677 seq_branch_adr 1677 0x1677 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1675 1675 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1676 1676 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 1677 1677 ioc_tvbs 2 fiu+val; Flow J 0x1678 seq_br_type 2 Push (branch address) seq_branch_adr 167a 0x167a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1678 1678 ioc_fiubs 1 val ; Flow J cc=False 0x1eec ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1eec 0x1eec seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1679 1679 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 167a 167a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 167b 167b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 167c 167c seq_br_type 7 Unconditional Call; Flow C 0x3273 seq_branch_adr 3273 0x3273 seq_en_micro 0 167d ; -------------------------------------------------------------------------------------- 167d ; Comes from: 167d ; 1682 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 167d ; 168e C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 167d ; 1694 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 167d ; -------------------------------------------------------------------------------------- 167d 167d fiu_mem_start 2 start-rd; Flow C cc=True 0x32ac ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 167e 167e fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 167f 167f fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 1680 0x1680 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 1680 1680 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1681 1681 <halt> ; Flow R 1682 ; -------------------------------------------------------------------------------------- 1682 ; 0x0160 Execute Variant_Record,Field_Read_Dynamic 1682 ; -------------------------------------------------------------------------------------- 1682 MACRO_Execute_Variant_Record,Field_Read_Dynamic: 1682 1682 dispatch_brk_class 8 ; Flow C 0x167d dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1682 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167d 0x167d typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 22 VR12:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 1683 1683 seq_b_timing 0 Early Condition; Flow J cc=True 0x1684 ; Flow J cc=#0x0 0x1684 seq_br_type b Case False seq_branch_adr 1684 0x1684 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 1684 1684 seq_br_type 3 Unconditional Branch; Flow J 0x15ee seq_branch_adr 15ee MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 1685 1685 seq_br_type 3 Unconditional Branch; Flow J 0x164a seq_branch_adr 164a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 1686 1686 seq_br_type 3 Unconditional Branch; Flow J 0x15f8 seq_branch_adr 15f8 MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum 1687 1687 seq_br_type 3 Unconditional Branch; Flow J 0x165c seq_branch_adr 165c MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 1688 ; -------------------------------------------------------------------------------------- 1688 ; 0x015f Execute Variant_Record,Field_Write_Dynamic 1688 ; -------------------------------------------------------------------------------------- 1688 MACRO_Execute_Variant_Record,Field_Write_Dynamic: 1688 1688 dispatch_brk_class 2 ; Flow C 0x167d dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1688 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167d 0x167d typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 21 VR12:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 1689 1689 seq_b_timing 0 Early Condition; Flow J cc=True 0x168a ; Flow J cc=#0x0 0x168a seq_br_type b Case False seq_branch_adr 168a 0x168a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 168a 168a seq_br_type 3 Unconditional Branch; Flow J 0x1624 seq_branch_adr 1624 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum 168b 168b seq_br_type 3 Unconditional Branch; Flow J 0x1626 seq_branch_adr 1626 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 168c 168c seq_br_type 3 Unconditional Branch; Flow J 0x162e seq_branch_adr 162e MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum 168d 168d seq_br_type 3 Unconditional Branch; Flow J 0x1638 seq_branch_adr 1638 MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 168e ; -------------------------------------------------------------------------------------- 168e ; 0x015e Execute Variant_Record,Field_Reference_Dynamic 168e ; -------------------------------------------------------------------------------------- 168e MACRO_Execute_Variant_Record,Field_Reference_Dynamic: 168e 168e dispatch_brk_class 8 ; Flow C 0x167d dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 168e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 167d 0x167d typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3c VR05:1c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 168f 168f seq_b_timing 0 Early Condition; Flow J cc=True 0x1690 ; Flow J cc=#0x0 0x1690 seq_br_type b Case False seq_branch_adr 1690 0x1690 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 1690 1690 seq_br_type 3 Unconditional Branch; Flow J 0x1648 seq_branch_adr 1648 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 1691 1691 seq_br_type 3 Unconditional Branch; Flow J 0x164a seq_branch_adr 164a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 1692 1692 seq_br_type 3 Unconditional Branch; Flow J 0x1656 seq_branch_adr 1656 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum 1693 1693 seq_br_type 3 Unconditional Branch; Flow J 0x165c seq_branch_adr 165c MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 1694 ; -------------------------------------------------------------------------------------- 1694 ; 0x015d Execute Variant_Record,Field_Type_Dynamic 1694 ; -------------------------------------------------------------------------------------- 1694 MACRO_Execute_Variant_Record,Field_Type_Dynamic: 1694 1694 dispatch_brk_class 8 ; Flow C 0x167d dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1694 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 167d 0x167d typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 2c VR05:0c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1695 1695 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1696 1696 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1697 0x1697 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1697 1697 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 1698 ; -------------------------------------------------------------------------------------- 1698 ; 0x2d00-0x2dff Execute Variant_Record,Field_Append,Fixed,Indirect,fieldnum 1698 ; 0x2f00-0x2fff Execute Variant_Record,Field_Append,Variant,Indirect,fieldnum 1698 ; -------------------------------------------------------------------------------------- 1698 MACRO_Execute_Variant_Record,Field_Append,Fixed,Indirect,fieldnum: 1698 MACRO_Execute_Variant_Record,Field_Append,Variant,Indirect,fieldnum: 1698 1698 dispatch_brk_class 8 ; Flow C cc=False 0x32a9 dispatch_csa_valid 3 dispatch_uadr 1698 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 1e TOP - 2 typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 1699 1699 fiu_mem_start 2 start-rd; Flow C cc=True 0x32ac ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 169a 169a fiu_vmux_sel 1 fill value; Flow C cc=True 0x32ae ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 169b 169b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x169d seq_br_type 1 Branch True seq_branch_adr 169d 0x169d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 169c 169c fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 169d 169d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x16a2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 16a2 0x16a2 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 169e 169e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 169f 169f seq_b_timing 0 Early Condition; Flow C cc=True 0x32ac seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16a0 16a0 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2456 seq_br_type 7 Unconditional Call seq_branch_adr 2456 0x2456 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16a1 16a1 seq_br_type 3 Unconditional Branch; Flow J 0x16b4 seq_branch_adr 16b4 0x16b4 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16a2 16a2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16a4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 16a4 0x16a4 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 16a3 16a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal 16a4 16a4 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x32ac fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 16a5 16a5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 16a6 16a6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16a9 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16a9 0x16a9 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 16a7 16a7 fiu_fill_mode_src 0 ; Flow J cc=True 0x16ac fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16ac 0x16ac typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16a8 16a8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16ad fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16ad 0x16ad typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16a9 16a9 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16aa 16aa fiu_fill_mode_src 0 ; Flow J cc=True 0x16ac fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16ac 0x16ac typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16ab 16ab fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16ad fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16ad 0x16ad typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16ac 16ac <default> 16ad 16ad fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 09 GP09 val_alu_func 1b A_OR_B val_b_adr 08 GP08 val_rand c START_MULTIPLY 16ae 16ae ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16af 16af ioc_fiubs 1 val ; Flow J cc=True 0x16b2 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16b2 0x16b2 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 16b0 16b0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 16b1 16b1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 16b2 16b2 seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 16b3 16b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x16c6 seq_br_type 5 Call True seq_branch_adr 16c6 0x16c6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16b4 16b4 fiu_mem_start 2 start-rd; Flow C cc=True 0x32ae ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16b5 16b5 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16b6 16b6 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2456 seq_br_type 7 Unconditional Call seq_branch_adr 2456 0x2456 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16b7 16b7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 04 GP04 val_b_adr 03 GP03 16b8 16b8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16b9 16b9 fiu_fill_mode_src 0 ; Flow J cc=False 0x16bf fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16bf 0x16bf seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16ba 16ba fiu_fill_mode_src 0 ; Flow C cc=True 0x32ae fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16bb 16bb fiu_fill_mode_src 0 ; Flow C cc=True 0x32ae fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16bc 16bc ioc_load_wdr 0 ; Flow J 0x16c4 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16c4 0x16c4 seq_random 02 ? 16bd 16bd fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16be 16be fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 16bf 16bf fiu_load_var 1 hold_var; Flow C cc=True 0x32ae fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16c0 16c0 fiu_fill_mode_src 0 ; Flow J cc=False 0x16bd fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 16bd 0x16bd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 16c1 16c1 fiu_fill_mode_src 0 ; Flow C cc=True 0x32ae fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16c2 16c2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR 16c3 16c3 ioc_load_wdr 0 ; Flow J 0x16c4 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 16c4 0x16c4 val_b_adr 07 GP07 16c4 16c4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16c5 16c5 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16c6 ; -------------------------------------------------------------------------------------- 16c6 ; Comes from: 16c6 ; 16b3 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 16c6 ; -------------------------------------------------------------------------------------- 16c6 16c6 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 16c7 16c7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16cb fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16cb 0x16cb typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 16c8 16c8 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x16c5 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 16c5 0x16c5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16c9 16c9 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16ca 16ca fiu_fill_mode_src 0 ; Flow J 0x16c6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16c6 0x16c6 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16cb 16cb seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 16cc 0x16cc seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 16cc 16cc seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16cd 16cd <halt> ; Flow R 16ce ; -------------------------------------------------------------------------------------- 16ce ; 0x2300-0x23ff Execute Variant_Record,Field_Type,fieldnum 16ce ; -------------------------------------------------------------------------------------- 16ce MACRO_Execute_Variant_Record,Field_Type,fieldnum: 16ce 16ce dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16ce dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 16cf 16cf fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16d0 16d0 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 16d1 0x16d1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 16d1 16d1 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae seq_en_micro 0 seq_random 02 ? 16d2 ; -------------------------------------------------------------------------------------- 16d2 ; 0x2200-0x22ff Execute Variant_Record,Field_Constrain,fieldnum 16d2 ; -------------------------------------------------------------------------------------- 16d2 MACRO_Execute_Variant_Record,Field_Constrain,fieldnum: 16d2 16d2 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16d2 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 16d3 16d3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 8 16d4 16d4 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x16d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16d7 0x16d7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 16d5 16d5 fiu_load_tar 1 hold_tar; Flow J cc=True 0x16df fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 16df 0x16df seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16d6 16d6 seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 16d7 16d7 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32ae fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ae 0x32ae seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16d8 16d8 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16da fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16da 0x16da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16d9 16d9 fiu_fill_mode_src 0 ; Flow J 0x16dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16dc 0x16dc typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16da 16da fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16db 16db fiu_fill_mode_src 0 ; Flow J 0x16dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16dc 0x16dc typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16dc 16dc seq_br_type 1 Branch True; Flow J cc=True 0x16df seq_branch_adr 16df 0x16df seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B 16dd 16dd seq_b_timing 0 Early Condition; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 16de 16de seq_br_type 7 Unconditional Call; Flow C 0x32ae seq_branch_adr 32ae 0x32ae 16df 16df fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16e6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16e6 0x16e6 typ_c_adr 36 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 16e0 16e0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16e2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16e2 0x16e2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16e1 16e1 fiu_fill_mode_src 0 ; Flow J 0x16e4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16e4 0x16e4 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16e2 16e2 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16e3 16e3 fiu_fill_mode_src 0 ; Flow J 0x16e4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16e4 0x16e4 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16e4 16e4 seq_br_type 1 Branch True; Flow J cc=True 0x16e6 seq_branch_adr 16e6 0x16e6 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 16e5 16e5 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 16e6 16e6 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16f0 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 16f0 0x16f0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16e7 16e7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x16ec fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 16ec 0x16ec seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16e8 16e8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16ea seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16ea 0x16ea seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16e9 16e9 fiu_fill_mode_src 0 ; Flow J 0x16ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ec 0x16ec val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16ea 16ea fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16eb 16eb fiu_fill_mode_src 0 ; Flow J 0x16ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ec 0x16ec val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16ec 16ec fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x16ef ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16ef 0x16ef seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16ed 16ed seq_br_type 0 Branch False; Flow J cc=False 0x16ef seq_branch_adr 16ef 0x16ef seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c 16ee 16ee fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x29b3 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 29b3 0x29b3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 16ef 16ef fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 16f0 16f0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x16ef fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 16ef 0x16ef seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 16f1 16f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x16ef fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 16ef 0x16ef seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 08 GP08 typ_frame 8 16f2 16f2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 16f3 16f3 ioc_load_wdr 0 ; Flow J 0x16ef ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16ef 0x16ef seq_random 02 ? 16f4 ; -------------------------------------------------------------------------------------- 16f4 ; 0x2100-0x21ff Execute Variant_Record,Set_Bounds,fieldnum 16f4 ; -------------------------------------------------------------------------------------- 16f4 MACRO_Execute_Variant_Record,Set_Bounds,fieldnum: 16f4 16f4 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 16f4 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 16f5 16f5 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16f6 16f6 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16f7 16f7 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 16f8 16f8 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x32a7 fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 16f9 16f9 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1701 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1701 0x1701 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16fa 16fa fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 16fb 16fb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x16fd fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16fd 0x16fd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16fc 16fc fiu_fill_mode_src 0 ; Flow J 0x16ff fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ff 0x16ff typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16fd 16fd fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16fe 16fe fiu_fill_mode_src 0 ; Flow J 0x16ff fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16ff 0x16ff typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16ff 16ff fiu_load_tar 1 hold_tar; Flow J cc=True 0x1702 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1702 0x1702 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1700 1700 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1701 1701 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1702 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1702 0x1702 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1702 1702 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1703 1703 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1704 1704 fiu_mem_start 2 start-rd; Flow J 0x170b ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 170b 0x170b seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1705 1705 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1706 1706 ioc_fiubs 1 val ; Flow J cc=True 0x1709 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1709 0x1709 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1707 1707 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1709 seq_br_type 1 Branch True seq_branch_adr 1709 0x1709 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1708 1708 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1709 1709 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1725 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1725 0x1725 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 170a 170a fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 170b 170b val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 170c 170c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 170d 170d fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 170e 170e fiu_load_var 1 hold_var; Flow C cc=False 0x32aa fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 170f 170f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1710 1710 ioc_fiubs 0 fiu ; Flow J cc=True 0x1716 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1716 0x1716 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 20 TR05:00 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1711 1711 ioc_fiubs 1 val ; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1712 1712 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 1713 1713 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1717 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1717 0x1717 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0f GP0f val_a_adr 03 GP03 val_alu_func 7 INC_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1714 1714 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1715 1715 seq_br_type 3 Unconditional Branch; Flow J 0x1717 seq_branch_adr 1717 0x1717 1716 1716 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1717 1717 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1725 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1725 0x1725 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1718 1718 seq_b_timing 0 Early Condition; Flow J cc=False 0x1705 seq_br_type 0 Branch False seq_branch_adr 1705 0x1705 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1719 1719 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1722 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1722 0x1722 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 171a 171a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 171b 171b fiu_load_var 1 hold_var; Flow C cc=False 0x32aa fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 171c 171c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1725 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1725 0x1725 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 171d 171d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1722 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1722 0x1722 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 171e 171e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x171b seq_br_type 0 Branch False seq_branch_adr 171b 0x171b seq_cond_sel 67 REFRESH_MACRO_EVENT 171f 171f seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1720 1720 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 1721 1721 seq_br_type 3 Unconditional Branch; Flow J 0x171b seq_branch_adr 171b 0x171b 1722 1722 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1723 1723 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1724 1724 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1725 ; -------------------------------------------------------------------------------------- 1725 ; Comes from: 1725 ; 1709 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1725 ; 1717 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1725 ; 171c C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1725 ; -------------------------------------------------------------------------------------- 1725 1725 fiu_fill_mode_src 0 ; Flow J cc=False 0x1728 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1728 0x1728 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1726 1726 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1727 1727 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 1728 1728 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1729 1729 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 172a 172a fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 172b 172b ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 172c ; -------------------------------------------------------------------------------------- 172c ; 0x2000-0x20ff Execute Variant_Record,Set_Variant,fieldnum 172c ; -------------------------------------------------------------------------------------- 172c MACRO_Execute_Variant_Record,Set_Variant,fieldnum: 172c 172c dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 172c dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 172d 172d fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 172e 172e fiu_fill_mode_src 0 ; Flow J cc=False 0x1736 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1736 0x1736 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 172f 172f fiu_fill_mode_src 0 ; Flow C cc=False 0x32a7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 1730 1730 fiu_fill_mode_src 0 ; Flow C cc=False 0x32a7 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1731 1731 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1732 1732 ioc_load_wdr 0 ; Flow J cc=False 0x173d ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 173d 0x173d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1733 1733 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1734 1734 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1735 1735 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1736 1736 fiu_load_var 1 hold_var; Flow C cc=False 0x32a7 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1737 1737 fiu_fill_mode_src 0 ; Flow J cc=False 0x1734 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1734 0x1734 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1738 1738 fiu_fill_mode_src 0 ; Flow C cc=False 0x32a7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3c GP03 1739 1739 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 173a 173a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 173b 173b ioc_load_wdr 0 ; Flow J cc=False 0x173d ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 173d 0x173d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 03 GP03 173c 173c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 173d 173d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 173e 173e ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 173f 173f fiu_vmux_sel 1 fill value; Flow C 0x2a2c ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a2c 0x2a2c val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1740 1740 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1741 1741 <halt> ; Flow R 1742 ; -------------------------------------------------------------------------------------- 1742 ; 0x016e Execute Variant_Record,Not_Equal 1742 ; 0x016f Execute Variant_Record,Equal 1742 ; -------------------------------------------------------------------------------------- 1742 MACRO_Execute_Variant_Record,Equal: 1742 MACRO_Execute_Variant_Record,Not_Equal: 1742 1742 dispatch_brk_class 8 ; Flow J cc=True 0x1744 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1742 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1744 0x1744 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1743 1743 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1744 1744 ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1745 1745 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1747 seq_br_type 1 Branch True seq_branch_adr 1747 0x1747 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1746 1746 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1747 1747 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1748 1748 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 1749 1749 seq_br_type 7 Unconditional Call; Flow C 0x26fa seq_branch_adr 26fa 0x26fa typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 174a 174a fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 174b 174b <halt> ; Flow R 174c ; -------------------------------------------------------------------------------------- 174c ; 0x016d Execute Variant_Record,Structure_Write 174c ; -------------------------------------------------------------------------------------- 174c MACRO_Execute_Variant_Record,Structure_Write: 174c 174c dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 174c dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 174d 174d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db7 0x1db7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 174e ; -------------------------------------------------------------------------------------- 174e ; 0x016c Execute Variant_Record,Is_Constrained 174e ; -------------------------------------------------------------------------------------- 174e MACRO_Execute_Variant_Record,Is_Constrained: 174e 174e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 174e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 174f 174f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1750 ; -------------------------------------------------------------------------------------- 1750 ; 0x015c Execute Variant_Record,Is_Constrained_Object 1750 ; -------------------------------------------------------------------------------------- 1750 MACRO_Execute_Variant_Record,Is_Constrained_Object: 1750 1750 dispatch_brk_class 8 ; Flow C 0x32fc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1750 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 1751 1751 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1752 ; -------------------------------------------------------------------------------------- 1752 ; 0x015b Execute Variant_Record,Make_Constrained 1752 ; -------------------------------------------------------------------------------------- 1752 MACRO_Execute_Variant_Record,Make_Constrained: 1752 1752 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1752 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 1753 1753 <halt> ; Flow R 1754 ; -------------------------------------------------------------------------------------- 1754 ; 0x016b Execute Variant_Record,Read_Variant 1754 ; -------------------------------------------------------------------------------------- 1754 MACRO_Execute_Variant_Record,Read_Variant: 1754 1754 dispatch_brk_class 8 ; Flow J cc=True 0x1757 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1754 dispatch_uses_tos 1 seq_br_type 1 Branch True seq_branch_adr 1757 0x1757 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1755 1755 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1757 seq_br_type 0 Branch False seq_branch_adr 1757 0x1757 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1756 1756 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1757 1757 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x175e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 175e 0x175e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1758 1758 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x175a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 175a 0x175a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1759 1759 fiu_fill_mode_src 0 ; Flow J 0x175c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 175c 0x175c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 175a 175a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 175b 175b fiu_fill_mode_src 0 ; Flow J 0x175c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 175c 0x175c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 175c 175c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 175d 0x175d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 175d 175d seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 seq_random 02 ? 175e 175e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 175f 175f <halt> ; Flow R 1760 ; -------------------------------------------------------------------------------------- 1760 ; 0x016a Execute Variant_Record,Indirects_Appended 1760 ; -------------------------------------------------------------------------------------- 1760 MACRO_Execute_Variant_Record,Indirects_Appended: 1760 1760 dispatch_brk_class 8 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1760 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 1f TOP - 1 typ_frame 1f 1761 1761 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1762 1762 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 21 TR02:01 typ_b_adr 1f TOP - 1 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1763 1763 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1766 fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1766 0x1766 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 1e TR02:01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1764 1764 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 1765 0x1765 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 1765 1765 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 seq_random 02 ? 1766 1766 fiu_load_var 1 hold_var; Flow J cc=True 0x176a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 176a 0x176a typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1767 1767 fiu_mem_start 3 start-wr ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 1768 1768 ioc_fiubs 1 val ; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 1769 1769 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 176a 176a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 176b 176b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 176c 176c fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 176d 176d fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 typ_c_adr 1d TR02:02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 176e 176e ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 01 GP01 176f 176f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1770 ; -------------------------------------------------------------------------------------- 1770 ; 0x0169 Execute Variant_Record,Read_Discriminant_Constraint 1770 ; -------------------------------------------------------------------------------------- 1770 MACRO_Execute_Variant_Record,Read_Discriminant_Constraint: 1770 1770 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1770 dispatch_uses_tos 1 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 2d TR09:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 1771 1771 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1772 1772 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B 1773 1773 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 30 TR05:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1774 1774 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1775 1775 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 1776 1776 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1777 1777 <halt> ; Flow R 1778 ; -------------------------------------------------------------------------------------- 1778 ; 0x0168 Execute Variant_Record,Reference_Makes_Copy 1778 ; -------------------------------------------------------------------------------------- 1778 MACRO_Execute_Variant_Record,Reference_Makes_Copy: 1778 1778 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1778 dispatch_uses_tos 1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1779 1779 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x177e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 21 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 177e 0x177e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 177a 177a ioc_tvbs 2 fiu+val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 177b 177b fiu_fill_mode_src 0 ; Flow J cc=False 0x177d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 177d 0x177d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 177c 177c seq_b_timing 0 Early Condition; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 177d 177d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 177e 177e fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x177d fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 177d 0x177d 177f 177f <halt> ; Flow R 1780 ; -------------------------------------------------------------------------------------- 1780 ; 0x0167 Execute Variant_Record,Structure_Query 1780 ; -------------------------------------------------------------------------------------- 1780 MACRO_Execute_Variant_Record,Structure_Query: 1780 1780 dispatch_brk_class 8 dispatch_csa_free 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1780 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1781 1781 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1783 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1783 0x1783 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1782 1782 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x1785 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1785 0x1785 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1783 1783 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1784 1784 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1785 1785 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1786 1786 fiu_mem_start 6 start_rd_if_false; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1787 1787 ioc_fiubs 1 val ; Flow C cc=True 0x1794 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1794 0x1794 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1e val_rand 2 DEC_LOOP_COUNTER 1788 1788 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 1789 1789 fiu_load_var 1 hold_var; Flow J cc=False 0x1786 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1786 0x1786 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR10:01 typ_frame 10 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 178a 178a fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x1791 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1791 0x1791 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 178b 178b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x178f fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 178f 0x178f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 7 178c 178c fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1792 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1792 0x1792 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 178d 178d fiu_load_var 1 hold_var; Flow C cc=True 0x1794 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1794 0x1794 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 178e 178e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x178c seq_br_type 1 Branch True seq_branch_adr 178c 0x178c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 178f 178f ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 1790 1790 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1791 1791 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 1792 1792 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1793 1793 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1794 ; -------------------------------------------------------------------------------------- 1794 ; Comes from: 1794 ; 1787 C True from color 0x1787 1794 ; 178d C True from color MACRO_Execute_Variant_Record,Structure_Query 1794 ; -------------------------------------------------------------------------------------- 1794 1794 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 1795 1795 fiu_mem_start 2 start-rd; Flow J 0x32fc ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 1796 ; -------------------------------------------------------------------------------------- 1796 ; 0x0166 Execute Variant_Record,Component_Offset 1796 ; -------------------------------------------------------------------------------------- 1796 MACRO_Execute_Variant_Record,Component_Offset: 1796 1796 dispatch_brk_class 8 ; Flow C cc=False 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1796 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 1797 1797 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1798 1798 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1799 1799 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 179a 0x179a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 179a 179a seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 seq_random 02 ? 179b 179b <halt> ; Flow R 179c ; -------------------------------------------------------------------------------------- 179c ; 0x0165 Execute Variant_Record,Convert 179c ; -------------------------------------------------------------------------------------- 179c MACRO_Execute_Variant_Record,Convert: 179c 179c dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 179c dispatch_uses_tos 1 ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 179d 179d ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x17a0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 17a0 0x17a0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 179e 179e fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 24e3 0x24e3 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 179f 179f seq_b_timing 1 Latch Condition; Flow C cc=False 0x3272 seq_br_type 4 Call False seq_branch_adr 3272 0x3272 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 17a0 17a0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x17a3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 17a3 0x17a3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 17a1 17a1 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17a2 17a2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 17a3 17a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR06:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 17a4 17a4 fiu_load_tar 1 hold_tar; Flow C cc=True 0x17a9 fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 17a9 0x17a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 17a5 17a5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2452 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17a6 17a6 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 17a7 17a7 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17a8 17a8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2f TOP val_c_mux_sel 2 ALU 17a9 ; -------------------------------------------------------------------------------------- 17a9 ; Comes from: 17a9 ; 17a4 C True from color 0x0a30 17a9 ; -------------------------------------------------------------------------------------- 17a9 17a9 seq_br_type 1 Branch True; Flow J cc=True 0x17ac seq_branch_adr 17ac 0x17ac seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17aa 17aa ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17ab 17ab seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 17ac 17ac ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17ad 17ad ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 17ae ; -------------------------------------------------------------------------------------- 17ae ; 0x0164 Execute Variant_Record,In_Type 17ae ; -------------------------------------------------------------------------------------- 17ae MACRO_Execute_Variant_Record,In_Type: 17ae 17ae dispatch_brk_class 8 ; Flow J cc=True 0x17b0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17ae seq_br_type 1 Branch True seq_branch_adr 17b0 0x17b0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17af 17af fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17b0 17b0 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e3 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e3 0x24e3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17b1 17b1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 17b2 ; -------------------------------------------------------------------------------------- 17b2 ; 0x0163 Execute Variant_Record,Not_In_Type 17b2 ; -------------------------------------------------------------------------------------- 17b2 MACRO_Execute_Variant_Record,Not_In_Type: 17b2 17b2 dispatch_brk_class 8 ; Flow J cc=True 0x17b4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17b2 seq_br_type 1 Branch True seq_branch_adr 17b4 0x17b4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17b3 17b3 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17b4 17b4 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e3 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e3 0x24e3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17b5 17b5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 17b6 ; -------------------------------------------------------------------------------------- 17b6 ; 0x0162 Execute Variant_Record,Check_In_Type 17b6 ; -------------------------------------------------------------------------------------- 17b6 MACRO_Execute_Variant_Record,Check_In_Type: 17b6 17b6 dispatch_brk_class 8 ; Flow J cc=True 0x17b8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17b6 seq_br_type 1 Branch True seq_branch_adr 17b8 0x17b8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17b7 17b7 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17b8 17b8 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e3 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e3 0x24e3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17b9 17b9 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17ba 0x17ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 17ba 17ba seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 seq_en_micro 0 seq_random 02 ? 17bb 17bb <halt> ; Flow R 17bc ; -------------------------------------------------------------------------------------- 17bc ; 0x0161 Execute Variant_Record,Check_In_Formal_Type 17bc ; -------------------------------------------------------------------------------------- 17bc MACRO_Execute_Variant_Record,Check_In_Formal_Type: 17bc 17bc dispatch_brk_class 8 ; Flow J cc=True 0x17be dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17bc seq_br_type 1 Branch True seq_branch_adr 17be 0x17be seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17bd 17bd fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17be 17be fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x24e3 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 24e3 0x24e3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17bf 17bf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3272 seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 17c0 17c0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 17c1 17c1 <halt> ; Flow R 17c2 ; -------------------------------------------------------------------------------------- 17c2 ; 0x0125 Execute Any,Set_Constraint 17c2 ; -------------------------------------------------------------------------------------- 17c2 MACRO_Execute_Any,Set_Constraint: 17c2 17c2 dispatch_brk_class 8 ; Flow J cc=False 0x17cf dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17c2 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 17cf 0x17cf seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17c3 17c3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x17c6 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17c6 0x17c6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17c4 17c4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x17c8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17c8 0x17c8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 36 GP09 val_c_adr 36 GP09 17c5 17c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x29b3 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 29b3 0x29b3 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 17c6 17c6 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17c7 0x17c7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 17c7 17c7 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 seq_random 02 ? 17c8 17c8 fiu_fill_mode_src 0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 17c9 17c9 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x17cb seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17cb 0x17cb seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 17ca 17ca fiu_fill_mode_src 0 ; Flow J 0x17cd fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17cd 0x17cd val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17cb 17cb fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 17cc 17cc fiu_fill_mode_src 0 ; Flow J 0x17cd fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17cd 0x17cd val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17cd 17cd seq_b_timing 0 Early Condition; Flow C cc=True 0x29b3 seq_br_type 5 Call True seq_branch_adr 29b3 0x29b3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 17ce 17ce fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 17cf 17cf fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17d0 0x17d0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 17d0 17d0 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 17d1 17d1 <halt> ; Flow R 17d2 ; -------------------------------------------------------------------------------------- 17d2 ; 0x3c00-0x3cff Execute Record,Field_Read,fieldnum 17d2 ; -------------------------------------------------------------------------------------- 17d2 MACRO_Execute_Record,Field_Read,fieldnum: 17d2 17d2 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17d2 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17d3 17d3 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x17dc fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17dc 0x17dc seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17d4 17d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x17d6 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17d6 0x17d6 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 17d5 17d5 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x17d8 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17d8 0x17d8 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17d6 17d6 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 17d7 17d7 fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17d8 0x17d8 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17d8 17d8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17d9 0x17d9 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 17d9 17d9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 17da ; -------------------------------------------------------------------------------------- 17da ; 0x017a Execute Record,Field_Read_Dynamic 17da ; -------------------------------------------------------------------------------------- 17da MACRO_Execute_Record,Field_Read_Dynamic: 17da 17da dispatch_brk_class 8 ; Flow C 0x180f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17da fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 180f 0x180f typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17db 17db fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x17d4 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 17d4 0x17d4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17dc 17dc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 17dd 17dd <halt> ; Flow R 17de ; -------------------------------------------------------------------------------------- 17de ; 0x3800-0x38ff Execute Record,Field_Write,fieldnum 17de ; -------------------------------------------------------------------------------------- 17de MACRO_Execute_Record,Field_Write,fieldnum: 17de 17de dispatch_brk_class 2 ; Flow C cc=True 0x32ac dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17de dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17df 17df fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e0 ; -------------------------------------------------------------------------------------- 17e0 ; 0x0179 Execute Record,Field_Write_Dynamic 17e0 ; -------------------------------------------------------------------------------------- 17e0 MACRO_Execute_Record,Field_Write_Dynamic: 17e0 17e0 dispatch_brk_class 2 ; Flow C 0x180f dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 17e0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 180f 0x180f typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17e1 17e1 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e2 ; -------------------------------------------------------------------------------------- 17e2 ; 0x3400-0x34ff Execute Record,Field_Reference,fieldnum 17e2 ; -------------------------------------------------------------------------------------- 17e2 MACRO_Execute_Record,Field_Reference,fieldnum: 17e2 17e2 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17e2 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 17e3 17e3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e4 ; -------------------------------------------------------------------------------------- 17e4 ; 0x0178 Execute Record,Field_Reference_Dynamic 17e4 ; -------------------------------------------------------------------------------------- 17e4 MACRO_Execute_Record,Field_Reference_Dynamic: 17e4 17e4 dispatch_brk_class 8 ; Flow C 0x180f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17e4 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 180f 0x180f seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 17e5 17e5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 17e6 ; -------------------------------------------------------------------------------------- 17e6 ; 0x3000-0x30ff Execute Record,Field_Type,fieldnum 17e6 ; -------------------------------------------------------------------------------------- 17e6 MACRO_Execute_Record,Field_Type,fieldnum: 17e6 17e6 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 17e6 dispatch_uses_tos 1 ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_b_adr 10 TOP 17e7 17e7 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17e8 0x17e8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 17e8 17e8 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 17e9 17e9 <halt> ; Flow R 17ea ; -------------------------------------------------------------------------------------- 17ea ; 0x0177 Execute Record,Field_Type_Dynamic 17ea ; -------------------------------------------------------------------------------------- 17ea MACRO_Execute_Record,Field_Type_Dynamic: 17ea 17ea dispatch_brk_class 8 ; Flow C 0x1814 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17ea fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1814 0x1814 seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 17eb 17eb fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17ec 0x17ec seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 17ec 17ec seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 17ed 17ed <halt> ; Flow R 17ee ; -------------------------------------------------------------------------------------- 17ee ; 0x017e Execute Record,Not_Equal 17ee ; 0x017f Execute Record,Equal 17ee ; -------------------------------------------------------------------------------------- 17ee MACRO_Execute_Record,Equal: 17ee MACRO_Execute_Record,Not_Equal: 17ee 17ee dispatch_brk_class 8 ; Flow C cc=False 0x1815 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17ee fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1815 0x1815 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 17ef 17ef fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32ac fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 17f0 17f0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x26fa fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 26fa 0x26fa typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 17f1 17f1 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 17f2 ; -------------------------------------------------------------------------------------- 17f2 ; 0x017d Execute Record,Structure_Write 17f2 ; -------------------------------------------------------------------------------------- 17f2 MACRO_Execute_Record,Structure_Write: 17f2 17f2 dispatch_brk_class 2 ; Flow C cc=False 0x1815 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17f2 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1815 0x1815 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17f3 17f3 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 17f4 17f4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x17f7 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 17f7 0x17f7 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 17f5 17f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 17f6 17f6 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 17f7 17f7 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 17f8 17f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1eec seq_br_type 4 Call False seq_branch_adr 1eec 0x1eec seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 17f9 17f9 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 17fa 0x17fa seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 17fa 17fa seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 17fb 17fb <halt> ; Flow R 17fc ; -------------------------------------------------------------------------------------- 17fc ; 0x017c Execute Record,Component_Offset 17fc ; -------------------------------------------------------------------------------------- 17fc MACRO_Execute_Record,Component_Offset: 17fc 17fc dispatch_brk_class 8 ; Flow C cc=False 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17fc fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 17fd 17fd fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 17fe 17fe <default> 17ff 17ff fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1800 1800 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1801 0x1801 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1801 1801 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 seq_random 02 ? 1802 ; -------------------------------------------------------------------------------------- 1802 ; 0x017b Execute Record,Convert 1802 ; -------------------------------------------------------------------------------------- 1802 MACRO_Execute_Record,Convert: 1802 1802 dispatch_brk_class 4 ; Flow C cc=False 0x1815 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1802 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 1815 0x1815 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1803 1803 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1804 1804 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1808 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1808 0x1808 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1805 1805 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1806 1806 seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1807 1807 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1808 1808 seq_br_type 1 Branch True; Flow J cc=True 0x180b seq_branch_adr 180b 0x180b seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1809 1809 ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180a 180a seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 180b 180b ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180c 180c ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 180d 180d ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 180e 180e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 180f ; -------------------------------------------------------------------------------------- 180f ; Comes from: 180f ; 17da C from color MACRO_Execute_Record,Field_Read,fieldnum 180f ; 17e0 C from color 0x0000 180f ; 17e4 C from color MACRO_Execute_Record,Field_Reference_Dynamic 180f ; -------------------------------------------------------------------------------------- 180f 180f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ac fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1810 1810 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ac seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1811 1811 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1812 1812 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1813 0x1813 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 10 TOP val_alu_func 19 X_XOR_B 1813 1813 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1814 ; -------------------------------------------------------------------------------------- 1814 ; Comes from: 1814 ; 17ea C from color MACRO_Execute_Record,Field_Type_Dynamic 1814 ; -------------------------------------------------------------------------------------- 1814 1814 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1810 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1810 0x1810 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1815 ; -------------------------------------------------------------------------------------- 1815 ; Comes from: 1815 ; 17ee C False from color 0x09ab 1815 ; 17f2 C False from color MACRO_Execute_Record,Structure_Write 1815 ; 1802 C False from color 0x0a2f 1815 ; -------------------------------------------------------------------------------------- 1815 1815 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand 8 SPARE_0x08 1816 1816 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1817 1817 <halt> ; Flow R 1818 ; -------------------------------------------------------------------------------------- 1818 ; 0x01de Execute Vector,Not_Equal 1818 ; 0x01df Execute Vector,Equal 1818 ; -------------------------------------------------------------------------------------- 1818 MACRO_Execute_Vector,Equal: 1818 MACRO_Execute_Vector,Not_Equal: 1818 1818 dispatch_brk_class 8 ; Flow J cc=True 0x181a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1818 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 181a 0x181a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1819 1819 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 181a 181a fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1825 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1825 0x1825 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 181b 181b fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 181c 181c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 181d 181d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x181f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 181f 0x181f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 181e 181e fiu_fill_mode_src 0 ; Flow J 0x1821 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1821 0x1821 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 181f 181f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1820 1820 fiu_fill_mode_src 0 ; Flow J 0x1821 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1821 0x1821 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1821 1821 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1822 1822 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1826 seq_br_type 1 Branch True seq_branch_adr 1826 0x1826 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1823 1823 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1824 1824 seq_br_type 3 Unconditional Branch; Flow J 0x1826 seq_branch_adr 1826 0x1826 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1825 1825 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1826 1826 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1831 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1831 0x1831 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1827 1827 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1828 1828 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1829 1829 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x182b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 182b 0x182b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 182a 182a fiu_fill_mode_src 0 ; Flow J 0x182d fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 182d 0x182d val_c_adr 39 GP06 val_c_source 0 FIU_BUS 182b 182b fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 182c 182c fiu_fill_mode_src 0 ; Flow J 0x182d fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 182d 0x182d val_c_adr 39 GP06 val_c_source 0 FIU_BUS 182d 182d seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 182e 182e seq_b_timing 1 Latch Condition; Flow J cc=True 0x1832 seq_br_type 1 Branch True seq_branch_adr 1832 0x1832 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 182f 182f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1830 1830 seq_br_type 3 Unconditional Branch; Flow J 0x1832 seq_branch_adr 1832 0x1832 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1831 1831 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1832 1832 ioc_fiubs 1 val ; Flow C cc=True 0x26fa seq_br_type 5 Call True seq_branch_adr 26fa 0x26fa seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1833 1833 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1834 0x1834 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1834 1834 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1835 0x1835 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1835 1835 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1837 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 1837 0x1837 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1836 1836 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1837 1837 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1839 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 1839 0x1839 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE 1838 1838 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1839 1839 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 183a 0x183a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 183a 183a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 183b 183b <halt> ; Flow R 183c ; -------------------------------------------------------------------------------------- 183c ; 0x01c0 Execute Vector,Greater_Equal 183c ; -------------------------------------------------------------------------------------- 183c MACRO_Execute_Vector,Greater_Equal: 183c 183c dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 183c ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 183d 183d fiu_mem_start 2 start-rd; Flow J 0x1840 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1840 MACRO_Execute_Vector,Less_Equal typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 183e ; -------------------------------------------------------------------------------------- 183e ; 0x01c2 Execute Vector,Greater 183e ; -------------------------------------------------------------------------------------- 183e MACRO_Execute_Vector,Greater: 183e 183e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 183e ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 183f 183f fiu_mem_start 2 start-rd; Flow J 0x1846 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1846 MACRO_Execute_Vector,Less typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 1840 ; -------------------------------------------------------------------------------------- 1840 ; 0x01bf Execute Vector,Less_Equal 1840 ; -------------------------------------------------------------------------------------- 1840 MACRO_Execute_Vector,Less_Equal: 1840 1840 dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1840 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1841 1841 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1848 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1848 0x1848 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 1842 1842 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1844 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1844 0x1844 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1843 1843 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1848 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1848 0x1848 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1844 1844 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1845 1845 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1848 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1848 0x1848 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1846 ; -------------------------------------------------------------------------------------- 1846 ; 0x01c1 Execute Vector,Less 1846 ; -------------------------------------------------------------------------------------- 1846 MACRO_Execute_Vector,Less: 1846 1846 dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1846 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 13 ONES typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1847 1847 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1842 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1842 0x1842 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 1848 1848 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1849 1849 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 184a 184a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 184b 184b fiu_fill_mode_src 0 ; Flow J cc=False 0x1850 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1850 0x1850 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 184c 184c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x184e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 184e 0x184e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 184d 184d fiu_fill_mode_src 0 ; Flow J 0x1850 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1850 0x1850 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 184e 184e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 184f 184f fiu_fill_mode_src 0 ; Flow J 0x1850 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1850 0x1850 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1850 1850 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1851 1851 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1852 1852 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1858 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1858 0x1858 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1853 1853 fiu_load_var 1 hold_var; Flow J cc=False 0x185b fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 185b 0x185b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 11 TOP + 1 val_a_adr 05 GP05 val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 1854 1854 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1856 fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1856 0x1856 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1855 1855 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1856 1856 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x185c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 185c 0x185c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 val_m_b_src 2 Bits 32…47 1857 1857 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x185b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 185b 0x185b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 20 VR00:00 1858 1858 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1859 1859 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 185a 185a fiu_fill_mode_src 0 ; Flow J cc=False 0x1860 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1860 0x1860 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 185b 185b fiu_mem_start 2 start-rd; Flow J cc=True 0x1861 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1861 0x1861 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 185c 185c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1862 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1862 0x1862 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 185d 185d fiu_fill_mode_src 0 ; Flow J cc=True 0x1864 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1864 0x1864 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 185e 185e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1859 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1859 0x1859 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 185f 185f fiu_fill_mode_src 0 ; Flow J cc=True 0x185b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 185b 0x185b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1860 1860 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1857 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1857 0x1857 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1861 1861 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1862 1862 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1863 1863 fiu_fill_mode_src 0 ; Flow J cc=False 0x185e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 185e 0x185e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1864 1864 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1865 1865 fiu_mem_start 2 start-rd; Flow J 0x185e seq_br_type 3 Unconditional Branch seq_branch_adr 185e 0x185e 1866 ; -------------------------------------------------------------------------------------- 1866 ; 0x01dd Execute Vector,First 1866 ; -------------------------------------------------------------------------------------- 1866 MACRO_Execute_Vector,First: 1866 1866 dispatch_brk_class 8 ; Flow J cc=True 0x186b dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1866 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 186b 0x186b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1867 1867 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1869 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1869 0x1869 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1868 1868 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1869 1869 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 186a 186a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 186b 186b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1867 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1867 0x1867 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 186c ; -------------------------------------------------------------------------------------- 186c ; 0x01dc Execute Vector,Last 186c ; -------------------------------------------------------------------------------------- 186c MACRO_Execute_Vector,Last: 186c 186c dispatch_brk_class 8 ; Flow J cc=True 0x1875 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 186c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1875 0x1875 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 186d 186d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1870 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1870 0x1870 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 186e 186e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 186f 186f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1873 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1873 0x1873 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1870 1870 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1871 1871 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1872 1872 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1873 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1873 0x1873 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1873 1873 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 1874 0x1874 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1874 1874 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1867 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1867 0x1867 seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 1875 1875 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1876 1876 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1877 1877 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1878 1878 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x187b fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 187b 0x187b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1879 1879 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 187a 0x187a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 187a 187a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1867 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1867 0x1867 seq_en_micro 0 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 187b 187b fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 7 187c ; -------------------------------------------------------------------------------------- 187c ; 0x01db Execute Vector,Length 187c ; -------------------------------------------------------------------------------------- 187c MACRO_Execute_Vector,Length: 187c 187c dispatch_brk_class 8 ; Flow J cc=True 0x1867 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 187c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1867 0x1867 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 187d 187d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1867 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1867 0x1867 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 187e ; -------------------------------------------------------------------------------------- 187e ; 0x01da Execute Vector,Bounds 187e ; -------------------------------------------------------------------------------------- 187e MACRO_Execute_Vector,Bounds: 187e 187e dispatch_brk_class 8 ; Flow J cc=True 0x1885 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 187e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1885 0x1885 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 187f 187f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1882 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1882 0x1882 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1880 1880 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 1881 1881 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1873 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1873 0x1873 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1882 1882 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1883 1883 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 1884 1884 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1873 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1873 0x1873 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1885 1885 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1886 1886 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1887 1887 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1888 1888 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x1878 seq_br_type 3 Unconditional Branch seq_branch_adr 1878 0x1878 seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1889 1889 <halt> ; Flow R 188a ; -------------------------------------------------------------------------------------- 188a ; 0x01d9 Execute Vector,Reverse_Bounds 188a ; -------------------------------------------------------------------------------------- 188a MACRO_Execute_Vector,Reverse_Bounds: 188a 188a dispatch_brk_class 8 ; Flow J cc=True 0x1893 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 188a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1893 0x1893 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 188b 188b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x188e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 188e 0x188e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 188c 188c fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 188d 188d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1891 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1891 0x1891 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 188e 188e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 188f 188f fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 1890 1890 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1891 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1891 0x1891 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1891 1891 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 1892 0x1892 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1892 1892 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x189b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 189b 0x189b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 1893 1893 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1894 1894 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1895 1895 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1896 1896 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1897 1897 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x189a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 189a 0x189a typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1898 1898 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 1899 0x1899 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1899 1899 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x189b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 189b 0x189b typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 189a 189a fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 189b 189b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x189d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 189d 0x189d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 189c 189c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 189d 189d fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 189e 189e fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 189f 189f <halt> ; Flow R 18a0 ; -------------------------------------------------------------------------------------- 18a0 ; 0x01d8 Execute Vector,Element_Type 18a0 ; -------------------------------------------------------------------------------------- 18a0 MACRO_Execute_Vector,Element_Type: 18a0 18a0 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18a0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18a1 18a1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 18a2 18a2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 18a3 18a3 <halt> ; Flow R 18a4 ; -------------------------------------------------------------------------------------- 18a4 ; 0x01d7 Execute Vector,Field_Read 18a4 ; -------------------------------------------------------------------------------------- 18a4 MACRO_Execute_Vector,Field_Read: 18a4 18a4 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18a4 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18a5 18a5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18b3 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18b3 0x18b3 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18a6 18a6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18b0 fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18b0 0x18b0 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18a7 18a7 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18b9 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18b9 0x18b9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18a8 18a8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18aa fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18aa 0x18aa seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 18a9 18a9 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x18ac fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18ac 0x18ac seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18aa 18aa fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18ab 18ab fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18ac 0x18ac seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18ac 18ac seq_br_type 0 Branch False; Flow J cc=False 0x18af seq_branch_adr 18af 0x18af seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 18ad 18ad fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 18ae 0x18ae seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 18ae 18ae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18af 18af fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 18b0 18b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18b1 18b1 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18a8 fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18a8 0x18a8 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18b2 18b2 fiu_load_oreg 1 hold_oreg; Flow J 0x18a8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18a8 0x18a8 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18b3 18b3 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18b4 18b4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18ba fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18ba 0x18ba seq_cond_sel 64 OFFSET_REGISTER_???? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18b5 18b5 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18b6 18b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18bd fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18bd 0x18bd seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18b7 18b7 ioc_fiubs 1 val ; Flow J cc=False 0x18c0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18c0 0x18c0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18b8 18b8 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x18a8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 18a8 0x18a8 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18b9 18b9 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 18ba 18ba fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18bb 18bb fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18bc 18bc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18b7 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18b7 0x18b7 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18bd 18bd ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18be 18be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18bf 18bf fiu_load_oreg 1 hold_oreg; Flow J 0x18a8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18a8 0x18a8 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18c0 18c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18c1 18c1 fiu_load_oreg 1 hold_oreg; Flow J 0x18a8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18a8 0x18a8 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18c2 ; -------------------------------------------------------------------------------------- 18c2 ; 0x018b Execute Subvector,Field_Read 18c2 ; -------------------------------------------------------------------------------------- 18c2 MACRO_Execute_Subvector,Field_Read: 18c2 18c2 dispatch_brk_class 8 ; Flow J 0x18a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18c2 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18a5 0x18a5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18c3 18c3 <halt> ; Flow R 18c4 ; -------------------------------------------------------------------------------------- 18c4 ; 0x01d6 Execute Vector,Field_Write 18c4 ; -------------------------------------------------------------------------------------- 18c4 MACRO_Execute_Vector,Field_Write: 18c4 18c4 dispatch_brk_class 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18c4 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18c5 18c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18cc fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18cc 0x18cc seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18c6 18c6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18c9 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18c9 0x18c9 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18c7 18c7 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18c8 18c8 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 18c9 18c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18ca 18ca fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18cb 18cb fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18cc 18cc fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18cd 18cd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18d3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18d3 0x18d3 seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18ce 18ce fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18cf 18cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18d6 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18d6 0x18d6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18d0 18d0 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x18d9 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18d9 0x18d9 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 01 GP01 val_rand c START_MULTIPLY 18d1 18d1 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18d2 18d2 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 18d3 18d3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18d4 18d4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18d5 18d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18d0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18d0 0x18d0 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18d6 18d6 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18d7 18d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18d8 18d8 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18d9 18d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18da 18da fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18db 18db <halt> ; Flow R 18dc ; -------------------------------------------------------------------------------------- 18dc ; 0x018a Execute Subvector,Field_Write 18dc ; -------------------------------------------------------------------------------------- 18dc MACRO_Execute_Subvector,Field_Write: 18dc 18dc dispatch_brk_class 2 ; Flow J 0x18c5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18dc dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18c5 0x18c5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18dd 18dd <halt> ; Flow R 18de ; -------------------------------------------------------------------------------------- 18de ; 0x01d5 Execute Vector,Field_Reference 18de ; -------------------------------------------------------------------------------------- 18de MACRO_Execute_Vector,Field_Reference: 18de 18de dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18de dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18df 18df fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18e6 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18e6 0x18e6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18e0 18e0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18e3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18e3 0x18e3 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18e1 18e1 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 18e2 0x18e2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18e2 18e2 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 18e3 18e3 ioc_tvbs 2 fiu+val; Flow J cc=False 0x18e2 seq_br_type 0 Branch False seq_branch_adr 18e2 0x18e2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18e4 18e4 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 18e5 0x18e5 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18e5 18e5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18e6 18e6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18e7 18e7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18ee seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18ee 0x18ee seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18e8 18e8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18e9 18e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18f1 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18f1 0x18f1 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18ea 18ea fiu_load_tar 1 hold_tar; Flow J cc=False 0x18ec fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18ec 0x18ec typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18eb 18eb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x18e2 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 18e2 0x18e2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18ec 18ec seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18ed 18ed fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18ee 18ee fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18ef 18ef fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18f0 18f0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18ea fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18ea 0x18ea seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18f1 18f1 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18f2 18f2 seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18f3 18f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18f4 ; -------------------------------------------------------------------------------------- 18f4 ; 0x0189 Execute Subvector,Field_Reference 18f4 ; -------------------------------------------------------------------------------------- 18f4 MACRO_Execute_Subvector,Field_Reference: 18f4 18f4 dispatch_brk_class 8 ; Flow J 0x18df dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f4 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_br_type 3 Unconditional Branch seq_branch_adr 18df 0x18df seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18f5 18f5 <halt> ; Flow R 18f6 ; -------------------------------------------------------------------------------------- 18f6 ; 0x01d4 Execute Vector,Structure_Write 18f6 ; -------------------------------------------------------------------------------------- 18f6 MACRO_Execute_Vector,Structure_Write: 18f6 18f6 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f6 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18f7 18f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de8 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de8 0x1de8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 18f8 ; -------------------------------------------------------------------------------------- 18f8 ; 0x01d1 Execute Vector,Xor 18f8 ; 0x01d2 Execute Vector,Or 18f8 ; 0x01d3 Execute Vector,And 18f8 ; -------------------------------------------------------------------------------------- 18f8 MACRO_Execute_Vector,And: 18f8 MACRO_Execute_Vector,Or: 18f8 MACRO_Execute_Vector,Xor: 18f8 18f8 dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18f9 18f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x18fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18fe 0x18fe seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 18fa 18fa fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18fc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18fc 0x18fc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 18fb 18fb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18ff fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18ff 0x18ff seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18fc 18fc fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18fd 18fd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18ff fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18ff 0x18ff seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18fe 18fe fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18ff 18ff fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_frame 2 1900 1900 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1901 1901 fiu_fill_mode_src 0 ; Flow J cc=True 0x1903 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1903 0x1903 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1902 1902 ioc_fiubs 2 typ ; Flow J 0x190d seq_br_type 3 Unconditional Branch seq_branch_adr 190d 0x190d val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1903 1903 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1905 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1905 0x1905 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 1904 1904 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1907 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1907 0x1907 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1905 1905 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1906 1906 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1907 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1907 0x1907 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1907 1907 fiu_fill_mode_src 0 ; Flow J cc=False 0x1909 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1909 0x1909 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1908 1908 fiu_fill_mode_src 0 ; Flow J 0x190b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 190b 0x190b typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 1909 1909 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 190a 190a fiu_fill_mode_src 0 ; Flow J 0x190b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 190b 0x190b typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 190b 190b ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 190c 190c ioc_fiubs 2 typ ; Flow J 0x190d seq_br_type 3 Unconditional Branch seq_branch_adr 190d 0x190d typ_a_adr 03 GP03 val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 190d 190d fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3271 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 190e 190e fiu_len_fill_lit 7d zero-fill 0x3d; Flow J cc=True 0x1911 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1911 0x1911 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 190f 190f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x191b seq_br_type f Unconditional Case Call seq_branch_adr 191b 0x191b seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1910 1910 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1911 1911 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1916 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1916 0x1916 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1912 1912 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1917 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1917 0x1917 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 1913 1913 fiu_fill_mode_src 0 ; Flow J 0x1914 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1914 0x1914 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1914 1914 fiu_fill_mode_src 0 ; Flow J cc=False 0x1919 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1919 0x1919 seq_cond_sel 65 CROSS_WORD_FIELD~ 1915 1915 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1916 1916 ioc_load_wdr 0 ; Flow J 0x1910 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1910 0x1910 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 1917 1917 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1918 1918 fiu_fill_mode_src 0 ; Flow J 0x1914 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1914 0x1914 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1919 1919 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 191a 191a fiu_fill_mode_src 0 ; Flow J 0x1916 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1916 0x1916 typ_mar_cntl 6 INCREMENT_MAR 191b ; -------------------------------------------------------------------------------------- 191b ; Comes from: 191b ; 190f C #0x0 from color MACRO_Execute_Vector,And 191b ; -------------------------------------------------------------------------------------- 191b 191b seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191c 191c seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191d 191d seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191e 191e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 191f 191f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192b 0x192b typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1920 1920 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 192f 0x192f typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1921 1921 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x191f ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 191f 0x191f 1922 1922 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1923 1923 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192b 0x192b typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1924 1924 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 192f 0x192f typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1925 1925 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1923 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1923 0x1923 1926 1926 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1927 1927 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 192b 0x192b typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1928 1928 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x192f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 192f 0x192f typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1929 1929 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1927 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1927 0x1927 192a 192a seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 192b ; -------------------------------------------------------------------------------------- 192b ; Comes from: 192b ; 191f C from color 0x191b 192b ; 1923 C from color 0x1922 192b ; 1927 C from color 0x1926 192b ; -------------------------------------------------------------------------------------- 192b 192b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1931 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1931 0x1931 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 192c 192c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 192d 192d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1933 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1933 0x1933 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 192e 192e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 192f ; -------------------------------------------------------------------------------------- 192f ; Comes from: 192f ; 1920 C from color 0x191b 192f ; 1924 C from color 0x1922 192f ; 1928 C from color 0x1926 192f ; -------------------------------------------------------------------------------------- 192f 192f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1935 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1935 0x1935 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1930 1930 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 1931 1931 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1932 1932 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x192d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 192d 0x192d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1933 1933 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1934 1934 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1935 1935 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1936 1936 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1937 1937 <halt> ; Flow R 1938 ; -------------------------------------------------------------------------------------- 1938 ; 0x01d0 Execute Vector,Complement 1938 ; -------------------------------------------------------------------------------------- 1938 MACRO_Execute_Vector,Complement: 1938 1938 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1938 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1939 1939 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3e GP01 val_c_source 0 FIU_BUS 193a 193a fiu_fill_mode_src 0 ; Flow J cc=True 0x193c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 193c 0x193c seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 193b 193b ioc_fiubs 2 typ ; Flow J 0x1946 seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 193c 193c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x193e ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 193e 0x193e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 193d 193d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1940 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1940 0x1940 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 193e 193e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 193f 193f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1940 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1940 0x1940 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1940 1940 fiu_fill_mode_src 0 ; Flow J cc=False 0x1942 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1942 0x1942 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1941 1941 fiu_fill_mode_src 0 ; Flow J 0x1944 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1944 0x1944 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 1942 1942 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1943 1943 fiu_fill_mode_src 0 ; Flow J 0x1944 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1944 0x1944 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1944 1944 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1945 1945 ioc_fiubs 2 typ ; Flow J 0x1946 seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1946 1946 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1957 seq_br_type 1 Branch True seq_branch_adr 1957 0x1957 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1947 1947 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1948 1948 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1949 1949 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x194c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 194c 0x194c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B 194a 194a seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 194b 194b fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B 194c 194c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1953 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1953 0x1953 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 194d 194d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 194e 194e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 194f 194f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1955 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1955 0x1955 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1950 1950 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1951 1951 ioc_load_wdr 0 ; Flow J cc=False 0x1949 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1949 0x1949 1952 1952 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1953 1953 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1954 1954 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x194e fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 194e 0x194e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1955 1955 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1956 1956 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1951 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1951 0x1951 typ_mar_cntl 6 INCREMENT_MAR 1957 1957 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x195c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 195c 0x195c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1958 1958 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x195d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 195d 0x195d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 1959 1959 fiu_fill_mode_src 0 ; Flow J 0x195a fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 195a 0x195a typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 195a 195a fiu_fill_mode_src 0 ; Flow J cc=False 0x195f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 195f 0x195f seq_cond_sel 65 CROSS_WORD_FIELD~ 195b 195b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 195c 195c ioc_load_wdr 0 ; Flow J 0x1952 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1952 0x1952 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 195d 195d fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 195e 195e fiu_fill_mode_src 0 ; Flow J 0x195a fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 195a 0x195a typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 195f 195f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1960 1960 fiu_fill_mode_src 0 ; Flow J 0x195c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 195c 0x195c typ_mar_cntl 6 INCREMENT_MAR 1961 1961 <halt> ; Flow R 1962 ; -------------------------------------------------------------------------------------- 1962 ; 0x01cf Execute Vector,Slice_Read 1962 ; -------------------------------------------------------------------------------------- 1962 MACRO_Execute_Vector,Slice_Read: 1962 1962 dispatch_brk_class 8 ; Flow C cc=True 0x32ac dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1962 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP 1963 1963 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1964 1964 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1984 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1984 0x1984 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1965 1965 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1968 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1968 0x1968 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1966 1966 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1967 1967 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1968 1968 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 1969 1969 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x197b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 197b 0x197b seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 196a 196a ioc_fiubs 0 fiu ; Flow C cc=False 0x329a ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 196b 196b ioc_fiubs 1 val ; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 196c 196c ioc_tvbs 2 fiu+val; Flow C cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 196d 196d fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 196e 196e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 196f 196f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1978 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1978 0x1978 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1970 1970 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32aa ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 1971 1971 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1972 1972 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1973 1973 fiu_mem_start 2 start-rd; Flow J cc=False 0x1977 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1977 0x1977 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1974 1974 ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1975 1975 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1976 1976 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1977 1977 ioc_fiubs 2 typ ; Flow C 0x329a seq_br_type 7 Unconditional Call seq_branch_adr 329a 0x329a seq_en_micro 0 typ_a_adr 05 GP05 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1978 1978 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32aa ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 1979 1979 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 197a 197a fiu_fill_mode_src 0 ; Flow J 0x1972 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1972 0x1972 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 197b 197b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 197c 197c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1980 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1980 0x1980 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 197d 197d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 197e 197e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 197f 197f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x196b fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 196b 0x196b typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1980 1980 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1981 1981 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 1982 1982 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 1983 1983 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x196b fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 196b 0x196b typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1984 1984 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32aa fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 30 TR05:10 typ_frame 5 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 1985 1985 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1986 1986 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1987 1987 fiu_fill_mode_src 0 ; Flow J cc=False 0x198e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 198e 0x198e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 1988 1988 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1989 1989 fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 198a 198a fiu_fill_mode_src 0 ; Flow J cc=True 0x1991 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1991 0x1991 seq_cond_sel 64 OFFSET_REGISTER_???? 198b 198b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 198c 198c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 198d 198d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 198e 198e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 198f 198f fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1990 1990 fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1991 1991 fiu_fill_mode_src 0 ; Flow J 0x198c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 198c 0x198c seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1992 ; -------------------------------------------------------------------------------------- 1992 ; 0x01ce Execute Vector,Slice_Write 1992 ; -------------------------------------------------------------------------------------- 1992 MACRO_Execute_Vector,Slice_Write: 1992 1992 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1992 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 1993 1993 fiu_load_tar 1 hold_tar; Flow C cc=False 0x19ba fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19ba 0x19ba seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1994 1994 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19b5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19b5 0x19b5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1995 1995 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1998 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1998 0x1998 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1996 1996 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1997 1997 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1998 1998 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19a3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19a3 0x19a3 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1999 1999 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 199a 199a ioc_fiubs 1 val ; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 199b 199b ioc_tvbs 2 fiu+val; Flow C cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 199c 199c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 199d 199d fiu_mem_start a start_continue_if_false seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 1d TOP - 3 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 199e 199e ioc_load_wdr 0 ; Flow J cc=True 0x19ac ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ac 0x19ac seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_latch 1 typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 199f 199f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x19b7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b7 0x19b7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19a0 19a0 ioc_fiubs 1 val ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19a1 19a1 ioc_fiubs 1 val ; Flow C cc=True 0x1eec seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 19a2 19a2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 19a3 19a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 19a4 19a4 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19a8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19a8 0x19a8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 19a5 19a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 19a6 19a6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19a7 19a7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199a fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199a 0x199a typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19a8 19a8 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19a9 19a9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 19aa 19aa fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19ab 19ab fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199a fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199a 0x199a typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19ac 19ac fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 19ad 19ad fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19b1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19b1 0x19b1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19ae 19ae fiu_fill_mode_src 0 ; Flow C cc=False 0x19b7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b7 0x19b7 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19af 19af ioc_fiubs 1 val ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19b0 19b0 seq_br_type 3 Unconditional Branch; Flow J 0x19a1 seq_branch_adr 19a1 0x19a1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19b1 19b1 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19b2 19b2 fiu_fill_mode_src 0 ; Flow C cc=False 0x19b7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19b7 0x19b7 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19b3 19b3 ioc_fiubs 1 val ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19b4 19b4 seq_br_type 3 Unconditional Branch; Flow J 0x19a1 seq_branch_adr 19a1 0x19a1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19b5 19b5 ioc_fiubs 1 val ; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 19b6 19b6 seq_br_type 3 Unconditional Branch; Flow J 0x199c seq_branch_adr 199c 0x199c val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 19b7 ; -------------------------------------------------------------------------------------- 19b7 ; Comes from: 19b7 ; 199f C False from color MACRO_Execute_Vector,Slice_Write 19b7 ; 19ae C False from color MACRO_Execute_Vector,Slice_Write 19b7 ; 19b2 C False from color MACRO_Execute_Vector,Slice_Write 19b7 ; -------------------------------------------------------------------------------------- 19b7 19b7 ioc_fiubs 1 val ; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 19b8 19b8 ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 19b9 0x19b9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 19b9 19b9 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 19ba ; -------------------------------------------------------------------------------------- 19ba ; Comes from: 19ba ; 1993 C False from color MACRO_Execute_Vector,Slice_Write 19ba ; -------------------------------------------------------------------------------------- 19ba 19ba fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19bb 19bb fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19bc 19bc seq_br_type a Unconditional Return; Flow R 19bd 19bd <halt> ; Flow R 19be ; -------------------------------------------------------------------------------------- 19be ; 0x01cd Execute Vector,Slice_Reference 19be ; -------------------------------------------------------------------------------------- 19be MACRO_Execute_Vector,Slice_Reference: 19be 19be dispatch_brk_class 2 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19be dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19bf 19bf fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x19c8 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 19c8 0x19c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19c0 19c0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 26 TR06:06 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 10 TOP 19c1 19c1 fiu_mem_start 4 continue ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 19c2 19c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19c7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 19c7 0x19c7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19c3 19c3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3271 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19c4 19c4 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 19c5 19c5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3271 seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 19c6 19c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19c7 19c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19c8 ; -------------------------------------------------------------------------------------- 19c8 ; Comes from: 19c8 ; 19bf C True from color MACRO_Execute_Vector,Slice_Reference 19c8 ; -------------------------------------------------------------------------------------- 19c8 19c8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19cb seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19cb 0x19cb seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 19c9 19c9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19ca 19ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 19cb 19cb fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19cc 19cc fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19cd 19cd fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 19ce ; -------------------------------------------------------------------------------------- 19ce ; 0x01cc Execute Vector,Catenate 19ce ; -------------------------------------------------------------------------------------- 19ce MACRO_Execute_Vector,Catenate: 19ce 19ce dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19ce dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19cf 19cf fiu_fill_mode_src 0 ; Flow J cc=False 0x19d6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 19d6 0x19d6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19d0 19d0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19d3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19d3 0x19d3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 19d1 19d1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 19d2 19d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19d7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19d7 0x19d7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d3 19d3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19d4 19d4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 19d5 19d5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19d7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19d7 0x19d7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d6 19d6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d7 19d7 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 19d8 19d8 fiu_mem_start a start_continue_if_false; Flow C cc=True 0x3277 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 19d9 19d9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19da 19da fiu_fill_mode_src 0 ; Flow J cc=False 0x19e1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 19e1 0x19e1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_source 0 FIU_BUS 19db 19db fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19de seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19de 0x19de seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19dc 19dc fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 19dd 19dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19e1 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19e1 0x19e1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19de 19de fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19df 19df fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 19e0 19e0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19e1 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19e1 0x19e1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19e1 19e1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19e2 19e2 fiu_load_var 1 hold_var; Flow J cc=True 0x19e4 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19e4 0x19e4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 19e3 19e3 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa 19e4 19e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_b_adr 05 GP05 val_rand c START_MULTIPLY 19e5 19e5 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 19e6 19e6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 19e7 19e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19f6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19f6 0x19f6 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 19e8 19e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3270 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 19e9 19e9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 19ea 19ea seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19eb 19eb ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 19ec 19ec fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19ed 19ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 19ee 19ee fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x19f0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19f0 0x19f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 19ef 19ef fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x19f2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 19f2 0x19f2 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 19f0 19f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 19f1 19f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x19f2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 19f2 0x19f2 typ_mar_cntl 6 INCREMENT_MAR 19f2 19f2 ioc_load_wdr 0 ; Flow C 0x1eec ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 seq_random 02 ? 19f3 19f3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19f4 19f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1eec fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19f5 19f5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 19f6 19f6 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19f7 19f7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 19f8 19f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19ed fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ed 0x19ed seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19f9 19f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x19fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 19fc 0x19fc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 19fa 19fa fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 19fb 19fb fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19fd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19fd 0x19fd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 19fc 19fc fiu_fill_mode_src 0 ; Flow J 0x1a00 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a00 0x1a00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 19fd 19fd fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19fe 19fe fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 19ff 19ff fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a00 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1a00 0x1a00 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 1a00 1a00 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a07 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a07 0x1a07 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 1a01 1a01 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a02 1a02 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a03 1a03 fiu_fill_mode_src 0 ; Flow J cc=True 0x1a0a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1a0a 0x1a0a seq_cond_sel 64 OFFSET_REGISTER_???? 1a04 1a04 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 1a05 1a05 ioc_fiubs 2 typ ; Flow C cc=True 0x32aa ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a06 1a06 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a07 1a07 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a08 1a08 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a09 1a09 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a0a 1a0a fiu_fill_mode_src 0 ; Flow J 0x1a05 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 1a05 0x1a05 typ_mar_cntl 6 INCREMENT_MAR 1a0b 1a0b <halt> ; Flow R 1a0c ; -------------------------------------------------------------------------------------- 1a0c ; 0x01cb Execute Vector,Append 1a0c ; -------------------------------------------------------------------------------------- 1a0c MACRO_Execute_Vector,Append: 1a0c 1a0c dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a0c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a0d 1a0d fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a0e 1a0e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a0f 1a0f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a10 1a10 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a11 1a11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a20 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a20 0x1a20 typ_c_adr 3c GP03 val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a12 1a12 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a13 1a13 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1a15 seq_br_type 1 Branch True seq_branch_adr 1a15 0x1a15 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a14 1a14 val_c_adr 3c GP03 1a15 1a15 ioc_tvbs 2 fiu+val; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a16 1a16 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a17 1a17 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a18 1a18 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a1e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a1e 0x1a1e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a19 1a19 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a1a 1a1a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 1a1b 1a1b fiu_vmux_sel 1 fill value; Flow C cc=True 0x1eec ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a1c 1a1c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a1d 1a1d fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a1e 1a1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a1f 1a1f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a1a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a1a 0x1a1a typ_mar_cntl 6 INCREMENT_MAR 1a20 1a20 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1a21 1a21 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a2a ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a2a 0x1a2a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a22 1a22 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a23 1a23 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a2d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1a2d 0x1a2d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a24 1a24 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a25 1a25 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3270 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a26 1a26 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a27 1a27 ioc_fiubs 1 val ; Flow J cc=True 0x1a17 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a17 0x1a17 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a28 1a28 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a17 seq_br_type 1 Branch True seq_branch_adr 1a17 0x1a17 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a29 1a29 seq_br_type 3 Unconditional Branch; Flow J 0x1a17 seq_branch_adr 1a17 0x1a17 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a2a 1a2a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a2b 1a2b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a2c 1a2c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a24 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1a24 0x1a24 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a2d 1a2d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator 1a2e 1a2e ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32aa seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_frame 6 1a2f 1a2f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a24 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a24 0x1a24 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 1a30 ; -------------------------------------------------------------------------------------- 1a30 ; 0x01ca Execute Vector,Prepend 1a30 ; -------------------------------------------------------------------------------------- 1a30 MACRO_Execute_Vector,Prepend: 1a30 1a30 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a30 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a31 1a31 fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a32 1a32 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a33 1a33 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329a fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a34 1a34 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a35 1a35 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1a42 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a42 0x1a42 typ_c_adr 3c GP03 val_a_adr 07 GP07 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a36 1a36 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x329a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a37 1a37 fiu_load_tar 1 hold_tar; Flow C cc=False 0x3270 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a38 1a38 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a39 1a39 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a3a 1a3a fiu_fill_mode_src 0 ; Flow J cc=False 0x1a40 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a40 0x1a40 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a3b 1a3b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a3c 1a3c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 6 1a3d 1a3d fiu_vmux_sel 1 fill value; Flow C cc=True 0x1eec ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a3e 1a3e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a3f 1a3f fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a40 1a40 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a41 1a41 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a3c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a3c 0x1a3c typ_mar_cntl 6 INCREMENT_MAR 1a42 1a42 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1a43 1a43 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1a4a fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a4a 0x1a4a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a44 1a44 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a45 1a45 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x3270 seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a46 1a46 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a47 1a47 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1a38 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a38 0x1a38 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a48 1a48 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a38 seq_br_type 1 Branch True seq_branch_adr 1a38 0x1a38 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a49 1a49 seq_br_type 3 Unconditional Branch; Flow J 0x1a38 seq_branch_adr 1a38 0x1a38 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a4a 1a4a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a4b 1a4b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a4c 1a4c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a45 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 1a45 0x1a45 1a4d ; -------------------------------------------------------------------------------------- 1a4d ; Comes from: 1a4d ; 1a9a C True from color 0x0a2d 1a4d ; 1aa2 C True from color 0x0a2d 1a4d ; 1ab8 C True from color 0x0a9f 1a4d ; -------------------------------------------------------------------------------------- 1a4d 1a4d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1a4e 1a4e seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a50 seq_br_type 1 Branch True seq_branch_adr 1a50 0x1a50 1a4f 1a4f fiu_fill_mode_src 0 ; Flow J 0x1a51 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a51 0x1a51 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1a50 1a50 fiu_fill_mode_src 0 ; Flow J 0x1a51 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a51 0x1a51 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a51 1a51 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a53 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a53 0x1a53 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1a52 1a52 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a53 1a53 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a54 1a54 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a55 1a55 <halt> ; Flow R 1a56 ; -------------------------------------------------------------------------------------- 1a56 ; 0x01c7 Execute Vector,Convert 1a56 ; -------------------------------------------------------------------------------------- 1a56 MACRO_Execute_Vector,Convert: 1a56 1a56 dispatch_brk_class 4 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a56 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a57 1a57 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a58 1a58 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a70 seq_br_type 1 Branch True seq_branch_adr 1a70 0x1a70 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a59 1a59 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a63 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a63 0x1a63 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a5a 1a5a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1a5b 1a5b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1a5c 1a5c fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1a5d 1a5d fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1a5e 1a5e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a60 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a60 0x1a60 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a5f 1a5f ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a60 1a60 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 1a61 1a61 ioc_fiubs 1 val ; Flow C cc=True 0x1eec seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1a62 1a62 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a63 ; -------------------------------------------------------------------------------------- 1a63 ; Comes from: 1a63 ; 1a59 C True from color 0x0a2d 1a63 ; 1a70 C True from color 0x0a2d 1a63 ; 1a99 C True from color 0x0a2d 1a63 ; -------------------------------------------------------------------------------------- 1a63 1a63 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a66 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a66 0x1a66 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a64 1a64 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a65 1a65 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a66 1a66 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a67 1a67 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a68 1a68 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a69 ; -------------------------------------------------------------------------------------- 1a69 ; Comes from: 1a69 ; 1a8b C False from color 0x0a2d 1a69 ; -------------------------------------------------------------------------------------- 1a69 1a69 fiu_mem_start 2 start-rd; Flow J 0x1a6e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1a6e 0x1a6e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6a ; -------------------------------------------------------------------------------------- 1a6a ; Comes from: 1a6a ; 1a71 C False from color 0x0a2d 1a6a ; -------------------------------------------------------------------------------------- 1a6a 1a6a fiu_mem_start 2 start-rd; Flow C 0x1a6e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1a6e 0x1a6e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6b 1a6b fiu_mem_start 2 start-rd; Flow J 0x32fc ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6c ; -------------------------------------------------------------------------------------- 1a6c ; Comes from: 1a6c ; 1a75 C False from color 0x0a2d 1a6c ; -------------------------------------------------------------------------------------- 1a6c 1a6c fiu_mem_start 2 start-rd; Flow C 0x1a6e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1a6e 0x1a6e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6d 1a6d fiu_mem_start 2 start-rd; Flow J 0x32fc ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a6e 1a6e <default> 1a6f 1a6f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1a70 1a70 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a63 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a63 0x1a63 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a71 1a71 fiu_load_var 1 hold_var; Flow C cc=False 0x1a6a fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 1a6a 0x1a6a seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B 1a72 1a72 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a73 1a73 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1a8a seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a8a 0x1a8a typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a74 1a74 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a75 1a75 seq_br_type 4 Call False; Flow C cc=False 0x1a6c seq_branch_adr 1a6c 0x1a6c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1a76 1a76 ioc_fiubs 1 val ; Flow C cc=True 0x3277 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1a77 1a77 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a78 1a78 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a7a fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a7a 0x1a7a seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a79 1a79 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a7a 1a7a fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 04 GP04 1a7b 1a7b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x329a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a7c 1a7c fiu_fill_mode_src 0 ; Flow J cc=False 0x1a86 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a86 0x1a86 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1a7d 1a7d fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1a7e 1a7e ioc_load_wdr 0 ; Flow C cc=True 0x1eec ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1a7f 1a7f fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1a80 0x1a80 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a80 1a80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1a81 1a81 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a82 1a82 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a88 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a88 0x1a88 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1a83 1a83 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a84 1a84 ioc_load_wdr 0 ; Flow C cc=True 0x32aa ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_rand 6 CHECK_CLASS_A_??_B 1a85 1a85 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a86 1a86 fiu_fill_mode_src 0 ; Flow C cc=False 0x32aa fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1a87 1a87 fiu_fill_mode_src 0 ; Flow J 0x1a7e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a7e 0x1a7e typ_mar_cntl 6 INCREMENT_MAR 1a88 1a88 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a89 1a89 fiu_fill_mode_src 0 ; Flow J 0x1a84 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a84 0x1a84 typ_mar_cntl 6 INCREMENT_MAR 1a8a 1a8a fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a8b 1a8b ioc_fiubs 2 typ ; Flow C cc=False 0x1a69 seq_br_type 4 Call False seq_branch_adr 1a69 0x1a69 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a8c 1a8c ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1a8d 1a8d fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1a90 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a90 0x1a90 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1a8e 1a8e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a8f 1a8f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a90 1a90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a92 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a92 0x1a92 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a91 1a91 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a92 1a92 ioc_fiubs 1 val ; Flow J cc=True 0x1a94 seq_br_type 1 Branch True seq_branch_adr 1a94 0x1a94 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 1a93 1a93 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1a94 1a94 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1a95 1a95 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a96 ; -------------------------------------------------------------------------------------- 1a96 ; 0x01c6 Execute Vector,Convert_To_Formal 1a96 ; -------------------------------------------------------------------------------------- 1a96 MACRO_Execute_Vector,Convert_To_Formal: 1a96 1a96 dispatch_brk_class 4 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a96 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a97 1a97 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a98 1a98 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a70 seq_br_type 1 Branch True seq_branch_adr 1a70 0x1a70 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a99 1a99 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a63 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a63 0x1a63 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a9a 1a9a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4d seq_br_type 5 Call True seq_branch_adr 1a4d 0x1a4d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1a9b 1a9b fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1a9c 1a9c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1a5c seq_br_type 0 Branch False seq_branch_adr 1a5c 0x1a5c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1a9d 1a9d seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1a9e ; -------------------------------------------------------------------------------------- 1a9e ; 0x01c5 Execute Vector,In_Type 1a9e ; -------------------------------------------------------------------------------------- 1a9e MACRO_Execute_Vector,In_Type: 1a9e 1a9e dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a9e dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a9f 1a9f fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1aa0 1aa0 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1aaf ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1aaf 0x1aaf seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 1aa1 1aa1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa5 0x1aa5 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1aa2 1aa2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4d seq_br_type 5 Call True seq_branch_adr 1a4d 0x1a4d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1aa3 1aa3 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1aa4 0x1aa4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 1aa4 1aa4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1aa5 ; -------------------------------------------------------------------------------------- 1aa5 ; Comes from: 1aa5 ; 1aa1 C True from color 0x0a2d 1aa5 ; 1aaf C True from color 0x0a2d 1aa5 ; 1ab7 C True from color 0x0a9f 1aa5 ; 1abb C True from color 0x0a9f 1aa5 ; -------------------------------------------------------------------------------------- 1aa5 1aa5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1aa8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1aa8 0x1aa8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1aa6 1aa6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1aa7 1aa7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1aa8 1aa8 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1aa9 1aa9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1aaa 1aaa fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1aab 1aab <halt> ; Flow R 1aac ; -------------------------------------------------------------------------------------- 1aac ; 0x01c4 Execute Vector,Not_In_Type 1aac ; -------------------------------------------------------------------------------------- 1aac MACRO_Execute_Vector,Not_In_Type: 1aac 1aac dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1aac dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1aad 1aad fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1aae 1aae fiu_tivi_src 4 fiu_var; Flow J cc=False 0x1aa1 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1aa1 0x1aa1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 1aaf 1aaf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa5 0x1aa5 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1ab0 1ab0 fiu_load_var 1 hold_var; Flow J cc=False 0x1aa4 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 1aa4 0x1aa4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 1ab1 1ab1 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ab2 1ab2 ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ab3 1ab3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1aa4 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1aa4 0x1aa4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1ab4 ; -------------------------------------------------------------------------------------- 1ab4 ; 0x01c3 Execute Vector,Check_In_Type 1ab4 ; -------------------------------------------------------------------------------------- 1ab4 MACRO_Execute_Vector,Check_In_Type: 1ab4 1ab4 dispatch_brk_class 8 ; Flow C cc=False 0x1ac1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ab4 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1ac1 0x1ac1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1ab5 1ab5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ab6 1ab6 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1abb seq_br_type 1 Branch True seq_branch_adr 1abb 0x1abb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 1ab7 1ab7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa5 0x1aa5 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1ab8 1ab8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a4d seq_br_type 5 Call True seq_branch_adr 1a4d 0x1a4d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1ab9 1ab9 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1aba 0x1aba seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1aba 1aba seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? 1abb 1abb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1aa5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1aa5 0x1aa5 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1abc 1abc fiu_load_var 1 hold_var; Flow C cc=False 0x3270 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 3270 0x3270 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 1abd 1abd fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1abe 1abe ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1abf 1abf fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1ac0 0x1ac0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1ac0 1ac0 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1ac1 ; -------------------------------------------------------------------------------------- 1ac1 ; Comes from: 1ac1 ; 1840 C False from color MACRO_Execute_Vector,Greater_Equal 1ac1 ; 1846 C False from color MACRO_Execute_Vector,Greater_Equal 1ac1 ; 18f8 C False from color MACRO_Execute_Vector,And 1ac1 ; 19be C False from color MACRO_Execute_Vector,Slice_Reference 1ac1 ; 19ce C False from color MACRO_Execute_Vector,Catenate 1ac1 ; 1a56 C False from color 0x0a2d 1ac1 ; 1a96 C False from color 0x0a2d 1ac1 ; 1a9e C False from color 0x0a2d 1ac1 ; 1aac C False from color 0x0a2d 1ac1 ; -------------------------------------------------------------------------------------- 1ac1 1ac1 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ac2 1ac2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1ac3 1ac3 seq_br_type a Unconditional Return; Flow R 1ac4 ; -------------------------------------------------------------------------------------- 1ac4 ; 0x022f Execute Access,Equal 1ac4 ; -------------------------------------------------------------------------------------- 1ac4 MACRO_Execute_Access,Equal: 1ac4 1ac4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ac4 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1ac5 1ac5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ac6 ; -------------------------------------------------------------------------------------- 1ac6 ; 0x022e Execute Access,Not_Equal 1ac6 ; -------------------------------------------------------------------------------------- 1ac6 MACRO_Execute_Access,Not_Equal: 1ac6 1ac6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ac6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1ac7 1ac7 <halt> ; Flow R 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 ; 0x022d Execute Access,Is_Null 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 MACRO_Execute_Access,Is_Null: 1ac8 1ac8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ac8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1ac9 1ac9 <halt> ; Flow R 1aca ; -------------------------------------------------------------------------------------- 1aca ; 0x022c Execute Access,Not_Null 1aca ; -------------------------------------------------------------------------------------- 1aca MACRO_Execute_Access,Not_Null: 1aca 1aca dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1aca fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1acb 1acb <halt> ; Flow R 1acc ; -------------------------------------------------------------------------------------- 1acc ; 0x022b Execute Access,Set_Null 1acc ; -------------------------------------------------------------------------------------- 1acc MACRO_Execute_Access,Set_Null: 1acc 1acc dispatch_brk_class 2 ; Flow J cc=True 0x1ad0 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1acc fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ad0 0x1ad0 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 14 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1acd 1acd fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a5 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 1ace 1ace fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 1acf 1acf ioc_load_wdr 0 ; Flow J 0x1ac5 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1ac5 0x1ac5 val_b_adr 39 VR02:19 val_frame 2 1ad0 1ad0 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3277 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 1ad1 1ad1 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x1ad3 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ad3 0x1ad3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 1ad2 1ad2 fiu_fill_mode_src 0 ; Flow J 0x1ad6 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ad6 0x1ad6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1ad3 1ad3 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ad4 1ad4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1ad5 1ad5 fiu_load_var 1 hold_var; Flow J 0x1ad6 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ad6 0x1ad6 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1ad6 1ad6 ioc_load_wdr 0 ; Flow J 0x1ac5 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac5 0x1ac5 1ad7 1ad7 <halt> ; Flow R 1ad8 ; -------------------------------------------------------------------------------------- 1ad8 ; 0x022a Execute Access,Element_Type 1ad8 ; -------------------------------------------------------------------------------------- 1ad8 MACRO_Execute_Access,Element_Type: 1ad8 1ad8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ad8 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1ad9 1ad9 fiu_load_tar 1 hold_tar; Flow J cc=False 0x1adc fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1adc 0x1adc seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1ada 1ada fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1adb 1adb fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1adc 1adc fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 1add 0x1add seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 1add 1add seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 seq_random 02 ? 1ade ; -------------------------------------------------------------------------------------- 1ade ; 0x0229 Execute Access,All_Read 1ade ; -------------------------------------------------------------------------------------- 1ade MACRO_Execute_Access,All_Read: 1ade 1ade dispatch_brk_class 8 ; Flow C cc=True 0x326f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ade dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 1adf 1adf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ae5 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1ae5 0x1ae5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1ae0 1ae0 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1ae1 1ae1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ae3 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ae3 0x1ae3 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1ae2 1ae2 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1ae6 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1ae6 0x1ae6 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ae3 1ae3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ae4 1ae4 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1ae6 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1ae6 0x1ae6 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ae5 1ae5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ae6 1ae6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ae7 0x1ae7 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ae7 1ae7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ae8 ; -------------------------------------------------------------------------------------- 1ae8 ; 0x0228 Execute Access,All_Write 1ae8 ; -------------------------------------------------------------------------------------- 1ae8 MACRO_Execute_Access,All_Write: 1ae8 1ae8 dispatch_brk_class 2 ; Flow C cc=True 0x326f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ae8 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 1ae9 1ae9 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x1d46 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d46 0x1d46 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1aea 1aea fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1aeb 1aeb fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1aec 1aec fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 1aed 1aed <halt> ; Flow R 1aee ; -------------------------------------------------------------------------------------- 1aee ; 0x0227 Execute Access,All_Reference 1aee ; -------------------------------------------------------------------------------------- 1aee MACRO_Execute_Access,All_Reference: 1aee 1aee dispatch_brk_class 8 ; Flow C cc=True 0x326f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1aee dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1aef 1aef fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1af0 ; -------------------------------------------------------------------------------------- 1af0 ; 0x0226 Execute Access,Convert 1af0 ; -------------------------------------------------------------------------------------- 1af0 MACRO_Execute_Access,Convert: 1af0 1af0 dispatch_brk_class 4 ; Flow J cc=True 0x1af2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af0 seq_br_type 1 Branch True seq_branch_adr 1af2 0x1af2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 1af1 1af1 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1af2 1af2 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b09 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1af3 1af3 <halt> ; Flow R 1af4 ; -------------------------------------------------------------------------------------- 1af4 ; 0x0222 Execute Access,Convert_Reference 1af4 ; -------------------------------------------------------------------------------------- 1af4 MACRO_Execute_Access,Convert_Reference: 1af4 1af4 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1af5 1af5 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 1af6 1af6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 1af7 1af7 typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 1af8 1af8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1af9 0x1af9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 1af9 1af9 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_csa_cntl 3 POP_CSA 1afa ; -------------------------------------------------------------------------------------- 1afa ; 0x0225 Execute Access,In_Type 1afa ; -------------------------------------------------------------------------------------- 1afa MACRO_Execute_Access,In_Type: 1afa 1afa dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1afa fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1afb 0x1afb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1afb 1afb ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1afc 1afc typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1afd 1afd seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1afe 1afe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1aff 1aff <halt> ; Flow R 1b00 ; -------------------------------------------------------------------------------------- 1b00 ; 0x0224 Execute Access,Not_In_Type 1b00 ; -------------------------------------------------------------------------------------- 1b00 MACRO_Execute_Access,Not_In_Type: 1b00 1b00 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b00 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b01 0x1b01 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1b01 1b01 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b02 1b02 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1b03 1b03 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b04 1b04 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b05 1b05 <halt> ; Flow R 1b06 ; -------------------------------------------------------------------------------------- 1b06 ; 0x0223 Execute Access,Check_In_Type 1b06 ; -------------------------------------------------------------------------------------- 1b06 MACRO_Execute_Access,Check_In_Type: 1b06 1b06 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b06 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b07 0x1b07 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 1b07 1b07 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b08 1b08 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b09 0x1b09 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1b09 1b09 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1b0a 1b0a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1b0b 1b0b seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1b0c ; -------------------------------------------------------------------------------------- 1b0c ; 0x0114 Execute Access,Size 1b0c ; -------------------------------------------------------------------------------------- 1b0c MACRO_Execute_Access,Size: 1b0c 1b0c dispatch_brk_class 8 ; Flow J cc=False 0x1b10 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b0c dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 1b10 0x1b10 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 10 1b0d 1b0d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b0e 1b0e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1b0f 1b0f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b10 1b10 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 10 TOP 1b11 1b11 seq_br_type 3 Unconditional Branch; Flow J 0x1b0d seq_branch_adr 1b0d 0x1b0d typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 1b12 ; -------------------------------------------------------------------------------------- 1b12 ; 0x0220 Execute Access,Deallocate 1b12 ; -------------------------------------------------------------------------------------- 1b12 MACRO_Execute_Access,Deallocate: 1b12 1b12 dispatch_brk_class 8 ; Flow J cc=True 0x1b1d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b12 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b1d 0x1b1d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1b13 1b13 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b14 1b14 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b15 1b15 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b16 1b16 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1b1d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b1d 0x1b1d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 13 1b17 1b17 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b18 1b18 fiu_fill_mode_src 0 ; Flow J cc=False 0x1b1e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b1e 0x1b1e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 1b19 1b19 fiu_fill_mode_src 0 ; Flow J cc=False 0x1b23 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b23 0x1b23 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b1a 1b1a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b1b 1b1b fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b1c 1b1c ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 1b1d 1b1d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b1e 1b1e fiu_fill_mode_src 0 ; Flow J cc=False 0x1b23 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b23 0x1b23 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1b1f 1b1f fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b20 1b20 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_c_adr 30 GP0f 1b21 1b21 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 0f GP0f 1b22 1b22 seq_br_type 3 Unconditional Branch; Flow J 0x1b1b seq_branch_adr 1b1b 0x1b1b val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b23 1b23 fiu_mem_start 2 start-rd; Flow C 0x3573 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3573 0x3573 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b24 1b24 fiu_mem_start 2 start-rd; Flow J cc=True 0x1b15 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b15 0x1b15 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b25 1b25 <halt> ; Flow R 1b26 ; -------------------------------------------------------------------------------------- 1b26 ; 0x0221 Execute Access,Allow_Deallocate 1b26 ; -------------------------------------------------------------------------------------- 1b26 MACRO_Execute_Access,Allow_Deallocate: 1b26 1b26 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b26 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b27 1b27 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b28 1b28 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1ac5 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac5 0x1ac5 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b29 1b29 typ_c_adr 3d GP02 1b2a 1b2a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b2b 1b2b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1ac5 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac5 0x1ac5 val_a_adr 21 VR13:01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 1b2c 1b2c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1ac5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ac5 0x1ac5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 39 GP06 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1b2d 1b2d fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 1b2e 1b2e ioc_load_wdr 0 ; Flow J 0x1ac5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac5 0x1ac5 typ_b_adr 06 GP06 1b2f 1b2f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32a7 seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 1b30 1b30 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a7 seq_br_type 9 Return False seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_frame 11 1b31 1b31 <halt> ; Flow R 1b32 ; -------------------------------------------------------------------------------------- 1b32 ; 0x0080 QQUnknown InMicrocode 1b32 ; -------------------------------------------------------------------------------------- 1b32 MACRO_1b32_QQUnknown_InMicrocode: 1b32 1b32 dispatch_brk_class 0 ; Flow J cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b32 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1b33 1b33 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b34 1b34 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 1b35 1b35 ioc_fiubs 2 typ ; Flow J cc=True 0x32a9 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a9 0x32a9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b36 1b36 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 01 GP01 val_b_adr 01 GP01 1b37 1b37 ioc_load_wdr 0 ; Flow J 0x1ac5 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ac5 0x1ac5 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1b38 ; -------------------------------------------------------------------------------------- 1b38 ; 0x0082 QQUnknown InMicrocode 1b38 ; -------------------------------------------------------------------------------------- 1b38 MACRO_1b38_QQUnknown_InMicrocode: 1b38 1b38 dispatch_brk_class 0 ; Flow J cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b38 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1b39 1b39 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b3a 1b3a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b3b 1b3b fiu_mem_start 3 start-wr; Flow J cc=True 0x32a7 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a7 0x32a7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1b3c 1b3c ioc_load_wdr 0 ; Flow J 0x1ac5 seq_br_type 3 Unconditional Branch seq_branch_adr 1ac5 0x1ac5 typ_csa_cntl 3 POP_CSA 1b3d 1b3d <halt> ; Flow R 1b3e ; -------------------------------------------------------------------------------------- 1b3e ; 0x0081 QQUnknown InMicrocode 1b3e ; -------------------------------------------------------------------------------------- 1b3e MACRO_1b3e_QQUnknown_InMicrocode: 1b3e 1b3e dispatch_brk_class 0 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b3e dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b3f 1b3f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b40 1b40 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b41 1b41 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b42 ; -------------------------------------------------------------------------------------- 1b42 ; 0x01fe Execute Array,Not_Equal 1b42 ; 0x01ff Execute Array,Equal 1b42 ; -------------------------------------------------------------------------------------- 1b42 MACRO_Execute_Array,Equal: 1b42 MACRO_Execute_Array,Not_Equal: 1b42 1b42 dispatch_brk_class 8 ; Flow J cc=True 0x1b44 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b42 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1b44 0x1b44 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1b43 1b43 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b44 1b44 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b45 1b45 seq_br_type 2 Push (branch address); Flow J 0x1b46 seq_branch_adr 1b73 0x1b73 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1b46 1b46 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x1b5e fiu_mem_start 6 start_rd_if_false fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1b5e 0x1b5e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1b47 1b47 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b48 1b48 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b49 1b49 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b4a 1b4a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b51 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b51 0x1b51 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b4b 1b4b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b4c 1b4c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1b6e fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1b6e 0x1b6e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b4d 1b4d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b55 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b55 0x1b55 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b4e 1b4e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b4f 1b4f seq_br_type 1 Branch True; Flow J cc=True 0x22b2 seq_branch_adr 22b2 0x22b2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b50 1b50 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b51 1b51 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b52 1b52 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b53 1b53 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1b6e fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1b6e 0x1b6e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b54 1b54 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1b4e ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1b4e 0x1b4e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b55 1b55 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b58 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b58 0x1b58 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b56 1b56 seq_br_type 1 Branch True; Flow J cc=True 0x22ba seq_branch_adr 22ba 0x22ba seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b57 1b57 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b58 ; -------------------------------------------------------------------------------------- 1b58 ; Comes from: 1b58 ; 1b55 C from color 0x09a6 1b58 ; 1b66 C from color 0x09a6 1b58 ; -------------------------------------------------------------------------------------- 1b58 1b58 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b5b ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b5b 0x1b5b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1b59 1b59 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b5a 1b5a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b69 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b69 0x1b69 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b5b 1b5b fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b5c 1b5c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b5d 1b5d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b69 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b69 0x1b69 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b5e 1b5e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b5f 1b5f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1b60 1b60 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b64 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b64 0x1b64 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b61 1b61 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b62 1b62 seq_br_type 1 Branch True; Flow J cc=True 0x22ac seq_branch_adr 22ac 0x22ac seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b63 1b63 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b64 1b64 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b65 1b65 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b66 1b66 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b58 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b58 0x1b58 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b67 1b67 seq_br_type 1 Branch True; Flow J cc=True 0x22a8 seq_branch_adr 22a8 0x22a8 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b68 1b68 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b69 1b69 seq_br_type 0 Branch False; Flow J cc=False 0x1b6b seq_branch_adr 1b6b 0x1b6b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1b6a 1b6a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1b6b 1b6b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1b6c 1b6c seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1b6d 0x1b6d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1b6d 1b6d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1b6e ; -------------------------------------------------------------------------------------- 1b6e ; Comes from: 1b6e ; 1b4c C from color 0x09a6 1b6e ; 1b53 C from color 0x09a6 1b6e ; -------------------------------------------------------------------------------------- 1b6e 1b6e seq_br_type 0 Branch False; Flow J cc=False 0x1b70 seq_branch_adr 1b70 0x1b70 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 1b6f 1b6f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b70 1b70 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1b71 1b71 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1b72 0x1b72 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1b72 1b72 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1b73 1b73 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1b76 seq_br_type 0 Branch False seq_branch_adr 1b76 0x1b76 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b74 1b74 ioc_fiubs 1 val ; Flow C 0x26fa seq_br_type 7 Unconditional Call seq_branch_adr 26fa 0x26fa seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 07 GP07 1b75 1b75 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1b76 1b76 seq_br_type 7 Unconditional Call; Flow C 0x1b7c seq_branch_adr 1b7c 0x1b7c typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1b77 1b77 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1b79 seq_br_type 1 Branch True seq_branch_adr 1b79 0x1b79 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1b78 1b78 seq_br_type 7 Unconditional Call; Flow C 0x1b7c seq_branch_adr 1b7c 0x1b7c typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1b79 1b79 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b7a 1b7a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b7b 0x1b7b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1b7b 1b7b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b7c ; -------------------------------------------------------------------------------------- 1b7c ; Comes from: 1b7c ; 1b76 C from color 0x1b73 1b7c ; 1b78 C from color 0x1b73 1b7c ; -------------------------------------------------------------------------------------- 1b7c 1b7c ioc_fiubs 2 typ ; Flow J cc=False 0x2254 seq_br_type 0 Branch False seq_branch_adr 2254 0x2254 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 07 GP07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1b7d 1b7d ioc_fiubs 1 val ; Flow J 0x225c seq_br_type 3 Unconditional Branch seq_branch_adr 225c 0x225c seq_en_micro 0 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1b7e ; -------------------------------------------------------------------------------------- 1b7e ; Comes from: 1b7e ; 1b96 C from color MACRO_Execute_Array,First 1b7e ; 1b98 C from color MACRO_Execute_Array,Last 1b7e ; 1b9a C from color MACRO_Execute_Array,Length 1b7e ; 1b9c C from color MACRO_Execute_Array,Last 1b7e ; 1b9e C from color MACRO_Execute_Array,First 1b7e ; -------------------------------------------------------------------------------------- 1b7e 1b7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1b8a fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b8a 0x1b8a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP 1b7f 1b7f fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b80 1b80 fiu_len_fill_lit 77 zero-fill 0x37; Flow C cc=True 0x32a7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1b81 1b81 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b82 1b82 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1b84 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b84 0x1b84 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1c DEC_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b83 1b83 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b84 1b84 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 04 GP04 1b85 1b85 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1b86 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1b86 0x1b86 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1b86 1b86 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b88 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b88 0x1b88 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1b87 1b87 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1b88 1b88 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b89 1b89 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1b8a 1b8a fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1b7f fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1b7f 0x1b7f typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1b8b 1b8b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1b8c 1b8c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b8e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b8e 0x1b8e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 1b8d 1b8d fiu_fill_mode_src 0 ; Flow J 0x1b90 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b90 0x1b90 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b8e 1b8e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b8f 1b8f fiu_fill_mode_src 0 ; Flow J 0x1b90 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b90 0x1b90 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b90 1b90 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1b92 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b92 0x1b92 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1b91 1b91 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b92 1b92 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b93 1b93 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1b94 1b94 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1b86 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1b86 0x1b86 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 1b95 1b95 <halt> ; Flow R 1b96 ; -------------------------------------------------------------------------------------- 1b96 ; 0x01fd Execute Array,First 1b96 ; -------------------------------------------------------------------------------------- 1b96 MACRO_Execute_Array,First: 1b96 1b96 dispatch_brk_class 8 ; Flow C 0x1b7e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b96 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b7e 0x1b7e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b97 1b97 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b98 ; -------------------------------------------------------------------------------------- 1b98 ; 0x01fc Execute Array,Last 1b98 ; -------------------------------------------------------------------------------------- 1b98 MACRO_Execute_Array,Last: 1b98 1b98 dispatch_brk_class 8 ; Flow C 0x1b7e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b98 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b7e 0x1b7e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b99 1b99 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9a ; -------------------------------------------------------------------------------------- 1b9a ; 0x01fb Execute Array,Length 1b9a ; -------------------------------------------------------------------------------------- 1b9a MACRO_Execute_Array,Length: 1b9a 1b9a dispatch_brk_class 8 ; Flow C 0x1b7e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9a dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b7e 0x1b7e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9b 1b9b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9c ; -------------------------------------------------------------------------------------- 1b9c ; 0x01fa Execute Array,Bounds 1b9c ; -------------------------------------------------------------------------------------- 1b9c MACRO_Execute_Array,Bounds: 1b9c 1b9c dispatch_brk_class 8 ; Flow C 0x1b7e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9c dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b7e 0x1b7e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9d 1b9d seq_br_type 3 Unconditional Branch; Flow J 0x1b99 seq_branch_adr 1b99 0x1b99 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b9e ; -------------------------------------------------------------------------------------- 1b9e ; 0x01f9 Execute Array,Reverse_Bounds 1b9e ; -------------------------------------------------------------------------------------- 1b9e MACRO_Execute_Array,Reverse_Bounds: 1b9e 1b9e dispatch_brk_class 8 ; Flow C 0x1b7e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b9e dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1b7e 0x1b7e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b9f 1b9f seq_br_type 3 Unconditional Branch; Flow J 0x1b97 seq_branch_adr 1b97 0x1b97 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 ; 0x01f8 Execute Array,Element_Type 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 MACRO_Execute_Array,Element_Type: 1ba0 1ba0 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ba0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ba1 1ba1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 1ba2 1ba2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1ba3 1ba3 <halt> ; Flow R 1ba4 ; -------------------------------------------------------------------------------------- 1ba4 ; 0x01ed Execute Array,In_Type 1ba4 ; -------------------------------------------------------------------------------------- 1ba4 MACRO_Execute_Array,In_Type: 1ba4 1ba4 dispatch_brk_class 8 ; Flow C cc=False 0x1bd1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ba4 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd1 0x1bd1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1ba5 1ba5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1ba6 1ba6 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bac fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bac 0x1bac seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ba7 1ba7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1baa seq_br_type 1 Branch True seq_branch_adr 1baa 0x1baa 1ba8 1ba8 seq_br_type 7 Unconditional Call; Flow C 0x2294 seq_branch_adr 2294 0x2294 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1ba9 1ba9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1baa 1baa ioc_fiubs 1 val ; Flow C 0x228a seq_br_type 7 Unconditional Call seq_branch_adr 228a 0x228a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bab 1bab fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bac 1bac seq_b_timing 1 Latch Condition; Flow J cc=True 0x1baf seq_br_type 1 Branch True seq_branch_adr 1baf 0x1baf 1bad 1bad seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bae 1bae fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1baf 1baf ioc_fiubs 1 val ; Flow C 0x226b seq_br_type 7 Unconditional Call seq_branch_adr 226b 0x226b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bb0 1bb0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bb1 1bb1 <halt> ; Flow R 1bb2 ; -------------------------------------------------------------------------------------- 1bb2 ; 0x01ec Execute Array,Not_In_Type 1bb2 ; -------------------------------------------------------------------------------------- 1bb2 MACRO_Execute_Array,Not_In_Type: 1bb2 1bb2 dispatch_brk_class 8 ; Flow C cc=False 0x1bd1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bb2 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd1 0x1bd1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bb3 1bb3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bb4 1bb4 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bba fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bba 0x1bba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bb5 1bb5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bb8 seq_br_type 1 Branch True seq_branch_adr 1bb8 0x1bb8 1bb6 1bb6 seq_br_type 7 Unconditional Call; Flow C 0x2294 seq_branch_adr 2294 0x2294 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bb7 1bb7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bb8 1bb8 ioc_fiubs 1 val ; Flow C 0x228a seq_br_type 7 Unconditional Call seq_branch_adr 228a 0x228a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bb9 1bb9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bba 1bba seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bbd seq_br_type 1 Branch True seq_branch_adr 1bbd 0x1bbd 1bbb 1bbb seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bbc 1bbc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bbd 1bbd ioc_fiubs 1 val ; Flow C 0x226b seq_br_type 7 Unconditional Call seq_branch_adr 226b 0x226b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bbe 1bbe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bbf 1bbf <halt> ; Flow R 1bc0 ; -------------------------------------------------------------------------------------- 1bc0 ; 0x01eb Execute Array,Check_In_Type 1bc0 ; -------------------------------------------------------------------------------------- 1bc0 MACRO_Execute_Array,Check_In_Type: 1bc0 1bc0 dispatch_brk_class 8 ; Flow C cc=False 0x1bd1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bc0 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1bd1 0x1bd1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bc1 1bc1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bc2 1bc2 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bca fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bca 0x1bca seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bc3 1bc3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bc7 seq_br_type 1 Branch True seq_branch_adr 1bc7 0x1bc7 1bc4 1bc4 seq_br_type 7 Unconditional Call; Flow C 0x2294 seq_branch_adr 2294 0x2294 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bc5 1bc5 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bc6 0x1bc6 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bc6 1bc6 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? 1bc7 1bc7 ioc_fiubs 1 val ; Flow C 0x228a seq_br_type 7 Unconditional Call seq_branch_adr 228a 0x228a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bc8 1bc8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bc9 0x1bc9 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bc9 1bc9 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? 1bca 1bca seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bce seq_br_type 1 Branch True seq_branch_adr 1bce 0x1bce 1bcb 1bcb seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bcc 1bcc fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bcd 0x1bcd seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bcd 1bcd seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? 1bce 1bce ioc_fiubs 1 val ; Flow C 0x226b seq_br_type 7 Unconditional Call seq_branch_adr 226b 0x226b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bcf 1bcf fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bd0 0x1bd0 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bd0 1bd0 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 seq_en_micro 0 seq_random 02 ? 1bd1 ; -------------------------------------------------------------------------------------- 1bd1 ; Comes from: 1bd1 ; 1ba4 C False from color 0x0a76 1bd1 ; 1bb2 C False from color 0x0a8a 1bd1 ; -------------------------------------------------------------------------------------- 1bd1 1bd1 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd2 1bd2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd3 1bd3 <halt> ; Flow R 1bd4 ; -------------------------------------------------------------------------------------- 1bd4 ; 0x01ef Execute Array,Convert 1bd4 ; -------------------------------------------------------------------------------------- 1bd4 MACRO_Execute_Array,Convert: 1bd4 1bd4 dispatch_brk_class 4 ; Flow J cc=True 0x1bd6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bd4 seq_br_type 1 Branch True seq_branch_adr 1bd6 0x1bd6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bd5 1bd5 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd6 1bd6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd7 1bd7 ioc_fiubs 2 typ ; Flow J cc=True 0x1bed seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bed 0x1bed seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1bd8 1bd8 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bdd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bdd 0x1bdd typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bd9 1bd9 seq_br_type 7 Unconditional Call; Flow C 0x22ac seq_branch_adr 22ac 0x22ac typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bda 1bda fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1be5 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be5 0x1be5 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bdb 1bdb ioc_fiubs 2 typ ; Flow C 0x2254 seq_br_type 7 Unconditional Call seq_branch_adr 2254 0x2254 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bdc 1bdc seq_br_type 3 Unconditional Branch; Flow J 0x1be2 seq_branch_adr 1be2 0x1be2 1bdd 1bdd ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1bde 1bde seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1bdf 1bdf ioc_fiubs 1 val ; Flow C 0x22a8 seq_br_type 7 Unconditional Call seq_branch_adr 22a8 0x22a8 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1be0 1be0 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1be5 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be5 0x1be5 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1be1 1be1 ioc_fiubs 2 typ ; Flow C 0x225c seq_br_type 7 Unconditional Call seq_branch_adr 225c 0x225c typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1be2 1be2 ioc_fiubs 2 typ ; Flow C cc=True 0x3270 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1be3 1be3 seq_br_type 7 Unconditional Call; Flow C 0x2254 seq_branch_adr 2254 0x2254 1be4 1be4 fiu_mem_start 2 start-rd; Flow C cc=True 0x3270 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1be5 1be5 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1be6 1be6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1be7 1be7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1be8 1be8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1bea fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bea 0x1bea seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1be9 1be9 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a0 0x32a0 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bea 1bea seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 37 GP08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1beb 1beb ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1bec 1bec fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bed 1bed fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bee 1bee seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bf2 seq_br_type 1 Branch True seq_branch_adr 1bf2 0x1bf2 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1bef 1bef seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1bf0 1bf0 fiu_mem_start 2 start-rd; Flow J cc=True 0x1bf5 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bf5 0x1bf5 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1bf1 1bf1 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1bf2 1bf2 seq_br_type 2 Push (branch address); Flow J 0x1bf3 seq_branch_adr 1c25 0x1c25 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1bf3 1bf3 ioc_fiubs 1 val ; Flow C 0x226b seq_br_type 7 Unconditional Call seq_branch_adr 226b 0x226b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bf4 1bf4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3270 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3270 0x3270 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1bf5 1bf5 <default> 1bf6 1bf6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bf7 1bf7 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1bf8 1bf8 ioc_fiubs 1 val ; Flow C cc=True 0x3277 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1bf9 1bf9 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bfa 1bfa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1bfc fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bfc 0x1bfc seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bfb 1bfb ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bfc 1bfc fiu_mem_start 2 start-rd; Flow C cc=False 0x329a ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_rand 2 DEC_LOOP_COUNTER 1bfd 1bfd fiu_mem_start 4 continue typ_c_adr 37 GP08 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1bfe 1bfe fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1bff 1bff fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1c00 1c00 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c01 1c01 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c02 1c02 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c13 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c13 0x1c13 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c03 1c03 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c04 1c04 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1c05 1c05 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c06 1c06 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c15 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c15 0x1c15 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 06 GP06 1c07 1c07 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c08 1c08 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 1c09 1c09 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 1c0a 1c0a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1bfe seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1bfe 0x1bfe seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 1c0b 1c0b fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1c0c 1c0c fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c0d 1c0d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c0e 1c0e fiu_fill_mode_src 0 ; Flow J cc=False 0x1c17 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c17 0x1c17 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c0f 1c0f fiu_fill_mode_src 0 ; Flow J cc=False 0x1c19 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1c19 0x1c19 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c10 1c10 ioc_load_wdr 0 ; Flow C cc=True 0x329a ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1c11 1c11 seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1c12 1c12 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c13 1c13 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c14 1c14 fiu_fill_mode_src 0 ; Flow J 0x1c04 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c04 0x1c04 typ_mar_cntl 6 INCREMENT_MAR 1c15 1c15 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c16 1c16 fiu_fill_mode_src 0 ; Flow J 0x1c08 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c08 0x1c08 typ_mar_cntl 6 INCREMENT_MAR 1c17 1c17 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c18 1c18 fiu_fill_mode_src 0 ; Flow J cc=True 0x1c10 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c10 0x1c10 typ_mar_cntl 6 INCREMENT_MAR 1c19 1c19 ioc_load_wdr 0 ; Flow J 0x1c1b ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c1b 0x1c1b val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c1a 1c1a ioc_load_wdr 0 ; Flow J cc=True 0x1c10 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c10 0x1c10 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 1c1b 1c1b fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 1c1c 1c1c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 6 1c1d 1c1d fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c1e 1c1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c1f 1c1f fiu_fill_mode_src 0 ; Flow J cc=False 0x1c22 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c22 0x1c22 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c20 1c20 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c1a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c1a 0x1c1a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 1c21 1c21 ioc_load_wdr 0 ; Flow J 0x1c10 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c10 0x1c10 val_rand 2 DEC_LOOP_COUNTER 1c22 1c22 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c23 1c23 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c1a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c1a 0x1c1a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1c24 1c24 ioc_load_wdr 0 ; Flow J 0x1c10 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c10 0x1c10 val_rand 2 DEC_LOOP_COUNTER 1c25 1c25 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1c29 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c29 0x1c29 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1c26 1c26 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c27 1c27 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c28 1c28 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1c2b fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c2b 0x1c2b typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c29 1c29 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c2a 1c2a fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c2b 1c2b seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1c2c 1c2c fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1c2d 1c2d fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x1c30 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1c30 0x1c30 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_c_adr 37 GP08 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1c2e 1c2e seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c33 seq_br_type 1 Branch True seq_branch_adr 1c33 0x1c33 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c2f 1c2f seq_br_type 3 Unconditional Branch; Flow J 0x1c38 seq_branch_adr 1c38 0x1c38 1c30 1c30 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1c31 1c31 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c32 1c32 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1c38 seq_br_type 1 Branch True seq_branch_adr 1c38 0x1c38 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c33 1c33 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1c35 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c35 0x1c35 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c34 1c34 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x329a seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 329a 0x329a val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1c35 1c35 ioc_fiubs 1 val ; Flow C cc=False 0x329a seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1c36 1c36 ioc_fiubs 1 val ; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1c37 1c37 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1c38 1c38 val_a_adr 04 GP04 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 1c39 1c39 seq_br_type 3 Unconditional Branch; Flow J 0x1c33 seq_branch_adr 1c33 0x1c33 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c3a ; -------------------------------------------------------------------------------------- 1c3a ; 0x01ee Execute Array,Convert_To_Formal 1c3a ; -------------------------------------------------------------------------------------- 1c3a MACRO_Execute_Array,Convert_To_Formal: 1c3a 1c3a dispatch_brk_class 4 ; Flow J cc=True 0x1c3c dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c3a seq_br_type 1 Branch True seq_branch_adr 1c3c 0x1c3c seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1c3b 1c3b fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c3c 1c3c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c3d 1c3d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bed seq_br_type 1 Branch True seq_branch_adr 1bed 0x1bed seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c3e 1c3e fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1c42 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c42 0x1c42 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c3f 1c3f seq_br_type 7 Unconditional Call; Flow C 0x2294 seq_branch_adr 2294 0x2294 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1c40 1c40 fiu_mem_start 2 start-rd; Flow J cc=True 0x1be5 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1be5 0x1be5 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c41 1c41 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1c42 1c42 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1c43 1c43 seq_br_type 2 Push (branch address); Flow J 0x1c44 seq_branch_adr 1be5 0x1be5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c44 1c44 ioc_fiubs 1 val ; Flow C 0x228a seq_br_type 7 Unconditional Call seq_branch_adr 228a 0x228a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c45 1c45 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3270 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3270 0x3270 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c46 ; -------------------------------------------------------------------------------------- 1c46 ; 0x01f4 Execute Array,Structure_Write 1c46 ; -------------------------------------------------------------------------------------- 1c46 MACRO_Execute_Array,Structure_Write: 1c46 1c46 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1c46 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c47 1c47 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e48 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e48 0x1e48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c48 ; -------------------------------------------------------------------------------------- 1c48 ; Comes from: 1c48 ; 1c68 C from color MACRO_Execute_Array,Field_Read 1c48 ; 1c70 C from color MACRO_Execute_Array,Field_Read 1c48 ; 1c7a C from color MACRO_Execute_Array,Field_Reference 1c48 ; 1c7c C from color MACRO_Execute_Subarray,Field_Reference 1c48 ; -------------------------------------------------------------------------------------- 1c48 1c48 fiu_mem_start 4 continue; Flow J cc=True 0x1c56 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c56 0x1c56 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1c49 1c49 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4a 1c4a fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1c51 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c51 0x1c51 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c4b 1c4b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c4c 1c4c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4d 1c4d fiu_mem_start 4 continue; Flow C cc=True 0x1c53 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1c53 0x1c53 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1c4e 1c4e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1c4a fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c4a 0x1c4a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c4f 1c4f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=False 0x1c51 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c51 0x1c51 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c50 1c50 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3270 seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c51 ; -------------------------------------------------------------------------------------- 1c51 ; Comes from: 1c51 ; 1c4a C False from color 0x0000 1c51 ; 1c4f C False from color 0x0000 1c51 ; 1c5c C False from color 0x0000 1c51 ; -------------------------------------------------------------------------------------- 1c51 1c51 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c52 1c52 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c53 ; -------------------------------------------------------------------------------------- 1c53 ; Comes from: 1c53 ; 1c4d C True from color 0x0000 1c53 ; -------------------------------------------------------------------------------------- 1c53 1c53 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1c54 1c54 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1c55 1c55 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1c56 1c56 fiu_len_fill_lit 45 zero-fill 0x5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_b_adr 10 TOP 1c57 1c57 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c58 1c58 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1c63 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c63 0x1c63 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_frame 2 1c59 1c59 fiu_fill_mode_src 0 ; Flow J cc=True 0x1c65 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c65 0x1c65 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c5a 1c5a fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1c5f fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c5f 0x1c5f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c5b 1c5b fiu_fill_mode_src 0 ; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c5c 1c5c fiu_mem_start 2 start-rd; Flow C cc=False 0x1c51 ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 1c51 0x1c51 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c5d 1c5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c5e 1c5e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c58 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c58 0x1c58 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 1c5f 1c5f fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c60 1c60 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c5c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1c5c 0x1c5c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c61 1c61 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1c62 1c62 seq_br_type 3 Unconditional Branch; Flow J 0x1c5c seq_branch_adr 1c5c 0x1c5c 1c63 1c63 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c64 1c64 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c5a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c5a 0x1c5a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c65 1c65 fiu_len_fill_lit 1f sign-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c66 1c66 seq_br_type 3 Unconditional Branch; Flow J 0x1c4f seq_branch_adr 1c4f 0x1c4f val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c67 1c67 <halt> ; Flow R 1c68 ; -------------------------------------------------------------------------------------- 1c68 ; 0x01f7 Execute Array,Field_Read 1c68 ; -------------------------------------------------------------------------------------- 1c68 MACRO_Execute_Array,Field_Read: 1c68 1c68 dispatch_brk_class 8 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c68 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c69 1c69 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1c72 fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 1c72 0x1c72 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1c6a 1c6a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1c6c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c6c 0x1c6c seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR 1c6b 1c6b fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1c6e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c6e 0x1c6e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c6c 1c6c fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c6d 1c6d fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c6e 0x1c6e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c6e 1c6e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1c6f 0x1c6f seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c6f 1c6f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c70 ; -------------------------------------------------------------------------------------- 1c70 ; 0x018f Execute Subarray,Field_Read 1c70 ; -------------------------------------------------------------------------------------- 1c70 MACRO_Execute_Subarray,Field_Read: 1c70 1c70 dispatch_brk_class 8 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c70 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c71 1c71 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1c6a fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 1c6a 0x1c6a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1c72 1c72 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c73 1c73 <halt> ; Flow R 1c74 ; -------------------------------------------------------------------------------------- 1c74 ; 0x01f6 Execute Array,Field_Write 1c74 ; -------------------------------------------------------------------------------------- 1c74 MACRO_Execute_Array,Field_Write: 1c74 1c74 dispatch_brk_class 2 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c74 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c75 1c75 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c76 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c76 0x1c76 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c76 1c76 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 2e TOP + 1 1c77 1c77 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x1d46 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d46 0x1d46 seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c78 ; -------------------------------------------------------------------------------------- 1c78 ; 0x018e Execute Subarray,Field_Write 1c78 ; -------------------------------------------------------------------------------------- 1c78 MACRO_Execute_Subarray,Field_Write: 1c78 1c78 dispatch_brk_class 2 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c78 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c79 1c79 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c76 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c76 0x1c76 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c7a ; -------------------------------------------------------------------------------------- 1c7a ; 0x01f5 Execute Array,Field_Reference 1c7a ; -------------------------------------------------------------------------------------- 1c7a MACRO_Execute_Array,Field_Reference: 1c7a 1c7a dispatch_brk_class 8 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c7b 1c7b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c7c ; -------------------------------------------------------------------------------------- 1c7c ; 0x018d Execute Subarray,Field_Reference 1c7c ; -------------------------------------------------------------------------------------- 1c7c MACRO_Execute_Subarray,Field_Reference: 1c7c 1c7c dispatch_brk_class 8 ; Flow C 0x1c48 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c48 0x1c48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c7d 1c7d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1c7e ; -------------------------------------------------------------------------------------- 1c7e ; 0x01f3 Execute Array,Subarray 1c7e ; -------------------------------------------------------------------------------------- 1c7e MACRO_Execute_Array,Subarray: 1c7e 1c7e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c7e fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c7f 1c7f seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR1c:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c80 1c80 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c81 1c81 ioc_tvbs 5 seq+seq; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c82 1c82 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c83 1c83 fiu_mem_start 4 continue typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1c84 1c84 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1c85 1c85 fiu_load_tar 1 hold_tar; Flow C 0x32fc fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1c86 1c86 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1c87 1c87 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1c88 1c88 ioc_fiubs 1 val ; Flow C cc=False 0x1c90 seq_br_type 4 Call False seq_branch_adr 1c90 0x1c90 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1c89 1c89 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c8a 1c8a fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1c83 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c83 0x1c83 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE 1c8b 1c8b ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 18 Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 1c8c 1c8c seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1c8d 1c8d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c8f seq_br_type 1 Branch True seq_branch_adr 1c8f 0x1c8f typ_csa_cntl 3 POP_CSA 1c8e 1c8e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 36 TR11:16 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1c8f 1c8f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 35 TR11:15 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1c90 ; -------------------------------------------------------------------------------------- 1c90 ; Comes from: 1c90 ; 1c88 C False from color MACRO_Execute_Array,Subarray 1c90 ; -------------------------------------------------------------------------------------- 1c90 1c90 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c91 1c91 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c92 ; -------------------------------------------------------------------------------------- 1c92 ; 0xc000-0xc1ff Store llvl,ldelta 1c92 ; -------------------------------------------------------------------------------------- 1c92 MACRO_Store_llvl,ldelta: 1c92 1c92 dispatch_brk_class 2 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1c92 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c93 1c93 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0a 0x1d0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c94 1c94 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0b ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0b 0x1d0b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1c95 1c95 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1c96 1c96 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 1c97 1c97 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1c98 ; -------------------------------------------------------------------------------------- 1c98 ; 0x009b Action Store_Dynamic 1c98 ; -------------------------------------------------------------------------------------- 1c98 MACRO_Action_Store_Dynamic: 1c98 1c98 dispatch_brk_class 2 ; Flow C 0x2c6e dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1c98 seq_br_type 7 Unconditional Call seq_branch_adr 2c6e 0x2c6e typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 1c99 1c99 fiu_mem_start 2 start-rd; Flow J cc=True 0x1c92 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c92 MACRO_Store_llvl,ldelta 1c9a ; -------------------------------------------------------------------------------------- 1c9a ; 0xc200-0xdfff Store llvl,ldelta 1c9a ; -------------------------------------------------------------------------------------- 1c9a MACRO_Store_llvl,ldelta: 1c9a 1c9a dispatch_brk_class 2 ; Flow J cc=True 0x1ca1 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1c9a fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ca1 0x1ca1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1c9b 1c9b fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0a 0x1d0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c9c 1c9c fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0b ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0b 0x1d0b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1c9d 1c9d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d0e seq_br_type 1 Branch True seq_branch_adr 1d0e 0x1d0e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1c9e 1c9e seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 1c9f 1c9f <halt> ; Flow R 1ca0 ; -------------------------------------------------------------------------------------- 1ca0 ; 0xa200-0xbfff Store_Unchecked llvl,ldelta 1ca0 ; -------------------------------------------------------------------------------------- 1ca0 MACRO_Store_Unchecked_llvl,ldelta: 1ca0 1ca0 dispatch_brk_class 2 ; Flow J cc=True 0x1c9b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ca0 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1c9b 0x1c9b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3f TR05:1f typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ca1 1ca1 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0x1c9b fiu_mem_start 7 start_wr_if_true fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1c9b 0x1c9b seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ca2 1ca2 ioc_load_wdr 0 ; Flow J cc=True 0x1ca3 ; Flow J cc=#0x0 0x1ca3 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1ca3 0x1ca3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1ca3 1ca3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca4 1ca4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca5 1ca5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1cab ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cab 0x1cab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ca6 1ca6 seq_br_type 3 Unconditional Branch; Flow J 0x1cab seq_branch_adr 1cab 0x1cab typ_csa_cntl 3 POP_CSA 1ca7 1ca7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1ca8 1ca8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1ca9 1ca9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1caa 1caa fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cab 0x1cab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cab 1cab fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1cac 1cac seq_br_type 3 Unconditional Branch; Flow J 0x1c9b seq_branch_adr 1c9b 0x1c9b typ_b_adr 03 GP03 typ_mar_cntl 1 RESTORE_RDR val_b_adr 03 GP03 1cad 1cad <halt> ; Flow R 1cae ; -------------------------------------------------------------------------------------- 1cae ; 0x0059 Store_Top Discrete,At_Offset_1 1cae ; -------------------------------------------------------------------------------------- 1cae MACRO_Store_Top_Discrete,At_Offset_1: 1cae 1cae dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cae fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1caf 1caf fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 ; 0x005a Store_Top Discrete,At_Offset_2 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 MACRO_Store_Top_Discrete,At_Offset_2: 1cb0 1cb0 dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cb0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cb1 1cb1 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cb2 ; -------------------------------------------------------------------------------------- 1cb2 ; 0x005b Store_Top Discrete,At_Offset_3 1cb2 ; -------------------------------------------------------------------------------------- 1cb2 MACRO_Store_Top_Discrete,At_Offset_3: 1cb2 1cb2 dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cb2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cb3 1cb3 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cb4 ; -------------------------------------------------------------------------------------- 1cb4 ; 0x005c Store_Top Discrete,At_Offset_4 1cb4 ; -------------------------------------------------------------------------------------- 1cb4 MACRO_Store_Top_Discrete,At_Offset_4: 1cb4 1cb4 dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cb4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cb5 1cb5 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cb6 ; -------------------------------------------------------------------------------------- 1cb6 ; 0x005d Store_Top Discrete,At_Offset_5 1cb6 ; -------------------------------------------------------------------------------------- 1cb6 MACRO_Store_Top_Discrete,At_Offset_5: 1cb6 1cb6 dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cb6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cb7 1cb7 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cb8 ; -------------------------------------------------------------------------------------- 1cb8 ; 0x005e Store_Top Discrete,At_Offset_6 1cb8 ; -------------------------------------------------------------------------------------- 1cb8 MACRO_Store_Top_Discrete,At_Offset_6: 1cb8 1cb8 dispatch_brk_class 2 ; Flow C 0x1cdd dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cb8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1cdd 0x1cdd seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cb9 1cb9 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1cba ; -------------------------------------------------------------------------------------- 1cba ; 0x0051 Store_Top_Unchecked Discrete,At_Offset_1 1cba ; -------------------------------------------------------------------------------------- 1cba MACRO_Store_Top_Unchecked_Discrete,At_Offset_1: 1cba 1cba dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cba fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cbb 1cbb <halt> ; Flow R 1cbc ; -------------------------------------------------------------------------------------- 1cbc ; 0x0052 Store_Top_Unchecked Discrete,At_Offset_2 1cbc ; -------------------------------------------------------------------------------------- 1cbc MACRO_Store_Top_Unchecked_Discrete,At_Offset_2: 1cbc 1cbc dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cbd 1cbd <halt> ; Flow R 1cbe ; -------------------------------------------------------------------------------------- 1cbe ; 0x0053 Store_Top_Unchecked Discrete,At_Offset_3 1cbe ; -------------------------------------------------------------------------------------- 1cbe MACRO_Store_Top_Unchecked_Discrete,At_Offset_3: 1cbe 1cbe dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cbf 1cbf <halt> ; Flow R 1cc0 ; -------------------------------------------------------------------------------------- 1cc0 ; 0x0054 Store_Top_Unchecked Discrete,At_Offset_4 1cc0 ; -------------------------------------------------------------------------------------- 1cc0 MACRO_Store_Top_Unchecked_Discrete,At_Offset_4: 1cc0 1cc0 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cc1 1cc1 <halt> ; Flow R 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 ; 0x0055 Store_Top_Unchecked Discrete,At_Offset_5 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 MACRO_Store_Top_Unchecked_Discrete,At_Offset_5: 1cc2 1cc2 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cc3 1cc3 <halt> ; Flow R 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 ; 0x0056 Store_Top_Unchecked Discrete,At_Offset_6 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 MACRO_Store_Top_Unchecked_Discrete,At_Offset_6: 1cc4 1cc4 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cc4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cc5 1cc5 <halt> ; Flow R 1cc6 ; -------------------------------------------------------------------------------------- 1cc6 ; 0x0049 Store_Top Float,At_Offset_1 1cc6 ; -------------------------------------------------------------------------------------- 1cc6 MACRO_Store_Top_Float,At_Offset_1: 1cc6 1cc6 dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cc6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cc7 1cc7 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cc8 ; -------------------------------------------------------------------------------------- 1cc8 ; 0x004a Store_Top Float,At_Offset_2 1cc8 ; -------------------------------------------------------------------------------------- 1cc8 MACRO_Store_Top_Float,At_Offset_2: 1cc8 1cc8 dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cc8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cc9 1cc9 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cca ; -------------------------------------------------------------------------------------- 1cca ; 0x004b Store_Top Float,At_Offset_3 1cca ; -------------------------------------------------------------------------------------- 1cca MACRO_Store_Top_Float,At_Offset_3: 1cca 1cca dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cca fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1ccb 1ccb fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1ccc ; -------------------------------------------------------------------------------------- 1ccc ; 0x004c Store_Top Float,At_Offset_4 1ccc ; -------------------------------------------------------------------------------------- 1ccc MACRO_Store_Top_Float,At_Offset_4: 1ccc 1ccc dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1ccc fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1ccd 1ccd fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cce ; -------------------------------------------------------------------------------------- 1cce ; 0x004d Store_Top Float,At_Offset_5 1cce ; -------------------------------------------------------------------------------------- 1cce MACRO_Store_Top_Float,At_Offset_5: 1cce 1cce dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cce fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1ccf 1ccf fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cd0 ; -------------------------------------------------------------------------------------- 1cd0 ; 0x004e Store_Top Float,At_Offset_6 1cd0 ; -------------------------------------------------------------------------------------- 1cd0 MACRO_Store_Top_Float,At_Offset_6: 1cd0 1cd0 dispatch_brk_class 2 ; Flow C 0x1ce0 dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cd0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1ce0 0x1ce0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cd1 1cd1 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 ; 0x0041 Store_Top_Unchecked Float,At_Offset_1 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 MACRO_Store_Top_Unchecked_Float,At_Offset_1: 1cd2 1cd2 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cd2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cd3 1cd3 <halt> ; Flow R 1cd4 ; -------------------------------------------------------------------------------------- 1cd4 ; 0x0042 Store_Top_Unchecked Float,At_Offset_2 1cd4 ; -------------------------------------------------------------------------------------- 1cd4 MACRO_Store_Top_Unchecked_Float,At_Offset_2: 1cd4 1cd4 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cd4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cd5 1cd5 <halt> ; Flow R 1cd6 ; -------------------------------------------------------------------------------------- 1cd6 ; 0x0043 Store_Top_Unchecked Float,At_Offset_3 1cd6 ; -------------------------------------------------------------------------------------- 1cd6 MACRO_Store_Top_Unchecked_Float,At_Offset_3: 1cd6 1cd6 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cd6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cd7 1cd7 <halt> ; Flow R 1cd8 ; -------------------------------------------------------------------------------------- 1cd8 ; 0x0044 Store_Top_Unchecked Float,At_Offset_4 1cd8 ; -------------------------------------------------------------------------------------- 1cd8 MACRO_Store_Top_Unchecked_Float,At_Offset_4: 1cd8 1cd8 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cd8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cd9 1cd9 <halt> ; Flow R 1cda ; -------------------------------------------------------------------------------------- 1cda ; 0x0045 Store_Top_Unchecked Float,At_Offset_5 1cda ; -------------------------------------------------------------------------------------- 1cda MACRO_Store_Top_Unchecked_Float,At_Offset_5: 1cda 1cda dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cda fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cdb 1cdb <halt> ; Flow R 1cdc ; -------------------------------------------------------------------------------------- 1cdc ; 0x0046 Store_Top_Unchecked Float,At_Offset_6 1cdc ; -------------------------------------------------------------------------------------- 1cdc MACRO_Store_Top_Unchecked_Float,At_Offset_6: 1cdc 1cdc dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cdc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cdd ; -------------------------------------------------------------------------------------- 1cdd ; Comes from: 1cdd ; 1cae C from color 0x0000 1cdd ; 1cb0 C from color 0x0000 1cdd ; 1cb2 C from color 0x0000 1cdd ; 1cb4 C from color 0x0000 1cdd ; 1cb6 C from color 0x0000 1cdd ; 1cb8 C from color 0x0000 1cdd ; -------------------------------------------------------------------------------------- 1cdd 1cdd ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP 1cde 1cde fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1cdf 0x1cdf seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1cdf 1cdf seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 1ce0 ; -------------------------------------------------------------------------------------- 1ce0 ; Comes from: 1ce0 ; 1cc6 C from color 0x0000 1ce0 ; 1cc8 C from color 0x0000 1ce0 ; 1cca C from color 0x0000 1ce0 ; 1ccc C from color 0x0000 1ce0 ; 1cce C from color 0x0000 1ce0 ; 1cd0 C from color 0x0000 1ce0 ; -------------------------------------------------------------------------------------- 1ce0 1ce0 ioc_fiubs 1 val ; Flow J cc=False 0x1cde seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1cde 0x1cde seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ce1 1ce1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1cdf seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1cdf 0x1cdf seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 1ce2 1ce2 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1cdf ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1cdf 0x1cdf seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1ce3 1ce3 <halt> ; Flow R 1ce4 ; -------------------------------------------------------------------------------------- 1ce4 ; 0x0039 Store_Top Access,At_Offset_1 1ce4 ; -------------------------------------------------------------------------------------- 1ce4 MACRO_Store_Top_Access,At_Offset_1: 1ce4 1ce4 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ce4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ce5 0x1ce5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1ce5 1ce5 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 ; 0x003a Store_Top Access,At_Offset_2 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 MACRO_Store_Top_Access,At_Offset_2: 1ce6 1ce6 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1ce6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ce7 0x1ce7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1ce7 1ce7 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 ; 0x003b Store_Top Access,At_Offset_3 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 MACRO_Store_Top_Access,At_Offset_3: 1ce8 1ce8 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1ce8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ce9 0x1ce9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1ce9 1ce9 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cea ; -------------------------------------------------------------------------------------- 1cea ; 0x003c Store_Top Access,At_Offset_4 1cea ; -------------------------------------------------------------------------------------- 1cea MACRO_Store_Top_Access,At_Offset_4: 1cea 1cea dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cea fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ceb 0x1ceb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1ceb 1ceb fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cec ; -------------------------------------------------------------------------------------- 1cec ; 0x003d Store_Top Access,At_Offset_5 1cec ; -------------------------------------------------------------------------------------- 1cec MACRO_Store_Top_Access,At_Offset_5: 1cec 1cec dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cec fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1ced 0x1ced seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1ced 1ced fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cee ; -------------------------------------------------------------------------------------- 1cee ; 0x003e Store_Top Access,At_Offset_6 1cee ; -------------------------------------------------------------------------------------- 1cee MACRO_Store_Top_Access,At_Offset_6: 1cee 1cee dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cee fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cef 0x1cef seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cef 1cef fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 ; 0x0031 Store_Top Heap_Access,At_Offset_1 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 MACRO_Store_Top_Heap_Access,At_Offset_1: 1cf0 1cf0 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cf0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf1 0x1cf1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cf1 1cf1 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 ; 0x0032 Store_Top Heap_Access,At_Offset_2 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 MACRO_Store_Top_Heap_Access,At_Offset_2: 1cf2 1cf2 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cf2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf3 0x1cf3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cf3 1cf3 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 ; 0x0033 Store_Top Heap_Access,At_Offset_3 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 MACRO_Store_Top_Heap_Access,At_Offset_3: 1cf4 1cf4 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cf4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf5 0x1cf5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cf5 1cf5 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 ; 0x0034 Store_Top Heap_Access,At_Offset_4 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 MACRO_Store_Top_Heap_Access,At_Offset_4: 1cf6 1cf6 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cf6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf7 0x1cf7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cf7 1cf7 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 ; 0x0035 Store_Top Heap_Access,At_Offset_5 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 MACRO_Store_Top_Heap_Access,At_Offset_5: 1cf8 1cf8 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cf8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cf9 0x1cf9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cf9 1cf9 fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1cfa ; -------------------------------------------------------------------------------------- 1cfa ; 0x0036 Store_Top Heap_Access,At_Offset_6 1cfa ; -------------------------------------------------------------------------------------- 1cfa MACRO_Store_Top_Heap_Access,At_Offset_6: 1cfa 1cfa dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cfa fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1cfb 0x1cfb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cfb 1cfb fiu_mem_start 2 start-rd; Flow J 0x1c9a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1c9a MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cfc ; -------------------------------------------------------------------------------------- 1cfc ; 0x1a00-0x1aff Execute Package,Field_Write,fieldnum 1cfc ; -------------------------------------------------------------------------------------- 1cfc MACRO_Execute_Package,Field_Write,fieldnum: 1cfc 1cfc dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 1cfc dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1cfd 1cfd ioc_random 17 force type bus receivers; Flow J cc=False 0x1cff ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1cff 0x1cff seq_cond_sel 79 IOC.PFR seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1cfe 1cfe fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x1d0a fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d0a 0x1d0a typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 1cff 1cff seq_br_type 0 Branch False; Flow J cc=False 0x1d08 seq_branch_adr 1d08 0x1d08 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 03 GP03 1d00 1d00 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0a 0x1d0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 1d01 1d01 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d0b ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d0b 0x1d0b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d02 1d02 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 1d03 1d03 <halt> ; Flow R 1d04 ; -------------------------------------------------------------------------------------- 1d04 ; 0x0097 Execute Package,Field_Write_Dynamic 1d04 ; -------------------------------------------------------------------------------------- 1d04 MACRO_Execute_Package,Field_Write_Dynamic: 1d04 1d04 dispatch_brk_class 2 ; Flow C cc=True 0x32a5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d04 fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 1d05 1d05 fiu_mem_start 2 start-rd; Flow C cc=True 0x32ac ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 1d06 1d06 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d07 1d07 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x1d00 seq_br_type 3 Unconditional Branch seq_branch_adr 1d00 0x1d00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d08 1d08 fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32a8 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1d09 1d09 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 1d0a 1d0a ioc_fiubs 1 val ; Flow J cc=True 0x1d0b ; Flow J cc=#0x0 0x1d26 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d26 0x1d26 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d0b 1d0b val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d0c 1d0c fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x1d0a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d0a 0x1d0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d0d 1d0d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d0e 1d0e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d14 seq_br_type 1 Branch True seq_branch_adr 1d14 0x1d14 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 1d0f 1d0f fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1d12 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 1d12 0x1d12 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d10 1d10 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 1d11 1d11 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d12 1d12 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d10 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d10 0x1d10 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d13 1d13 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 1d14 1d14 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1d10 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d10 0x1d10 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 1d15 1d15 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d10 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d10 0x1d10 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1d16 1d16 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1d10 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1d10 0x1d10 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d17 1d17 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1d1a fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 71 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d1a 0x1d1a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 1d18 1d18 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d24 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d24 0x1d24 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 1d19 1d19 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 1d1a 1d1a fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d1b 1d1b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1d1c 1d1c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP val_b_adr 01 GP01 1d1d 1d1d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d1e 1d1e ioc_load_wdr 0 ; Flow J 0x1d11 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d11 0x1d11 val_b_adr 10 TOP 1d1f 1d1f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1d20 1d20 ioc_load_wdr 0 ; Flow J cc=True 0x1d25 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d25 0x1d25 val_b_adr 06 GP06 1d21 1d21 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1d24 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d24 0x1d24 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1d22 1d22 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1d23 1d23 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1d24 1d24 seq_br_type 3 Unconditional Branch; Flow J 0x1d1f seq_branch_adr 1d1f 0x1d1f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d25 1d25 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1d1d fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d1d 0x1d1d typ_a_adr 10 TOP 1d26 1d26 fiu_mem_start 3 start-wr; Flow J 0x1d5a ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d5a 0x1d5a typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d27 1d27 fiu_mem_start 2 start-rd; Flow J 0x1d61 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d61 0x1d61 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d28 1d28 fiu_mem_start 3 start-wr; Flow J 0x1d6e ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d6e 0x1d6e typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d29 1d29 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1d75 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d75 0x1d75 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d2a 1d2a fiu_mem_start 7 start_wr_if_true; Flow J 0x1d86 ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1d86 0x1d86 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d2b 1d2b fiu_mem_start 2 start-rd; Flow J 0x1d91 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d91 0x1d91 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d2c 1d2c seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1d2d 1d2d seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1d2e 1d2e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d2f 1d2f seq_br_type 7 Unconditional Call; Flow C 0x326a seq_branch_adr 326a 0x326a 1d30 1d30 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d31 1d31 seq_br_type 7 Unconditional Call; Flow C 0x326a seq_branch_adr 326a 0x326a 1d32 1d32 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d33 1d33 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d34 1d34 fiu_mem_start 7 start_wr_if_true; Flow J 0x1d8b ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1d8b 0x1d8b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d35 1d35 fiu_mem_start 2 start-rd; Flow J 0x1d9c ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d9c 0x1d9c typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d36 1d36 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d37 1d37 fiu_mem_start 2 start-rd; Flow J 0x1db0 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1db0 0x1db0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d38 1d38 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d39 1d39 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db7 0x1db7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d3a 1d3a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3b 1d3b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3c 1d3c seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1d3d 1d3d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3e 1d3e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d3f 1d3f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d40 1d40 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d41 1d41 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de8 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de8 0x1de8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d42 1d42 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d43 1d43 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0c 0x1e0c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d44 1d44 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d45 1d45 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e48 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e48 0x1e48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d46 1d46 ioc_fiubs 1 val ; Flow J cc=True 0x1d47 ; Flow J cc=#0x0 0x1d47 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d47 0x1d47 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d47 1d47 fiu_load_oreg 1 hold_oreg; Flow J 0x1d63 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d63 0x1d63 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d48 1d48 fiu_load_oreg 1 hold_oreg; Flow J 0x1d75 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d75 0x1d75 typ_a_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d49 1d49 fiu_load_oreg 1 hold_oreg; Flow J 0x1d95 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1d95 0x1d95 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d4a 1d4a seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1d4b 1d4b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d4c 1d4c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d4d 1d4d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d4e 1d4e fiu_load_oreg 1 hold_oreg; Flow J 0x1d9e fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d9e 0x1d9e seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1d4f 1d4f fiu_mem_start 2 start-rd; Flow J 0x1db0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1db0 0x1db0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d50 1d50 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1db7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1db7 0x1db7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d51 1d51 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d52 1d52 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d53 1d53 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d54 1d54 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de8 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de8 0x1de8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d55 1d55 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e0c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e0c 0x1e0c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d56 1d56 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e48 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e48 0x1e48 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d57 ; -------------------------------------------------------------------------------------- 1d57 ; Comes from: 1d57 ; 1db4 C False from color 0x1d37 1d57 ; 1e0d C False from color MACRO_Execute_Matrix,Structure_Write 1d57 ; 1e21 C False from color MACRO_Execute_Matrix,Structure_Write 1d57 ; -------------------------------------------------------------------------------------- 1d57 1d57 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1d58 0x1d58 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1d58 1d58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 1d59 1d59 ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 1d5a 1d5a ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_c_adr 3b GP04 1d5b 1d5b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d5c 0x1d5c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d5c 1d5c fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1d5d 1d5d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d5e 1d5e fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1d5f 1d5f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326c seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1d60 1d60 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 1d61 1d61 ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d62 1d62 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d63 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d63 0x1d63 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d63 1d63 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d66 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d66 0x1d66 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 1d64 1d64 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d65 1d65 ioc_load_wdr 0 ; Flow J 0x1d6a ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d6a 0x1d6a seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1d66 1d66 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1d67 1d67 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1d68 1d68 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1d69 1d69 ioc_load_wdr 0 ; Flow J 0x1d6a ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d6a 0x1d6a typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d6a 1d6a fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d6b 0x1d6b seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d6b 1d6b fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d6c 1d6c fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1d5d ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1d5d 0x1d5d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1d6d 1d6d ioc_load_wdr 0 ; Flow J 0x1d5d seq_br_type 3 Unconditional Branch seq_branch_adr 1d5d 0x1d5d typ_b_adr 05 GP05 val_b_adr 05 GP05 1d6e 1d6e ioc_load_wdr 0 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_c_adr 3b GP04 1d6f 1d6f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d71 seq_br_type 1 Branch True seq_branch_adr 1d71 0x1d71 typ_csa_cntl 3 POP_CSA 1d70 1d70 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d73 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d73 0x1d73 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d71 1d71 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d73 seq_br_type 1 Branch True seq_branch_adr 1d73 0x1d73 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 1d72 1d72 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d73 0x1d73 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d73 1d73 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1d74 1d74 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c 1d75 1d75 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d7b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d7b 0x1d7b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_c_adr 3b GP04 1d76 1d76 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d77 1d77 ioc_load_wdr 0 ; Flow J cc=True 0x1d79 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d79 0x1d79 seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1d78 1d78 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d82 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d82 0x1d82 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d79 1d79 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d82 seq_br_type 1 Branch True seq_branch_adr 1d82 0x1d82 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA 1d7a 1d7a fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1d82 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d82 0x1d82 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d7b 1d7b fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_c_adr 3b GP04 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1d7c 1d7c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1d7d 1d7d fiu_mem_start 4 continue; Flow J cc=True 0x1d80 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d80 0x1d80 seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1d7e 1d7e ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d7f 1d7f fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1d82 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d82 0x1d82 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d80 1d80 ioc_load_wdr 0 ; Flow J cc=True 0x1d82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d82 0x1d82 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d81 1d81 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1d82 0x1d82 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1d82 1d82 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d83 1d83 fiu_mem_start a start_continue_if_false ioc_load_wdr 0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1d84 1d84 ioc_load_wdr 0 ; Flow C cc=True 0x326c seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 05 GP05 val_b_adr 05 GP05 1d85 1d85 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c 1d86 1d86 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d8a seq_br_type 1 Branch True seq_branch_adr 1d8a 0x1d8a seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d87 1d87 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d88 1d88 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1d8e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d8e 0x1d8e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d89 1d89 ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1d8a 1d8a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d8b 1d8b seq_b_timing 1 Latch Condition; Flow J cc=True 0x1d8a seq_br_type 1 Branch True seq_branch_adr 1d8a 0x1d8a seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d8c 1d8c seq_br_type 7 Unconditional Call; Flow C 0x2492 seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d8d 1d8d fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1d89 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d89 0x1d89 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d8e 1d8e fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1d8f 1d8f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1d90 1d90 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1d91 1d91 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1d92 1d92 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d95 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d95 0x1d95 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d93 1d93 fiu_load_tar 1 hold_tar; Flow C 0x2488 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2488 0x2488 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1d94 1d94 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1d8e fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d8e 0x1d8e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d95 1d95 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d99 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d99 0x1d99 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1d96 1d96 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d93 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d93 0x1d93 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d97 1d97 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 1d98 1d98 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d99 1d99 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1d9a 1d9a fiu_fill_mode_src 0 ; Flow J cc=False 0x1d93 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d93 0x1d93 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1d9b 1d9b fiu_load_var 1 hold_var; Flow J 0x1d97 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d97 0x1d97 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1d9c 1d9c fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1d9d 1d9d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d9e fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d9e 0x1d9e seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d9e 1d9e fiu_fill_mode_src 0 ; Flow J cc=False 0x1da1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1da1 0x1da1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 1d9f 1d9f fiu_fill_mode_src 0 ; Flow C cc=True 0x1dac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dac 0x1dac typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1da0 1da0 ioc_load_wdr 0 ; Flow J 0x1da5 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1da5 0x1da5 seq_random 02 ? typ_c_adr 3b GP04 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 1da1 1da1 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1da2 1da2 fiu_fill_mode_src 0 ; Flow C cc=True 0x1dac fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dac 0x1dac typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 1da3 1da3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1da4 1da4 ioc_load_wdr 0 ; Flow J 0x1da5 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1da5 0x1da5 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1da5 1da5 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1da6 0x1da6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1da6 1da6 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1da7 1da7 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1da9 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1da9 0x1da9 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 1da8 1da8 ioc_load_wdr 0 ; Flow J 0x1da9 seq_br_type 3 Unconditional Branch seq_branch_adr 1da9 0x1da9 typ_b_adr 05 GP05 val_b_adr 05 GP05 1da9 1da9 fiu_load_tar 1 hold_tar; Flow C 0x2492 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 2492 0x2492 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1daa 1daa fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1d8e ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1d8e 0x1d8e typ_b_adr 1f TOP - 1 1dab 1dab fiu_load_oreg 1 hold_oreg; Flow J 0x1d9e fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d9e 0x1d9e seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1dac ; -------------------------------------------------------------------------------------- 1dac ; Comes from: 1dac ; 1d9f C True from color 0x1d28 1dac ; 1da2 C True from color 0x1d28 1dac ; -------------------------------------------------------------------------------------- 1dac 1dac fiu_tivi_src c mar_0xc; Flow C cc=False 0x32af ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1dad 1dad fiu_fill_mode_src 0 ; Flow J cc=False 0x1daf fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1daf 0x1daf seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1dae 1dae fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1daf 1daf fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1db0 1db0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1db4 seq_br_type 1 Branch True seq_branch_adr 1db4 0x1db4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1db1 1db1 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1db2 1db2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1db3 1db3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1db4 1db4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1db5 1db5 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1eec seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1db6 1db6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1db7 1db7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dba seq_br_type 1 Branch True seq_branch_adr 1dba 0x1dba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 39 GP06 1db8 1db8 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1db9 1db9 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dba 1dba fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1dbb 1dbb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1dc4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc4 0x1dc4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_c_adr 38 GP07 1dbc 1dbc ioc_tvbs 2 fiu+val; Flow J cc=True 0x1dc1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dc1 0x1dc1 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dbd 1dbd seq_br_type 7 Unconditional Call; Flow C 0x26fa seq_branch_adr 26fa 0x26fa typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1dbe 1dbe ioc_fiubs 1 val ; Flow C cc=True 0x3272 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3272 0x3272 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1dbf 1dbf seq_br_type 7 Unconditional Call; Flow C 0x2456 seq_branch_adr 2456 0x2456 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1dc0 1dc0 ioc_fiubs 1 val ; Flow J 0x1dc4 seq_br_type 3 Unconditional Branch seq_branch_adr 1dc4 0x1dc4 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1dc1 1dc1 fiu_load_oreg 1 hold_oreg; Flow C 0x24e3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 24e3 0x24e3 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dc2 1dc2 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1dc5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dc5 0x1dc5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1dc3 1dc3 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 1dc4 1dc4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1dc5 1dc5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dd1 seq_br_type 1 Branch True seq_branch_adr 1dd1 0x1dd1 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1dc6 1dc6 fiu_fill_mode_src 0 ; Flow J cc=True 0x1dd3 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dd3 0x1dd3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1dc7 1dc7 ioc_fiubs 1 val ; Flow J cc=False 0x1dce seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dce 0x1dce seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1dc8 1dc8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dc9 1dc9 seq_b_timing 0 Early Condition; Flow J cc=True 0x1dce seq_br_type 1 Branch True seq_branch_adr 1dce 0x1dce seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1dca 1dca fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dcb 1dcb ioc_fiubs 1 val ; Flow J cc=True 0x1dce seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1dce 0x1dce seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1dcc 1dcc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1dce seq_br_type 1 Branch True seq_branch_adr 1dce 0x1dce seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 03 GP03 1dcd 1dcd seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1dce 1dce typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1dcf 1dcf seq_br_type 7 Unconditional Call; Flow C 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_csa_cntl 3 POP_CSA typ_frame 5 1dd0 1dd0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dd1 1dd1 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1dd2 1dd2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dd3 1dd3 ioc_fiubs 1 val ; Flow J cc=False 0x1ddd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ddd 0x1ddd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1dd4 1dd4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dd5 1dd5 seq_b_timing 0 Early Condition; Flow J cc=True 0x1dda seq_br_type 1 Branch True seq_branch_adr 1dda 0x1dda seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1dd6 1dd6 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dd7 1dd7 ioc_fiubs 1 val ; Flow J cc=False 0x1dcc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1dcc 0x1dcc seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 1dd8 1dd8 seq_br_type 1 Branch True; Flow J cc=True 0x1dce seq_branch_adr 1dce 0x1dce seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1dd9 1dd9 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1dda 1dda ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1ddf seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ddf 0x1ddf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 1ddb 1ddb seq_b_timing 1 Latch Condition; Flow J cc=True 0x1ddf seq_br_type 1 Branch True seq_branch_adr 1ddf 0x1ddf 1ddc 1ddc seq_br_type 3 Unconditional Branch; Flow J 0x1dcf seq_branch_adr 1dcf 0x1dcf typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1ddd 1ddd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dde 1dde seq_b_timing 0 Early Condition; Flow J cc=True 0x1de2 seq_br_type 1 Branch True seq_branch_adr 1de2 0x1de2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1ddf 1ddf fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de0 1de0 seq_br_type 1 Branch True; Flow J cc=True 0x1dce seq_branch_adr 1dce 0x1dce seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de1 1de1 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1de2 1de2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1de5 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1de5 0x1de5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1de3 1de3 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de4 1de4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de5 1de5 seq_br_type 7 Unconditional Call; Flow C 0x2456 seq_branch_adr 2456 0x2456 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1de6 1de6 seq_br_type 1 Branch True; Flow J cc=True 0x1dce seq_branch_adr 1dce 0x1dce seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1de7 1de7 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1de8 1de8 ioc_fiubs 0 fiu ; Flow J cc=True 0x1e00 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e00 0x1e00 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1de9 1de9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1dea 1dea ioc_tvbs 2 fiu+val; Flow C cc=False 0x1eec seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_csa_cntl 3 POP_CSA typ_frame 5 1deb 1deb fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1dec 0x1dec seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dec 1dec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 03 GP03 1ded 1ded fiu_mem_start 2 start-rd; Flow J cc=True 0x1df1 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df1 0x1df1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dee 1dee fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1dfd seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dfd 0x1dfd typ_mar_cntl 6 INCREMENT_MAR 1def 1def <default> 1df0 1df0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1dfb fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dfb 0x1dfb typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1df1 1df1 fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1df2 1df2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1df3 1df3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1df4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1df4 0x1df4 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1df4 1df4 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1df9 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1df9 0x1df9 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1df5 1df5 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dfb fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1dfb 0x1dfb seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1df6 1df6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1df7 1df7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1eec seq_br_type 4 Call False seq_branch_adr 1eec 0x1eec seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1df8 1df8 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3271 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3271 0x3271 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1df9 1df9 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1dfa 1dfa fiu_fill_mode_src 0 ; Flow J cc=True 0x1df6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1df6 0x1df6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1dfb 1dfb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3271 seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 1dfc 1dfc fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dfd 1dfd seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1dfe 1dfe seq_br_type 5 Call True; Flow C cc=True 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1dff 1dff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e00 1e00 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e01 1e01 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1df4 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1df4 0x1df4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e02 1e02 fiu_fill_mode_src 0 ; Flow J cc=True 0x1e06 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e06 0x1e06 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1e03 1e03 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 38 GP07 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1e04 1e04 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e05 1e05 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e06 1e06 ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 38 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1e07 1e07 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1e08 1e08 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1df4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df4 0x1df4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e09 1e09 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e0b seq_br_type 1 Branch True seq_branch_adr 1e0b 0x1e0b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e0a 1e0a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e0b 1e0b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1df4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1df4 0x1df4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 1e0c 1e0c ioc_fiubs 0 fiu ; Flow J cc=True 0x1e21 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e21 0x1e21 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1e0d 1e0d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e0e 1e0e fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1e16 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e16 0x1e16 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1e0f 1e0f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e18 seq_br_type 1 Branch True seq_branch_adr 1e18 0x1e18 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 1e10 1e10 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1e13 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1e13 0x1e13 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1e11 1e11 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e12 1e12 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e3f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3f 0x1e3f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e13 1e13 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e14 1e14 seq_br_type 5 Call True; Flow C cc=True 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e15 1e15 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e16 1e16 ioc_tvbs 2 fiu+val; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1e17 1e17 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e18 1e18 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e19 1e19 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e1c seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e1c 0x1e1c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e1a 1e1a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e1b 1e1b fiu_fill_mode_src 0 ; Flow J 0x1e1d fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e1d 0x1e1d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e1c 1e1c fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e1d 1e1d fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e20 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e20 0x1e20 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e1e 1e1e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e1f 1e1f fiu_fill_mode_src 0 ; Flow J 0x1e3f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3f 0x1e3f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e20 1e20 fiu_fill_mode_src 0 ; Flow J 0x1e3f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3f 0x1e3f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e21 1e21 fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d57 fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 1e22 1e22 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e23 1e23 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e26 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e26 0x1e26 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e24 1e24 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e25 1e25 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e27 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e27 0x1e27 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e26 1e26 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e27 1e27 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e2a seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e2a 0x1e2a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e28 1e28 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e29 1e29 fiu_fill_mode_src 0 ; Flow J 0x1e2b fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e2b 0x1e2b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e2a 1e2a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e2b 1e2b fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e2f seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e2f 0x1e2f typ_mar_cntl 6 INCREMENT_MAR 1e2c 1e2c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e2d 1e2d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e2e 1e2e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e3f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3f 0x1e3f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e2f 1e2f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e30 1e30 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e3a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e3a 0x1e3a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e31 1e31 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e32 1e32 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e33 1e33 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e3d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e3d 0x1e3d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e34 1e34 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e35 1e35 ioc_fiubs 1 val ; Flow J cc=True 0x1e39 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e39 0x1e39 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e36 1e36 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e38 seq_br_type 1 Branch True seq_branch_adr 1e38 0x1e38 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e37 1e37 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e38 1e38 ioc_fiubs 1 val ; Flow J 0x1e3f seq_br_type 3 Unconditional Branch seq_branch_adr 1e3f 0x1e3f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e39 1e39 seq_br_type 3 Unconditional Branch; Flow J 0x1e3f seq_branch_adr 1e3f 0x1e3f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 1e3a 1e3a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e3b 1e3b fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e3c 1e3c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e33 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e33 0x1e33 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e3d 1e3d fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e3e 1e3e fiu_fill_mode_src 0 ; Flow J 0x1e35 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e35 0x1e35 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e3f 1e3f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e44 seq_br_type 1 Branch True seq_branch_adr 1e44 0x1e44 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1e40 1e40 fiu_mem_start 2 start-rd; Flow C cc=False 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e41 1e41 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e42 1e42 seq_br_type 5 Call True; Flow C cc=True 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e43 1e43 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e44 1e44 fiu_mem_start 2 start-rd; Flow C cc=False 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e45 1e45 seq_br_type 4 Call False; Flow C cc=False 0x3271 seq_branch_adr 3271 0x3271 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 0 PASS_A 1e46 1e46 seq_br_type 4 Call False; Flow C cc=False 0x3271 seq_branch_adr 3271 0x3271 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A 1e47 1e47 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e48 1e48 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e5b seq_br_type 1 Branch True seq_branch_adr 1e5b 0x1e5b seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e49 1e49 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d57 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e4a 1e4a fiu_mem_start 2 start-rd; Flow J cc=False 0x1e77 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e77 0x1e77 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 1e4b 1e4b seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e53 seq_br_type 1 Branch True seq_branch_adr 1e53 0x1e53 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1e4c 1e4c fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1e79 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1e79 0x1e79 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e4d 1e4d seq_br_type 7 Unconditional Call; Flow C 0x22ac seq_branch_adr 22ac 0x22ac typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e4e 1e4e seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e77 seq_br_type 1 Branch True seq_branch_adr 1e77 0x1e77 1e4f 1e4f ioc_fiubs 2 typ ; Flow C 0x2254 seq_br_type 7 Unconditional Call seq_branch_adr 2254 0x2254 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e50 1e50 ioc_fiubs 2 typ ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e51 1e51 seq_br_type 7 Unconditional Call; Flow C 0x2254 seq_branch_adr 2254 0x2254 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e52 1e52 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3271 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e53 1e53 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1e79 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1e79 0x1e79 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e54 1e54 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e55 1e55 seq_br_type 7 Unconditional Call; Flow C 0x22a8 seq_branch_adr 22a8 0x22a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e56 1e56 ioc_fiubs 1 val ; Flow J cc=True 0x1e77 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e77 0x1e77 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e57 1e57 ioc_fiubs 2 typ ; Flow C 0x225c seq_br_type 7 Unconditional Call seq_branch_adr 225c 0x225c typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e58 1e58 ioc_fiubs 2 typ ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e59 1e59 seq_br_type 7 Unconditional Call; Flow C 0x2254 seq_branch_adr 2254 0x2254 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e5a 1e5a fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3271 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e5b 1e5b fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d57 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d57 0x1d57 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 03 GP03 1e5c 1e5c fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e5d 1e5d fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e5e 1e5e val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e5f 1e5f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1e68 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e68 0x1e68 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e60 1e60 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1e61 1e61 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1e79 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1e79 0x1e79 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e62 1e62 seq_br_type 7 Unconditional Call; Flow C 0x22b2 seq_branch_adr 22b2 0x22b2 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e63 1e63 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e77 seq_br_type 1 Branch True seq_branch_adr 1e77 0x1e77 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1e64 1e64 ioc_fiubs 2 typ ; Flow C 0x2254 seq_br_type 7 Unconditional Call seq_branch_adr 2254 0x2254 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e65 1e65 ioc_fiubs 1 val ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1e66 1e66 ioc_fiubs 2 typ ; Flow C 0x225c seq_br_type 7 Unconditional Call seq_branch_adr 225c 0x225c seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e67 1e67 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3271 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e68 1e68 ioc_fiubs 1 val ; Flow C 0x22ba seq_br_type 7 Unconditional Call seq_branch_adr 22ba 0x22ba typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e69 1e69 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1e7b fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e7b 0x1e7b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 1f TOP - 1 1e6a 1e6a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e6b 1e6b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e70 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e70 0x1e70 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e6c 1e6c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e6d 1e6d fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1e6e 1e6e seq_br_type 4 Call False; Flow C cc=False 0x1e73 seq_branch_adr 1e73 0x1e73 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e6f 1e6f ioc_fiubs 1 val ; Flow J 0x1e77 seq_br_type 3 Unconditional Branch seq_branch_adr 1e77 0x1e77 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 1e70 1e70 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e71 1e71 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e72 1e72 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e6e fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e6e 0x1e6e val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1e73 1e73 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1e74 1e74 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e75 1e75 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e76 1e76 ioc_fiubs 1 val ; Flow J 0x1e77 seq_br_type 3 Unconditional Branch seq_branch_adr 1e77 0x1e77 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1e77 1e77 ioc_tvbs 2 fiu+val; Flow C 0x1eec seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1e78 1e78 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e79 ; -------------------------------------------------------------------------------------- 1e79 ; Comes from: 1e79 ; 1e4c C False from color 0x0000 1e79 ; 1e53 C False from color 0x0000 1e79 ; 1e61 C False from color 0x0000 1e79 ; -------------------------------------------------------------------------------------- 1e79 1e79 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e7a 1e7a seq_br_type a Unconditional Return; Flow R 1e7b 1e7b ioc_fiubs 2 typ ; Flow C 0x225c ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 225c 0x225c typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e7c 1e7c ioc_fiubs 1 val ; Flow C cc=True 0x3271 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1e7d 1e7d ioc_fiubs 2 typ ; Flow C 0x225c seq_br_type 7 Unconditional Call seq_branch_adr 225c 0x225c seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e7e 1e7e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3271 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3271 0x3271 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e7f 1e7f <halt> ; Flow R 1e80 ; -------------------------------------------------------------------------------------- 1e80 ; 0x032d Declare_Type Record,Defined 1e80 ; -------------------------------------------------------------------------------------- 1e80 MACRO_Declare_Type_Record,Defined: 1e80 1e80 dispatch_brk_class 4 ; Flow J 0x1e81 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e80 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e81 0x1e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e81 1e81 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_frame 1c val_a_adr 10 TOP val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e82 1e82 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1e83 1e83 ioc_tvbs 2 fiu+val typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1e84 1e84 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 1e85 1e85 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x26b6 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 1e86 1e86 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 10 TOP 1e87 1e87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1e8b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1e8b 0x1e8b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT 1e88 1e88 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1e8f fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1e8f 0x1e8f typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1e89 1e89 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1e8a 1e8a fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 22 TR08:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1e8b ; -------------------------------------------------------------------------------------- 1e8b ; Comes from: 1e8b ; 1e87 C False from color MACRO_Declare_Type_Record,Defined 1e8b ; 1eac C False from color MACRO_Complete_Type_Record,By_Defining 1e8b ; -------------------------------------------------------------------------------------- 1e8b 1e8b seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1e8c 0x1e8c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1e8c 1e8c seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1e8d 0x1e8d seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1e8d 1e8d seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1e8e ; -------------------------------------------------------------------------------------- 1e8e ; 0x0327 Declare_Type Record,Defined_Incomplete 1e8e ; -------------------------------------------------------------------------------------- 1e8e MACRO_Declare_Type_Record,Defined_Incomplete: 1e8e 1e8e dispatch_brk_class 4 ; Flow J 0x1e81 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e8e fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e81 0x1e81 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e8f ; -------------------------------------------------------------------------------------- 1e8f ; Comes from: 1e8f ; 1e88 C True from color MACRO_Declare_Type_Record,Defined 1e8f ; 1ead C True from color MACRO_Complete_Type_Record,By_Defining 1e8f ; -------------------------------------------------------------------------------------- 1e8f 1e8f fiu_mem_start 8 start_wr_if_false; Flow R cc=False fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1e90 0x1e90 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 1e90 1e90 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1d A_AND_NOT_B val_frame 2 1e91 1e91 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 1e92 ; -------------------------------------------------------------------------------------- 1e92 ; 0x032e Declare_Type Record,Defined,Visible 1e92 ; -------------------------------------------------------------------------------------- 1e92 MACRO_Declare_Type_Record,Defined,Visible: 1e92 1e92 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e92 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1e93 1e93 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1e81 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e81 0x1e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1e94 ; -------------------------------------------------------------------------------------- 1e94 ; 0x0328 Declare_Type Record,Defined_Incomplete,Visible 1e94 ; -------------------------------------------------------------------------------------- 1e94 MACRO_Declare_Type_Record,Defined_Incomplete,Visible: 1e94 1e94 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1e94 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1e95 1e95 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1e81 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e81 0x1e81 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1e96 ; -------------------------------------------------------------------------------------- 1e96 ; 0x032a Declare_Type Record,Incomplete 1e96 ; -------------------------------------------------------------------------------------- 1e96 MACRO_Declare_Type_Record,Incomplete: 1e96 1e96 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1e96 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1e97 1e97 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1e98 1e98 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1e99 1e99 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1e9a 1e9a fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e9d fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e9d 0x1e9d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 val_rand 2 DEC_LOOP_COUNTER 1e9b 1e9b ioc_load_wdr 0 ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1e9c 1e9c fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1e9b fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e9b 0x1e9b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 1e9d 1e9d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 1e9e 1e9e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1e9f 1e9f <halt> ; Flow R 1ea0 ; -------------------------------------------------------------------------------------- 1ea0 ; 0x032b Declare_Type Record,Incomplete,Visible 1ea0 ; -------------------------------------------------------------------------------------- 1ea0 MACRO_Declare_Type_Record,Incomplete,Visible: 1ea0 1ea0 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ea0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1ea1 1ea1 fiu_load_oreg 1 hold_oreg; Flow J 0x1e97 fiu_offs_lit 44 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1e97 0x1e97 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ea2 ; -------------------------------------------------------------------------------------- 1ea2 ; 0x0326 Complete_Type Record,By_Defining 1ea2 ; -------------------------------------------------------------------------------------- 1ea2 MACRO_Complete_Type_Record,By_Defining: 1ea2 1ea2 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ea2 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1e 1ea3 1ea3 ioc_load_wdr 0 ; Flow C cc=True 0x32a5 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1c val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1ea4 1ea4 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x3277 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 1ea5 1ea5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1ea6 1ea6 ioc_fiubs 1 val ; Flow C cc=True 0x32a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 1ea7 1ea7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ea8 1ea8 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand c WRITE_OUTER_FRAME val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 1ea9 1ea9 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 05 GP05 val_a_adr 16 PRODUCT 1eaa 1eaa ioc_tvbs 3 fiu+fiu; Flow C 0x26b6 seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1eab 1eab fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 04 GP04 1eac 1eac fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1e8b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1e8b 0x1e8b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 7 FINISH_POP_DOWN typ_rand d SET_PASS_PRIVACY_BIT 1ead 1ead fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1e8f fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1e8f 0x1e8f typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1eae 1eae ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 1eaf 1eaf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1eb0 ; -------------------------------------------------------------------------------------- 1eb0 ; 0x0325 Complete_Type Record,By_Renaming 1eb0 ; -------------------------------------------------------------------------------------- 1eb0 MACRO_Complete_Type_Record,By_Renaming: 1eb0 1eb0 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1eb0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1eb1 1eb1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1eb2 1eb2 fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 1eb3 1eb3 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 1eb4 1eb4 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 1eb5 1eb5 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 1eb6 1eb6 seq_br_type 4 Call False; Flow C cc=False 0x32a9 seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1eb7 1eb7 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 1eb8 1eb8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1eb9 1eb9 fiu_mem_start 3 start-wr; Flow J cc=True 0x1ebf ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ebf 0x1ebf seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1eba 1eba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1ebb 1ebb fiu_mem_start 2 start-rd; Flow J 0x1eb8 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1eb8 0x1eb8 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 1ebc ; -------------------------------------------------------------------------------------- 1ebc ; 0x0324 Complete_Type Record,By_Component_Completion 1ebc ; -------------------------------------------------------------------------------------- 1ebc MACRO_Complete_Type_Record,By_Component_Completion: 1ebc 1ebc dispatch_brk_class 4 ; Flow C 0x32fc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ebc fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1ebd 1ebd fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 35 VR09:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 1ebe 1ebe fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1ebf ; Flow J cc=#0x0 0x1ebf fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1ebf 0x1ebf seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ebf 1ebf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ec0 1ec0 fiu_tivi_src c mar_0xc; Flow J 0x1ec3 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ec3 0x1ec3 typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ec1 1ec1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1ec2 1ec2 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1ec3 1ec3 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1ed1 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ed1 0x1ed1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ec4 1ec4 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 1ec5 1ec5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 1ec6 1ec6 ioc_load_wdr 0 ; Flow J cc=False 0x1ecb seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ecb 0x1ecb typ_b_adr 03 GP03 val_b_adr 03 GP03 1ec7 1ec7 fiu_load_tar 1 hold_tar; Flow C cc=True 0x1ece fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1ece 0x1ece seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 1ec8 1ec8 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 1ec9 1ec9 ioc_fiubs 1 val ; Flow J cc=True 0x1ec3 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1ec3 0x1ec3 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1eca 1eca ioc_fiubs 1 val ; Flow J 0x1ec3 seq_br_type 3 Unconditional Branch seq_branch_adr 1ec3 0x1ec3 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ecb 1ecb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1ecc 1ecc seq_b_timing 1 Latch Condition; Flow C cc=True 0x1ece seq_br_type 5 Call True seq_branch_adr 1ece 0x1ece val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ecd 1ecd fiu_mem_start 3 start-wr; Flow J 0x1ec8 ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1ec8 0x1ec8 typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 1ece ; -------------------------------------------------------------------------------------- 1ece ; Comes from: 1ece ; 1ec7 C True from color MACRO_Complete_Type_Record,By_Renaming 1ece ; 1ecc C True from color MACRO_Complete_Type_Record,By_Renaming 1ece ; -------------------------------------------------------------------------------------- 1ece 1ece seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 1ecf 1ecf seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1ed0 0x1ed0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1ed0 1ed0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3277 seq_br_type 9 Return False seq_branch_adr 3277 0x3277 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 1ed1 1ed1 ioc_fiubs 1 val seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ed2 1ed2 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1ed3 1ed3 ioc_load_wdr 0 ; Flow J 0x1ebf seq_br_type 3 Unconditional Branch seq_branch_adr 1ebf 0x1ebf typ_b_adr 02 GP02 val_b_adr 02 GP02 1ed4 ; -------------------------------------------------------------------------------------- 1ed4 ; 0x0321 Declare_Variable Record,Visible 1ed4 ; -------------------------------------------------------------------------------------- 1ed4 MACRO_Declare_Variable_Record,Visible: 1ed4 1ed4 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ed4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 1ed5 1ed5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1eeb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1eeb 0x1eeb seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ed6 1ed6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ed7 0x1ed7 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) seq_random 04 Load_save_offset+? typ_a_adr 28 TR07:08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ed7 1ed7 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1edf ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1edf 0x1edf seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_frame 2 1ed8 1ed8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1edb seq_br_type 1 Branch True seq_branch_adr 1edb 0x1edb seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 04 GP04 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1ed9 1ed9 ioc_fiubs 1 val ; Flow C 0x2a2c seq_br_type 7 Unconditional Call seq_branch_adr 2a2c 0x2a2c typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1eda 1eda fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1edb 1edb fiu_tivi_src c mar_0xc; Flow J cc=False 0x1ede ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 1ede 0x1ede seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 1edc 1edc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a2c seq_br_type 5 Call True seq_branch_adr 2a2c 0x2a2c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1edd 1edd fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1ede 0x1ede seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ede 1ede seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1edf 1edf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1ee0 1ee0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a0 seq_br_type 5 Call True seq_branch_adr 32a0 0x32a0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_frame 2 val_rand 9 PASS_A_HIGH 1ee1 1ee1 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a seq_en_micro 0 1ee2 ; -------------------------------------------------------------------------------------- 1ee2 ; 0x0322 Declare_Variable Record 1ee2 ; -------------------------------------------------------------------------------------- 1ee2 MACRO_Declare_Variable_Record: 1ee2 1ee2 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ee2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 1ee3 1ee3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1ed6 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ed6 0x1ed6 seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ee4 ; -------------------------------------------------------------------------------------- 1ee4 ; 0x0320 Declare_Variable Record,Duplicate 1ee4 ; -------------------------------------------------------------------------------------- 1ee4 MACRO_Declare_Variable_Record,Duplicate: 1ee4 1ee4 dispatch_brk_class 4 ; Flow C cc=False 0x32a5 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ee4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1ee5 1ee5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ee6 1ee6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1ee9 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1ee9 0x1ee9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1ee7 1ee7 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x3277 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_frame 2 1ee8 1ee8 fiu_tivi_src c mar_0xc; Flow C cc=False 0x329a ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1ee9 1ee9 ioc_fiubs 1 val ; Flow C 0x1eec ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1eec 0x1eec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 1eea 1eea fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1eeb 1eeb seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1eec ; -------------------------------------------------------------------------------------- 1eec ; Comes from: 1eec ; 076e C from color 0x0767 1eec ; 115c C from color 0x1115 1eec ; 1166 C from color 0x1162 1eec ; 1190 C from color 0x111b 1eec ; 1196 C from color 0x111b 1eec ; 11c3 C from color 0x111b 1eec ; 11cf C from color 0x111b 1eec ; 1312 C from color MACRO_Declare_Variable_Variant_Record,Duplicate 1eec ; 17a6 C from color 0x0a30 1eec ; 17f8 C False from color MACRO_Execute_Record,Structure_Write 1eec ; 1806 C from color 0x0a2f 1eec ; 180d C from color 0x0a2f 1eec ; 1975 C from color MACRO_Execute_Vector,Slice_Read 1eec ; 19a1 C True from color MACRO_Execute_Vector,Slice_Write 1eec ; 19f2 C from color MACRO_Execute_Vector,Catenate 1eec ; 19f4 C from color MACRO_Execute_Vector,Catenate 1eec ; 1a61 C True from color 0x0a2d 1eec ; 1a7e C True from color 0x0a2d 1eec ; 1a94 C from color 0x0a2d 1eec ; 1c36 C from color 0x1c25 1eec ; 1db5 C True from color 0x1d37 1eec ; 1e14 C True from color MACRO_Execute_Matrix,Structure_Write 1eec ; 1e16 C from color MACRO_Execute_Matrix,Structure_Write 1eec ; 1e42 C True from color MACRO_Execute_Matrix,Structure_Write 1eec ; 1ee9 C from color MACRO_Declare_Variable_Record,Duplicate 1eec ; -------------------------------------------------------------------------------------- 1eec 1eec fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1f4a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f4a 0x1f4a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1eed 1eed fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1ef8 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ef8 0x1ef8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 1eee 1eee fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1ef3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ef3 0x1ef3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 1eef 1eef fiu_fill_mode_src 0 ; Flow J 0x1ef0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef0 0x1ef0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ef0 1ef0 fiu_fill_mode_src 0 ; Flow J cc=False 0x1ef5 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ef5 0x1ef5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1ef1 1ef1 fiu_fill_mode_src 0 ; Flow J 0x1ef2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1ef2 1ef2 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1ef3 1ef3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ef4 1ef4 fiu_fill_mode_src 0 ; Flow J 0x1ef0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ef0 0x1ef0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ef5 1ef5 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ef6 1ef6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1ef7 1ef7 fiu_load_var 1 hold_var; Flow J 0x1ef2 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1ef8 1ef8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1f01 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f01 0x1f01 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ef9 1ef9 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f1c fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f1c 0x1f1c typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 1efa 1efa fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1efb 1efb fiu_fill_mode_src 0 ; Flow J cc=True 0x1f05 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1f05 0x1f05 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1efc 1efc fiu_mem_start 2 start-rd; Flow J 0x1efd ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1efd 0x1efd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1efd 1efd seq_br_type 3 Unconditional Branch; Flow J 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 1efe 1efe fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1eff 1eff fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1eee fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1eee 0x1eee seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1f00 1f00 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1ef9 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ef9 0x1ef9 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1f01 1f01 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f1f fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f1f 0x1f1f seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1f02 1f02 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f04 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f04 0x1f04 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1f03 1f03 seq_br_type 0 Branch False; Flow J cc=False 0x1efd seq_branch_adr 1efd 0x1efd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1f04 1f04 fiu_fill_mode_src 0 ; Flow J 0x1f05 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f05 0x1f05 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f05 1f05 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f09 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f09 0x1f09 typ_mar_cntl 6 INCREMENT_MAR 1f06 1f06 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f07 1f07 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f08 1f08 fiu_fill_mode_src 0 ; Flow J 0x1ef2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f09 1f09 fiu_load_tar 1 hold_tar; Flow J cc=False 0x1f0f fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f0f 0x1f0f seq_cond_sel 64 OFFSET_REGISTER_???? 1f0a 1f0a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f14 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1f14 0x1f14 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f0b 1f0b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f0c 1f0c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f0d 1f0d fiu_fill_mode_src 0 ; Flow J 0x1f0e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f0e 0x1f0e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f0e 1f0e fiu_mem_start 4 continue; Flow J 0x1ef2 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1ef2 0x1ef2 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 1f0f 1f0f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f14 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 1f14 0x1f14 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f10 1f10 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 1f11 1f11 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f13 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f13 0x1f13 seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f12 1f12 fiu_fill_mode_src 0 ; Flow J 0x1f0e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f0e 0x1f0e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f13 1f13 fiu_fill_mode_src 0 ; Flow J 0x1f0e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f0e 0x1f0e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f14 1f14 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f19 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1f19 0x1f19 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl 1 RESTORE_RDR val_c_adr 31 GP0e 1f15 1f15 seq_en_micro 0 1f16 1f16 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f19 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1f19 0x1f19 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f17 1f17 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 1f18 1f18 ioc_adrbs 2 typ ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f19 0x1f19 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA 1f19 1f19 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0e GP0e 1f1a 1f1a fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1f1b 1f1b fiu_mem_start 3 start-wr; Flow J 0x1efd ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1efd 0x1efd seq_random 06 Pop_stack+? 1f1c 1f1c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f1d 1f1d fiu_fill_mode_src 0 ; Flow J cc=True 0x1f25 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f25 0x1f25 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f1e 1f1e fiu_load_oreg 1 hold_oreg; Flow J 0x1f22 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f22 0x1f22 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 1f1f 1f1f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f20 1f20 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1f27 seq_br_type 1 Branch True seq_branch_adr 1f27 0x1f27 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 1f21 1f21 fiu_fill_mode_src 0 ; Flow J 0x1f22 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f22 0x1f22 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f22 1f22 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f23 1f23 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f24 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f24 1f24 ioc_load_wdr 0 ; Flow J 0x1f2c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f2c 0x1f2c seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f25 1f25 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f2c fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f2c 0x1f2c seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f26 1f26 fiu_fill_mode_src 0 ; Flow J 0x1f29 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f29 0x1f29 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f27 1f27 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f2c fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f2c 0x1f2c seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f28 1f28 fiu_fill_mode_src 0 ; Flow J 0x1f29 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f29 0x1f29 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f29 1f29 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1f2a 1f2a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 1f2b 1f2b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f24 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f2c 1f2c fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1efe fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1efe 0x1efe seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f2d 1f2d fiu_mem_start 4 continue; Flow J cc=False 0x1f3c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f3c 0x1f3c seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f2e 1f2e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f2f 1f2f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f39 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f39 0x1f39 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f30 1f30 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f31 1f31 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329a seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f32 1f32 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f33 1f33 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f36 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f36 0x1f36 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f34 1f34 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1f35 1f35 fiu_mem_start 2 start-rd; Flow C 0x32fc seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc 1f36 1f36 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f38 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f38 0x1f38 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f37 1f37 fiu_load_oreg 1 hold_oreg; Flow J 0x1f32 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f32 0x1f32 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f38 1f38 ioc_load_wdr 0 ; Flow J 0x1efe ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1efe 0x1efe typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f39 1f39 ioc_load_wdr 0 ; Flow J cc=False 0x1efe ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1efe 0x1efe seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f3a 1f3a seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 1f3b 1f3b seq_br_type 3 Unconditional Branch; Flow J 0x1efe seq_branch_adr 1efe 0x1efe 1f3c 1f3c fiu_load_var 1 hold_var; Flow J cc=False 0x1f47 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f47 0x1f47 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f3d 1f3d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f3e 1f3e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f3f 1f3f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329a seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f40 1f40 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f44 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f44 0x1f44 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f41 1f41 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a82 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f42 1f42 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f43 1f43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f40 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f40 0x1f40 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f44 1f44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f45 1f45 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1f46 1f46 ioc_load_wdr 0 ; Flow J 0x1efe ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1efe 0x1efe typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f47 1f47 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f48 1f48 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f49 1f49 ioc_load_wdr 0 ; Flow J 0x1efe ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1efe 0x1efe typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f4a ; -------------------------------------------------------------------------------------- 1f4a ; Comes from: 1f4a ; 1eec C True from color 0x0000 1f4a ; -------------------------------------------------------------------------------------- 1f4a 1f4a fiu_tivi_src 4 fiu_var; Flow R cc=False ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1f4b 0x1f4b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f4b 1f4b fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f4c 1f4c fiu_len_fill_lit 49 zero-fill 0x9 fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 1f4d 1f4d seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1f4e 0x1f4e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 1f4e 1f4e seq_br_type 7 Unconditional Call; Flow C 0x32c1 seq_branch_adr 32c1 0x32c1 1f4f 1f4f <halt> ; Flow R 1f50 ; -------------------------------------------------------------------------------------- 1f50 ; 0x03d1 Declare_Type Access,Constrained 1f50 ; -------------------------------------------------------------------------------------- 1f50 MACRO_Declare_Type_Access,Constrained: 1f50 1f50 dispatch_brk_class 4 ; Flow J 0x1f58 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f50 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f58 0x1f58 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f51 1f51 <halt> ; Flow R 1f52 ; -------------------------------------------------------------------------------------- 1f52 ; 0x03d2 Declare_Type Access,Constrained,Visible 1f52 ; -------------------------------------------------------------------------------------- 1f52 MACRO_Declare_Type_Access,Constrained,Visible: 1f52 1f52 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f52 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f53 1f53 fiu_mem_start 2 start-rd; Flow J 0x1f58 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f58 0x1f58 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f54 ; -------------------------------------------------------------------------------------- 1f54 ; 0x03ab Declare_Type Heap_Access,Constrained 1f54 ; -------------------------------------------------------------------------------------- 1f54 MACRO_Declare_Type_Heap_Access,Constrained: 1f54 1f54 dispatch_brk_class 4 ; Flow J 0x1f59 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f54 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f59 0x1f59 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f55 1f55 <halt> ; Flow R 1f56 ; -------------------------------------------------------------------------------------- 1f56 ; 0x03ac Declare_Type Heap_Access,Constrained,Visible 1f56 ; -------------------------------------------------------------------------------------- 1f56 MACRO_Declare_Type_Heap_Access,Constrained,Visible: 1f56 1f56 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f56 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f57 1f57 fiu_mem_start 2 start-rd; Flow J 0x1f59 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f59 0x1f59 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f58 1f58 fiu_load_tar 1 hold_tar; Flow J 0x1f5a fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f5a 0x1f5a seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 1f59 1f59 fiu_load_tar 1 hold_tar; Flow J 0x1f5a fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f5a 0x1f5a seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 7 1f5a 1f5a fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f5b 1f5b fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1f5c 1f5c ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f5d 1f5d fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a7 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 1f5e 1f5e seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x1f64 seq_br_type f Unconditional Case Call seq_branch_adr 1f64 0x1f64 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1f5f 1f5f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1f60 1f60 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 1f61 1f61 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 1f62 1f62 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 01 GP01 1f63 1f63 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1f64 ; -------------------------------------------------------------------------------------- 1f64 ; Comes from: 1f64 ; 1f5e C #0x0 from color MACRO_Declare_Type_Access,Constrained 1f64 ; -------------------------------------------------------------------------------------- 1f64 1f64 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f65 1f65 fiu_mem_start 2 start-rd; Flow J 0x1f6c ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f6c 0x1f6c typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1f66 1f66 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f67 1f67 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f68 1f68 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f69 1f69 seq_br_type 3 Unconditional Branch; Flow J 0x1f71 seq_branch_adr 1f71 0x1f71 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f6a 1f6a seq_br_type 3 Unconditional Branch; Flow J 0x1f71 seq_branch_adr 1f71 0x1f71 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f6b 1f6b fiu_mem_start 2 start-rd; Flow J 0x1f79 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f79 0x1f79 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1f6c 1f6c ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1f6d 1f6d fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1f6e 1f6e <default> 1f6f 1f6f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1f70 1f70 fiu_mem_start 2 start-rd; Flow J 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3242 0x3242 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f71 1f71 ioc_fiubs 1 val ; Flow C cc=False 0x32a7 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1f72 1f72 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f73 0x1f73 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 1f73 1f73 fiu_mem_start 2 start-rd; Flow C 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3242 0x3242 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f74 1f74 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1f75 1f75 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1f76 1f76 seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1f77 1f77 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f78 0x1f78 typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 1f78 1f78 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 1f79 1f79 <default> 1f7a 1f7a fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x1f71 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f71 0x1f71 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1f7b 1f7b <halt> ; Flow R 1f7c ; -------------------------------------------------------------------------------------- 1f7c ; 0x0341 Complete_Type Array,By_Constraining 1f7c ; -------------------------------------------------------------------------------------- 1f7c MACRO_Complete_Type_Array,By_Constraining: 1f7c 1f7c dispatch_brk_class 4 ; Flow C cc=True 0x32a9 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1f7c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f7d 1f7d fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1f7e 1f7e fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 1f7f 1f7f fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x1f84 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1f84 0x1f84 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 9 PASS_A_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f80 1f80 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1f81 1f81 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1f82 1f82 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1f89 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f89 0x1f89 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 1f83 1f83 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 1f84 1f84 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1f85 1f85 <default> 1f86 1f86 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f87 1f87 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1f88 0x1f88 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 1f88 1f88 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 1f89 1f89 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_lit 0 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1f8a 1f8a fiu_mem_start 4 continue; Flow J cc=False 0x1fa8 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fa8 0x1fa8 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f8b 1f8b fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1f8c 1f8c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1f97 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1f97 0x1f97 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f8d 1f8d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1fa5 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fa5 0x1fa5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1f8e 1f8e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3270 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1f8f 1f8f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f9e fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1f9e 0x1f9e seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f90 1f90 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f91 1f91 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1d TOP - 3 1f92 1f92 ioc_load_wdr 0 ; Flow C cc=True 0x3270 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1f93 1f93 seq_b_timing 0 Early Condition; Flow C cc=False 0x1f95 seq_br_type 4 Call False seq_branch_adr 1f95 0x1f95 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA 1f94 1f94 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1f95 ; -------------------------------------------------------------------------------------- 1f95 ; Comes from: 1f95 ; 1f93 C False from color MACRO_Complete_Type_Array,By_Constraining 1f95 ; -------------------------------------------------------------------------------------- 1f95 1f95 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1f96 1f96 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 1f97 ; -------------------------------------------------------------------------------------- 1f97 ; Comes from: 1f97 ; 1f8c C True from color MACRO_Complete_Type_Array,By_Constraining 1f97 ; -------------------------------------------------------------------------------------- 1f97 1f97 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1f98 1f98 fiu_mem_start 4 continue; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f99 0x1f99 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1f99 1f99 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 1f9a ; -------------------------------------------------------------------------------------- 1f9a ; Comes from: 1f9a ; 1faa C True from color MACRO_Complete_Type_Array,By_Constraining 1f9a ; -------------------------------------------------------------------------------------- 1f9a 1f9a <default> 1f9b 1f9b fiu_mem_start 2 start-rd; Flow J 0x1f98 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f98 0x1f98 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1f9c ; -------------------------------------------------------------------------------------- 1f9c ; Comes from: 1f9c ; 1fd9 C True from color MACRO_Complete_Type_Array,By_Constraining 1f9c ; -------------------------------------------------------------------------------------- 1f9c 1f9c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1f9d 0x1f9d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 1f9d 1f9d seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 1f9e ; -------------------------------------------------------------------------------------- 1f9e ; Comes from: 1f9e ; 1f8f C False from color MACRO_Complete_Type_Array,By_Constraining 1f9e ; -------------------------------------------------------------------------------------- 1f9e 1f9e fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f9f 1f9f ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fa0 1fa0 seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fa3 seq_br_type 4 Call False seq_branch_adr 1fa3 0x1fa3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fa1 1fa1 seq_br_type 4 Call False; Flow C cc=False 0x1fa4 seq_branch_adr 1fa4 0x1fa4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fa2 1fa2 fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 1fa3 ; -------------------------------------------------------------------------------------- 1fa3 ; Comes from: 1fa3 ; 1fa0 C False from color 0x1f9c 1fa3 ; -------------------------------------------------------------------------------------- 1fa3 1fa3 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fa4 0x1fa4 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 1fa4 ; -------------------------------------------------------------------------------------- 1fa4 ; Comes from: 1fa4 ; 1fa1 C False from color 0x1f9c 1fa4 ; -------------------------------------------------------------------------------------- 1fa4 1fa4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1fa5 ; -------------------------------------------------------------------------------------- 1fa5 ; Comes from: 1fa5 ; 1f8d C False from color MACRO_Complete_Type_Array,By_Constraining 1fa5 ; -------------------------------------------------------------------------------------- 1fa5 1fa5 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fa6 1fa6 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fa7 1fa7 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fa8 1fa8 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fa9 1fa9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fd9 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fd9 0x1fd9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 1faa 1faa fiu_mem_start 4 continue; Flow C cc=True 0x1f9a ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f9a 0x1f9a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1b TOP - 5 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1fab 1fab fiu_mem_start 4 continue; Flow C cc=True 0x1fc3 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1fc3 0x1fc3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1fac 1fac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fc6 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fc6 0x1fc6 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fad 1fad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3270 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1fae 1fae seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fca seq_br_type 4 Call False seq_branch_adr 1fca 0x1fca seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1faf 1faf fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1fb0 1fb0 ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fb1 1fb1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1fb2 1fb2 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fb3 1fb3 val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fb4 1fb4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1b TOP - 5 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 1fb5 1fb5 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x1fd2 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd2 0x1fd2 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fb6 1fb6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 1fb7 1fb7 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1fb8 1fb8 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x1fd4 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd4 0x1fd4 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1fb9 1fb9 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 02 ? typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1fba 1fba fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1b TOP - 5 1fbb 1fbb fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1fbc 1fbc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1fc0 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1fc0 0x1fc0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 1fbd 1fbd ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 1fbe 1fbe typ_csa_cntl 3 POP_CSA 1fbf 1fbf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1fc0 1fc0 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1fc1 1fc1 ioc_load_wdr 0 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 1fc2 1fc2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1fc3 ; -------------------------------------------------------------------------------------- 1fc3 ; Comes from: 1fc3 ; 1fab C True from color MACRO_Complete_Type_Array,By_Constraining 1fc3 ; -------------------------------------------------------------------------------------- 1fc3 1fc3 seq_br_type 4 Call False; Flow C cc=False 0x3270 seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 1fc4 1fc4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1fc5 1fc5 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1fc6 1fc6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fc7 1fc7 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fc8 1fc8 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fc9 1fc9 seq_br_type 3 Unconditional Branch; Flow J 0x1faf seq_branch_adr 1faf 0x1faf val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fca ; -------------------------------------------------------------------------------------- 1fca ; Comes from: 1fca ; 1fae C False from color MACRO_Complete_Type_Array,By_Constraining 1fca ; -------------------------------------------------------------------------------------- 1fca 1fca val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1fcb 1fcb fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1fcc 1fcc seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fcd 1fcd seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fd0 seq_br_type 4 Call False seq_branch_adr 1fd0 0x1fd0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fce 1fce seq_br_type 4 Call False; Flow C cc=False 0x1fd1 seq_branch_adr 1fd1 0x1fd1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1fcf 1fcf seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fd0 ; -------------------------------------------------------------------------------------- 1fd0 ; Comes from: 1fd0 ; 1fcd C False from color 0x1fca 1fd0 ; -------------------------------------------------------------------------------------- 1fd0 1fd0 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fd1 0x1fd1 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 1fd1 ; -------------------------------------------------------------------------------------- 1fd1 ; Comes from: 1fd1 ; 1fce C False from color 0x1fca 1fd1 ; -------------------------------------------------------------------------------------- 1fd1 1fd1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1fd2 ; -------------------------------------------------------------------------------------- 1fd2 ; Comes from: 1fd2 ; 1fb5 C False from color MACRO_Complete_Type_Array,By_Constraining 1fd2 ; -------------------------------------------------------------------------------------- 1fd2 1fd2 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fd3 1fd3 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1c TOP - 4 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1fd4 ; -------------------------------------------------------------------------------------- 1fd4 ; Comes from: 1fd4 ; 1fb8 C False from color MACRO_Complete_Type_Array,By_Constraining 1fd4 ; -------------------------------------------------------------------------------------- 1fd4 1fd4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd5 1fd5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd6 1fd6 seq_br_type 4 Call False; Flow C cc=False 0x1fd8 seq_branch_adr 1fd8 0x1fd8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 1fd7 1fd7 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 1fd8 ; -------------------------------------------------------------------------------------- 1fd8 ; Comes from: 1fd8 ; 1fd6 C False from color 0x1fd4 1fd8 ; -------------------------------------------------------------------------------------- 1fd8 1fd8 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1fd9 1fd9 seq_b_timing 1 Latch Condition; Flow C cc=True 0x1f9c seq_br_type 5 Call True seq_branch_adr 1f9c 0x1f9c 1fda 1fda fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 1fdb 1fdb fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1fdc 1fdc typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 1fdd 1fdd fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1fde 1fde val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 1fdf 1fdf fiu_load_tar 1 hold_tar; Flow J cc=True 0x1fe8 fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1fe8 0x1fe8 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 1fe0 1fe0 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1fe1 1fe1 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 1fe2 1fe2 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 1fe3 1fe3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fe4 1fe4 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1fe5 1fe5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1fe6 1fe6 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1fe7 1fe7 fiu_load_tar 1 hold_tar; Flow J 0x1fe8 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1fe8 0x1fe8 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1fe8 1fe8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1ffe fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ffe 0x1ffe seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 1fe9 1fe9 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 1fea 1fea ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1feb 1feb ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1fec 1fec fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fed 1fed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fee 1fee seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1fef 1fef fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ffd fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ffd 0x1ffd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ff0 1ff0 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3270 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3270 0x3270 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1ff1 1ff1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1ff2 1ff2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 1ff3 1ff3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 1ff4 1ff4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 1ff5 1ff5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 1ff6 1ff6 ioc_fiubs 2 typ ; Flow J cc=True 0x1fe8 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1fe8 0x1fe8 seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ff7 1ff7 seq_br_type 0 Branch False; Flow J cc=False 0x1ffc seq_branch_adr 1ffc 0x1ffc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ff8 1ff8 seq_br_type 0 Branch False; Flow J cc=False 0x1ffc seq_branch_adr 1ffc 0x1ffc seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ff9 1ff9 seq_br_type 0 Branch False; Flow J cc=False 0x1ffc seq_branch_adr 1ffc 0x1ffc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffa 1ffa seq_br_type 0 Branch False; Flow J cc=False 0x1ffc seq_branch_adr 1ffc 0x1ffc seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ffb 1ffb seq_br_type 1 Branch True; Flow J cc=True 0x1fe8 seq_branch_adr 1fe8 0x1fe8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 1ffc 1ffc ioc_fiubs 2 typ ; Flow J 0x1fe8 seq_br_type 3 Unconditional Branch seq_branch_adr 1fe8 0x1fe8 typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ffd 1ffd seq_br_type 3 Unconditional Branch; Flow J 0x1ff2 seq_branch_adr 1ff2 0x1ff2 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ffe 1ffe fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1fff 1fff ioc_load_wdr 0 ; Flow C cc=False 0x2003 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2003 0x2003 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_b_adr 01 GP01 val_b_adr 0f GP0f 2000 2000 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 05 GP05 val_alu_func 0 PASS_A 2001 2001 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 2002 2002 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2003 ; -------------------------------------------------------------------------------------- 2003 ; Comes from: 2003 ; 1fff C False from color MACRO_Complete_Type_Array,By_Constraining 2003 ; -------------------------------------------------------------------------------------- 2003 2003 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2004 2004 ioc_fiubs 1 val ; Flow J 0x2215 seq_br_type 3 Unconditional Branch seq_branch_adr 2215 0x2215 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 2005 2005 <halt> ; Flow R 2006 ; -------------------------------------------------------------------------------------- 2006 ; 0x0343 Complete_Type Array,By_Defining 2006 ; -------------------------------------------------------------------------------------- 2006 MACRO_Complete_Type_Array,By_Defining: 2006 2006 dispatch_brk_class 4 ; Flow C cc=True 0x32a9 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2006 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2007 2007 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 2008 2008 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 2009 2009 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a5 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame a val_c_adr 37 GP08 val_c_source 0 FIU_BUS 200a 200a fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3b GP04 val_c_source 0 FIU_BUS 200b 200b fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 200c 200c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 200d 200d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 200e 200e fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 200f 200f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a6 seq_br_type f Unconditional Case Call seq_branch_adr 20a6 0x20a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2010 2010 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2015 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2015 0x2015 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2011 2011 seq_br_type 2 Push (branch address); Flow J 0x2012 seq_branch_adr 2015 0x2015 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 2012 2012 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2013 0x2013 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 2013 2013 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20b6 seq_br_type 1 Branch True seq_branch_adr 20b6 0x20b6 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 2d TR09:0d typ_frame 9 2014 2014 seq_br_type 3 Unconditional Branch; Flow J 0x20b9 seq_branch_adr 20b9 0x20b9 2015 2015 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2032 seq_br_type 1 Branch True seq_branch_adr 2032 0x2032 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_rand 2 DEC_LOOP_COUNTER 2016 2016 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2017 2017 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2018 2018 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2019 2019 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2021 seq_br_type 1 Branch True seq_branch_adr 2021 0x2021 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 201a 201a seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 201b 201b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 201c 201c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2024 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2024 0x2024 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 201d 201d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 201e 201e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 201f 201f fiu_mem_start 3 start-wr; Flow J cc=True 0x2024 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2024 0x2024 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2020 2020 fiu_mem_start 3 start-wr; Flow J 0x2024 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2024 0x2024 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2021 2021 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2022 2022 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2023 2023 fiu_mem_start 3 start-wr; Flow J 0x2024 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2024 0x2024 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2024 2024 fiu_mem_start 4 continue; Flow C cc=True 0x32a5 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2025 2025 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 2026 2026 fiu_load_var 1 hold_var; Flow J cc=True 0x202a fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 202a 0x202a typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2027 2027 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 2028 2028 typ_csa_cntl 3 POP_CSA 2029 2029 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 202a 202a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 202b 202b fiu_tivi_src 4 fiu_var; Flow J 0x202c ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 2028 0x2028 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 202c 202c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 202d 0x202d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 23 TR01:03 typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 202d 202d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 202e 202e <default> 202f 202f fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2030 2030 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2031 0x2031 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f val_b_adr 0f GP0f 2031 2031 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2032 2032 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2033 2033 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2034 2034 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x203d seq_br_type 1 Branch True seq_branch_adr 203d 0x203d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 2035 2035 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2036 2036 ioc_fiubs 1 val ; Flow C cc=False 0x3276 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2037 2037 seq_b_timing 1 Latch Condition; Flow J cc=True 0x203c seq_br_type 1 Branch True seq_branch_adr 203c 0x203c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2038 2038 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2039 2039 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 203a 203a seq_br_type 1 Branch True; Flow J cc=True 0x203c seq_branch_adr 203c 0x203c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 203b 203b seq_br_type 3 Unconditional Branch; Flow J 0x203c seq_branch_adr 203c 0x203c val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 203c 203c seq_br_type 3 Unconditional Branch; Flow J 0x203f seq_branch_adr 203f 0x203f typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 203d 203d ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 203e 203e seq_br_type 3 Unconditional Branch; Flow J 0x203c seq_branch_adr 203c 0x203c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 203f 203f fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 2040 2040 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 04 GP04 val_rand 2 DEC_LOOP_COUNTER 2041 2041 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2042 2042 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x3299 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3299 0x3299 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2043 2043 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 2044 2044 ioc_load_wdr 0 ; Flow J 0x2045 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2045 0x2045 val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2045 2045 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2046 2046 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2047 2047 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2048 2048 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2049 2049 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x204b seq_br_type 0 Branch False seq_branch_adr 204b 0x204b seq_cond_sel 67 REFRESH_MACRO_EVENT 204a 204a seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 204b 204b seq_br_type 0 Branch False; Flow J cc=False 0x2057 seq_branch_adr 2057 0x2057 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 204c 204c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204d 204d seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204e 204e ioc_fiubs 1 val ; Flow C cc=False 0x3276 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 204f 204f seq_en_micro 0 2050 2050 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2055 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2055 0x2055 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2051 2051 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2052 2052 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2053 2053 fiu_mem_start 3 start-wr; Flow J cc=True 0x2055 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2055 0x2055 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2054 2054 fiu_mem_start 3 start-wr; Flow J 0x2055 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2055 0x2055 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2055 2055 fiu_mem_start 4 continue; Flow J 0x2056 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 2045 0x2045 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 2056 2056 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x205a ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 205a 0x205a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 2057 2057 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2058 2058 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 2059 2059 fiu_mem_start 3 start-wr; Flow J 0x2055 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2055 0x2055 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 205a 205a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 205b 205b fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 205c 205c ioc_load_wdr 0 ; Flow C cc=False 0x2060 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2060 0x2060 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 205d 205d ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 205e 205e seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 205f 205f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2060 2060 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2061 2061 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2062 2062 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 2063 2063 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 2064 2064 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2065 2065 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2066 2066 fiu_load_tar 1 hold_tar; Flow J 0x2067 fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 2068 0x2068 typ_b_adr 01 GP01 2067 2067 seq_br_type 3 Unconditional Branch; Flow J 0x202c seq_branch_adr 202c 0x202c 2068 2068 seq_br_type 3 Unconditional Branch; Flow J 0x2215 seq_branch_adr 2215 0x2215 2069 2069 <halt> ; Flow R 206a ; -------------------------------------------------------------------------------------- 206a ; 0x0355 Declare_Type Array,Defined_Incomplete 206a ; -------------------------------------------------------------------------------------- 206a MACRO_Declare_Type_Array,Defined_Incomplete: 206a 206a dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 206a fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 206b 206b seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206d seq_br_type f Unconditional Case Call seq_branch_adr 206d 0x206d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 206c 206c seq_br_type 7 Unconditional Call; Flow C 0x20ca seq_branch_adr 20ca MACRO_Declare_Type_Array,Defined 206d ; -------------------------------------------------------------------------------------- 206d ; Comes from: 206d ; 206b C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete 206d ; 209c C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 206d ; 209f C #0x0 from color 0x209d 206d ; 20a4 C #0x0 from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 206d ; -------------------------------------------------------------------------------------- 206d 206d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2082 seq_br_type 9 Return False seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 206e 206e seq_br_type a Unconditional Return; Flow R 206f 206f seq_br_type a Unconditional Return; Flow R 2070 2070 seq_br_type a Unconditional Return; Flow R 2071 2071 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2072 2072 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2073 2073 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2074 2074 seq_br_type a Unconditional Return; Flow R 2075 2075 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2082 seq_br_type 9 Return False seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2076 2076 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x207d seq_br_type 9 Return False seq_branch_adr 207d 0x207d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2077 2077 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2078 2078 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2079 2079 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 207a 207a ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2080 seq_br_type 9 Return False seq_branch_adr 2080 0x2080 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207b 207b ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2080 seq_br_type 9 Return False seq_branch_adr 2080 0x2080 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207c 207c ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2080 seq_br_type 9 Return False seq_branch_adr 2080 0x2080 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 207d 207d fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2082 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2082 0x2082 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE 207e 207e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2082 seq_br_type 1 Branch True seq_branch_adr 2082 0x2082 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 207f 207f seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2080 2080 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2082 seq_br_type 0 Branch False seq_branch_adr 2082 0x2082 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 2081 2081 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2082 2082 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2084 seq_br_type 0 Branch False seq_branch_adr 2084 0x2084 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 2083 2083 seq_br_type 3 Unconditional Branch; Flow J 0x20bb seq_branch_adr 20bb 0x20bb typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 2084 2084 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2085 2085 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2086 2086 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2087 2087 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x208f seq_br_type 1 Branch True seq_branch_adr 208f 0x208f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 2088 2088 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2089 2089 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 208a 208a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2092 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2092 0x2092 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 208b 208b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 208c 208c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 208d 208d fiu_mem_start 3 start-wr; Flow J cc=True 0x2092 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2092 0x2092 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 208e 208e fiu_mem_start 3 start-wr; Flow J 0x2092 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2092 0x2092 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 208f 208f ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2090 2090 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2091 2091 fiu_mem_start 3 start-wr; Flow J 0x2092 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2092 0x2092 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2092 2092 fiu_mem_start 4 continue; Flow C cc=True 0x32a5 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2093 2093 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3b VR02:1b val_frame 2 2094 2094 fiu_load_var 1 hold_var; Flow J cc=True 0x2097 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2097 0x2097 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2095 2095 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2096 2096 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2097 2097 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2098 2098 fiu_tivi_src 4 fiu_var; Flow J 0x2096 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2096 0x2096 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 2099 2099 <halt> ; Flow R 209a ; -------------------------------------------------------------------------------------- 209a ; 0x0356 Declare_Type Array,Defined_Incomplete,Visible 209a ; -------------------------------------------------------------------------------------- 209a MACRO_Declare_Type_Array,Defined_Incomplete,Visible: 209a 209a dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 209a seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 209b 209b fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 209c 209c seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206d seq_br_type f Unconditional Case Call seq_branch_adr 206d 0x206d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 209d 209d seq_br_type 7 Unconditional Call; Flow C 0x2112 seq_branch_adr 2112 MACRO_Declare_Type_Array,Defined,Visible 209e ; -------------------------------------------------------------------------------------- 209e ; 0x0348 Declare_Type Array,Defined_Incomplete,Bounds_With_Object 209e ; -------------------------------------------------------------------------------------- 209e MACRO_Declare_Type_Array,Defined_Incomplete,Bounds_With_Object: 209e 209e dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 209e fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 209f 209f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206d seq_br_type f Unconditional Case Call seq_branch_adr 206d 0x206d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20a0 20a0 seq_br_type 7 Unconditional Call; Flow C 0x2118 seq_branch_adr 2118 MACRO_Declare_Type_Array,Defined,Bounds_With_Object 20a1 20a1 <halt> ; Flow R 20a2 ; -------------------------------------------------------------------------------------- 20a2 ; 0x0349 Declare_Type Array,Defined_Incomplete,Visible,Bounds_With_Object 20a2 ; -------------------------------------------------------------------------------------- 20a2 MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object: 20a2 20a2 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20a2 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 20a3 20a3 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20a4 20a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x206d seq_br_type f Unconditional Case Call seq_branch_adr 206d 0x206d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20a5 20a5 seq_br_type 7 Unconditional Call; Flow C 0x211c seq_branch_adr 211c MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object 20a6 ; -------------------------------------------------------------------------------------- 20a6 ; Comes from: 20a6 ; 200f C #0x0 from color MACRO_Complete_Type_Array,By_Defining 20a6 ; 20cb C #0x0 from color MACRO_Declare_Type_Array,Defined 20a6 ; 2114 C #0x0 from color MACRO_Declare_Type_Array,Defined,Visible 20a6 ; 2119 C #0x0 from color MACRO_Declare_Type_Array,Defined,Bounds_With_Object 20a6 ; 211e C #0x0 from color 0x2010 20a6 ; -------------------------------------------------------------------------------------- 20a6 20a6 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20a7 20a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20a8 20a8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20a9 20a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20aa 20aa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ab 20ab seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ac 20ac seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ad 20ad fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ae 20ae fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20af 20af fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20b6 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20b6 0x20b6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b0 20b0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b1 20b1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b2 20b2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20b3 20b3 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20b9 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20b9 0x20b9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b4 20b4 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20b9 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20b9 0x20b9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b5 20b5 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20b9 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20b9 0x20b9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20b6 20b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20b7 0x20b7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 20b7 20b7 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 20b8 0x20b8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 20b8 20b8 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 20b9 20b9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20ba 0x20ba seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 val_a_adr 14 ZEROS 20ba 20ba seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 20bb 20bb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32aa fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20bc 20bc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20bd 20bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20c7 seq_br_type 1 Branch True seq_branch_adr 20c7 0x20c7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20be 20be seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20bf 20bf ioc_fiubs 1 val ; Flow C cc=False 0x3276 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20c0 20c0 ioc_tvbs 5 seq+seq; Flow J cc=True 0x20c5 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20c5 0x20c5 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20c1 20c1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20c2 20c2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20c3 20c3 seq_br_type 1 Branch True; Flow J cc=True 0x20c5 seq_branch_adr 20c5 0x20c5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20c4 20c4 seq_br_type 3 Unconditional Branch; Flow J 0x20c5 seq_branch_adr 20c5 0x20c5 val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20c5 20c5 seq_b_timing 0 Early Condition; Flow J cc=True 0x20e5 seq_br_type 1 Branch True seq_branch_adr 20e5 0x20e5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 34 VR05:14 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 20c6 20c6 seq_br_type 3 Unconditional Branch; Flow J 0x20e5 seq_branch_adr 20e5 0x20e5 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 35 VR05:15 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20c7 20c7 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 20c8 20c8 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 20c9 20c9 seq_br_type 3 Unconditional Branch; Flow J 0x20c5 seq_branch_adr 20c5 0x20c5 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20ca ; -------------------------------------------------------------------------------------- 20ca ; 0x035d Declare_Type Array,Defined 20ca ; Comes from: 20ca ; 206c C from color 0x2010 20ca ; -------------------------------------------------------------------------------------- 20ca MACRO_Declare_Type_Array,Defined: 20ca 20ca dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20ca fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20cb 20cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a6 seq_br_type f Unconditional Case Call seq_branch_adr 20a6 0x20a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20cc 20cc ioc_tvbs 2 fiu+val; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 20cd 20cd seq_b_timing 1 Latch Condition; Flow J cc=True 0x20bb seq_br_type 1 Branch True seq_branch_adr 20bb 0x20bb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 20ce 20ce ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 20cf 20cf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20d0 20d0 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20d1 20d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20db seq_br_type 1 Branch True seq_branch_adr 20db 0x20db seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20d2 20d2 seq_b_timing 1 Latch Condition; Flow C cc=False 0x20d9 seq_br_type 4 Call False seq_branch_adr 20d9 0x20d9 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20d3 20d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20d4 20d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x20de fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20de 0x20de seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20d5 20d5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20d6 20d6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20d7 20d7 fiu_mem_start 3 start-wr; Flow J cc=True 0x20de ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 20de 0x20de seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20d8 20d8 fiu_mem_start 3 start-wr; Flow J 0x20de ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20de 0x20de typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20d9 ; -------------------------------------------------------------------------------------- 20d9 ; Comes from: 20d9 ; 20d2 C False from color 0x2010 20d9 ; -------------------------------------------------------------------------------------- 20d9 20d9 seq_br_type 1 Branch True; Flow J cc=True 0x3276 seq_branch_adr 3276 0x3276 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 20da 20da seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 20db 20db ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 20dc 20dc typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 20dd 20dd fiu_mem_start 3 start-wr; Flow J 0x20de ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20de 0x20de typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20de 20de fiu_mem_start 4 continue; Flow C cc=True 0x32a5 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 20df 20df fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 20e0 20e0 fiu_load_var 1 hold_var; Flow J cc=True 0x20e3 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20e3 0x20e3 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 20e1 20e1 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20e2 20e2 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 20e3 20e3 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20e4 20e4 fiu_tivi_src 4 fiu_var; Flow J 0x20e2 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 20e2 0x20e2 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 20e5 20e5 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 20e6 20e6 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 10 TOP val_rand 2 DEC_LOOP_COUNTER 20e7 20e7 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20e8 20e8 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x3299 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3299 0x3299 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 20e9 20e9 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 20ea 20ea ioc_load_wdr 0 ; Flow J 0x20eb ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 20eb 0x20eb val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20eb 20eb fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20ec 20ec fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20ed 20ed ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 20ee 20ee ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20ef 20ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x20f1 seq_br_type 0 Branch False seq_branch_adr 20f1 0x20f1 seq_cond_sel 67 REFRESH_MACRO_EVENT 20f0 20f0 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 20f1 20f1 seq_br_type 0 Branch False; Flow J cc=False 0x20fd seq_branch_adr 20fd 0x20fd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 20f2 20f2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f3 20f3 seq_b_timing 1 Latch Condition; Flow C cc=False 0x3276 seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f4 20f4 ioc_fiubs 1 val ; Flow C cc=False 0x3276 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20f5 20f5 seq_en_micro 0 20f6 20f6 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x20fb ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20fb 0x20fb seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20f7 20f7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20f8 20f8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20f9 20f9 fiu_mem_start 3 start-wr; Flow J cc=True 0x20fb ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 20fb 0x20fb seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20fa 20fa fiu_mem_start 3 start-wr; Flow J 0x20fb ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20fb 0x20fb typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20fb 20fb fiu_mem_start 4 continue; Flow J 0x20fc ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 20eb 0x20eb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 20fc 20fc ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2100 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2100 0x2100 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 20fd 20fd typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 20fe 20fe ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 20ff 20ff fiu_mem_start 3 start-wr; Flow J 0x20fb ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20fb 0x20fb typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2100 2100 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2104 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2104 0x2104 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2101 2101 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2102 2102 ioc_load_wdr 0 ; Flow C cc=False 0x210b seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 210b 0x210b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2103 2103 ioc_adrbs 2 typ ; Flow J 0x2107 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2107 0x2107 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2104 2104 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2105 2105 ioc_load_wdr 0 ; Flow C cc=False 0x210b seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 210b 0x210b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 3b VR02:1b val_frame 2 2106 2106 ioc_adrbs 2 typ ; Flow J 0x2107 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2107 0x2107 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2107 2107 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 2108 2108 fiu_mem_start 3 start-wr fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2109 2109 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 210a 210a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 210b ; -------------------------------------------------------------------------------------- 210b ; Comes from: 210b ; 2102 C False from color 0x2010 210b ; 2105 C False from color 0x2010 210b ; -------------------------------------------------------------------------------------- 210b 210b val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 210c 210c ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 210d 210d fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 210e 210e ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 210f 210f ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2110 2110 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2111 2111 fiu_load_tar 1 hold_tar; Flow J 0x2215 fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2215 0x2215 typ_b_adr 01 GP01 2112 ; -------------------------------------------------------------------------------------- 2112 ; 0x035e Declare_Type Array,Defined,Visible 2112 ; Comes from: 2112 ; 209d C from color 0x209d 2112 ; -------------------------------------------------------------------------------------- 2112 MACRO_Declare_Type_Array,Defined,Visible: 2112 2112 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2112 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2113 2113 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 2114 2114 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a6 seq_br_type f Unconditional Case Call seq_branch_adr 20a6 0x20a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2115 2115 ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cd seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cd 0x20cd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2116 2116 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2117 2117 <halt> ; Flow R 2118 ; -------------------------------------------------------------------------------------- 2118 ; 0x0350 Declare_Type Array,Defined,Bounds_With_Object 2118 ; Comes from: 2118 ; 20a0 C from color 0x20a0 2118 ; -------------------------------------------------------------------------------------- 2118 MACRO_Declare_Type_Array,Defined,Bounds_With_Object: 2118 2118 dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2118 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2119 2119 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a6 seq_br_type f Unconditional Case Call seq_branch_adr 20a6 0x20a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 211a 211a ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cd seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cd 0x20cd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 211b 211b seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 211c ; -------------------------------------------------------------------------------------- 211c ; 0x0351 Declare_Type Array,Defined,Visible,Bounds_With_Object 211c ; Comes from: 211c ; 20a5 C from color 0x20a5 211c ; -------------------------------------------------------------------------------------- 211c MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object: 211c 211c dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 211c seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 211d 211d fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 211e 211e seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20a6 seq_br_type f Unconditional Case Call seq_branch_adr 20a6 0x20a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 211f 211f ioc_tvbs 2 fiu+val; Flow J cc=False 0x20cd seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20cd 0x20cd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2120 2120 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2121 2121 <halt> ; Flow R 2122 ; -------------------------------------------------------------------------------------- 2122 ; 0x035b Declare_Type Array,Constrained 2122 ; -------------------------------------------------------------------------------------- 2122 MACRO_Declare_Type_Array,Constrained: 2122 2122 dispatch_brk_class 4 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2122 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 2123 2123 fiu_mem_start 4 continue; Flow J cc=False 0x2144 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2144 0x2144 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2124 2124 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2125 2125 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2133 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2133 0x2133 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2126 2126 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2141 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2141 0x2141 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 24 TR07:04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2127 2127 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2130 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2130 0x2130 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 2128 2128 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x213a fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 213a 0x213a seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2129 2129 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 212a 212a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1e TOP - 2 212b 212b ioc_load_wdr 0 ; Flow C cc=True 0x2132 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2132 0x2132 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 212c 212c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 212d 0x212d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 212d 212d fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 212e 212e fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 212f 212f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2130 ; -------------------------------------------------------------------------------------- 2130 ; Comes from: 2130 ; 2127 C True from color MACRO_Declare_Type_Array,Constrained 2130 ; -------------------------------------------------------------------------------------- 2130 2130 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3270 seq_br_type 1 Branch True seq_branch_adr 3270 0x3270 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 05 ? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2131 2131 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2132 ; -------------------------------------------------------------------------------------- 2132 ; Comes from: 2132 ; 212b C True from color MACRO_Declare_Type_Array,Constrained 2132 ; -------------------------------------------------------------------------------------- 2132 2132 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3270 seq_br_type 9 Return False seq_branch_adr 3270 0x3270 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2133 ; -------------------------------------------------------------------------------------- 2133 ; Comes from: 2133 ; 2125 C True from color MACRO_Declare_Type_Array,Constrained 2133 ; -------------------------------------------------------------------------------------- 2133 2133 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2134 2134 fiu_mem_start 4 continue; Flow R cc=False ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2135 0x2135 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2135 2135 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2136 ; -------------------------------------------------------------------------------------- 2136 ; Comes from: 2136 ; 2146 C True from color MACRO_Declare_Type_Array,Constrained 2136 ; -------------------------------------------------------------------------------------- 2136 2136 <default> 2137 2137 fiu_mem_start 2 start-rd; Flow J 0x2134 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2134 0x2134 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2138 ; -------------------------------------------------------------------------------------- 2138 ; Comes from: 2138 ; 2175 C True from color MACRO_Declare_Type_Array,Constrained 2138 ; -------------------------------------------------------------------------------------- 2138 2138 ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2139 0x2139 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2139 2139 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 213a ; -------------------------------------------------------------------------------------- 213a ; Comes from: 213a ; 2128 C False from color MACRO_Declare_Type_Array,Constrained 213a ; -------------------------------------------------------------------------------------- 213a 213a fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 213b 213b ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 213c 213c seq_b_timing 1 Latch Condition; Flow C cc=False 0x213f seq_br_type 4 Call False seq_branch_adr 213f 0x213f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 213d 213d seq_br_type 4 Call False; Flow C cc=False 0x2140 seq_branch_adr 2140 0x2140 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 213e 213e fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 213f ; -------------------------------------------------------------------------------------- 213f ; Comes from: 213f ; 213c C False from color 0x2138 213f ; -------------------------------------------------------------------------------------- 213f 213f seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2140 0x2140 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 2140 ; -------------------------------------------------------------------------------------- 2140 ; Comes from: 2140 ; 213d C False from color 0x2138 2140 ; -------------------------------------------------------------------------------------- 2140 2140 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 2141 ; -------------------------------------------------------------------------------------- 2141 ; Comes from: 2141 ; 2126 C False from color MACRO_Declare_Type_Array,Constrained 2141 ; -------------------------------------------------------------------------------------- 2141 2141 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2142 2142 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2143 2143 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2144 2144 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2145 2145 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2175 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2175 0x2175 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2146 2146 fiu_mem_start 4 continue; Flow C cc=True 0x2136 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2136 0x2136 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2147 2147 fiu_mem_start 4 continue; Flow C cc=True 0x215f ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 215f 0x215f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2148 2148 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2162 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2162 0x2162 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2d TR07:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2149 2149 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3270 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 214a 214a seq_b_timing 1 Latch Condition; Flow C cc=False 0x2166 seq_br_type 4 Call False seq_branch_adr 2166 0x2166 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 214b 214b fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 214c 214c ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 214d 214d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 214e 214e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 214f 214f val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2150 2150 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2151 2151 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x216e seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 216e 0x216e val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2152 2152 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 2153 2153 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 2154 2154 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x2170 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2170 0x2170 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2155 2155 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2156 2156 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1c TOP - 4 2157 2157 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 2158 2158 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x215b fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 215b 0x215b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2159 2159 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 215a 215a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 215b 215b fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 215c 215c ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 215d 215d typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 215e 215e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 215f ; -------------------------------------------------------------------------------------- 215f ; Comes from: 215f ; 2147 C True from color MACRO_Declare_Type_Array,Constrained 215f ; -------------------------------------------------------------------------------------- 215f 215f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2160 2160 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2161 2161 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2162 2162 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2163 2163 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2164 2164 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2165 2165 seq_br_type 3 Unconditional Branch; Flow J 0x214b seq_branch_adr 214b 0x214b val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2166 ; -------------------------------------------------------------------------------------- 2166 ; Comes from: 2166 ; 214a C False from color MACRO_Declare_Type_Array,Constrained 2166 ; -------------------------------------------------------------------------------------- 2166 2166 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2167 2167 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2168 2168 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 2169 2169 seq_b_timing 1 Latch Condition; Flow C cc=False 0x216c seq_br_type 4 Call False seq_branch_adr 216c 0x216c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 216a 216a seq_br_type 4 Call False; Flow C cc=False 0x216d seq_branch_adr 216d 0x216d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 216b 216b seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 216c ; -------------------------------------------------------------------------------------- 216c ; Comes from: 216c ; 2169 C False from color 0x2166 216c ; -------------------------------------------------------------------------------------- 216c 216c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 216d 0x216d seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 216d ; -------------------------------------------------------------------------------------- 216d ; Comes from: 216d ; 216a C False from color 0x2166 216d ; -------------------------------------------------------------------------------------- 216d 216d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 216e ; -------------------------------------------------------------------------------------- 216e ; Comes from: 216e ; 2151 C False from color MACRO_Declare_Type_Array,Constrained 216e ; -------------------------------------------------------------------------------------- 216e 216e typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 216f 216f ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1d TOP - 3 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2170 ; -------------------------------------------------------------------------------------- 2170 ; Comes from: 2170 ; 2154 C False from color MACRO_Declare_Type_Array,Constrained 2170 ; -------------------------------------------------------------------------------------- 2170 2170 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2171 2171 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2172 2172 seq_br_type 4 Call False; Flow C cc=False 0x2174 seq_branch_adr 2174 0x2174 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2173 2173 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 2174 ; -------------------------------------------------------------------------------------- 2174 ; Comes from: 2174 ; 2172 C False from color 0x2170 2174 ; -------------------------------------------------------------------------------------- 2174 2174 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2175 2175 ioc_fiubs 0 fiu ; Flow C cc=True 0x2138 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2138 0x2138 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 2176 2176 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 33 TR02:13 typ_alu_func 1a PASS_B typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2177 2177 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1 A_PLUS_B typ_b_adr 33 TR02:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2178 2178 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 2179 2179 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 217a 217a typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 32 TR08:12 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 217b 217b fiu_load_tar 1 hold_tar; Flow J cc=True 0x2185 fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2185 0x2185 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 217c 217c fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 217d 217d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 217e 217e seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 217f 217f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2180 2180 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 2181 2181 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2182 2182 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2183 2183 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2184 2184 fiu_load_tar 1 hold_tar; Flow J 0x2185 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2185 0x2185 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2185 2185 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x219d fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 219d 0x219d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 2186 2186 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2187 2187 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2188 2188 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2189 2189 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 218a 218a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x218d seq_br_type 0 Branch False seq_branch_adr 218d 0x218d seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 218b 218b seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 218c 218c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 218d 218d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 218e 218e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x219c fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 219c 0x219c seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 218f 218f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3270 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3270 0x3270 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2190 2190 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3270 seq_br_type 5 Call True seq_branch_adr 3270 0x3270 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 2191 2191 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 2192 2192 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 2193 2193 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 2194 2194 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2195 2195 ioc_fiubs 2 typ ; Flow J cc=True 0x2185 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2185 0x2185 seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2196 2196 seq_br_type 0 Branch False; Flow J cc=False 0x219b seq_branch_adr 219b 0x219b seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2197 2197 seq_br_type 0 Branch False; Flow J cc=False 0x219b seq_branch_adr 219b 0x219b seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2198 2198 seq_br_type 0 Branch False; Flow J cc=False 0x219b seq_branch_adr 219b 0x219b seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2199 2199 seq_br_type 0 Branch False; Flow J cc=False 0x219b seq_branch_adr 219b 0x219b seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 219a 219a seq_br_type 1 Branch True; Flow J cc=True 0x2185 seq_branch_adr 2185 0x2185 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 219b 219b ioc_fiubs 2 typ ; Flow J 0x2185 seq_br_type 3 Unconditional Branch seq_branch_adr 2185 0x2185 typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 219c 219c seq_br_type 3 Unconditional Branch; Flow J 0x2191 seq_branch_adr 2191 0x2191 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 219d 219d fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 219e 219e ioc_load_wdr 0 ; Flow C cc=False 0x21a4 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 21a4 0x21a4 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 0f GP0f 219f 219f ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 2 val_a_adr 05 GP05 val_alu_func 0 PASS_A 21a0 21a0 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 21a1 21a1 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 21a2 21a2 ioc_load_wdr 0 val_b_adr 39 VR02:19 val_frame 2 21a3 21a3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 21a4 ; -------------------------------------------------------------------------------------- 21a4 ; Comes from: 21a4 ; 219e C False from color MACRO_Declare_Type_Array,Constrained 21a4 ; -------------------------------------------------------------------------------------- 21a4 21a4 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 21a5 21a5 ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 21a6 21a6 val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU 21a7 21a7 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 21a8 21a8 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 21a9 21a9 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 21aa 21aa seq_br_type 3 Unconditional Branch; Flow J 0x2215 seq_branch_adr 2215 0x2215 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 21ab 21ab <halt> ; Flow R 21ac ; -------------------------------------------------------------------------------------- 21ac ; 0x034e Declare_Type Array,Constrained,Bounds_With_Object 21ac ; -------------------------------------------------------------------------------------- 21ac MACRO_Declare_Type_Array,Constrained,Bounds_With_Object: 21ac 21ac dispatch_brk_class 4 ; Flow J 0x2123 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21ac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21ad 21ad <halt> ; Flow R 21ae ; -------------------------------------------------------------------------------------- 21ae ; 0x035c Declare_Type Array,Constrained,Visible 21ae ; -------------------------------------------------------------------------------------- 21ae MACRO_Declare_Type_Array,Constrained,Visible: 21ae 21ae dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21ae seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21af 21af fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2123 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21b0 ; -------------------------------------------------------------------------------------- 21b0 ; 0x034f Declare_Type Array,Constrained,Visible,Bounds_With_Object 21b0 ; -------------------------------------------------------------------------------------- 21b0 MACRO_Declare_Type_Array,Constrained,Visible,Bounds_With_Object: 21b0 21b0 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b0 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b1 21b1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2123 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21b2 ; -------------------------------------------------------------------------------------- 21b2 ; 0x0353 Declare_Type Array,Constrained_Incomplete 21b2 ; -------------------------------------------------------------------------------------- 21b2 MACRO_Declare_Type_Array,Constrained_Incomplete: 21b2 21b2 dispatch_brk_class 4 ; Flow J 0x2123 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 21b3 21b3 <halt> ; Flow R 21b4 ; -------------------------------------------------------------------------------------- 21b4 ; 0x0346 Declare_Type Array,Constrained_Incomplete,Bounds_With_Object 21b4 ; -------------------------------------------------------------------------------------- 21b4 MACRO_Declare_Type_Array,Constrained_Incomplete,Bounds_With_Object: 21b4 21b4 dispatch_brk_class 4 ; Flow J 0x2123 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21b5 21b5 <halt> ; Flow R 21b6 ; -------------------------------------------------------------------------------------- 21b6 ; 0x0354 Declare_Type Array,Constrained_Incomplete,Visible 21b6 ; -------------------------------------------------------------------------------------- 21b6 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible: 21b6 21b6 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b6 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b7 21b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2123 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21b8 ; -------------------------------------------------------------------------------------- 21b8 ; 0x0347 Declare_Type Array,Constrained_Incomplete,Visible,Bounds_With_Object 21b8 ; -------------------------------------------------------------------------------------- 21b8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible,Bounds_With_Object: 21b8 21b8 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21b8 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21b9 21b9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2123 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2123 0x2123 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21ba ; -------------------------------------------------------------------------------------- 21ba ; 0x03a3 Complete_Type Heap_Access,By_Defining 21ba ; -------------------------------------------------------------------------------------- 21ba MACRO_Complete_Type_Heap_Access,By_Defining: 21ba 21ba dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 21ba fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21bb 21bb ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21bc 21bc fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 21bd 21bd fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21be 21be ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2212 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2212 0x2212 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 21bf 21bf fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a5 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21c0 21c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c 21c1 21c1 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 26 TR06:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 21c2 21c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x21c7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 21c7 0x21c7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_frame c 21c3 21c3 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 21c4 21c4 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 21c5 21c5 ioc_load_wdr 0 typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 21c6 21c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21c7 ; -------------------------------------------------------------------------------------- 21c7 ; Comes from: 21c7 ; 21c2 C #0x0 from color 0x2003 21c7 ; -------------------------------------------------------------------------------------- 21c7 21c7 fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cd 0x21cd typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21c8 21c8 fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cd 0x21cd typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21c9 21c9 fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21cd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cd 0x21cd typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21ca 21ca seq_br_type 3 Unconditional Branch; Flow J 0x21cb seq_branch_adr 21cb 0x21cb typ_c_adr 3b GP04 21cb 21cb seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 21cc 21cc fiu_mem_start 8 start_wr_if_false; Flow R cc=False ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21cd 0x21cd typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21cd 21cd typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 21ce 21ce fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21cf 21cf <halt> ; Flow R 21d0 ; -------------------------------------------------------------------------------------- 21d0 ; 0x03a2 Complete_Type Heap_Access,By_Renaming 21d0 ; -------------------------------------------------------------------------------------- 21d0 MACRO_Complete_Type_Heap_Access,By_Renaming: 21d0 21d0 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 21d0 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21d1 21d1 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21d2 21d2 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 21d3 21d3 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21d4 21d4 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x2212 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2212 0x2212 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 21d5 21d5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 2b VR06:0b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 21d6 21d6 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 21d7 21d7 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 21d8 21d8 fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 21d9 21d9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 21da 21da fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 21db 21db fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 21dc 21dc fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 21dd 21dd ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 21de 21de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21df 21df <halt> ; Flow R 21e0 ; -------------------------------------------------------------------------------------- 21e0 ; 0x03a1 Complete_Type Heap_Access,By_Constraining 21e0 ; -------------------------------------------------------------------------------------- 21e0 MACRO_Complete_Type_Heap_Access,By_Constraining: 21e0 21e0 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 21e0 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21e1 21e1 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21e2 21e2 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 21e3 21e3 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21e4 21e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2212 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2212 0x2212 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 21e5 21e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21e6 21e6 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 21e7 21e7 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 21e8 21e8 fiu_load_tar 1 hold_tar; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 21e9 21e9 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 21ea 21ea fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a7 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 21eb 21eb ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x21f1 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 21f1 0x21f1 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21ec 21ec fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 21ed 21ed fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 21ee 21ee fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 21ef 21ef ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 21f0 21f0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21f1 ; -------------------------------------------------------------------------------------- 21f1 ; Comes from: 21f1 ; 21eb C #0x0 from color 0x2003 21f1 ; -------------------------------------------------------------------------------------- 21f1 21f1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f2 21f2 fiu_mem_start 2 start-rd; Flow J 0x21f9 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 21f9 0x21f9 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 21f3 21f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f4 21f4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f5 21f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 21f6 21f6 seq_br_type 3 Unconditional Branch; Flow J 0x21fe seq_branch_adr 21fe 0x21fe seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 21f7 21f7 seq_br_type 3 Unconditional Branch; Flow J 0x21fe seq_branch_adr 21fe 0x21fe seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 21f8 21f8 fiu_mem_start 2 start-rd; Flow J 0x2206 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2206 0x2206 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 21f9 21f9 <default> 21fa 21fa fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a7 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 21fb 21fb <default> 21fc 21fc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 21fd 21fd fiu_mem_start 2 start-rd; Flow J 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3242 0x3242 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21fe 21fe seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 21ff 21ff seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2200 0x2200 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 05 GP05 2200 2200 fiu_mem_start 2 start-rd; Flow C 0x3242 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3242 0x3242 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2201 2201 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2202 2202 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2203 2203 seq_br_type 7 Unconditional Call; Flow C 0x2260 seq_branch_adr 2260 0x2260 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2204 2204 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2205 0x2205 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 2205 2205 seq_br_type 7 Unconditional Call; Flow C 0x3270 seq_branch_adr 3270 0x3270 2206 2206 <default> 2207 2207 fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x21fe fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 21fe 0x21fe val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2208 ; -------------------------------------------------------------------------------------- 2208 ; 0x03a0 Complete_Type Heap_Access,By_Component_Completion 2208 ; -------------------------------------------------------------------------------------- 2208 MACRO_Complete_Type_Heap_Access,By_Component_Completion: 2208 2208 dispatch_brk_class 4 ; Flow C cc=True 0x32a9 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2208 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2209 2209 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 220a 220a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 220b 220b fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 220c 220c fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 220d 220d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x220e seq_br_type f Unconditional Case Call seq_branch_adr 220e 0x220e seq_en_micro 0 220e ; -------------------------------------------------------------------------------------- 220e ; Comes from: 220e ; 220d C #0x0 from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 220e ; -------------------------------------------------------------------------------------- 220e 220e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 220f 220f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2210 2210 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2211 2211 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2212 2212 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2213 2213 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 2214 2214 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2215 2215 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2216 2216 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 2217 2217 fiu_mem_start 4 continue typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 2218 2218 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2222 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2222 0x2222 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2219 2219 fiu_load_var 1 hold_var; Flow J cc=True 0x221b fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 221b 0x221b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 221a 221a ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 221b 221b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 221c 221c fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 37 VR06:17 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 6 221d 221d ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 221e 221e fiu_load_var 1 hold_var; Flow J cc=True 0x2220 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2220 0x2220 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 221f 221f ioc_fiubs 0 fiu val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2220 2220 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2221 2221 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x2215 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2215 0x2215 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 08 GP08 2222 2222 fiu_load_var 1 hold_var; Flow J cc=True 0x2224 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2224 0x2224 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2223 2223 ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2224 2224 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2225 2225 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 08 GP08 val_b_adr 37 VR06:17 val_frame 6 2226 ; -------------------------------------------------------------------------------------- 2226 ; Comes from: 2226 ; 10f5 C from color 0x10d5 2226 ; 11cd C from color 0x111b 2226 ; 1233 C from color 0x11ff 2226 ; 123c C from color 0x11ff 2226 ; -------------------------------------------------------------------------------------- 2226 2226 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2227 2227 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2228 2228 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2229 2229 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a82 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 36 GP09 val_c_source 0 FIU_BUS 222a 222a fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 222b 222b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 222c 222c fiu_fill_mode_src 0 ; Flow J cc=False 0x223b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 223b 0x223b seq_cond_sel 65 CROSS_WORD_FIELD~ 222d 222d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 222e 222e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 222f 222f fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 2230 2230 fiu_fill_mode_src 0 ; Flow J cc=False 0x223d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 223d 0x223d seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2231 2231 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2232 2232 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2233 2233 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2234 2234 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2228 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2228 0x2228 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 2235 2235 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2236 2236 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 2237 2237 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2238 2238 fiu_fill_mode_src 0 ; Flow J cc=False 0x223f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 223f 0x223f seq_cond_sel 65 CROSS_WORD_FIELD~ 2239 2239 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223a 223a ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 223b 223b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223c 223c fiu_fill_mode_src 0 ; Flow J 0x222e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 222e 0x222e typ_mar_cntl 6 INCREMENT_MAR 223d 223d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 223e 223e fiu_fill_mode_src 0 ; Flow J 0x2232 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2232 0x2232 typ_mar_cntl 6 INCREMENT_MAR 223f 223f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2240 2240 fiu_fill_mode_src 0 ; Flow J 0x223a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 223a 0x223a typ_mar_cntl 6 INCREMENT_MAR 2241 2241 ioc_load_wdr 0 ; Flow C cc=True 0x2a82 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2242 2242 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2243 2243 fiu_fill_mode_src 0 ; Flow J cc=False 0x2251 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2251 0x2251 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2244 2244 fiu_fill_mode_src 0 ; Flow J cc=True 0x223a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 223a 0x223a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 2245 2245 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2246 ; -------------------------------------------------------------------------------------- 2246 ; Comes from: 2246 ; 10f8 C True from color 0x10d5 2246 ; 11d2 C from color 0x111b 2246 ; 123d C from color 0x11ff 2246 ; -------------------------------------------------------------------------------------- 2246 2246 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2247 2247 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 10 2248 2248 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 6 2249 2249 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 6 224a 224a fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 224b 224b fiu_fill_mode_src 0 ; Flow J cc=False 0x224e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 224e 0x224e seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 08 GP08 224c 224c fiu_fill_mode_src 0 ; Flow J cc=False 0x2241 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2241 0x2241 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 224d 224d ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 224e 224e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 224f 224f fiu_fill_mode_src 0 ; Flow J cc=False 0x2241 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2241 0x2241 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2250 2250 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2251 2251 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2252 2252 fiu_fill_mode_src 0 ; Flow J cc=False 0x2245 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2245 0x2245 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2253 2253 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2254 ; -------------------------------------------------------------------------------------- 2254 ; Comes from: 2254 ; 10f1 C from color 0x10d5 2254 ; 11b9 C from color 0x111b 2254 ; 1bdb C from color 0x0000 2254 ; 1be3 C from color 0x0000 2254 ; 1e4f C from color 0x0000 2254 ; 1e51 C from color 0x0000 2254 ; 1e59 C from color 0x0000 2254 ; 1e64 C from color 0x0000 2254 ; -------------------------------------------------------------------------------------- 2254 2254 val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2255 2255 fiu_mem_start 2 start-rd; Flow J cc=False 0x2258 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2258 0x2258 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2256 2256 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 2257 2257 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2258 2258 seq_b_timing 0 Early Condition; Flow J cc=True 0x225b seq_br_type 1 Branch True seq_branch_adr 225b 0x225b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2259 2259 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2255 seq_br_type 1 Branch True seq_branch_adr 2255 0x2255 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 225a 225a seq_br_type a Unconditional Return; Flow R val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 225b 225b ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x225a seq_br_type 8 Return True seq_branch_adr 225a 0x225a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 225c ; -------------------------------------------------------------------------------------- 225c ; Comes from: 225c ; 1be1 C from color 0x0000 225c ; 1e57 C from color 0x0000 225c ; 1e66 C from color 0x0000 225c ; 1e7b C from color 0x0000 225c ; 1e7d C from color 0x0000 225c ; -------------------------------------------------------------------------------------- 225c 225c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 225d 225d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22c1 0x22c1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 225e 225e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x225a seq_br_type 1 Branch True seq_branch_adr 225a 0x225a seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 225f 225f seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x225c seq_br_type 8 Return True seq_branch_adr 225c 0x225c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2260 ; -------------------------------------------------------------------------------------- 2260 ; Comes from: 2260 ; 0506 C from color 0x04fa 2260 ; 11c6 C from color 0x111b 2260 ; 122e C from color 0x11ff 2260 ; 1bad C from color 0x0a76 2260 ; 1bbb C from color 0x0a8a 2260 ; 1bcb C from color 0x0a9e 2260 ; 1bef C from color 0x0000 2260 ; 1f76 C from color 0x1f69 2260 ; 2203 C from color 0x21f6 2260 ; -------------------------------------------------------------------------------------- 2260 2260 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2261 0x2261 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2261 2261 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2262 2262 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22a6 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a6 0x22a6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2263 2263 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2264 2264 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2269 seq_br_type 0 Branch False seq_branch_adr 2269 0x2269 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2265 2265 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x226a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 226a 0x226a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2266 2266 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2267 2267 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 2268 2268 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x2260 seq_br_type 8 Return True seq_branch_adr 2260 0x2260 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 2269 2269 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 226a 0x226a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 226a 226a seq_br_type 3 Unconditional Branch; Flow J 0x2260 seq_branch_adr 2260 0x2260 typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 226b ; -------------------------------------------------------------------------------------- 226b ; Comes from: 226b ; 11bc C from color 0x111b 226b ; 1baf C from color 0x0a76 226b ; 1bbd C from color 0x0a8a 226b ; 1bce C from color 0x0a9e 226b ; 1bf3 C from color 0x0000 226b ; -------------------------------------------------------------------------------------- 226b 226b fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 226c 0x226c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 226c 226c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 226d 226d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22a0 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22a0 0x22a0 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 226e 226e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2272 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 2272 0x2272 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 08 GP08 226f 226f ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2270 2270 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2273 seq_br_type 1 Branch True seq_branch_adr 2273 0x2273 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2271 2271 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x226b seq_br_type 8 Return True seq_branch_adr 226b 0x226b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 2272 2272 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2273 0x2273 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2273 2273 seq_br_type 3 Unconditional Branch; Flow J 0x226b seq_branch_adr 226b 0x226b typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2274 ; -------------------------------------------------------------------------------------- 2274 ; Comes from: 2274 ; 227c C from color 0x227c 2274 ; 227e C from color 0x227e 2274 ; -------------------------------------------------------------------------------------- 2274 2274 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2275 2275 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2276 2276 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 31 VR02:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 2277 2277 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 2278 2278 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 2279 2279 seq_b_timing 1 Latch Condition; Flow J cc=True 0x227b seq_br_type 1 Branch True seq_branch_adr 227b 0x227b 227a 227a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 227b 227b fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 227c ; -------------------------------------------------------------------------------------- 227c ; Comes from: 227c ; 2292 C from color 0x228a 227c ; 229e C from color 0x2294 227c ; -------------------------------------------------------------------------------------- 227c 227c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2274 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2274 0x2274 typ_b_adr 06 GP06 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 227d 227d ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 227e ; -------------------------------------------------------------------------------------- 227e ; Comes from: 227e ; 229d C from color 0x2294 227e ; -------------------------------------------------------------------------------------- 227e 227e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2274 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2274 0x2274 typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 227f 227f ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2280 ; -------------------------------------------------------------------------------------- 2280 ; Comes from: 2280 ; 2291 C from color 0x228a 2280 ; -------------------------------------------------------------------------------------- 2280 2280 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 2281 2281 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2282 2282 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2283 2283 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 2284 2284 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2285 2285 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2286 2286 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2288 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2288 0x2288 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2287 2287 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2288 2288 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2289 2289 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 228a ; -------------------------------------------------------------------------------------- 228a ; Comes from: 228a ; 1192 C from color 0x111b 228a ; 1baa C from color 0x0a76 228a ; 1bb8 C from color 0x0a8a 228a ; 1bc7 C from color 0x0a9e 228a ; 1c44 C from color 0x0000 228a ; -------------------------------------------------------------------------------------- 228a 228a ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 228b 228b fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 228c 0x228c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 228c 228c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 228d 228d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 228e 228e fiu_load_oreg 1 hold_oreg; Flow C 0x22a0 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22a0 0x22a0 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 228f 228f seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2290 0x2290 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 2290 2290 seq_br_type 1 Branch True; Flow J cc=True 0x228b seq_branch_adr 228b 0x228b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2291 2291 ioc_fiubs 2 typ ; Flow C 0x2280 seq_br_type 7 Unconditional Call seq_branch_adr 2280 0x2280 typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2292 2292 ioc_fiubs 2 typ ; Flow C 0x227c seq_br_type 7 Unconditional Call seq_branch_adr 227c 0x227c typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2293 2293 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x228b seq_branch_adr 228b 0x228b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 2294 ; -------------------------------------------------------------------------------------- 2294 ; Comes from: 2294 ; 11b6 C from color 0x111b 2294 ; 1ba8 C from color 0x0a76 2294 ; 1bb6 C from color 0x0a8a 2294 ; 1bc4 C from color 0x0a9e 2294 ; 1c3f C from color 0x0000 2294 ; -------------------------------------------------------------------------------------- 2294 2294 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 2295 2295 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2296 0x2296 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2296 2296 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2297 2297 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2298 2298 fiu_mem_start 2 start-rd; Flow C cc=True 0x22a6 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a6 0x22a6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2299 2299 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 229a 229a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 229b 229b seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 229c 0x229c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 229c 229c seq_br_type 1 Branch True; Flow J cc=True 0x2295 seq_branch_adr 2295 0x2295 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 229d 229d ioc_fiubs 2 typ ; Flow C 0x227e seq_br_type 7 Unconditional Call seq_branch_adr 227e 0x227e typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 229e 229e ioc_fiubs 2 typ ; Flow C 0x227c seq_br_type 7 Unconditional Call seq_branch_adr 227c 0x227c typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 229f 229f seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x2295 seq_branch_adr 2295 0x2295 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22a0 ; -------------------------------------------------------------------------------------- 22a0 ; Comes from: 22a0 ; 226d C from color 0x226b 22a0 ; 228e C from color 0x228a 22a0 ; -------------------------------------------------------------------------------------- 22a0 22a0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22a3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22a3 0x22a3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22a1 22a1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a2 22a2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22a3 22a3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22a4 22a4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22a5 22a5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22a6 ; -------------------------------------------------------------------------------------- 22a6 ; Comes from: 22a6 ; 2262 C True from color 0x2260 22a6 ; 2298 C True from color 0x2294 22a6 ; 22ae C True from color 0x09a6 22a6 ; -------------------------------------------------------------------------------------- 22a6 22a6 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 22a7 22a7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 22a8 ; -------------------------------------------------------------------------------------- 22a8 ; Comes from: 22a8 ; 1bdf C from color 0x0000 22a8 ; 1e55 C from color 0x0000 22a8 ; -------------------------------------------------------------------------------------- 22a8 22a8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22a9 0x22a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22a9 22a9 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22aa 22aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c1 0x22c1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22ab 22ab seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22a8 seq_branch_adr 22a8 0x22a8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22ac ; -------------------------------------------------------------------------------------- 22ac ; Comes from: 22ac ; 1bd9 C from color 0x0000 22ac ; 1e4d C from color 0x0000 22ac ; -------------------------------------------------------------------------------------- 22ac 22ac fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22ad 0x22ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22ad 22ad seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22ae 22ae fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22a6 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22a6 0x22a6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22af 22af typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22b0 22b0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22b1 22b1 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ac seq_branch_adr 22ac 0x22ac seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22b2 ; -------------------------------------------------------------------------------------- 22b2 ; Comes from: 22b2 ; 1e62 C from color 0x0000 22b2 ; -------------------------------------------------------------------------------------- 22b2 22b2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22b3 0x22b3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22b3 22b3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22b8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22b8 0x22b8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22b4 22b4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22b5 22b5 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22b6 22b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2a82 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22b7 22b7 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22b2 seq_branch_adr 22b2 0x22b2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22b8 22b8 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22b9 22b9 fiu_fill_mode_src 0 ; Flow J 0x22b5 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 22b5 0x22b5 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22ba ; -------------------------------------------------------------------------------------- 22ba ; Comes from: 22ba ; 1e68 C from color 0x0000 22ba ; -------------------------------------------------------------------------------------- 22ba 22ba fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22bb 0x22bb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22bb 22bb fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22be seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22be 0x22be seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22bc 22bc fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22c1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c1 0x22c1 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22bd 22bd seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ba seq_branch_adr 22ba 0x22ba seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22be 22be fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22bf 22bf fiu_fill_mode_src 0 ; Flow C 0x22c1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22c1 0x22c1 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22c0 22c0 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ba seq_branch_adr 22ba 0x22ba seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22c1 ; -------------------------------------------------------------------------------------- 22c1 ; Comes from: 22c1 ; 225d C from color 0x1b7c 22c1 ; 22aa C from color 0x09a6 22c1 ; 22bc C from color 0x09a6 22c1 ; 22bf C from color 0x09a6 22c1 ; -------------------------------------------------------------------------------------- 22c1 22c1 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22c3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22c3 0x22c3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22c2 22c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22c3 22c3 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22c4 22c4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22c5 22c5 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 val_rand a PASS_B_HIGH 22c6 22c6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3d VR06:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 22c7 22c7 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x22eb fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22eb 0x22eb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22c8 22c8 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=#0x0 0x22cb fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 22cb 0x22cb seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22c9 22c9 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 22ca 22ca ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 22cb ; -------------------------------------------------------------------------------------- 22cb ; Comes from: 22cb ; 22c8 C #0x0 from color 0x0000 22cb ; -------------------------------------------------------------------------------------- 22cb 22cb seq_br_type 3 Unconditional Branch; Flow J 0x3400 seq_branch_adr 3400 0x3400 seq_en_micro 0 seq_random 05 ? typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 22cc 22cc seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 22cd 22cd seq_br_type 3 Unconditional Branch; Flow J 0x22cf seq_branch_adr 22cf 0x22cf seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 22ce 22ce seq_br_type 3 Unconditional Branch; Flow J 0x22cf seq_branch_adr 22cf 0x22cf seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 22cf 22cf seq_br_type 0 Branch False; Flow J cc=False 0x22ed seq_branch_adr 22ed 0x22ed seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22d0 22d0 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 22d1 22d1 ioc_tvbs 2 fiu+val; Flow C cc=True 0x22d7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22d7 0x22d7 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 22d2 22d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 22d3 0x22d3 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 0b GP0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 22d3 22d3 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 5 val_rand a PASS_B_HIGH 22d4 22d4 ioc_load_wdr 0 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 22d5 22d5 ioc_adrbs 2 typ ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 22d6 22d6 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 22d7 22d7 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x22d6 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 22d6 0x22d6 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22d8 22d8 ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 22d9 22d9 seq_br_type 0 Branch False; Flow J cc=False 0x22ec seq_branch_adr 22ec 0x22ec seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22da 22da fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_a_adr 3a VR12:1a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 22db 22db fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 24 VR05:04 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 22dc 22dc ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x22e2 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 22e2 0x22e2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 22dd 22dd fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x22ec fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ec 0x22ec seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR 22de 22de fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22dc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 22dc 0x22dc seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 22df 22df fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ec fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 4c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ec 0x22ec seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 22e0 22e0 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 22e1 22e1 fiu_load_tar 1 hold_tar; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE 22e2 22e2 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ec fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ec 0x22ec seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 22e3 22e3 fiu_mem_start 3 start-wr ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 7 22e4 22e4 ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 7 22e5 22e5 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x22ea fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 22ea 0x22ea seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 0d GP0d val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22e6 22e6 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 22e7 22e7 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x22ec fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 22ec 0x22ec seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 22e8 22e8 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0d GP0d 22e9 22e9 ioc_adrbs 2 typ ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 22ea ; -------------------------------------------------------------------------------------- 22ea ; Comes from: 22ea ; 22e5 C True from color 0x0000 22ea ; -------------------------------------------------------------------------------------- 22ea 22ea seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1 22eb 22eb fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x22ed fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 22ed 0x22ed seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 22ec 22ec seq_br_type 3 Unconditional Branch; Flow J 0x22ed seq_branch_adr 22ed 0x22ed seq_en_micro 0 seq_random 06 Pop_stack+? 22ed 22ed fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 22ee 22ee fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x22c5 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 22c5 0x22c5 typ_a_adr 05 GP05 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A 22ef 22ef <halt> ; Flow R 22f0 ; -------------------------------------------------------------------------------------- 22f0 ; 0x0358 Declare_Type Array,Incomplete 22f0 ; -------------------------------------------------------------------------------------- 22f0 MACRO_Declare_Type_Array,Incomplete: 22f0 22f0 dispatch_brk_class 4 ; Flow J 0x22f1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 22f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f1 0x22f1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 22f1 22f1 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 22f2 22f2 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 22f3 22f3 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 22f4 22f4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 22f5 22f5 fiu_mem_start 4 continue fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 22f6 22f6 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x22f7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 22f7 0x22f7 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 24 TR09:04 typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 22f7 22f7 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x22fb fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 22fb 0x22fb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 22f8 22f8 fiu_mem_start 4 continue; Flow J cc=False 0x22f7 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 22f7 0x22f7 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 22f9 22f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 22fa 22fa fiu_mem_start 3 start-wr; Flow J 0x22f7 seq_br_type 3 Unconditional Branch seq_branch_adr 22f7 0x22f7 22fb 22fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 22fc 22fc fiu_mem_start 3 start-wr val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 32 VR06:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 22fd 22fd fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 22fe 22fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x22fe fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22fe 0x22fe seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 37 VR06:17 val_frame 6 22ff 22ff fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR11:09 val_frame 11 2300 2300 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 2301 0x2301 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2301 2301 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2302 0x2302 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2302 2302 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2303 2303 <halt> ; Flow R 2304 ; -------------------------------------------------------------------------------------- 2304 ; 0x0359 Declare_Type Array,Incomplete,Visible 2304 ; -------------------------------------------------------------------------------------- 2304 MACRO_Declare_Type_Array,Incomplete,Visible: 2304 2304 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2304 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2305 2305 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x22f1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f1 0x22f1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2306 ; -------------------------------------------------------------------------------------- 2306 ; 0x034b Declare_Type Array,Incomplete,Bounds_With_Object 2306 ; -------------------------------------------------------------------------------------- 2306 MACRO_Declare_Type_Array,Incomplete,Bounds_With_Object: 2306 2306 dispatch_brk_class 4 ; Flow J 0x22f1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2306 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f1 0x22f1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2307 2307 <halt> ; Flow R 2308 ; -------------------------------------------------------------------------------------- 2308 ; 0x034c Declare_Type Array,Incomplete,Visible,Bounds_With_Object 2308 ; -------------------------------------------------------------------------------------- 2308 MACRO_Declare_Type_Array,Incomplete,Visible,Bounds_With_Object: 2308 2308 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2308 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2309 2309 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x22f1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 22f1 0x22f1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 230a ; -------------------------------------------------------------------------------------- 230a ; 0x0340 Complete_Type Array,By_Component_Completion 230a ; -------------------------------------------------------------------------------------- 230a MACRO_Complete_Type_Array,By_Component_Completion: 230a 230a dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 230a fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 230b 230b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 230c 230c fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 230d 230d seq_b_timing 0 Early Condition; Flow J cc=True 0x230e ; Flow J cc=#0x0 0x230e seq_br_type b Case False seq_branch_adr 230e 0x230e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 230e 230e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 230f 230f fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x2312 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2312 0x2312 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2310 2310 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2311 2311 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 2312 2312 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 2313 2313 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3277 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2314 2314 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 2d VR11:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 2315 2315 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2316 2316 seq_br_type 3 Unconditional Branch; Flow J 0x2317 seq_branch_adr 2317 0x2317 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 2317 2317 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2318 2318 ioc_load_wdr 0 2319 2319 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 231a 231a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 231b 231b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 231c 231c seq_b_timing 1 Latch Condition; Flow J cc=True 0x2322 seq_br_type 1 Branch True seq_branch_adr 2322 0x2322 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 231d 231d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 231e 231e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 231f 231f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2321 seq_br_type 1 Branch True seq_branch_adr 2321 0x2321 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 2320 2320 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2322 seq_br_type 1 Branch True seq_branch_adr 2322 0x2322 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2321 2321 ioc_tvbs 1 typ+fiu; Flow J 0x2322 seq_br_type 3 Unconditional Branch seq_branch_adr 2322 0x2322 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2322 2322 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2326 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2326 0x2326 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2323 2323 <default> 2324 2324 ioc_tvbs c mem+mem+csa+dummy val_a_adr 2b VR06:0b val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2325 2325 seq_br_type 3 Unconditional Branch; Flow J 0x2317 seq_branch_adr 2317 0x2317 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2326 2326 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 3b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 01 GP01 2327 2327 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert 2328 2328 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2329 2329 ioc_load_wdr 0 ; Flow J 0x230e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 230e 0x230e val_b_adr 02 GP02 232a ; -------------------------------------------------------------------------------------- 232a ; 0x0342 Complete_Type Array,By_Renaming 232a ; -------------------------------------------------------------------------------------- 232a MACRO_Complete_Type_Array,By_Renaming: 232a 232a dispatch_brk_class 4 ; Flow C cc=True 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 232a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 232b 232b fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 232c 232c fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 232d 232d fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a5 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_rand 9 PASS_A_HIGH val_c_adr 39 GP06 val_c_source 0 FIU_BUS 232e 232e fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 232f 232f fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand e CHECK_CLASS_SYSTEM_B 2330 2330 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2331 2331 fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2332 2332 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2333 2333 fiu_mem_start 4 continue; Flow C cc=True 0x3277 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 2334 2334 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 2335 2335 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2336 2336 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 2337 2337 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2338 2338 fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2339 2339 ioc_load_wdr 0 ; Flow J cc=True 0x233f ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 233f 0x233f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 233a 233a fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 233b 233b fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 233c 233c ioc_load_wdr 0 ; Flow J cc=False 0x2337 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2337 0x2337 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 05 GP05 typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 05 GP05 233d 233d seq_b_timing 1 Latch Condition; Flow C cc=True 0x2342 seq_br_type 5 Call True seq_branch_adr 2342 0x2342 typ_csa_cntl 3 POP_CSA 233e 233e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 233f 233f fiu_mem_start 3 start-wr; Flow J cc=False 0x2341 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2341 0x2341 seq_cond_sel 64 OFFSET_REGISTER_???? seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2340 2340 fiu_load_oreg 1 hold_oreg; Flow J 0x233c fiu_mem_start 4 continue fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 233c 0x233c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2341 2341 fiu_mem_start 4 continue; Flow J 0x233c seq_br_type 3 Unconditional Branch seq_branch_adr 233c 0x233c seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2342 ; -------------------------------------------------------------------------------------- 2342 ; Comes from: 2342 ; 233d C True from color MACRO_Complete_Type_Array,By_Renaming 2342 ; -------------------------------------------------------------------------------------- 2342 2342 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2343 2343 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2344 2344 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2345 2345 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x2342 seq_br_type 8 Return True seq_branch_adr 2342 0x2342 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2346 ; -------------------------------------------------------------------------------------- 2346 ; 0x0305 Complete_Type Variant_Record,By_Constraining_Incomplete 2346 ; -------------------------------------------------------------------------------------- 2346 MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete: 2346 2346 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2346 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH 2347 2347 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2348 2348 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2349 2349 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2f TR13:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 234a 234a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 234b 234b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR13:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 234c 234c fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 234d 234d fiu_mem_start 4 continue typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 234e 234e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 24 TR09:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 234f 234f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2350 2350 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 39 VR13:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 2351 2351 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2352 2352 seq_b_timing 0 Early Condition; Flow J cc=True 0x2356 seq_br_type 1 Branch True seq_branch_adr 2356 0x2356 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2353 2353 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2355 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2355 0x2355 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 2354 2354 seq_br_type 3 Unconditional Branch; Flow J 0x2356 seq_branch_adr 2356 0x2356 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2355 2355 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32ab seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2356 2356 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER 2357 2357 seq_br_type 7 Unconditional Call; Flow C 0x2480 seq_branch_adr 2480 0x2480 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2358 2358 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2359 2359 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 235a 235a ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 235b 235b typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 235c 235c fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 235d 235d fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x236c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 236c 0x236c typ_a_adr 14 ZEROS 235e 235e fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 235f 235f fiu_mem_start 4 continue typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2360 2360 ioc_load_wdr 0 ; Flow C 0x236f seq_br_type 7 Unconditional Call seq_branch_adr 236f 0x236f seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2361 2361 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value 2362 2362 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2363 2363 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 2364 2364 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 2365 2365 ioc_fiubs 0 fiu ; Flow J 0x2366 seq_br_type 2 Push (branch address) seq_branch_adr 2367 0x2367 seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2366 2366 seq_br_type 3 Unconditional Branch; Flow J 0x237f seq_branch_adr 237f 0x237f seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2367 2367 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2368 2368 ioc_load_wdr 0 2369 2369 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 236a 236a seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 236b 236b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 236c ; -------------------------------------------------------------------------------------- 236c ; Comes from: 236c ; 235d C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 236c ; -------------------------------------------------------------------------------------- 236c 236c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 22 TR02:02 typ_frame 2 236d 236d fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 236e 236e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 236f ; -------------------------------------------------------------------------------------- 236f ; Comes from: 236f ; 2360 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 236f ; -------------------------------------------------------------------------------------- 236f 236f fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2370 0x2370 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2370 2370 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2371 2371 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2372 2372 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 2373 2373 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x23ed ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23ed 0x23ed seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2374 2374 <default> 2375 2375 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2376 2376 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2377 2377 seq_b_timing 1 Latch Condition; Flow J cc=True 0x237a seq_br_type 1 Branch True seq_branch_adr 237a 0x237a seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 2378 2378 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 2379 2379 ioc_load_wdr 0 ; Flow J 0x236f seq_br_type 3 Unconditional Branch seq_branch_adr 236f 0x236f typ_b_adr 2b TR08:0b typ_frame 8 val_b_adr 05 GP05 237a 237a fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 237b 237b <default> 237c 237c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 237d 237d ioc_load_wdr 0 ; Flow J 0x236f seq_br_type 3 Unconditional Branch seq_branch_adr 236f 0x236f seq_en_micro 0 typ_b_adr 06 GP06 val_b_adr 0f GP0f 237e 237e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 237f 237f fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2380 0x2380 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2380 2380 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2381 2381 fiu_mem_start 3 start-wr; Flow J 0x237e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 237e 0x237e typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2382 2382 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2383 2383 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2384 0x2384 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2384 2384 seq_br_type 2 Push (branch address); Flow J 0x2385 seq_branch_adr 2382 0x2382 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 2385 2385 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238a 0x238a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2386 2386 seq_br_type 7 Unconditional Call; Flow C 0x238e seq_branch_adr 238e 0x238e 2387 2387 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2388 2388 seq_br_type 3 Unconditional Branch; Flow J 0x237f seq_branch_adr 237f 0x237f 2389 2389 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 238a 238a fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x238c ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 238c 0x238c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 238b 238b ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x2389 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2389 0x2389 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 238c ; -------------------------------------------------------------------------------------- 238c ; Comes from: 238c ; 238a C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238c ; -------------------------------------------------------------------------------------- 238c 238c seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 238d 238d fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 238e ; -------------------------------------------------------------------------------------- 238e ; Comes from: 238e ; 2386 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238e ; 23b9 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238e ; 23dd C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238e ; 23e8 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 238e ; -------------------------------------------------------------------------------------- 238e 238e fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 238f 238f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var 2390 2390 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2391 2391 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2392 2392 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2393 0x2393 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2393 2393 seq_br_type 2 Push (branch address); Flow J 0x2394 seq_branch_adr 2391 0x2391 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2394 2394 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2395 2395 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2396 0x2396 2396 2396 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_frame 4 2397 2397 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2398 2398 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2399 2399 fiu_mem_start 2 start-rd; Flow J cc=True 0x23ad ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 23ad 0x23ad typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 239a 239a typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 239b 239b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 239c 239c fiu_load_tar 1 hold_tar; Flow C 0x323d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 239d 239d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 239e 239e fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 239f 239f ioc_load_wdr 0 ; Flow C cc=True 0x32ab ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 23a0 23a0 fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 23a1 23a1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x23a5 seq_br_type 1 Branch True seq_branch_adr 23a5 0x23a5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 23a2 23a2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 23a3 23a3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 23a4 23a4 fiu_load_var 1 hold_var; Flow J 0x23b1 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 23b1 0x23b1 seq_en_micro 0 val_a_adr 0f GP0f 23a5 23a5 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x23ab ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23ab 0x23ab seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 23a6 23a6 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 23a7 23a7 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23aa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 23aa 0x23aa seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 23a8 23a8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23a5 seq_br_type 1 Branch True seq_branch_adr 23a5 0x23a5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 23a9 23a9 seq_br_type 3 Unconditional Branch; Flow J 0x23a2 seq_branch_adr 23a2 0x23a2 seq_en_micro 0 23aa 23aa fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x23b1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 23b1 0x23b1 seq_en_micro 0 23ab ; -------------------------------------------------------------------------------------- 23ab ; Comes from: 23ab ; 23a5 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23ab ; -------------------------------------------------------------------------------------- 23ab 23ab seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 23ac 23ac fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 23ad 23ad fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 23ae 23ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 23af 23af ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 23b0 23b0 fiu_load_tar 1 hold_tar; Flow C 0x323d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23b1 23b1 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 23b2 23b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x23b5 seq_br_type 5 Call True seq_branch_adr 23b5 0x23b5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 23b3 23b3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 23b4 23b4 seq_br_type a Unconditional Return; Flow R 23b5 ; -------------------------------------------------------------------------------------- 23b5 ; Comes from: 23b5 ; 23b2 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23b5 ; -------------------------------------------------------------------------------------- 23b5 23b5 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 23b6 23b6 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23b7 0x23b7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23b7 23b7 seq_br_type 2 Push (branch address); Flow J 0x23b8 seq_branch_adr 23b6 0x23b6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 23b8 23b8 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238a 0x238a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 23b9 23b9 seq_br_type 7 Unconditional Call; Flow C 0x238e seq_branch_adr 238e 0x238e 23ba 23ba fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23bb 23bb seq_b_timing 1 Latch Condition; Flow J cc=True 0x2391 seq_br_type 1 Branch True seq_branch_adr 2391 0x2391 23bc 23bc typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 23bd 23bd seq_br_type 3 Unconditional Branch; Flow J 0x2391 seq_branch_adr 2391 0x2391 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 23be ; -------------------------------------------------------------------------------------- 23be ; 0x0304 Complete_Type Variant_Record,By_Completing_Constraint 23be ; -------------------------------------------------------------------------------------- 23be MACRO_Complete_Type_Variant_Record,By_Completing_Constraint: 23be 23be dispatch_brk_class 4 ; Flow C cc=True 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23be fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 23bf 23bf fiu_mem_start 4 continue typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 23c0 23c0 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23c1 23c1 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a7 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 23c2 23c2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23c3 23c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 23c4 23c4 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3277 fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 23c5 23c5 fiu_mem_start 4 continue; Flow C cc=True 0x32a7 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 23c6 23c6 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 23c7 23c7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 23c8 23c8 ioc_tvbs 2 fiu+val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 23c9 23c9 seq_br_type 7 Unconditional Call; Flow C 0x2480 seq_branch_adr 2480 0x2480 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 23ca 23ca fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_b_adr 09 GP09 23cb 23cb fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23cc 23cc fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23cd 23cd fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 23ce 23ce ioc_tvbs 2 fiu+val; Flow J cc=True 0x23e0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 23e0 0x23e0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 23cf 23cf fiu_load_var 1 hold_var; Flow C 0x237f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 237f 0x237f typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 23d0 23d0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 23d1 23d1 ioc_fiubs 0 fiu ; Flow C 0x23da seq_br_type 7 Unconditional Call seq_branch_adr 23da 0x23da typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 23d2 23d2 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 23d3 23d3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 23d4 23d4 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 23d5 23d5 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 23d6 23d6 ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 10 TOP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 23d7 23d7 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 23d8 23d8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x25ac seq_br_type 1 Branch True seq_branch_adr 25ac 0x25ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 5 23d9 23d9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 23da 23da fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23db 0x23db seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23db 23db seq_br_type 2 Push (branch address); Flow J 0x23dc seq_branch_adr 23da 0x23da seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 23dc 23dc fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238a 0x238a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23dd 23dd seq_br_type 7 Unconditional Call; Flow C 0x238e seq_branch_adr 238e 0x238e 23de 23de fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23df 23df seq_br_type 3 Unconditional Branch; Flow J 0x237f seq_branch_adr 237f 0x237f 23e0 23e0 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x23e1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 23d2 0x23d2 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 23e1 23e1 ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 23e2 23e2 fiu_load_var 1 hold_var; Flow C 0x2391 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2391 0x2391 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 23e3 23e3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 23e4 23e4 ioc_fiubs 0 fiu ; Flow J 0x23e5 seq_br_type 3 Unconditional Branch seq_branch_adr 23e5 0x23e5 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 23e5 23e5 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23e6 0x23e6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23e6 23e6 seq_br_type 2 Push (branch address); Flow J 0x23e7 seq_branch_adr 23b6 0x23b6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 23e7 23e7 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x238a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 238a 0x238a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 23e8 23e8 seq_br_type 7 Unconditional Call; Flow C 0x238e seq_branch_adr 238e 0x238e 23e9 23e9 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23ea 23ea seq_b_timing 1 Latch Condition; Flow J cc=True 0x2391 seq_br_type 1 Branch True seq_branch_adr 2391 0x2391 23eb 23eb typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 23ec 23ec seq_br_type 3 Unconditional Branch; Flow J 0x2391 seq_branch_adr 2391 0x2391 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 23ed ; -------------------------------------------------------------------------------------- 23ed ; Comes from: 23ed ; 2373 C True from color 0x236f 23ed ; -------------------------------------------------------------------------------------- 23ed 23ed seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 23ee 23ee fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 23ef 23ef <halt> ; Flow R 23f0 ; -------------------------------------------------------------------------------------- 23f0 ; 0x031c Declare_Type Variant_Record,Constrained,Visible 23f0 ; -------------------------------------------------------------------------------------- 23f0 MACRO_Declare_Type_Variant_Record,Constrained,Visible: 23f0 23f0 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23f0 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 23f1 23f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x23f3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 23f3 0x23f3 seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 22 VR06:02 val_frame 6 23f2 ; -------------------------------------------------------------------------------------- 23f2 ; 0x031b Declare_Type Variant_Record,Constrained 23f2 ; -------------------------------------------------------------------------------------- 23f2 MACRO_Declare_Type_Variant_Record,Constrained: 23f2 23f2 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23f2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 39 VR02:19 val_frame 2 23f3 23f3 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 23f4 23f4 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR08:09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 23f5 23f5 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 23f6 23f6 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 23f7 23f7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 23f8 23f8 seq_b_timing 0 Early Condition; Flow J cc=True 0x23fc seq_br_type 1 Branch True seq_branch_adr 23fc 0x23fc seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23f9 23f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x23fb fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 23fb 0x23fb seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 23fa 23fa seq_br_type 3 Unconditional Branch; Flow J 0x23fc seq_branch_adr 23fc 0x23fc val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23fb 23fb ioc_tvbs 2 fiu+val; Flow C cc=False 0x32ab seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23fc 23fc fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 val_a_adr 17 LOOP_COUNTER 23fd 23fd seq_br_type 7 Unconditional Call; Flow C 0x2480 seq_branch_adr 2480 0x2480 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 23fe 23fe fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 23ff 23ff fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2400 2400 ioc_fiubs 0 fiu ; Flow J cc=True 0x241e seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 241e 0x241e seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2401 2401 seq_br_type 7 Unconditional Call; Flow C 0x2409 seq_branch_adr 2409 0x2409 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2402 2402 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2403 2403 ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2404 2404 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 2405 2405 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 2406 2406 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 2407 2407 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 06 GP06 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2408 2408 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2409 ; -------------------------------------------------------------------------------------- 2409 ; Comes from: 2409 ; 2401 C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 2409 ; 241f C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 2409 ; -------------------------------------------------------------------------------------- 2409 2409 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 240a 240a fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 240b 240b fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 240c 240c fiu_mem_start a start_continue_if_false typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 240d 240d fiu_load_var 1 hold_var; Flow C 0x2413 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 2413 0x2413 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_b_adr 02 GP02 240e 240e fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 240f 240f fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2410 2410 seq_br_type 7 Unconditional Call; Flow C 0x2422 seq_branch_adr 2422 0x2422 seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2411 2411 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 2412 2412 ioc_fiubs 0 fiu ; Flow J 0x2444 seq_br_type 3 Unconditional Branch seq_branch_adr 2444 0x2444 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2413 ; -------------------------------------------------------------------------------------- 2413 ; Comes from: 2413 ; 240d C from color 0x2409 2413 ; -------------------------------------------------------------------------------------- 2413 2413 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2414 0x2414 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2414 2414 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2415 2415 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2416 2416 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 2417 2417 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2418 2418 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2450 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2450 0x2450 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2419 2419 seq_b_timing 1 Latch Condition; Flow J cc=True 0x241c seq_br_type 1 Branch True seq_branch_adr 241c 0x241c seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_a_adr 2b TR08:0b typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 241a 241a fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 241b 241b ioc_load_wdr 0 ; Flow J 0x2413 seq_br_type 3 Unconditional Branch seq_branch_adr 2413 0x2413 typ_b_adr 06 GP06 val_b_adr 05 GP05 241c 241c fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 241d 241d fiu_mem_start 3 start-wr; Flow J 0x241b ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 241b 0x241b typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 241e 241e fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 241f 241f ioc_tvbs 1 typ+fiu; Flow C 0x2409 seq_br_type 7 Unconditional Call seq_branch_adr 2409 0x2409 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2420 2420 fiu_mem_start 3 start-wr; Flow C cc=True 0x32ab ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 0 PASS_A 2421 2421 ioc_load_wdr 0 ; Flow J 0x2402 seq_br_type 3 Unconditional Branch seq_branch_adr 2402 0x2402 typ_b_adr 01 GP01 val_b_adr 02 GP02 2422 ; -------------------------------------------------------------------------------------- 2422 ; Comes from: 2422 ; 2410 C from color 0x2409 2422 ; -------------------------------------------------------------------------------------- 2422 2422 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2423 0x2423 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2423 2423 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2424 2424 fiu_load_var 1 hold_var; Flow C cc=True 0x2450 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2450 0x2450 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2425 2425 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2422 seq_br_type 1 Branch True seq_branch_adr 2422 0x2422 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3a GP05 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_frame 7 2426 2426 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2427 2427 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2428 2428 fiu_mem_start 2 start-rd; Flow J cc=True 0x243c ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 243c 0x243c typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2429 2429 typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 242a 242a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 242b 242b fiu_load_tar 1 hold_tar; Flow C 0x323d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 242c 242c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 242d 242d fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 242e 242e ioc_load_wdr 0 ; Flow C cc=True 0x32ab ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 242f 242f fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 2430 2430 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2434 seq_br_type 1 Branch True seq_branch_adr 2434 0x2434 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2431 2431 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 2432 2432 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2433 2433 fiu_load_var 1 hold_var; Flow J 0x2440 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2440 0x2440 seq_en_micro 0 val_a_adr 0f GP0f 2434 2434 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x243a ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 243a 0x243a seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 2435 2435 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2436 2436 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2439 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2439 0x2439 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 2437 2437 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2434 seq_br_type 1 Branch True seq_branch_adr 2434 0x2434 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 2438 2438 seq_br_type 3 Unconditional Branch; Flow J 0x2431 seq_branch_adr 2431 0x2431 seq_en_micro 0 2439 2439 fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x2440 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2440 0x2440 seq_en_micro 0 243a ; -------------------------------------------------------------------------------------- 243a ; Comes from: 243a ; 2434 C True from color 0x0000 243a ; -------------------------------------------------------------------------------------- 243a 243a seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 243b 243b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 243c 243c fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 243d 243d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 243e 243e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a7 seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 243f 243f fiu_load_tar 1 hold_tar; Flow C 0x323d fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2440 2440 ioc_tvbs 1 typ+fiu; Flow J 0x2441 seq_br_type 2 Push (branch address) seq_branch_adr 2422 0x2422 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2441 2441 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2443 seq_br_type 5 Call True seq_branch_adr 2443 0x2443 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 2442 2442 fiu_mem_start 3 start-wr; Flow J 0x32fc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 2443 ; -------------------------------------------------------------------------------------- 2443 ; Comes from: 2443 ; 2441 C True from color 0x0000 2443 ; -------------------------------------------------------------------------------------- 2443 2443 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2444 2444 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2445 0x2445 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2445 2445 seq_br_type 2 Push (branch address); Flow J 0x2446 seq_branch_adr 2444 0x2444 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 2446 2446 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x244e fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 244e 0x244e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2447 2447 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 2448 2448 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2449 2449 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2450 fiu_mem_start 8 start_wr_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2450 0x2450 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 244a 244a seq_b_timing 1 Latch Condition; Flow J cc=True 0x2422 seq_br_type 1 Branch True seq_branch_adr 2422 0x2422 244b 244b typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 244c 244c seq_br_type 3 Unconditional Branch; Flow J 0x2422 seq_branch_adr 2422 0x2422 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 244d 244d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 244e 244e fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2450 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2450 0x2450 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 244f 244f ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x244d seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 244d 0x244d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 2450 ; -------------------------------------------------------------------------------------- 2450 ; Comes from: 2450 ; 2418 C True from color 0x2413 2450 ; 2424 C True from color 0x0000 2450 ; 2449 C True from color 0x0000 2450 ; 244e C True from color 0x2409 2450 ; -------------------------------------------------------------------------------------- 2450 2450 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 2451 2451 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 2452 ; -------------------------------------------------------------------------------------- 2452 ; Comes from: 2452 ; 09f3 C from color MACRO_Execute_Any,Size 2452 ; 1311 C from color MACRO_Declare_Variable_Variant_Record,Duplicate 2452 ; 1747 C from color 0x09ac 2452 ; 17a5 C from color 0x0a30 2452 ; -------------------------------------------------------------------------------------- 2452 2452 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x2455 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2455 0x2455 typ_mar_cntl 6 INCREMENT_MAR 2453 2453 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2454 2454 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x2456 seq_br_type 8 Return True seq_branch_adr 2456 0x2456 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2455 2455 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x3277 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2456 ; -------------------------------------------------------------------------------------- 2456 ; Comes from: 2456 ; 116d C from color 0x1169 2456 ; 16a0 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2456 ; 16b6 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2456 ; -------------------------------------------------------------------------------------- 2456 2456 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x245d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 245d 0x245d seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 2457 2457 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x245a ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 245a 0x245a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2458 2458 fiu_fill_mode_src 0 ; Flow J cc=False 0x2485 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2485 0x2485 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2459 2459 seq_br_type 3 Unconditional Branch; Flow J 0x2455 seq_branch_adr 2455 0x2455 245a 245a fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 245b 245b fiu_fill_mode_src 0 ; Flow J cc=False 0x2485 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2485 0x2485 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 245c 245c seq_br_type 3 Unconditional Branch; Flow J 0x2455 seq_branch_adr 2455 0x2455 245d 245d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 245e 245e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 245f 245f fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a82 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2460 2460 seq_b_timing 0 Early Condition; Flow J cc=True 0x246d seq_br_type 1 Branch True seq_branch_adr 246d 0x246d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2461 2461 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x246d ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 246d 0x246d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2462 2462 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x247e seq_br_type 5 Call True seq_branch_adr 247e 0x247e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2463 2463 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2461 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2461 0x2461 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2464 2464 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2465 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2461 0x2461 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 2465 2465 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2468 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2468 0x2468 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2466 2466 fiu_fill_mode_src 0 ; Flow J 0x246a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 246a 0x246a typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2467 2467 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x2466 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2466 0x2466 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2468 2468 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2469 2469 fiu_fill_mode_src 0 ; Flow J 0x246a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 246a 0x246a typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 246a 246a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 246b 0x246b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 246b 246b seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 246c 0x246c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_rand 5 CHECK_CLASS_B_LIT 246c 246c seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32ac seq_br_type 8 Return True seq_branch_adr 32ac 0x32ac seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 246d 246d fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 246e 0x246e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 246e 246e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2470 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2470 0x2470 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 246f 246f fiu_fill_mode_src 0 ; Flow J 0x2472 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2472 0x2472 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2470 2470 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2471 2471 fiu_fill_mode_src 0 ; Flow J 0x2472 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2472 0x2472 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2472 2472 fiu_mem_start 2 start-rd; Flow J cc=False 0x2474 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2474 0x2474 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2473 2473 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 2474 2474 seq_b_timing 0 Early Condition; Flow J cc=True 0x2477 seq_br_type 1 Branch True seq_branch_adr 2477 0x2477 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 2475 2475 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x2a82 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 2476 2476 fiu_mem_start 2 start-rd; Flow J 0x2474 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2474 0x2474 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2477 2477 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x247c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 247c 0x247c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2478 2478 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2479 2479 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 247a 0x247a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 247a 247a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x247e seq_br_type 5 Call True seq_branch_adr 247e 0x247e seq_cond_sel 67 REFRESH_MACRO_EVENT 247b 247b fiu_load_tar 1 hold_tar; Flow J cc=True 0x2478 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2478 0x2478 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 247c 247c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2467 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2467 0x2467 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 247d 247d fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x247a ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 247a 0x247a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 247e 247e seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 247f 247f fiu_mem_start 2 start-rd; Flow J 0x32fc seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc 2480 ; -------------------------------------------------------------------------------------- 2480 ; Comes from: 2480 ; 12e1 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2480 ; 2357 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2480 ; 23c9 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2480 ; 23fd C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 2480 ; -------------------------------------------------------------------------------------- 2480 2480 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0x2484 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2484 0x2484 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2481 2481 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 2482 2482 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2483 2483 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x32a7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 32a7 0x32a7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2484 2484 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2485 2485 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2486 2486 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2487 0x2487 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2487 2487 seq_br_type 3 Unconditional Branch; Flow J 0x2483 seq_branch_adr 2483 0x2483 2488 ; -------------------------------------------------------------------------------------- 2488 ; Comes from: 2488 ; 113e C from color 0x110d 2488 ; 1af1 C from color 0x0a31 2488 ; 1afd C from color 0x0a7b 2488 ; 1b03 C from color 0x0a8f 2488 ; 1b07 C from color 0x0a31 2488 ; 1d87 C from color 0x1d28 2488 ; 1d93 C from color 0x1d28 2488 ; -------------------------------------------------------------------------------------- 2488 2488 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2489 2489 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 248a 0x248a typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 248a 248a <default> 248b 248b fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 248c 248c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 248d 248d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 248e 0x248e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 248e 248e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A 248f 248f fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2498 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2498 0x2498 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2490 2490 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x24e0 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 24e0 0x24e0 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 2491 2491 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2492 ; -------------------------------------------------------------------------------------- 2492 ; Comes from: 2492 ; 0c31 C from color 0x0a33 2492 ; 0c3d C from color 0x0a7c 2492 ; 0c43 C from color 0x0a90 2492 ; 0c47 C from color 0x0a33 2492 ; 1148 C from color 0x110d 2492 ; 1d8c C from color 0x1d28 2492 ; 1da9 C from color 0x1d28 2492 ; -------------------------------------------------------------------------------------- 2492 2492 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2493 2493 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2494 0x2494 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2494 2494 <default> 2495 2495 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 2496 2496 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2497 2497 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x248e seq_br_type 8 Return True seq_branch_adr 248e 0x248e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2498 2498 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x249b fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 249b 0x249b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2499 2499 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x24c4 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24c4 0x24c4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 249a 249a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x24c4 seq_br_type 1 Branch True seq_branch_adr 24c4 0x24c4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS 249b 249b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x24ac seq_br_type 1 Branch True seq_branch_adr 24ac 0x24ac seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 249c 249c fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 249d 0x249d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 249d 249d typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 249e 249e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24de fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 249f 249f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24a1 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24a1 0x24a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24a0 24a0 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x249c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 249c 0x249c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24a1 24a1 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24a2 0x24a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24a2 24a2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_frame 12 val_rand c START_MULTIPLY 24a3 24a3 fiu_load_oreg 1 hold_oreg seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24a4 24a4 fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24a5 24a5 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24a6 24a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 24a7 24a7 typ_a_adr 09 GP09 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 24a8 24a8 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24a9 24a9 <default> 24aa 24aa fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24ab 24ab seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x249c seq_branch_adr 249c 0x249c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24ac 24ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24ad 0x24ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 20 TR05:00 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24ad 24ad fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24b2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24b2 0x24b2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24ae 24ae fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24af 24af fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24de fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24b0 24b0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24b7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24b7 0x24b7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24b1 24b1 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24ac seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ac 0x24ac seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24b2 24b2 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24b3 24b3 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24b4 24b4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24de fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24b5 24b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24b7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24b7 0x24b7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24b6 24b6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24ac seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ac 0x24ac seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24b7 24b7 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24b8 0x24b8 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24b8 24b8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 24b9 24b9 ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24ba 24ba fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 12 val_rand c START_MULTIPLY 24bb 24bb fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24bc 24bc fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B 24bd 24bd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24bf ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24bf 0x24bf seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT 24be 24be fiu_fill_mode_src 0 ; Flow J 0x24c1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24c1 0x24c1 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24bf 24bf fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24c0 24c0 fiu_fill_mode_src 0 ; Flow J 0x24c1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24c1 0x24c1 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24c1 24c1 typ_c_adr 36 GP09 24c2 24c2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24c3 24c3 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x24ac seq_branch_adr 24ac 0x24ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24c4 24c4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x24cf seq_br_type 1 Branch True seq_branch_adr 24cf 0x24cf seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 24c5 24c5 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24c6 0x24c6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24c6 24c6 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24c7 24c7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x24de fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24c8 24c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24c5 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24c5 0x24c5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24c9 24c9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ca 0x24ca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24ca 24ca fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24cb 24cb ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24cc 24cc fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 24cd 24cd seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x24c5 seq_br_type 8 Return True seq_branch_adr 24c5 0x24c5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24ce 24ce seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24cf 0x24cf seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24cf 24cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x24d8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 24d8 0x24d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 24d0 24d0 fiu_load_var 1 hold_var; Flow J cc=True 0x24d6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24d6 0x24d6 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 09 GP09 24d1 24d1 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24d2 0x24d2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24d2 24d2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24d3 24d3 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24d4 24d4 fiu_load_var 1 hold_var; Flow J cc=False 0x24ce fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24ce 0x24ce seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 24d5 24d5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x24d7 seq_br_type 8 Return True seq_branch_adr 24d7 0x24d7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 24d6 24d6 seq_b_timing 0 Early Condition; Flow J cc=False 0x24cf seq_br_type 0 Branch False seq_branch_adr 24cf 0x24cf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 24d7 24d7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24d8 ; -------------------------------------------------------------------------------------- 24d8 ; Comes from: 24d8 ; 24cf C from color 0x2488 24d8 ; -------------------------------------------------------------------------------------- 24d8 24d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24db seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24db 0x24db seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 24d9 24d9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24da 24da fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x24de fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24db 24db fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24dc 24dc fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24dd 24dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 24de 0x24de seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24de ; -------------------------------------------------------------------------------------- 24de ; Comes from: 24de ; 249e C True from color 0x2488 24de ; 24af C True from color 0x2488 24de ; 24b4 C True from color 0x2488 24de ; 24c7 C True from color 0x2488 24de ; -------------------------------------------------------------------------------------- 24de 24de seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 24df 24df fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 24e0 24e0 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 24e1 24e1 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x24e5 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24e5 0x24e5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 24e2 24e2 fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24e3 ; -------------------------------------------------------------------------------------- 24e3 ; Comes from: 24e3 ; 116a C from color 0x1169 24e3 ; 179e C True from color 0x0a30 24e3 ; 17b0 C True from color 0x0a7a 24e3 ; 17b4 C True from color 0x0a8e 24e3 ; 17b8 C True from color MACRO_Execute_Variant_Record,Check_In_Type 24e3 ; 17be C True from color 0x0aa2 24e3 ; 1dc1 C from color 0x0000 24e3 ; -------------------------------------------------------------------------------------- 24e3 24e3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 24e4 24e4 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32ac fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 24e5 24e5 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x24fb fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 24fb 0x24fb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24e6 24e6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 24e7 24e7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24ee ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24ee 0x24ee seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 24e8 24e8 fiu_fill_mode_src 0 ; Flow J cc=True 0x24f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24f0 0x24f0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 24e9 24e9 seq_b_timing 0 Early Condition; Flow J cc=True 0x24f2 seq_br_type 1 Branch True seq_branch_adr 24f2 0x24f2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24ea 24ea fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 24eb 24eb ioc_tvbs 1 typ+fiu; Flow J cc=True 0x24fa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24fa 0x24fa seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24ec 24ec fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 24ed 24ed fiu_mem_start a start_continue_if_false; Flow J cc=True 0x24e8 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 24e8 0x24e8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 24ee 24ee fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24ef 24ef fiu_fill_mode_src 0 ; Flow J cc=False 0x24e9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 24e9 0x24e9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 24f0 24f0 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 24f1 24f1 fiu_mem_start 2 start-rd; Flow J 0x24e9 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 24e9 0x24e9 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 24f2 24f2 fiu_fill_mode_src 0 ; Flow J cc=True 0x24f7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24f7 0x24f7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 24f3 24f3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24f8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24f8 0x24f8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 24f4 24f4 fiu_fill_mode_src 0 ; Flow J cc=True 0x24fa fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24fa 0x24fa seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 24f5 24f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 24f6 0x24f6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 24f6 24f6 seq_br_type 7 Unconditional Call; Flow C 0x3272 seq_branch_adr 3272 0x3272 24f7 24f7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 24f8 24f8 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24f9 24f9 fiu_fill_mode_src 0 ; Flow J cc=True 0x24f5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24f5 0x24f5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 24fa 24fa fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24fb 24fb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x24fe fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24fe 0x24fe seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 24fc 24fc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24ff ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24ff 0x24ff seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24fd 24fd fiu_fill_mode_src 0 ; Flow J 0x24f5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f5 0x24f5 24fe 24fe fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24ff 24ff fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2500 2500 fiu_fill_mode_src 0 ; Flow J 0x24f5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f5 0x24f5 2501 2501 <halt> ; Flow R 2502 ; -------------------------------------------------------------------------------------- 2502 ; 0x0319 Declare_Type Variant_Record,Incomplete,Visible 2502 ; -------------------------------------------------------------------------------------- 2502 MACRO_Declare_Type_Variant_Record,Incomplete,Visible: 2502 2502 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2502 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2503 2503 seq_br_type 3 Unconditional Branch; Flow J 0x2505 seq_branch_adr 2505 0x2505 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2504 ; -------------------------------------------------------------------------------------- 2504 ; 0x0318 Declare_Type Variant_Record,Incomplete 2504 ; -------------------------------------------------------------------------------------- 2504 MACRO_Declare_Type_Variant_Record,Incomplete: 2504 2504 dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2504 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2505 2505 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2507 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2507 0x2507 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 2 2506 2506 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32ab ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2507 2507 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ab fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2508 2508 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 2509 2509 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ab fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3a GP05 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 250a 250a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 250b 250b fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 250c 250c ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 26 VR05:06 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR05:00 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 250d 250d fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2510 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2510 0x2510 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 250e 250e fiu_tivi_src 6 fiu_fiu; Flow C cc=True 0x2a82 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 20 TR08:00 typ_frame 8 250f 250f fiu_mem_start 3 start-wr; Flow J cc=True 0x250e ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 250e 0x250e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 2510 2510 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2511 2511 ioc_load_wdr 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2c TR09:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2512 2512 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_b_adr 21 TR00:01 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2513 2513 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2514 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2514 0x2514 typ_a_adr 05 GP05 val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2514 2514 fiu_load_var 1 hold_var; Flow J cc=True 0x251a fiu_mem_start 6 start_rd_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 251a 0x251a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 06 GP06 val_rand 2 DEC_LOOP_COUNTER 2515 2515 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 2516 2516 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fc fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2517 2517 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2518 2518 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2a82 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 val_b_adr 02 GP02 2519 2519 ioc_tvbs 1 typ+fiu; Flow J 0x2514 seq_br_type 3 Unconditional Branch seq_branch_adr 2514 0x2514 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 251a 251a ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 04 GP04 val_alu_func 0 PASS_A 251b 251b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x251e fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 251e 0x251e seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 251c 251c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 251d 251d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 251e ; -------------------------------------------------------------------------------------- 251e ; Comes from: 251e ; 251b C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 251e ; 252c C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 251e ; -------------------------------------------------------------------------------------- 251e 251e fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a82 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 251f 251f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x251e fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 251e 0x251e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2520 ; -------------------------------------------------------------------------------------- 2520 ; 0x0312 Declare_Type Variant_Record,Constrained_Incomplete,Visible 2520 ; -------------------------------------------------------------------------------------- 2520 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete,Visible: 2520 2520 dispatch_brk_class 4 ; Flow C cc=False 0x3277 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2520 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2521 2521 seq_br_type 3 Unconditional Branch; Flow J 0x2523 seq_branch_adr 2523 0x2523 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2522 ; -------------------------------------------------------------------------------------- 2522 ; 0x0311 Declare_Type Variant_Record,Constrained_Incomplete 2522 ; -------------------------------------------------------------------------------------- 2522 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete: 2522 2522 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2522 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2523 2523 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 2524 2524 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2525 2525 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32ab fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 2526 2526 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x2529 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2529 0x2529 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2527 2527 fiu_tivi_src 6 fiu_fiu; Flow C cc=True 0x2a82 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 2b TR08:0b typ_frame 8 val_rand 2 DEC_LOOP_COUNTER 2528 2528 fiu_mem_start 3 start-wr; Flow J cc=False 0x2527 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2527 0x2527 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2529 2529 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 252a 252a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 10 TOP 252b 252b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 3b VR02:1b val_b_adr 1f TOP - 1 val_frame 2 252c 252c fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x251e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 251e 0x251e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 27 TR08:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 252d 252d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x251d fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 251d 0x251d seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 252e ; -------------------------------------------------------------------------------------- 252e ; 0x0307 Complete_Type Variant_Record,By_Defining 252e ; -------------------------------------------------------------------------------------- 252e MACRO_Complete_Type_Variant_Record,By_Defining: 252e 252e dispatch_brk_class 4 ; Flow C 0x32fc dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 252e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR02:02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 252f 252f fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x3277 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 2530 2530 fiu_mem_start 4 continue; Flow C cc=True 0x32a9 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2531 2531 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ab fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR06:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 2532 2532 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR09:0e typ_frame 9 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2533 2533 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2534 2534 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2535 2535 fiu_tivi_src 1 tar_val; Flow J cc=True 0x2573 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2573 0x2573 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2536 2536 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1d TOP - 3 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2537 2537 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2538 2538 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2539 2539 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 253a 253a ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 253b 253b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 253c 253c seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 253d 253d ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 253e 253e fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 253f 253f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 2540 2540 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2541 2541 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 2542 2542 ioc_fiubs 0 fiu ; Flow C 0x26b6 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1d TOP - 3 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2543 2543 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2544 2544 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2545 2545 seq_b_timing 0 Early Condition; Flow J cc=False 0x2547 seq_br_type 0 Branch False seq_branch_adr 2547 0x2547 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 2546 2546 seq_br_type 3 Unconditional Branch; Flow J 0x2548 seq_branch_adr 2548 0x2548 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2547 2547 seq_br_type 3 Unconditional Branch; Flow J 0x2548 seq_branch_adr 2548 0x2548 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2548 2548 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2549 2549 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x255b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 255b 0x255b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 254a 254a ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 254b 254b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 254c 254c fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 254d 254d ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 254e 254e seq_br_type 7 Unconditional Call; Flow C 0x26b6 seq_branch_adr 26b6 0x26b6 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 254f 254f fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2550 2550 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2553 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2553 0x2553 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2551 2551 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2548 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2548 0x2548 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2552 2552 ioc_fiubs 0 fiu ; Flow J 0x2548 seq_br_type 3 Unconditional Branch seq_branch_adr 2548 0x2548 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2553 ; -------------------------------------------------------------------------------------- 2553 ; Comes from: 2553 ; 2550 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Defining 2553 ; 25a5 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Defining 2553 ; 260e C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2553 ; -------------------------------------------------------------------------------------- 2553 2553 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2554 2554 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 2555 2555 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2556 2556 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2554 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2554 0x2554 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2557 2557 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2558 2558 fiu_mem_start 3 start-wr; Flow J 0x2554 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2554 0x2554 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2559 2559 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 255a 255a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2554 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2554 0x2554 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 255b 255b ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 255c 255c seq_b_timing 0 Early Condition; Flow C cc=False 0x256a seq_br_type 4 Call False seq_branch_adr 256a 0x256a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 255d 255d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ab seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 255e 255e typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 255f 255f fiu_tivi_src c mar_0xc; Flow C cc=True 0x2568 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2568 0x2568 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 2560 2560 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2561 2561 seq_b_timing 0 Early Condition; Flow C cc=False 0x2571 seq_br_type 4 Call False seq_branch_adr 2571 0x2571 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2562 2562 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2563 2563 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2564 2564 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2565 2565 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 2566 2566 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 2567 2567 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2568 ; -------------------------------------------------------------------------------------- 2568 ; Comes from: 2568 ; 255f C True from color 0x255c 2568 ; -------------------------------------------------------------------------------------- 2568 2568 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 2569 2569 seq_b_timing 0 Early Condition; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 256a ; -------------------------------------------------------------------------------------- 256a ; Comes from: 256a ; 255c C False from color 0x255c 256a ; -------------------------------------------------------------------------------------- 256a 256a seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 256b 0x256b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 256b 256b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 256c 256c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 256d 0x256d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 256d 256d seq_br_type 1 Branch True; Flow J cc=True 0x2570 seq_branch_adr 2570 0x2570 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 256e 256e seq_br_type 1 Branch True; Flow J cc=True 0x2570 seq_branch_adr 2570 0x2570 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 256f 256f seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 2570 0x2570 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2570 2570 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 2571 ; -------------------------------------------------------------------------------------- 2571 ; Comes from: 2571 ; 2561 C False from color 0x255c 2571 ; -------------------------------------------------------------------------------------- 2571 2571 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2572 0x2572 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2572 2572 seq_br_type a Unconditional Return; Flow R typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2573 2573 seq_br_type 4 Call False; Flow C cc=False 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1d TOP - 3 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2574 2574 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1c TOP - 4 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2575 2575 ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2576 2576 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ab fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 1d TOP - 3 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 2577 2577 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 2578 2578 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ab 0x32ab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2579 2579 ioc_tvbs 1 typ+fiu val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 257a 257a seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 257b 257b fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_b_adr 03 GP03 257c 257c fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 257d 257d seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 257e 257e seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 257f 257f ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2580 2580 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2581 2581 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 2582 2582 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2583 2583 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 2584 2584 ioc_fiubs 0 fiu ; Flow C 0x26b6 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1c TOP - 4 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2585 2585 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2586 2586 seq_br_type 7 Unconditional Call; Flow C 0x26db seq_branch_adr 26db 0x26db seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2587 2587 seq_br_type 1 Branch True; Flow J cc=True 0x258c seq_branch_adr 258c 0x258c seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2588 2588 val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 2589 2589 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 258a 258a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x258c seq_br_type 1 Branch True seq_branch_adr 258c 0x258c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 258b 258b typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 258c 258c ioc_fiubs 1 val ; Flow J cc=True 0x258e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 258e 0x258e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 258d 258d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 258e 258e seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 258f 258f typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 2590 2590 val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 2591 2591 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2592 2592 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 2593 2593 ioc_fiubs 0 fiu ; Flow J 0x2594 seq_br_type 3 Unconditional Branch seq_branch_adr 2594 0x2594 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2594 2594 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2595 2595 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x255b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 255b 0x255b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2596 2596 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2597 2597 ioc_fiubs 1 val ; Flow C cc=True 0x32ab ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2598 2598 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2599 2599 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 259a 259a fiu_load_var 1 hold_var; Flow C cc=True 0x2a82 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 259b 259b ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 259c 259c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 259d 259d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 259e 259e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 259f 259f seq_br_type 7 Unconditional Call; Flow C 0x26b6 seq_branch_adr 26b6 0x26b6 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25a0 25a0 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 25a1 25a1 ioc_fiubs 2 typ ; Flow J cc=True 0x25a3 seq_br_type 1 Branch True seq_branch_adr 25a3 0x25a3 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25a2 25a2 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 25a3 25a3 seq_br_type 7 Unconditional Call; Flow C 0x26db seq_branch_adr 26db 0x26db val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25a4 25a4 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 25a5 25a5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2553 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2553 0x2553 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 25a6 25a6 seq_br_type 0 Branch False; Flow J cc=False 0x2594 seq_branch_adr 2594 0x2594 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 25a7 25a7 seq_br_type 3 Unconditional Branch; Flow J 0x2594 seq_branch_adr 2594 0x2594 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 25a8 ; -------------------------------------------------------------------------------------- 25a8 ; 0x0303 Complete_Type Variant_Record,By_Component_Completion 25a8 ; -------------------------------------------------------------------------------------- 25a8 MACRO_Complete_Type_Variant_Record,By_Component_Completion: 25a8 25a8 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 25a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25a9 25a9 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25aa 25aa fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25ab 25ab fiu_mem_start 2 start-rd; Flow J cc=True 0x25ac ; Flow J cc=#0x0 0x25b1 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 25b1 0x25b1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25ac 25ac fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 25ad 25ad typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25ae 25ae fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25af 25af fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25b0 25b0 seq_br_type 3 Unconditional Branch; Flow J 0x25b5 seq_branch_adr 25b5 0x25b5 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 25b1 25b1 seq_br_type 3 Unconditional Branch; Flow J 0x2628 seq_branch_adr 2628 0x2628 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b2 25b2 ioc_fiubs 2 typ ; Flow J 0x25b5 seq_br_type 3 Unconditional Branch seq_branch_adr 25b5 0x25b5 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 38 GP07 val_c_source 0 FIU_BUS 25b3 25b3 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b4 25b4 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25b5 25b5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 25b6 25b6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 25b7 25b7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25b8 25b8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 31 GP0e val_c_source 0 FIU_BUS 25b9 25b9 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 25ba 25ba ioc_tvbs 3 fiu+fiu; Flow J 0x25bb seq_br_type 3 Unconditional Branch seq_branch_adr 25bb 0x25bb seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25bb 25bb fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x25ea ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 25ea 0x25ea seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 25bc 25bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x25dc seq_br_type 5 Call True seq_branch_adr 25dc 0x25dc seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 25bd 25bd fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25be 25be ioc_fiubs 2 typ ; Flow J cc=False 0x25c4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 25c4 0x25c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 25bf 25bf fiu_load_tar 1 hold_tar; Flow C cc=True 0x25df fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25df 0x25df seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 25c0 25c0 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 25c1 25c1 seq_b_timing 1 Latch Condition; Flow C cc=False 0x25c7 seq_br_type 4 Call False seq_branch_adr 25c7 0x25c7 typ_c_adr 30 GP0f 25c2 25c2 ioc_fiubs 1 val ; Flow J cc=True 0x25bb ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 25bb 0x25bb seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c3 25c3 ioc_fiubs 1 val ; Flow J 0x25bb seq_br_type 3 Unconditional Branch seq_branch_adr 25bb 0x25bb val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c4 25c4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 25c5 25c5 ioc_tvbs 2 fiu+val; Flow C cc=True 0x25df seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 25df 0x25df seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 25c6 25c6 fiu_mem_start 3 start-wr; Flow J 0x25c2 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 25c2 0x25c2 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 25c7 ; -------------------------------------------------------------------------------------- 25c7 ; Comes from: 25c7 ; 25c1 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25c7 ; -------------------------------------------------------------------------------------- 25c7 25c7 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x25c9 seq_br_type 1 Branch True seq_branch_adr 25c9 0x25c9 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25c8 25c8 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25c9 25c9 seq_br_type 4 Call False; Flow C cc=False 0x25cc seq_branch_adr 25cc 0x25cc seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25ca 25ca fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 25cb 0x25cb seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25cb 25cb seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25cc ; -------------------------------------------------------------------------------------- 25cc ; Comes from: 25cc ; 25c9 C False from color 0x25c7 25cc ; 2603 C False from color 0x2601 25cc ; -------------------------------------------------------------------------------------- 25cc 25cc fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25cd 25cd fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 36 GP09 val_c_source 0 FIU_BUS 25ce 25ce fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x25d3 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25d3 0x25d3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 2 25cf 25cf seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25d0 25d0 seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 25d1 25d1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 25d2 25d2 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 0c GP0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25d3 25d3 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x25da ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25da 0x25da seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25d4 25d4 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 25d5 25d5 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x25d8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25d8 0x25d8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 25d6 25d6 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x25d3 seq_br_type 1 Branch True seq_branch_adr 25d3 0x25d3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 25d7 25d7 seq_br_type 3 Unconditional Branch; Flow J 0x25d0 seq_branch_adr 25d0 0x25d0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25d8 25d8 seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 25d9 25d9 seq_br_type 3 Unconditional Branch; Flow J 0x25d0 seq_branch_adr 25d0 0x25d0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 25da ; -------------------------------------------------------------------------------------- 25da ; Comes from: 25da ; 25d3 C True from color 0x25cc 25da ; -------------------------------------------------------------------------------------- 25da 25da seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 25db 25db fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25dc ; -------------------------------------------------------------------------------------- 25dc ; Comes from: 25dc ; 25bc C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25dc ; 25f6 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25dc ; -------------------------------------------------------------------------------------- 25dc 25dc seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 25dd 25dd fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 25de 25de seq_br_type a Unconditional Return; Flow R 25df ; -------------------------------------------------------------------------------------- 25df ; Comes from: 25df ; 25bf C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25df ; 25c5 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25df ; -------------------------------------------------------------------------------------- 25df 25df fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x25e4 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25e4 0x25e4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 25e0 25e0 seq_b_timing 1 Latch Condition; Flow J cc=False 0x25e7 seq_br_type 0 Branch False seq_branch_adr 25e7 0x25e7 seq_en_micro 0 25e1 25e1 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e2 0x25e2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25e2 25e2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e3 0x25e3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 25e3 25e3 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 25e4 ; -------------------------------------------------------------------------------------- 25e4 ; Comes from: 25e4 ; 2606 C True from color 0x2606 25e4 ; -------------------------------------------------------------------------------------- 25e4 25e4 seq_en_micro 0 typ_c_adr 32 GP0d 25e5 25e5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 25e6 0x25e6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var seq_en_micro 0 typ_b_adr 0d GP0d typ_c_lit 1 typ_frame 9 25e6 25e6 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 25e7 25e7 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e8 0x25e8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25e8 25e8 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 25e9 0x25e9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 25e9 25e9 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 25ea 25ea fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25eb 25eb ioc_fiubs 1 val typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 25ec 25ec seq_b_timing 1 Latch Condition; Flow J cc=True 0x25ee seq_br_type 1 Branch True seq_branch_adr 25ee 0x25ee seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B 25ed 25ed typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 25ee 25ee typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 25ef 25ef fiu_vmux_sel 1 fill value; Flow J cc=True 0x25f1 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 25f1 0x25f1 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f0 25f0 seq_br_type 3 Unconditional Branch; Flow J 0x25f1 seq_branch_adr 25f1 0x25f1 seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 25f1 25f1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2616 seq_br_type 1 Branch True seq_branch_adr 2616 0x2616 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25f2 25f2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25f3 25f3 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 25f4 25f4 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x25f5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 25f5 0x25f5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 25f5 25f5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x260a ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 260a 0x260a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 25f6 25f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x25dc seq_br_type 5 Call True seq_branch_adr 25dc 0x25dc seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 25f7 25f7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f8 25f8 ioc_fiubs 2 typ ; Flow J cc=False 0x25fe ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 25fe 0x25fe seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 25f9 25f9 fiu_load_tar 1 hold_tar; Flow C cc=True 0x2606 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2606 0x2606 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 25fa 25fa ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 25fb 25fb seq_b_timing 1 Latch Condition; Flow C cc=False 0x2601 seq_br_type 4 Call False seq_branch_adr 2601 0x2601 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 03 GP03 typ_c_adr 30 GP0f 25fc 25fc ioc_fiubs 1 val ; Flow J cc=True 0x25f5 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 25f5 0x25f5 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25fd 25fd ioc_fiubs 1 val ; Flow J 0x25f5 seq_br_type 3 Unconditional Branch seq_branch_adr 25f5 0x25f5 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25fe 25fe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 25ff 25ff ioc_tvbs 2 fiu+val; Flow C cc=True 0x2606 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2606 0x2606 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2600 2600 fiu_mem_start 3 start-wr; Flow J 0x25fc ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 25fc 0x25fc seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 2601 ; -------------------------------------------------------------------------------------- 2601 ; Comes from: 2601 ; 25fb C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2601 ; -------------------------------------------------------------------------------------- 2601 2601 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2603 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2603 0x2603 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2602 2602 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2603 2603 seq_br_type 4 Call False; Flow C cc=False 0x25cc seq_branch_adr 25cc 0x25cc seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2604 2604 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 2605 0x2605 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2605 2605 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2606 ; -------------------------------------------------------------------------------------- 2606 ; Comes from: 2606 ; 25f9 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2606 ; 25ff C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2606 ; -------------------------------------------------------------------------------------- 2606 2606 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x25e4 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 25e4 0x25e4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2607 2607 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2608 0x2608 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2608 2608 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2609 0x2609 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2609 2609 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 260a 260a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x260c fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 260c 0x260c seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 260b 260b val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 260c 260c fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2612 fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 2612 0x2612 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 03 GP03 260d 260d fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 260e 260e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2553 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2553 0x2553 seq_en_micro 0 260f 260f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2611 seq_br_type 1 Branch True seq_branch_adr 2611 0x2611 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 2610 2610 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2611 2611 seq_br_type 3 Unconditional Branch; Flow J 0x25f1 seq_branch_adr 25f1 0x25f1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 2612 2612 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 2613 2613 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2611 seq_br_type 1 Branch True seq_branch_adr 2611 0x2611 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2614 2614 seq_br_type 3 Unconditional Branch; Flow J 0x2610 seq_branch_adr 2610 0x2610 2615 ; -------------------------------------------------------------------------------------- 2615 ; Comes from: 2615 ; 2617 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2615 ; 2618 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2615 ; -------------------------------------------------------------------------------------- 2615 2615 seq_br_type a Unconditional Return; Flow R val_rand 1 INC_LOOP_COUNTER 2616 2616 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2617 2617 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2615 seq_br_type 5 Call True seq_branch_adr 2615 0x2615 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 2618 2618 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2615 seq_br_type 5 Call True seq_branch_adr 2615 0x2615 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 2619 2619 seq_b_timing 0 Early Condition; Flow J cc=False 0x2619 seq_br_type 0 Branch False seq_branch_adr 2619 0x2619 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_rand 2 DEC_LOOP_COUNTER 261a 261a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2623 seq_br_type 1 Branch True seq_branch_adr 2623 0x2623 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 typ_rand d SET_PASS_PRIVACY_BIT 261b 261b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 261c 261c seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 261d 261d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2623 seq_br_type 0 Branch False seq_branch_adr 2623 0x2623 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 261e 261e seq_br_type 1 Branch True; Flow J cc=True 0x2622 seq_branch_adr 2622 0x2622 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 261f 261f seq_b_timing 0 Early Condition; Flow J cc=False 0x2622 seq_br_type 0 Branch False seq_branch_adr 2622 0x2622 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2620 2620 seq_b_timing 0 Early Condition; Flow J cc=False 0x2622 seq_br_type 0 Branch False seq_branch_adr 2622 0x2622 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2621 2621 seq_b_timing 0 Early Condition; Flow J cc=True 0x2623 seq_br_type 1 Branch True seq_branch_adr 2623 0x2623 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 2622 2622 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 2623 2623 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2624 2624 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR11:13 val_frame 11 2625 2625 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2626 2626 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2627 2627 ioc_load_wdr 0 ; Flow J cc=True 0x2629 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2629 0x2629 typ_b_adr 03 GP03 val_b_adr 03 GP03 2628 2628 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2629 2629 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 262a ; -------------------------------------------------------------------------------------- 262a ; 0x0306 Complete_Type Variant_Record,By_Renaming 262a ; -------------------------------------------------------------------------------------- 262a MACRO_Complete_Type_Variant_Record,By_Renaming: 262a 262a dispatch_brk_class 4 ; Flow C 0x32fc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 262a fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 262b 262b fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 262c 262c fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 262d 262d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 262e 262e fiu_load_var 1 hold_var; Flow C cc=False 0x32a7 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 262f 262f fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2630 2630 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x3277 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2631 2631 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a9 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2632 2632 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 27 VR08:07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 8 2633 2633 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 2634 2634 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x2635 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32a7 0x32a7 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER 2635 2635 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2637 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2637 0x2637 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2636 2636 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2637 2637 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 2638 2638 fiu_mem_start 3 start-wr; Flow J cc=True 0x2636 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2636 0x2636 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 2639 2639 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 263a ; -------------------------------------------------------------------------------------- 263a ; Comes from: 263a ; 2656 C from color MACRO_Declare_Type_Variant_Record,Defined 263a ; 2692 C from color MACRO_Declare_Type_Variant_Record,Defined 263a ; -------------------------------------------------------------------------------------- 263a 263a seq_b_timing 1 Latch Condition; Flow C cc=False 0x3277 seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 263b 263b ioc_fiubs 1 val ; Flow C cc=True 0x32a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 39 GP06 val_c_mux_sel 2 ALU 263c 263c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x2640 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2640 0x2640 typ_a_adr 1f TOP - 1 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 263d 263d fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2646 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2646 0x2646 typ_a_adr 1c TOP - 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 263e 263e fiu_len_fill_lit 7d zero-fill 0x3d; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1b TOP - 5 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1b TOP - 5 263f 263f fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2649 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2649 0x2649 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1c TOP - 4 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2640 2640 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_b_adr 1c TOP - 4 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2641 2641 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2642 2642 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2643 2643 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2646 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2646 0x2646 typ_a_adr 1b TOP - 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1b TOP - 5 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2644 2644 fiu_len_fill_lit 7d zero-fill 0x3d; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1a TOP - 6 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1a TOP - 6 2645 2645 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2649 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2649 0x2649 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1b TOP - 5 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2646 ; -------------------------------------------------------------------------------------- 2646 ; Comes from: 2646 ; 263d C from color 0x263a 2646 ; 2643 C from color 0x263a 2646 ; -------------------------------------------------------------------------------------- 2646 2646 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR05:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2647 2647 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2648 2648 fiu_len_fill_lit 78 zero-fill 0x38; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 28 VR05:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 2649 2649 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 264a 264a fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32ab fiu_offs_lit 50 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 264b 264b fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 264c 264c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR05:00 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 26 VR05:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 264d 264d ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 264e 264e fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 264f 0x264f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 264f 264f typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2650 2650 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32fc fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2651 2651 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2652 2652 ioc_load_wdr 0 ; Flow C cc=True 0x2a82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 2653 2653 ioc_tvbs 1 typ+fiu; Flow J 0x264e seq_br_type 3 Unconditional Branch seq_branch_adr 264e 0x264e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2654 ; -------------------------------------------------------------------------------------- 2654 ; 0x031e Declare_Type Variant_Record,Defined,Visible 2654 ; -------------------------------------------------------------------------------------- 2654 MACRO_Declare_Type_Variant_Record,Defined,Visible: 2654 2654 dispatch_brk_class 4 ; Flow J 0x2655 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2654 seq_br_type 2 Push (branch address) seq_branch_adr 2657 0x2657 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 2655 2655 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x263a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 263a 0x263a seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2656 ; -------------------------------------------------------------------------------------- 2656 ; 0x031d Declare_Type Variant_Record,Defined 2656 ; -------------------------------------------------------------------------------------- 2656 MACRO_Declare_Type_Variant_Record,Defined: 2656 2656 dispatch_brk_class 4 ; Flow C 0x263a dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2656 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 263a 0x263a seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2657 2657 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2694 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2694 0x2694 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2658 2658 ioc_fiubs 0 fiu ; Flow C 0x26b6 seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2659 2659 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 265a 265a typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 265b 265b typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 265c 265c seq_b_timing 0 Early Condition; Flow C cc=False 0x2683 seq_br_type 4 Call False seq_branch_adr 2683 0x2683 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 265d 265d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 265e 265e ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2668 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2668 0x2668 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 265f 265f ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2660 2660 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2661 2661 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2662 2662 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2663 2663 seq_br_type 7 Unconditional Call; Flow C 0x26b6 seq_branch_adr 26b6 0x26b6 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2664 2664 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2665 2665 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2676 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2676 0x2676 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2666 2666 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x265d seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 265d 0x265d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2667 2667 ioc_fiubs 0 fiu ; Flow J 0x265d seq_br_type 3 Unconditional Branch seq_branch_adr 265d 0x265d val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2668 2668 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR07:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 03 GP03 val_b_adr 1c TOP - 4 2669 2669 ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 266a 266a fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x267e fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 267e 0x267e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 1e TOP - 2 266b 266b ioc_fiubs 0 fiu ; Flow C cc=True 0x32ab ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 266c 266c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_b_adr 10 TOP 266d 266d ioc_fiubs 0 fiu typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 266e 266e seq_b_timing 0 Early Condition; Flow C cc=False 0x2684 seq_br_type 4 Call False seq_branch_adr 2684 0x2684 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 266f 266f fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 08 GP08 2670 2670 fiu_mem_start 4 continue ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 2671 2671 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 2672 2672 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2673 2673 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 23 VR08:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 2674 2674 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR08:1d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 2675 2675 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2676 ; -------------------------------------------------------------------------------------- 2676 ; Comes from: 2676 ; 2665 C #0x0 from color MACRO_Declare_Type_Variant_Record,Defined 2676 ; 26b2 C #0x0 from color MACRO_Declare_Type_Variant_Record,Defined 2676 ; -------------------------------------------------------------------------------------- 2676 2676 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2677 2677 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 2678 2678 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2679 2679 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2677 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2677 0x2677 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 267a 267a fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 267b 267b fiu_mem_start 3 start-wr; Flow J 0x2677 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2677 0x2677 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 267c 267c fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 267d 267d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2677 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2677 0x2677 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 267e ; -------------------------------------------------------------------------------------- 267e ; Comes from: 267e ; 266a C False from color 0x266a 267e ; -------------------------------------------------------------------------------------- 267e 267e seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 267f 0x267f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 267f 267f ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2680 0x2680 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2680 2680 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x2682 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 2682 0x2682 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 2681 2681 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 2682 0x2682 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 1c TOP - 4 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2682 2682 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f 2683 ; -------------------------------------------------------------------------------------- 2683 ; Comes from: 2683 ; 265c C False from color MACRO_Declare_Type_Variant_Record,Defined 2683 ; 269b C True from color MACRO_Declare_Type_Variant_Record,Defined 2683 ; -------------------------------------------------------------------------------------- 2683 2683 seq_br_type a Unconditional Return; Flow R typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 2684 ; -------------------------------------------------------------------------------------- 2684 ; Comes from: 2684 ; 266e C False from color 0x266a 2684 ; -------------------------------------------------------------------------------------- 2684 2684 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2685 0x2685 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2685 2685 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2686 2686 fiu_tivi_src c mar_0xc; Flow R cc=False ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2687 0x2687 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 2687 2687 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 2688 2688 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 2689 2689 ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 25 TR09:05 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 08 GP08 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 268a 268a fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR08:00 typ_frame 8 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 268b 268b fiu_len_fill_lit 7d zero-fill 0x3d; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 268c 0x268c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 21 VR05:01 val_frame 5 268c 268c ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 268d 268d fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_rand 2 DEC_LOOP_COUNTER 268e 268e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 268f 268f fiu_mem_start 8 start_wr_if_false; Flow R cc=True ; Flow J cc=False 0x268e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 268e 0x268e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2690 ; -------------------------------------------------------------------------------------- 2690 ; 0x0316 Declare_Type Variant_Record,Defined_Incomplete,Visible 2690 ; -------------------------------------------------------------------------------------- 2690 MACRO_Declare_Type_Variant_Record,Defined_Incomplete,Visible: 2690 2690 dispatch_brk_class 4 ; Flow J 0x2691 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2690 seq_br_type 2 Push (branch address) seq_branch_adr 2693 0x2693 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 2691 2691 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x263a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 263a 0x263a seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2692 ; -------------------------------------------------------------------------------------- 2692 ; 0x0315 Declare_Type Variant_Record,Defined_Incomplete 2692 ; -------------------------------------------------------------------------------------- 2692 MACRO_Declare_Type_Variant_Record,Defined_Incomplete: 2692 2692 dispatch_brk_class 4 ; Flow C 0x263a dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2692 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 263a 0x263a seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2693 2693 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2658 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2658 0x2658 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2694 2694 ioc_fiubs 0 fiu ; Flow C 0x26b6 seq_br_type 7 Unconditional Call seq_branch_adr 26b6 0x26b6 typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2695 2695 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2696 2696 seq_br_type 7 Unconditional Call; Flow C 0x26db seq_branch_adr 26db 0x26db typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2697 2697 seq_br_type 1 Branch True; Flow J cc=True 0x269b seq_branch_adr 269b 0x269b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2698 2698 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2699 2699 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x269b seq_br_type 1 Branch True seq_branch_adr 269b 0x269b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 269a 269a typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 269b 269b ioc_fiubs 1 val ; Flow C cc=True 0x2683 seq_br_type 5 Call True seq_branch_adr 2683 0x2683 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 269c 269c seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 269d 269d typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 269e 269e typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 269f 269f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 26a0 26a0 ioc_fiubs 0 fiu ; Flow J 0x26a1 seq_br_type 3 Unconditional Branch seq_branch_adr 26a1 0x26a1 val_a_adr 1b TOP - 5 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26a1 26a1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26a2 26a2 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x26b5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 26b5 0x26b5 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26a3 26a3 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 26a4 26a4 ioc_fiubs 1 val ; Flow C cc=True 0x32ab ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 26a5 26a5 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32ab fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26a6 26a6 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 26a7 26a7 fiu_load_var 1 hold_var; Flow C cc=True 0x2a82 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 26a8 26a8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26a9 26a9 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 26aa 26aa fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 26ab 26ab ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32ab seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26ac 26ac seq_br_type 7 Unconditional Call; Flow C 0x26b6 seq_branch_adr 26b6 0x26b6 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26ad 26ad val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 26ae 26ae ioc_fiubs 2 typ ; Flow J cc=True 0x26b0 seq_br_type 1 Branch True seq_branch_adr 26b0 0x26b0 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26af 26af val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26b0 26b0 seq_br_type 7 Unconditional Call; Flow C 0x26db seq_branch_adr 26db 0x26db val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 26b1 26b1 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 26b2 26b2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2676 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2676 0x2676 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 26b3 26b3 seq_br_type 0 Branch False; Flow J cc=False 0x26a1 seq_branch_adr 26a1 0x26a1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 26b4 26b4 seq_br_type 3 Unconditional Branch; Flow J 0x26a1 seq_branch_adr 26a1 0x26a1 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26b5 26b5 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x2669 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2669 0x2669 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_b_adr 1b TOP - 5 26b6 ; -------------------------------------------------------------------------------------- 26b6 ; Comes from: 26b6 ; 1e85 C from color MACRO_Declare_Type_Record,Defined 26b6 ; 1eaa C from color MACRO_Complete_Type_Record,By_Defining 26b6 ; 2542 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b6 ; 254e C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b6 ; 2584 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b6 ; 259f C from color MACRO_Complete_Type_Variant_Record,By_Defining 26b6 ; 2658 C from color MACRO_Declare_Type_Variant_Record,Defined 26b6 ; 2663 C from color MACRO_Declare_Type_Variant_Record,Defined 26b6 ; 2694 C from color MACRO_Declare_Type_Variant_Record,Defined 26b6 ; 26ac C from color MACRO_Declare_Type_Variant_Record,Defined 26b6 ; -------------------------------------------------------------------------------------- 26b6 26b6 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26b7 0x26b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 26b7 26b7 seq_br_type 3 Unconditional Branch; Flow J 0x26b9 seq_branch_adr 26b9 0x26b9 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 26b8 26b8 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x26d6 seq_br_type 4 Call False seq_branch_adr 26d6 0x26d6 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 26b9 26b9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 26ba 26ba fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x26bd fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26bd 0x26bd seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 26bb 26bb fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x26d3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 26d3 0x26d3 seq_en_micro 0 26bc 26bc seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 26bd ; -------------------------------------------------------------------------------------- 26bd ; Comes from: 26bd ; 26ba C #0x0 from color 0x26b6 26bd ; -------------------------------------------------------------------------------------- 26bd 26bd fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d3 0x26d3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26be 26be fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26bf 26bf fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c0 26c0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c1 26c1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c2 26c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c3 26c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c4 26c4 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26c5 26c5 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d3 0x26d3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 26c6 26c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26cd fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26cd 0x26cd typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26c7 26c7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c8 26c8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26c9 26c9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26ca 26ca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d1 0x26d1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26cb 26cb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d1 0x26d1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26cc 26cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26d1 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26d1 0x26d1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26cd 26cd fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d3 0x26d3 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 1 RESTORE_RDR val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26ce 26ce fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x26d0 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d0 0x26d0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE 26cf 26cf fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a7 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 26d0 26d0 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26d3 0x26d3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 26d1 26d1 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x26d3 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 26d3 0x26d3 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26d2 26d2 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a7 seq_br_type 9 Return False seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 26d3 26d3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26d7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26d7 0x26d7 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU 26d4 26d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x26b8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 26b8 0x26b8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 3c VR07:1c val_frame 7 26d5 26d5 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 26d6 0x26d6 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26d6 26d6 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 35 TR07:15 typ_frame 7 val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26d7 ; -------------------------------------------------------------------------------------- 26d7 ; Comes from: 26d7 ; 26f5 C #0x0 from color 0x26e3 26d7 ; -------------------------------------------------------------------------------------- 26d7 26d7 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26d8 26d8 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26d9 26d9 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26da 26da fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_offs_lit 40 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26db ; -------------------------------------------------------------------------------------- 26db ; Comes from: 26db ; 2586 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26db ; 25a3 C from color MACRO_Complete_Type_Variant_Record,By_Defining 26db ; 2696 C from color MACRO_Declare_Type_Variant_Record,Defined 26db ; 26b0 C from color MACRO_Declare_Type_Variant_Record,Defined 26db ; -------------------------------------------------------------------------------------- 26db 26db fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26dc 0x26dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26dc 26dc seq_br_type 3 Unconditional Branch; Flow J 0x26de seq_branch_adr 26de 0x26de typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 2b VR08:0b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 26dd 26dd seq_br_type 4 Call False; Flow C cc=False 0x26d6 seq_branch_adr 26d6 0x26d6 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 2c VR07:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 26de 26de fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 26df 26df fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x26e2 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26e2 0x26e2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26e0 26e0 fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x26f5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 26f5 0x26f5 seq_en_micro 0 26e1 26e1 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 26e2 ; -------------------------------------------------------------------------------------- 26e2 ; Comes from: 26e2 ; 26df C #0x0 from color 0x26b6 26e2 ; -------------------------------------------------------------------------------------- 26e2 26e2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e3 26e3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x26ea fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26ea 0x26ea seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 26e4 26e4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e5 26e5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e6 26e6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26e7 26e7 fiu_mem_start 2 start-rd; Flow J 0x26ec ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 26ec 0x26ec typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 26e8 26e8 fiu_mem_start 2 start-rd; Flow J 0x26ed ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 26ed 0x26ed typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 26e9 26e9 seq_br_type 3 Unconditional Branch; Flow J 0x26ee seq_branch_adr 26ee 0x26ee 26ea 26ea seq_b_timing 0 Early Condition; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 26eb 26eb fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x26f5 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26f5 0x26f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 26ec 26ec seq_br_type 3 Unconditional Branch; Flow J 0x26f1 seq_branch_adr 26f1 0x26f1 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26ed 26ed seq_br_type 3 Unconditional Branch; Flow J 0x26f1 seq_branch_adr 26f1 0x26f1 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 7 26ee 26ee fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 5 26ef 26ef fiu_len_fill_lit 7a zero-fill 0x3a fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 3f VR02:1f val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 26f0 26f0 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26f1 26f1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 26f2 26f2 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x26f4 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 26f4 0x26f4 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_c_adr 30 GP0f val_a_adr 31 VR02:11 val_c_adr 30 GP0f val_frame 2 26f3 26f3 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26f4 26f4 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26f5 0x26f5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_b_adr 0f GP0f 26f5 ; -------------------------------------------------------------------------------------- 26f5 ; Comes from: 26f5 ; 26e0 C True from color 0x26e0 26f5 ; -------------------------------------------------------------------------------------- 26f5 26f5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26d7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26d7 0x26d7 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 26f6 26f6 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x26dd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 26dd 0x26dd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26f7 26f7 fiu_load_var 1 hold_var; Flow C cc=False 0x26f9 fiu_tivi_src 1 tar_val seq_br_type 4 Call False seq_branch_adr 26f9 0x26f9 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 0 PASS_A 26f8 26f8 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True ; Flow J cc=False 0x26d6 fiu_offs_lit 50 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 26d6 0x26d6 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26f9 ; -------------------------------------------------------------------------------------- 26f9 ; Comes from: 26f9 ; 26f7 C False from color 0x26b6 26f9 ; -------------------------------------------------------------------------------------- 26f9 26f9 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26fa ; -------------------------------------------------------------------------------------- 26fa ; Comes from: 26fa ; 1461 C True from color 0x09aa 26fa ; 1749 C from color 0x09ac 26fa ; 17f0 C from color 0x09ab 26fa ; 1832 C True from color 0x09a9 26fa ; 1b74 C from color 0x1b73 26fa ; 1dbd C from color 0x0000 26fa ; -------------------------------------------------------------------------------------- 26fa 26fa fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 26fb 26fb fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2706 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2706 0x2706 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 26fc 26fc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2701 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2701 0x2701 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 26fd 26fd fiu_fill_mode_src 0 ; Flow J 0x26fe fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26fe 0x26fe typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 26fe 26fe fiu_fill_mode_src 0 ; Flow J cc=False 0x2703 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2703 0x2703 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 26ff 26ff fiu_fill_mode_src 0 ; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2700 2700 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2701 2701 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2702 2702 fiu_fill_mode_src 0 ; Flow J 0x26fe fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26fe 0x26fe typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2703 2703 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2704 2704 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2705 2705 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2706 2706 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x270d fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 270d 0x270d seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2707 2707 fiu_load_tar 1 hold_tar; Flow J cc=True 0x271a fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 271a 0x271a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 2708 2708 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2709 2709 fiu_fill_mode_src 0 ; Flow J 0x2710 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2710 0x2710 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 270a 270a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 270b 270b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x26fc fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 26fc 0x26fc seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 270c 270c fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2707 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2707 0x2707 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 270d 270d fiu_load_tar 1 hold_tar; Flow J cc=True 0x271a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 271a 0x271a 270e 270e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 270f 270f fiu_fill_mode_src 0 ; Flow J 0x2710 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2710 0x2710 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2710 2710 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2714 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2714 0x2714 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2711 2711 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA 2712 2712 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2717 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2713 2713 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2700 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2700 0x2700 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2714 2714 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2715 2715 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2717 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2716 2716 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2700 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2700 0x2700 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2717 ; -------------------------------------------------------------------------------------- 2717 ; Comes from: 2717 ; 2712 C True from color 0x26fa 2717 ; 2715 C True from color 0x26fa 2717 ; 272e C True from color 0x26fa 2717 ; 2732 C True from color 0x26fa 2717 ; 2739 C True from color 0x26fa 2717 ; 273f C True from color 0x26fa 2717 ; 2744 C True from color 0x26fa 2717 ; -------------------------------------------------------------------------------------- 2717 2717 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 2718 2718 fiu_mem_start 2 start-rd 2719 2719 seq_br_type a Unconditional Return; Flow R 271a 271a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2721 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2721 0x2721 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 271b 271b fiu_fill_mode_src 0 ; Flow J cc=True 0x2729 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2729 0x2729 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 271c 271c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 271d 271d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2725 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2725 0x2725 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 271e 271e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 271f 271f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2720 2720 ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x2729 seq_br_type 9 Return False seq_branch_adr 2729 0x2729 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2721 2721 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 2722 2722 fiu_fill_mode_src 0 ; Flow J cc=True 0x2729 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2729 0x2729 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2723 2723 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2724 2724 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x271e fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 271e 0x271e seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2725 2725 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2726 2726 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2727 2727 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2728 0x2728 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2728 2728 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2729 0x2729 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2729 2729 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x270a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 270a 0x270a seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 272a 272a fiu_mem_start 4 continue; Flow J cc=False 0x2734 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2734 0x2734 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 272b 272b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 272c 272c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329a seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 272d 272d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2732 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2732 0x2732 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 272e 272e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2717 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 272f 272f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2730 0x2730 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2730 2730 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2731 2731 fiu_load_oreg 1 hold_oreg; Flow J 0x272d fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 272d 0x272d typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2732 2732 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2717 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2733 2733 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x270a seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270a 0x270a seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2734 2734 fiu_load_var 1 hold_var; Flow J cc=False 0x2742 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2742 0x2742 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2735 2735 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2736 2736 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 2737 2737 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329a seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 2738 2738 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x273d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 273d 0x273d typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2739 2739 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2717 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 273a 273a ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273b 0x273b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 273b 273b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 273c 273c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2738 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2738 0x2738 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 273d 273d fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 273e 273e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273f 0x273f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 273f 273f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2717 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT 2740 2740 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2741 0x2741 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2741 2741 ioc_tvbs 2 fiu+val; Flow R cc=True ; Flow J cc=False 0x270a seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270a 0x270a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2742 2742 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2743 2743 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2744 2744 ioc_fiubs 0 fiu ; Flow C cc=True 0x2717 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2717 0x2717 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2745 2745 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x270a seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 270a 0x270a seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2746 ; -------------------------------------------------------------------------------------- 2746 ; 0x02cb Declare_Variable Entry 2746 ; -------------------------------------------------------------------------------------- 2746 MACRO_Declare_Variable_Entry: 2746 2746 dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2746 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 6 2747 2747 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2748 2748 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 val_rand a PASS_B_HIGH 2749 2749 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x274d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 274d 0x274d seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 274a 274a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 274b 274b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3277 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 274c 274c fiu_len_fill_lit 58 zero-fill 0x18; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 1c ? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 274d ; -------------------------------------------------------------------------------------- 274d ; Comes from: 274d ; 2749 C True from color MACRO_Declare_Variable_Entry 274d ; 2753 C True from color 0x0000 274d ; -------------------------------------------------------------------------------------- 274d 274d seq_br_type a Unconditional Return; Flow R val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 274e ; -------------------------------------------------------------------------------------- 274e ; 0x02c9 Declare_Variable Family 274e ; -------------------------------------------------------------------------------------- 274e MACRO_Declare_Variable_Family: 274e 274e dispatch_brk_class 4 ; Flow C cc=False 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 274e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 6 274f 274f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2750 2750 fiu_tivi_src 1 tar_val; Flow C cc=False 0x32aa ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2751 2751 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x2760 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2760 0x2760 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 2752 2752 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3277 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 3277 0x3277 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2753 2753 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x274d seq_br_type 5 Call True seq_branch_adr 274d 0x274d seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 val_rand a PASS_B_HIGH 2754 2754 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x275b seq_br_type 5 Call True seq_branch_adr 275b 0x275b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 2755 2755 fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 2756 2756 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2756 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2756 0x2756 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2757 2757 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x275e fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 275e 0x275e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 20 TOP - 0x1 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2758 2758 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2759 2759 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 275a 275a fiu_mem_start 3 start-wr; Flow J 0x2756 seq_br_type 3 Unconditional Branch seq_branch_adr 2756 0x2756 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A val_a_adr 30 VR05:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 275b ; -------------------------------------------------------------------------------------- 275b ; Comes from: 275b ; 2754 C True from color 0x0000 275b ; -------------------------------------------------------------------------------------- 275b 275b fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 275c 275c ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 275d 275d fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf65 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f65 0x0f65 275e 275e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 02 GP02 275f 275f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 3b TR06:1b typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2760 2760 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA 2761 2761 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32aa ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2762 2762 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x275e fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 275e 0x275e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2763 2763 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2764 ; -------------------------------------------------------------------------------------- 2764 ; 0x02cf Declare_Variable Select 2764 ; -------------------------------------------------------------------------------------- 2764 MACRO_Declare_Variable_Select: 2764 2764 dispatch_brk_class 4 ; Flow J 0x2767 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2764 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2767 0x2767 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 34 TR05:14 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2765 ; -------------------------------------------------------------------------------------- 2765 ; Comes from: 2765 ; 2768 C True from color 0x0000 2765 ; -------------------------------------------------------------------------------------- 2765 2765 seq_br_type a Unconditional Return; Flow R typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2766 ; -------------------------------------------------------------------------------------- 2766 ; 0x02ce Declare_Variable Select,Choice_Open 2766 ; -------------------------------------------------------------------------------------- 2766 MACRO_Declare_Variable_Select,Choice_Open: 2766 2766 dispatch_brk_class 4 ; Flow J 0x2767 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2766 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2767 0x2767 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 20 TR06:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2767 2767 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2781 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2781 0x2781 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 1d TOP - 3 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 2768 2768 seq_b_timing 1 Latch Condition; Flow C cc=True 0x2765 seq_br_type 5 Call True seq_branch_adr 2765 0x2765 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2769 2769 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x32b0 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32b0 0x32b0 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 276a 276a fiu_load_var 1 hold_var; Flow C cc=True 0x32aa fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 276b 276b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 30 VR06:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 276c 276c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 3e TR05:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1 A_PLUS_B val_b_adr 2f VR05:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 276d 276d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2774 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2774 0x2774 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 276e 276e fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 276f 276f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2770 2770 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2771 2771 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_frame 2 2772 2772 ioc_load_wdr 0 ; Flow C cc=True 0x2a82 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 2773 2773 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x276e fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 276e 0x276e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2774 2774 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x277c ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 277c 0x277c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2775 2775 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 2776 2776 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2777 2777 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2778 2778 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2779 2779 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 36 TR02:16 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 277a 277a fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x2a82 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_random 02 ? typ_a_adr 14 ZEROS typ_b_adr 02 GP02 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 277b 277b fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2775 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2775 0x2775 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 277c 277c fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x277e fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 277e 0x277e typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 277d 277d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 277e 277e ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 1 START_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 277f 277f ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2780 2780 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2781 2781 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x32b0 seq_br_type 9 Return False seq_branch_adr 32b0 0x32b0 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2a TR07:0a typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 2782 ; -------------------------------------------------------------------------------------- 2782 ; 0x0271 Execute Discrete,Times 2782 ; -------------------------------------------------------------------------------------- 2782 MACRO_Execute_Discrete,Times: 2782 2782 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2782 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 2783 2783 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2784 0x2784 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 2784 2784 ioc_fiubs 0 fiu ; Flow J cc=True 0x2795 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2795 0x2795 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2785 2785 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2788 seq_br_type 0 Branch False seq_branch_adr 2788 0x2788 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2786 2786 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2787 2787 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2788 2788 seq_b_timing 1 Latch Condition; Flow J cc=True 0x278e seq_br_type 1 Branch True seq_branch_adr 278e 0x278e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 2789 2789 seq_b_timing 1 Latch Condition; Flow J cc=True 0x278b seq_br_type 1 Branch True seq_branch_adr 278b 0x278b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 278a 278a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x278d fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 278d 0x278d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 278b 278b seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 278c 278c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 278d 278d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 278e 278e seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 278f 278f seq_b_timing 1 Latch Condition; Flow J cc=False 0x2791 seq_br_type 0 Branch False seq_branch_adr 2791 0x2791 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2790 2790 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2794 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2794 0x2794 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 2791 2791 fiu_load_var 1 hold_var; Flow C cc=True 0x3276 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2792 2792 fiu_load_var 1 hold_var; Flow C cc=False 0x3276 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 2793 2793 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2787 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2794 2794 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2795 2795 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2796 2796 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x279b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 279b 0x279b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2797 2797 ioc_fiubs 1 val ; Flow J cc=True 0x279c ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 279c 0x279c seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 2798 2798 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 2799 2799 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 279a 0x279a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 279a 279a ioc_fiubs 0 fiu ; Flow J 0x2785 seq_br_type 3 Unconditional Branch seq_branch_adr 2785 0x2785 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 279b 279b fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 11 TOP + 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 279c 279c ioc_fiubs 1 val ; Flow J cc=True 0x27ad seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27ad 0x27ad seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 279d 279d ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 279e 279e seq_b_timing 1 Latch Condition; Flow J cc=False 0x27a0 seq_br_type 0 Branch False seq_branch_adr 27a0 0x27a0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 279f 279f seq_br_type 3 Unconditional Branch; Flow J 0x27ad seq_branch_adr 27ad 0x27ad seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27a0 27a0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27a6 seq_br_type 1 Branch True seq_branch_adr 27a6 0x27a6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27a1 27a1 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27a3 seq_br_type 1 Branch True seq_branch_adr 27a3 0x27a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27a2 27a2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27a5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27a5 0x27a5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27a3 27a3 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27a4 27a4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 27a5 27a5 ioc_tvbs 1 typ+fiu; Flow J 0x27ad seq_br_type 3 Unconditional Branch seq_branch_adr 27ad 0x27ad seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27a6 27a6 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27a7 27a7 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27a9 seq_br_type 0 Branch False seq_branch_adr 27a9 0x27a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27a8 27a8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27ac fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27ac 0x27ac seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27a9 27a9 fiu_load_var 1 hold_var; Flow C cc=True 0x3276 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27aa 27aa fiu_load_var 1 hold_var; Flow C cc=False 0x3276 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27ab 27ab fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27ad fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27ad 0x27ad seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27ac 27ac ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27ad 27ad fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 27ae ; -------------------------------------------------------------------------------------- 27ae ; 0x026d Execute Discrete,Exponentiate 27ae ; -------------------------------------------------------------------------------------- 27ae MACRO_Execute_Discrete,Exponentiate: 27ae 27ae dispatch_brk_class 8 ; Flow J cc=False 0x27cf dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 27ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 27cf 0x27cf seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 2 27af 27af ioc_fiubs 1 val ; Flow C cc=True 0x27d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 27d9 0x27d9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 27b0 27b0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu 27b1 27b1 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27b2 ; Flow J cc=#0x0 0x27b2 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27b2 0x27b2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27b2 27b2 ioc_fiubs 1 val ; Flow J 0x27b4 seq_br_type 3 Unconditional Branch seq_branch_adr 27b4 0x27b4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 27b3 27b3 fiu_load_var 1 hold_var; Flow J 0x27bb fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 27bb 0x27bb seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27b4 27b4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x27b8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27b8 0x27b8 seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 27b5 27b5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b6 27b6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b7 27b7 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27b8 27b8 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27b9 ; Flow J cc=#0x0 0x27b2 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 27b2 0x27b2 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 27b9 27b9 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 27ba 27ba ioc_fiubs 0 fiu ; Flow J 0x27b8 seq_br_type 3 Unconditional Branch seq_branch_adr 27b8 0x27b8 27bb 27bb ioc_fiubs 1 val ; Flow J cc=True 0x27cb seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27cb 0x27cb seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27bc 27bc ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27bd 27bd seq_b_timing 1 Latch Condition; Flow J cc=False 0x27bf seq_br_type 0 Branch False seq_branch_adr 27bf 0x27bf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27be 27be seq_br_type 3 Unconditional Branch; Flow J 0x27cb seq_branch_adr 27cb 0x27cb seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27bf 27bf seq_b_timing 1 Latch Condition; Flow J cc=True 0x27c5 seq_br_type 1 Branch True seq_branch_adr 27c5 0x27c5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27c0 27c0 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27c2 seq_br_type 1 Branch True seq_branch_adr 27c2 0x27c2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27c1 27c1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27c4 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27c4 0x27c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27c2 27c2 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27c3 27c3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 0 PASS_A 27c4 27c4 ioc_tvbs 1 typ+fiu; Flow J 0x27cb seq_br_type 3 Unconditional Branch seq_branch_adr 27cb 0x27cb seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27c5 27c5 seq_b_timing 1 Latch Condition; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27c6 27c6 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27c8 seq_br_type 0 Branch False seq_branch_adr 27c8 0x27c8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27c7 27c7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27c4 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27c4 0x27c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27c8 27c8 fiu_load_var 1 hold_var; Flow C cc=True 0x3276 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27c9 27c9 fiu_load_var 1 hold_var; Flow C cc=False 0x3276 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27ca 27ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27cb fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27cb 0x27cb seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27cb 27cb ioc_fiubs 2 typ ; Flow J cc=True 0x27b2 seq_br_type 1 Branch True seq_branch_adr 27b2 0x27b2 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 27cc 27cc seq_b_timing 0 Early Condition; Flow J cc=False 0x27ce seq_br_type 0 Branch False seq_branch_adr 27ce 0x27ce seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 27cd 27cd fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27ce 27ce fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27cf 27cf ioc_tvbs 2 fiu+val; Flow J cc=True 0x27d8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27d8 0x27d8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A 27d0 27d0 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27d3 seq_br_type 1 Branch True seq_branch_adr 27d3 0x27d3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand b DIVIDE 27d1 27d1 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27cd seq_br_type 1 Branch True seq_branch_adr 27cd 0x27cd seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27d2 27d2 seq_br_type 7 Unconditional Call; Flow C 0x326e seq_branch_adr 326e 0x326e 27d3 27d3 ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 27d4 27d4 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 27d5 0x27d5 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 27d5 27d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d6 27d6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d7 27d7 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2787 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2787 0x2787 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27d8 27d8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 27d9 27d9 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x27dc fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 27dc 0x27dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 27da 27da seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 27db 0x27db seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_frame 2 27db 27db fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x27e0 fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27e0 0x27e0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 05 GP05 27dc 27dc fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27dd ; Flow J cc=#0x0 0x27dd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27dd 0x27dd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 27dd 27dd fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2787 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2787 0x2787 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 6 27de 27de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 27df 27df fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2787 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2787 0x2787 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 5 27e0 27e0 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27e1 ; Flow J cc=#0x0 0x27e1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27e1 0x27e1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 27e1 27e1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 27e2 27e2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 27e3 27e3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 27e4 27e4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 27e5 27e5 <halt> ; Flow R 27e6 ; -------------------------------------------------------------------------------------- 27e6 ; 0x0141 Execute Discrete,Multiply_And_Scale 27e6 ; -------------------------------------------------------------------------------------- 27e6 MACRO_Execute_Discrete,Multiply_And_Scale: 27e6 27e6 dispatch_brk_class 8 ; Flow C cc=False 0x2800 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 27e6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 2800 0x2800 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 27e7 27e7 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x2802 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 2802 0x2802 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 27e8 27e8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 27e9 27e9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 27ea 27ea fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 27eb 27eb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27ec 27ec seq_br_type 0 Branch False; Flow J cc=False 0x2803 seq_branch_adr 2803 0x2803 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 2b TR02:0b typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27ed 27ed ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 27ee 27ee seq_b_timing 0 Early Condition; Flow J cc=True 0x27fd seq_br_type 1 Branch True seq_branch_adr 27fd 0x27fd seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 27ef 27ef ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR11:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 27f0 27f0 seq_b_timing 0 Early Condition; Flow J cc=True 0x27f8 seq_br_type 1 Branch True seq_branch_adr 27f8 0x27f8 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 27f1 27f1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27f2 27f2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_b_src 2 Bits 32…47 27f3 27f3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 27f4 27f4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 27f5 27f5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 27f6 27f6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27f7 27f7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 27f8 27f8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27f9 27f9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27fa 27fa seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 27fb 27fb seq_br_type 3 Unconditional Branch; Flow J 0x27fd seq_branch_adr 27fd 0x27fd seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 27fc 27fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3276 seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 27fd 27fd fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x27fc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 27fc 0x27fc seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 0 PASS_A val_a_adr 02 GP02 27fe 27fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x27ad fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27ad 0x27ad typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 27ff 27ff fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3276 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2800 2800 seq_br_type 0 Branch False; Flow J cc=False 0x2803 seq_branch_adr 2803 0x2803 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2801 2801 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA 2802 2802 seq_br_type 1 Branch True; Flow J cc=True 0x2801 seq_branch_adr 2801 0x2801 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2803 2803 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2804 ; -------------------------------------------------------------------------------------- 2804 ; 0x0247 Execute Float,Equal 2804 ; -------------------------------------------------------------------------------------- 2804 MACRO_Execute_Float,Equal: 2804 2804 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2804 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2805 2805 <halt> ; Flow R 2806 ; -------------------------------------------------------------------------------------- 2806 ; 0x014e Execute Float,Equal_Zero 2806 ; -------------------------------------------------------------------------------------- 2806 MACRO_Execute_Float,Equal_Zero: 2806 2806 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2806 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2807 2807 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2808 ; -------------------------------------------------------------------------------------- 2808 ; 0x0245 Execute Float,Greater 2808 ; -------------------------------------------------------------------------------------- 2808 MACRO_Execute_Float,Greater: 2808 2808 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2808 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2809 2809 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2807 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2807 0x2807 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 280a ; -------------------------------------------------------------------------------------- 280a ; 0x014c Execute Float,Greater_Zero 280a ; -------------------------------------------------------------------------------------- 280a MACRO_Execute_Float,Greater_Zero: 280a 280a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 280a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 280b 280b <halt> ; Flow R 280c ; -------------------------------------------------------------------------------------- 280c ; 0x0246 Execute Float,Not_Equal 280c ; -------------------------------------------------------------------------------------- 280c MACRO_Execute_Float,Not_Equal: 280c 280c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 280c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 280d 280d <halt> ; Flow R 280e ; -------------------------------------------------------------------------------------- 280e ; 0x014d Execute Float,Not_Equal_Zero 280e ; -------------------------------------------------------------------------------------- 280e MACRO_Execute_Float,Not_Equal_Zero: 280e 280e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 280e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 280f 280f fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2810 ; -------------------------------------------------------------------------------------- 2810 ; 0x0244 Execute Float,Less 2810 ; -------------------------------------------------------------------------------------- 2810 MACRO_Execute_Float,Less: 2810 2810 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2810 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2811 2811 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x280f fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 280f 0x280f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2812 ; -------------------------------------------------------------------------------------- 2812 ; 0x014b Execute Float,Less_Zero 2812 ; -------------------------------------------------------------------------------------- 2812 MACRO_Execute_Float,Less_Zero: 2812 2812 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2812 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2813 2813 <halt> ; Flow R 2814 ; -------------------------------------------------------------------------------------- 2814 ; 0x0243 Execute Float,Greater_Equal 2814 ; -------------------------------------------------------------------------------------- 2814 MACRO_Execute_Float,Greater_Equal: 2814 2814 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2814 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2815 2815 fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2816 0x2816 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2816 2816 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2817 2817 <halt> ; Flow R 2818 ; -------------------------------------------------------------------------------------- 2818 ; 0x014a Execute Float,Greater_Equal_Zero 2818 ; -------------------------------------------------------------------------------------- 2818 MACRO_Execute_Float,Greater_Equal_Zero: 2818 2818 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2818 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2819 2819 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 281a ; -------------------------------------------------------------------------------------- 281a ; 0x0242 Execute Float,Less_Equal 281a ; -------------------------------------------------------------------------------------- 281a MACRO_Execute_Float,Less_Equal: 281a 281a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 281a ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 281b 281b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2819 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2819 0x2819 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 281c ; -------------------------------------------------------------------------------------- 281c ; 0x0149 Execute Float,Less_Equal_Zero 281c ; -------------------------------------------------------------------------------------- 281c MACRO_Execute_Float,Less_Equal_Zero: 281c 281c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 281c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 281d 281d <halt> ; Flow R 281e ; -------------------------------------------------------------------------------------- 281e ; 0x0241 Execute Float,First 281e ; -------------------------------------------------------------------------------------- 281e MACRO_Execute_Float,First: 281e 281e dispatch_brk_class 8 ; Flow J 0x281f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 281e dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_br_type 3 Unconditional Branch seq_branch_adr 281f 0x281f typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 281f 281f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2820 ; -------------------------------------------------------------------------------------- 2820 ; 0x0240 Execute Float,Last 2820 ; -------------------------------------------------------------------------------------- 2820 MACRO_Execute_Float,Last: 2820 2820 dispatch_brk_class 8 ; Flow J 0x281f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2820 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 281f 0x281f typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 2821 2821 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2822 ; -------------------------------------------------------------------------------------- 2822 ; 0x023f Execute Float,Unary_Minus 2822 ; -------------------------------------------------------------------------------------- 2822 MACRO_Execute_Float,Unary_Minus: 2822 2822 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2822 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2823 2823 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2821 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2821 0x2821 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2824 ; -------------------------------------------------------------------------------------- 2824 ; 0x023e Execute Float,Absolute_Value 2824 ; -------------------------------------------------------------------------------------- 2824 MACRO_Execute_Float,Absolute_Value: 2824 2824 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2824 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2825 2825 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c seq_en_micro 0 seq_random 02 ? 2826 ; -------------------------------------------------------------------------------------- 2826 ; 0x023d Execute Float,Plus 2826 ; -------------------------------------------------------------------------------------- 2826 MACRO_Execute_Float,Plus: 2826 2826 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2826 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2827 2827 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2828 2828 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x2839 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2839 0x2839 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP 2829 2829 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2834 fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2834 0x2834 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 282a 282a fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2842 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2842 0x2842 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 282b 282b fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x282c fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 282c 0x282c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 282c 282c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2832 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2832 0x2832 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 282d 282d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2841 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2841 0x2841 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2a TR02:0a typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 282e 282e fiu_len_fill_lit 74 zero-fill 0x34 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 05 GP05 282f 282f fiu_fill_mode_src 0 ; Flow J cc=False 0x2844 fiu_len_fill_lit 73 zero-fill 0x33 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 2844 0x2844 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 2830 2830 fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 2831 2831 fiu_len_fill_lit 73 zero-fill 0x33; Flow R cc=False ; Flow J cc=True 0x2833 fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2833 0x2833 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2832 2832 seq_b_timing 0 Early Condition; Flow J cc=False 0x283e seq_br_type 0 Branch False seq_branch_adr 283e 0x283e seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2833 2833 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2834 2834 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2842 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2842 0x2842 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2835 2835 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x282c fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 282c 0x282c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2836 ; -------------------------------------------------------------------------------------- 2836 ; 0x023c Execute Float,Minus 2836 ; -------------------------------------------------------------------------------------- 2836 MACRO_Execute_Float,Minus: 2836 2836 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2836 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2837 2837 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2838 2838 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2829 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2829 0x2829 seq_random 02 ? typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2839 2839 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x283f fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 283f 0x283f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 283a 283a fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2843 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2843 0x2843 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 283b 283b fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x283c fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 283c 0x283c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 283c 283c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x282d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 282d 0x282d seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 283d 283d seq_b_timing 0 Early Condition; Flow J cc=True 0x2833 seq_br_type 1 Branch True seq_branch_adr 2833 0x2833 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 283e 283e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 283f 283f fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2843 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2843 0x2843 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 2 INC_A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2840 2840 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x283c fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 283c 0x283c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2841 2841 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2842 2842 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2843 2843 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2844 2844 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x2841 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 0 Branch False seq_branch_adr 2841 0x2841 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_frame 11 2845 2845 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2833 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2833 0x2833 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2846 ; -------------------------------------------------------------------------------------- 2846 ; 0x023b Execute Float,Times 2846 ; -------------------------------------------------------------------------------------- 2846 MACRO_Execute_Float,Times: 2846 2846 dispatch_brk_class 8 ; Flow J cc=True 0x286d dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2846 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 286d 0x286d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2847 2847 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3c TR08:1c typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2848 2848 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x286d fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 286d 0x286d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 2d VR1b:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1b 2849 2849 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x285a seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 285a 0x285a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 284a 284a seq_b_timing 0 Early Condition; Flow J cc=True 0x2867 seq_br_type 1 Branch True seq_branch_adr 2867 0x2867 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 284b 284b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 284c 284c seq_b_timing 1 Latch Condition; Flow J cc=True 0x286e seq_br_type 1 Branch True seq_branch_adr 286e 0x286e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 284d 284d seq_b_timing 1 Latch Condition; Flow J cc=True 0x2872 seq_br_type 1 Branch True seq_branch_adr 2872 0x2872 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 284e 284e seq_br_type 0 Branch False; Flow J cc=False 0x2876 seq_branch_adr 2876 0x2876 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 284f 284f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2876 seq_br_type 1 Branch True seq_branch_adr 2876 0x2876 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 2850 2850 seq_br_type 7 Unconditional Call; Flow C 0x288c seq_branch_adr 288c 0x288c seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 2851 2851 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2852 2852 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2853 2853 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2854 2854 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2855 2855 fiu_load_var 1 hold_var; Flow J cc=True 0x2858 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2858 0x2858 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2856 2856 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_var 1 hold_var fiu_offs_lit 42 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 2857 2857 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2858 0x2858 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2858 2858 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 2859 2859 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 285a 285a seq_b_timing 0 Early Condition; Flow J cc=True 0x2861 seq_br_type 1 Branch True seq_branch_adr 2861 0x2861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 285b 285b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 285c 285c seq_b_timing 1 Latch Condition; Flow J cc=True 0x286e seq_br_type 1 Branch True seq_branch_adr 286e 0x286e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 285d 285d seq_b_timing 1 Latch Condition; Flow J cc=True 0x2872 seq_br_type 1 Branch True seq_branch_adr 2872 0x2872 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 285e 285e seq_br_type 0 Branch False; Flow J cc=False 0x2876 seq_branch_adr 2876 0x2876 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 285f 285f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2876 seq_br_type 1 Branch True seq_branch_adr 2876 0x2876 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 2860 2860 seq_br_type 3 Unconditional Branch; Flow J 0x2851 seq_branch_adr 2851 0x2851 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 2861 2861 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2862 2862 seq_b_timing 1 Latch Condition; Flow J cc=True 0x286e seq_br_type 1 Branch True seq_branch_adr 286e 0x286e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2863 2863 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2872 seq_br_type 1 Branch True seq_branch_adr 2872 0x2872 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 2864 2864 seq_br_type 0 Branch False; Flow J cc=False 0x2876 seq_branch_adr 2876 0x2876 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2865 2865 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2876 seq_br_type 1 Branch True seq_branch_adr 2876 0x2876 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2866 2866 seq_br_type 3 Unconditional Branch; Flow J 0x2854 seq_branch_adr 2854 0x2854 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2867 2867 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 2868 2868 seq_b_timing 1 Latch Condition; Flow J cc=True 0x286e seq_br_type 1 Branch True seq_branch_adr 286e 0x286e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2869 2869 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2872 seq_br_type 1 Branch True seq_branch_adr 2872 0x2872 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 286a 286a seq_br_type 0 Branch False; Flow J cc=False 0x2876 seq_branch_adr 2876 0x2876 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 286b 286b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2876 seq_br_type 1 Branch True seq_branch_adr 2876 0x2876 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 286c 286c seq_br_type 3 Unconditional Branch; Flow J 0x2851 seq_branch_adr 2851 0x2851 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 286d 286d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 286e 286e fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x286d fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 286d 0x286d seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 286f 286f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 2870 2870 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 2871 2871 ioc_tvbs 3 fiu+fiu; Flow J 0x2879 seq_br_type 3 Unconditional Branch seq_branch_adr 2879 0x2879 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2872 2872 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2873 2873 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 2874 2874 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 2875 2875 ioc_tvbs 3 fiu+fiu; Flow J 0x2879 seq_br_type 3 Unconditional Branch seq_branch_adr 2879 0x2879 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2876 2876 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_b_adr 02 GP02 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2877 2877 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2878 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 287b 0x287b seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2878 2878 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2885 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2885 0x2885 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2879 2879 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287a 287a seq_br_type 7 Unconditional Call; Flow C 0x2885 seq_branch_adr 2885 0x2885 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 287b 287b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 287c 287c seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287d 287d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x287f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 287f 0x287f seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 287e 287e fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x2880 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2880 0x2880 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 287f 287f fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 2880 2880 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x3276 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 2881 2881 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x2883 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2883 0x2883 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR09:03 typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2882 2882 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2883 2883 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x286d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 286d 0x286d seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 2884 2884 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2885 ; -------------------------------------------------------------------------------------- 2885 ; Comes from: 2885 ; 28a9 C from color MACRO_Execute_Float,Exponentiate 2885 ; -------------------------------------------------------------------------------------- 2885 2885 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 2886 2886 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 2887 2887 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 2888 2888 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 2889 2889 seq_br_type 7 Unconditional Call; Flow C 0x288c seq_branch_adr 288c 0x288c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 288a 288a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 288b 288b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 288c ; -------------------------------------------------------------------------------------- 288c ; Comes from: 288c ; 2850 C from color MACRO_Execute_Float,Times 288c ; 2889 C from color MACRO_Execute_Float,Times 288c ; -------------------------------------------------------------------------------------- 288c 288c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 288d 288d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 288e 288e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 288f 288f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 2890 ; -------------------------------------------------------------------------------------- 2890 ; 0x0239 Execute Float,Exponentiate 2890 ; -------------------------------------------------------------------------------------- 2890 MACRO_Execute_Float,Exponentiate: 2890 2890 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2890 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2891 2891 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2895 fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 2895 0x2895 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2892 2892 fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_rand 5 COUNT_ZEROS 2893 2893 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 29 VR05:09 val_frame 5 2894 2894 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2895 2895 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2897 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2897 0x2897 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 2896 2896 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 2897 2897 fiu_load_var 1 hold_var; Flow J 0x289a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 289a 0x289a typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2898 2898 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x28a8 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 28a8 0x28a8 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 2899 2899 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 289a 289a fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x28a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 28a8 0x28a8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 289b 289b fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x2898 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2898 0x2898 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 289c 289c fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x289e fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 289e 0x289e seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3b TR11:1b typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 14 ZEROS 289d 289d fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x28a6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 28a6 0x28a6 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_c_adr 3b GP04 typ_frame 11 val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 289e 289e fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28a6 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28a6 0x28a6 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 3f TR08:1f typ_b_adr 03 GP03 typ_frame 8 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 289f 289f fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x28a2 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28a2 0x28a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 28a0 28a0 seq_br_type 0 Branch False; Flow J cc=False 0x28a7 seq_branch_adr 28a7 0x28a7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 10 TOP 28a1 28a1 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28a5 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28a5 0x28a5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 val_a_adr 39 VR12:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 12 28a2 28a2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28a3 0x28a3 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a3 28a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 28a4 28a4 seq_br_type 3 Unconditional Branch; Flow J 0x28ae seq_branch_adr 28ae MACRO_Execute_Float,Divide val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28a5 28a5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28a7 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 28a7 0x28a7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a6 28a6 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28a7 0x28a7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28a7 28a7 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 28a8 28a8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28a9 28a9 ioc_tvbs 2 fiu+val; Flow C 0x2885 seq_br_type 7 Unconditional Call seq_branch_adr 2885 0x2885 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 28aa 28aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a5 seq_br_type 1 Branch True seq_branch_adr 28a5 0x28a5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 28ab 28ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a6 seq_br_type 1 Branch True seq_branch_adr 28a6 0x28a6 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28ac 28ac ioc_load_wdr 0 ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 28ad 0x28ad seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28ad 28ad ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28ae ; -------------------------------------------------------------------------------------- 28ae ; 0x023a Execute Float,Divide 28ae ; -------------------------------------------------------------------------------------- 28ae MACRO_Execute_Float,Divide: 28ae 28ae dispatch_brk_class 8 ; Flow C cc=True 0x3275 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28ae fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 3 LEFT_I_A val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 28af 28af fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x28bd fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 28bd 0x28bd seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 28b0 28b0 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 23 VR09:03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 28b1 28b1 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28c5 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c5 0x28c5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28b2 28b2 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28c0 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c0 0x28c0 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 28b3 28b3 fiu_len_fill_lit 61 zero-fill 0x21 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b4 28b4 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_tivi_src 8 type_var seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 35 TR02:15 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b5 28b5 fiu_fill_mode_src 0 fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b6 28b6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b7 28b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x28b7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 28b7 0x28b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b8 28b8 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28ba fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28ba 0x28ba seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 3f TR08:1f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28b9 28b9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 0b fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 28ba 28ba ioc_tvbs 2 fiu+val; Flow C cc=True 0x3276 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 28bb 28bb fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3e TR08:1e typ_frame 8 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 28bc 28bc fiu_len_fill_lit 0b sign-fill 0xb; Flow R cc=True ; Flow J cc=False 0x28c2 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28c2 0x28c2 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28bd ; -------------------------------------------------------------------------------------- 28bd ; Comes from: 28bd ; 28af C True from color MACRO_Execute_Float,Exponentiate 28bd ; -------------------------------------------------------------------------------------- 28bd 28bd fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 26 VR05:06 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 28be 28be fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 28bf 28bf fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 28c0 28c0 seq_br_type 4 Call False; Flow C cc=False 0x3276 seq_branch_adr 3276 0x3276 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 28c1 28c1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28c2 28c2 fiu_len_fill_lit 7e zero-fill 0x3e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 28c3 28c3 fiu_fill_mode_src 0 ; Flow J cc=False 0x28c1 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 28c1 0x28c1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 23 VR09:03 val_frame 9 28c4 28c4 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28c5 28c5 fiu_load_var 1 hold_var; Flow J cc=True 0x28c9 fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28c9 0x28c9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_alu_func 3 LEFT_I_A val_b_adr 39 VR02:19 val_frame 2 val_rand 5 COUNT_ZEROS 28c6 28c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28c1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28c1 0x28c1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 3 LEFT_I_A val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 28c7 28c7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 28c8 28c8 fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x28b2 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28b2 0x28b2 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 28c9 28c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28c0 seq_br_type 1 Branch True seq_branch_adr 28c0 0x28c0 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 28ca 28ca fiu_len_fill_lit 74 zero-fill 0x34; Flow C cc=True 0x3276 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3276 0x3276 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR08:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 28cb 28cb ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 28cc 28cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x28bb fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 28bb 0x28bb typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 28cd 28cd <halt> ; Flow R 28ce ; -------------------------------------------------------------------------------------- 28ce ; 0x0238 Execute Float,Convert 28ce ; -------------------------------------------------------------------------------------- 28ce MACRO_Execute_Float,Convert: 28ce 28ce dispatch_brk_class 4 ; Flow J cc=True 0x28d0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28ce dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28d0 0x28d0 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 28cf 28cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2825 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2825 0x2825 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28d0 28d0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2825 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2825 0x2825 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 28d1 28d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2825 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2825 0x2825 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28d2 ; -------------------------------------------------------------------------------------- 28d2 ; 0x0237 Execute Float,Convert_From_Discrete 28d2 ; -------------------------------------------------------------------------------------- 28d2 MACRO_Execute_Float,Convert_From_Discrete: 28d2 28d2 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28d2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 28d3 28d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28d7 0x28d7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 28d4 28d4 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 28d5 0x28d5 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR11:19 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 28d5 28d5 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 28d6 28d6 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 28d7 28d7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_rand 5 COUNT_ZEROS 28d8 28d8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 28d9 28d9 fiu_fill_mode_src 0 ; Flow J 0x28d5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 28d5 0x28d5 seq_en_micro 0 val_a_adr 38 VR11:18 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 28da ; -------------------------------------------------------------------------------------- 28da ; 0x0236 Execute Float,Truncate_To_Discrete 28da ; -------------------------------------------------------------------------------------- 28da MACRO_Execute_Float,Truncate_To_Discrete: 28da 28da dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28da fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 28db 28db fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28de fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28de 0x28de seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 28dc 28dc fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e0 0x28e0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28dd 28dd fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x28e1 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 28e1 0x28e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 37 VR11:17 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 11 28de 28de fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e0 0x28e0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28df 28df fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x28e9 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 28e9 0x28e9 seq_en_micro 0 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 28e0 28e0 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 28e1 0x28e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 28e1 28e1 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 28e2 ; -------------------------------------------------------------------------------------- 28e2 ; 0x0235 Execute Float,Round_To_Discrete 28e2 ; -------------------------------------------------------------------------------------- 28e2 MACRO_Execute_Float,Round_To_Discrete: 28e2 28e2 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 28e2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 28e3 28e3 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 28e4 28e4 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28e0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28e0 0x28e0 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_frame 11 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 28e5 28e5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28e8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28e8 0x28e8 seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 28e6 28e6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28e7 28e7 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28e1 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28e1 0x28e1 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 28e8 28e8 fiu_len_fill_lit 00 sign-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28e9 28e9 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28e1 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28e1 0x28e1 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 28ea ; -------------------------------------------------------------------------------------- 28ea ; 0x0230 Execute Float,In_Range 28ea ; -------------------------------------------------------------------------------------- 28ea MACRO_Execute_Float,In_Range: 28ea 28ea dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 28ea fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 28eb 28eb fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28f0 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28f0 0x28f0 typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 31 VR02:11 val_frame 2 28ec 28ec fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28f7 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28f7 0x28f7 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 28ed 28ed <halt> ; Flow R 28ee ; -------------------------------------------------------------------------------------- 28ee ; 0x014f Execute Float,Not_In_Range 28ee ; -------------------------------------------------------------------------------------- 28ee MACRO_Execute_Float,Not_In_Range: 28ee 28ee dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 28ee fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 28ef 28ef fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x28ec fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 28ec 0x28ec typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 39 VR02:19 val_frame 2 28f0 28f0 ioc_tvbs 2 fiu+val; Flow J cc=True 0x28f7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 28f1 28f1 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28f7 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 28f2 ; -------------------------------------------------------------------------------------- 28f2 ; 0x0234 Execute Float,In_Type 28f2 ; -------------------------------------------------------------------------------------- 28f2 MACRO_Execute_Float,In_Type: 28f2 28f2 dispatch_brk_class 8 ; Flow J cc=True 0x28f5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28f2 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f5 0x28f5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 28f3 28f3 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x28f7 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28f7 0x28f7 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 28f4 ; -------------------------------------------------------------------------------------- 28f4 ; 0x0233 Execute Float,Not_In_Type 28f4 ; -------------------------------------------------------------------------------------- 28f4 MACRO_Execute_Float,Not_In_Type: 28f4 28f4 dispatch_brk_class 8 ; Flow J cc=False 0x28f3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28f4 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg fiu_offs_lit 01 ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28f3 0x28f3 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 28f5 28f5 fiu_load_var 1 hold_var; Flow J cc=True 0x28f7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 28f6 28f6 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 28f7 28f7 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 28f8 ; -------------------------------------------------------------------------------------- 28f8 ; 0x0232 Execute Float,Check_In_Type 28f8 ; -------------------------------------------------------------------------------------- 28f8 MACRO_Execute_Float,Check_In_Type: 28f8 28f8 dispatch_brk_class 8 ; Flow J cc=True 0x28fa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 28f8 dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28fa 0x28fa seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 28f9 28f9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2825 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2825 0x2825 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28fa 28fa ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2825 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2825 0x2825 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 28fb 28fb fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2825 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2825 0x2825 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 28fc ; -------------------------------------------------------------------------------------- 28fc ; 0x0231 Execute Float,Write_Unchecked 28fc ; -------------------------------------------------------------------------------------- 28fc MACRO_Execute_Float,Write_Unchecked: 28fc 28fc dispatch_brk_class 2 ; Flow C cc=False 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28fc fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 28fd 28fd typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 28fe 28fe fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3277 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 28ff 28ff fiu_fill_mode_src 0 ; Flow J cc=False 0x2901 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2901 0x2901 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 2900 2900 fiu_fill_mode_src 0 ; Flow J 0x2904 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2904 0x2904 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2901 2901 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2902 2902 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2903 2903 fiu_load_var 1 hold_var; Flow J 0x2904 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2904 0x2904 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2904 2904 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 2905 2905 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2906 ; -------------------------------------------------------------------------------------- 2906 ; 0x4800-0x4fff Short_Literal slit 2906 ; -------------------------------------------------------------------------------------- 2906 MACRO_Short_Literal_slit: 2906 2906 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2906 fiu_len_fill_lit 0a sign-fill 0xa fiu_mem_start 2 start-rd fiu_offs_lit 75 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2907 2907 fiu_mem_start 2 start-rd; Flow J 0x290f ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 290f 0x290f seq_en_micro 0 seq_random 38 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE 2908 ; -------------------------------------------------------------------------------------- 2908 ; 0x6000-0x67ff Indirect_Literal Discrete,pcrel,literal 2908 ; -------------------------------------------------------------------------------------- 2908 MACRO_Indirect_Literal_Discrete,pcrel,literal: 2908 2908 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 2908 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_random 38 ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2909 2909 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x2907 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2907 0x2907 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 290a ; -------------------------------------------------------------------------------------- 290a ; 0x5800-0x5fff Indirect_Literal Float,pcrel,dbl 290a ; -------------------------------------------------------------------------------------- 290a MACRO_Indirect_Literal_Float,pcrel,dbl: 290a 290a dispatch_brk_class 8 ; Flow J 0x2909 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 290a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2909 0x2909 seq_random 38 ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 290b 290b fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x290d fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290d 0x290d seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 290c ; -------------------------------------------------------------------------------------- 290c ; 0x00a2 Action Push_Discrete_Extended 290c ; -------------------------------------------------------------------------------------- 290c MACRO_Action_Push_Discrete_Extended: 290c 290c dispatch_brk_class 8 ; Flow J 0x290b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 290c fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290b 0x290b seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 290d 290d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x290f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 290f 0x290f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 290e ; -------------------------------------------------------------------------------------- 290e ; 0x00a1 Action Push_Float_Extended 290e ; -------------------------------------------------------------------------------------- 290e MACRO_Action_Push_Float_Extended: 290e 290e dispatch_brk_class 8 ; Flow J 0x290b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 290e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 290b 0x290b seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 290f 290f fiu_mem_start a start_continue_if_false; Flow J cc=True 0x2909 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2909 0x2909 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 2910 2910 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2911 2911 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2912 ; -------------------------------------------------------------------------------------- 2912 ; 0x0093 PushFullAddress InMicrocode,caddr 2912 ; -------------------------------------------------------------------------------------- 2912 MACRO_PushFullAddress_InMicrocode,caddr: 2912 2912 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2912 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2913 2913 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2914 2914 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2915 2915 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2916 ; -------------------------------------------------------------------------------------- 2916 ; 0x5000-0x57ff Indirect_Literal Any,pcrel,literal 2916 ; -------------------------------------------------------------------------------------- 2916 MACRO_Indirect_Literal_Any,pcrel,literal: 2916 2916 dispatch_brk_class 8 ; Flow C 0x2921 dispatch_csa_valid 1 dispatch_uadr 2916 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2921 0x2921 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 2917 2917 fiu_tivi_src c mar_0xc; Flow C 0x2961 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2961 0x2961 seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2918 2918 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 2919 2919 <halt> ; Flow R 291a ; -------------------------------------------------------------------------------------- 291a ; 0x00a0 Action Push_Structure_Extended,abs,mark 291a ; -------------------------------------------------------------------------------------- 291a MACRO_Action_Push_Structure_Extended,abs,mark: 291a 291a dispatch_brk_class 8 ; Flow C 0x2921 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 291a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2921 0x2921 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 291b 291b fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 291c 291c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x291d fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2918 0x2918 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 291d 291d ioc_fiubs 1 val ; Flow J 0x2961 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2961 0x2961 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 291e ; -------------------------------------------------------------------------------------- 291e ; 0x0115 Execute Any,Structure_Clear 291e ; -------------------------------------------------------------------------------------- 291e MACRO_Execute_Any,Structure_Clear: 291e 291e dispatch_brk_class 4 ; Flow C 0x2921 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 291e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2921 0x2921 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 291f 291f seq_br_type 7 Unconditional Call; Flow C 0x2a2c seq_branch_adr 2a2c 0x2a2c seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2920 2920 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 2921 ; -------------------------------------------------------------------------------------- 2921 ; Comes from: 2921 ; 2916 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2921 ; 291e C from color MACRO_Execute_Any,Structure_Clear 2921 ; -------------------------------------------------------------------------------------- 2921 2921 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2929 seq_br_type 1 Branch True seq_branch_adr 2929 0x2929 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP 2922 2922 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x292a fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 292a 0x292a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_latch 1 typ_b_adr 10 TOP typ_frame 8 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2923 2923 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x2928 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2928 0x2928 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2924 2924 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2925 2925 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2926 2926 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 03 GP03 2927 2927 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2928 2928 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x32a9 fiu_oreg_src 0 rotator output ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 38 ? typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 9 LOAD_MAR_CODE 2929 2929 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2928 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2928 0x2928 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 292a 292a fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 292b 292b ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 292c 292c fiu_len_fill_lit 4a zero-fill 0xa; Flow C 0x210 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c 292d 292d fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 292e 292e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2931 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2931 0x2931 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 292f 292f fiu_fill_mode_src 0 ; Flow C cc=False 0x2937 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2937 0x2937 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2930 2930 seq_br_type 3 Unconditional Branch; Flow J 0x2934 seq_branch_adr 2934 0x2934 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2931 2931 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2932 2932 fiu_fill_mode_src 0 ; Flow C cc=False 0x2937 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2937 0x2937 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2933 2933 seq_br_type 3 Unconditional Branch; Flow J 0x2934 seq_branch_adr 2934 0x2934 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2934 2934 fiu_load_oreg 1 hold_oreg; Flow R cc=True fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2935 0x2935 seq_en_micro 0 seq_random 38 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2935 2935 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2936 2936 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2937 ; -------------------------------------------------------------------------------------- 2937 ; Comes from: 2937 ; 292f C False from color 0x292d 2937 ; 2932 C False from color 0x292d 2937 ; -------------------------------------------------------------------------------------- 2937 2937 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2939 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2939 0x2939 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2938 2938 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2939 2939 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 293a 293a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 293b 293b <halt> ; Flow R 293c ; -------------------------------------------------------------------------------------- 293c ; 0x0092 Action Push_String_Extended,pse 293c ; -------------------------------------------------------------------------------------- 293c MACRO_Action_Push_String_Extended,pse: 293c 293c dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 293c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 293d 293d fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2941 fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2941 0x2941 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 293e ; -------------------------------------------------------------------------------------- 293e ; 0x0091 Action Push_String_Extended_Indexed,pse 293e ; -------------------------------------------------------------------------------------- 293e MACRO_Action_Push_String_Extended_Indexed,pse: 293e 293e dispatch_brk_class 4 ; Flow C cc=False 0x326c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 293e fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 3d VR02:1d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 293f 293f fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2940 2940 fiu_tivi_src 1 tar_val; Flow J 0x2941 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2941 0x2941 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2941 2941 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame c typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A 2942 2942 fiu_mem_start a start_continue_if_false ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2943 2943 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2944 2944 fiu_len_fill_lit 4f zero-fill 0xf fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2945 2945 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_frame 6 2946 2946 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x294c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 294c 0x294c typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2947 2947 fiu_vmux_sel 1 fill value; Flow J cc=True 0x294a ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 294a 0x294a seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2948 2948 seq_br_type 7 Unconditional Call; Flow C 0x2961 seq_branch_adr 2961 0x2961 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 2949 2949 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 294a 294a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x294c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 294c 0x294c typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 294b 294b ioc_load_wdr 0 ; Flow J 0x2949 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2949 0x2949 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 294c ; -------------------------------------------------------------------------------------- 294c ; Comes from: 294c ; 2946 C from color MACRO_Action_Push_String_Extended,pse 294c ; 294a C from color MACRO_Action_Push_String_Extended,pse 294c ; -------------------------------------------------------------------------------------- 294c 294c fiu_fill_mode_src 0 ; Flow J cc=False 0x294e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 294e 0x294e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 294d 294d fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 294e 294e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 294f 294f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2950 ; -------------------------------------------------------------------------------------- 2950 ; 0x0090 Action Store_String_Extended,pse 2950 ; -------------------------------------------------------------------------------------- 2950 MACRO_Action_Store_String_Extended,pse: 2950 2950 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2950 dispatch_uses_tos 1 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2951 2951 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_frame 2 2952 2952 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2953 2953 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 2954 2954 fiu_mem_start a start_continue_if_false seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2955 2955 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2956 2956 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x2958 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2958 0x2958 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2957 2957 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2958 2958 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x295c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 5d fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 295c 0x295c typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 2959 2959 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2960 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2960 0x2960 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 295a 295a fiu_len_fill_lit 7c zero-fill 0x3c; Flow C cc=True 0x2961 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 2961 0x2961 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 295b 295b fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3271 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3271 0x3271 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 295c ; -------------------------------------------------------------------------------------- 295c ; Comes from: 295c ; 2958 C True from color 0x0000 295c ; -------------------------------------------------------------------------------------- 295c 295c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x295e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 295e 0x295e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 295d 295d fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 295e 295e fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 295f 295f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2960 ; -------------------------------------------------------------------------------------- 2960 ; Comes from: 2960 ; 2959 C True from color 0x0000 2960 ; -------------------------------------------------------------------------------------- 2960 2960 fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2961 ; -------------------------------------------------------------------------------------- 2961 ; Comes from: 2961 ; 2917 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2961 ; 2948 C from color MACRO_Action_Push_String_Extended,pse 2961 ; -------------------------------------------------------------------------------------- 2961 2961 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2962 2962 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x296d fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 296d 0x296d seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 2963 2963 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2968 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2968 0x2968 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 2964 2964 fiu_fill_mode_src 0 ; Flow J 0x2965 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2965 0x2965 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2965 2965 fiu_fill_mode_src 0 ; Flow J cc=False 0x296a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 296a 0x296a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2966 2966 fiu_fill_mode_src 0 ; Flow J 0x2967 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2967 2967 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2968 2968 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2969 2969 fiu_fill_mode_src 0 ; Flow J 0x2965 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2965 0x2965 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 296a 296a fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 296b 296b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 296c 296c fiu_load_var 1 hold_var; Flow J 0x2967 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 296d 296d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2976 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2976 0x2976 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 296e 296e fiu_load_tar 1 hold_tar; Flow J cc=True 0x2989 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2989 0x2989 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 296f 296f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2970 2970 fiu_fill_mode_src 0 ; Flow J cc=True 0x297a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 297a 0x297a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2971 2971 fiu_mem_start 2 start-rd; Flow J 0x2972 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2972 0x2972 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2972 2972 seq_br_type 3 Unconditional Branch; Flow J 0x2961 seq_branch_adr 2961 0x2961 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 2973 2973 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2974 2974 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2963 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2963 0x2963 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 01 GP01 2975 2975 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x296e fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 296e 0x296e seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2976 2976 fiu_load_tar 1 hold_tar; Flow J cc=True 0x298c fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 298c 0x298c seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2977 2977 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2979 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2979 0x2979 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2978 2978 seq_br_type 0 Branch False; Flow J cc=False 0x2972 seq_branch_adr 2972 0x2972 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2979 2979 fiu_fill_mode_src 0 ; Flow J 0x297a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 297a 0x297a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 297a 297a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x297e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 297e 0x297e typ_mar_cntl 6 INCREMENT_MAR 297b 297b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 297c 297c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 297d 297d fiu_fill_mode_src 0 ; Flow J 0x2967 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 297e 297e fiu_load_tar 1 hold_tar; Flow J cc=False 0x2984 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2984 0x2984 seq_cond_sel 64 OFFSET_REGISTER_???? 297f 297f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2972 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2972 0x2972 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2980 2980 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2981 2981 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2982 2982 fiu_fill_mode_src 0 ; Flow J 0x2983 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2983 0x2983 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2983 2983 fiu_mem_start 4 continue; Flow J 0x2967 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2967 0x2967 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 2984 2984 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2972 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 2972 0x2972 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2985 2985 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 2986 2986 fiu_fill_mode_src 0 ; Flow J cc=True 0x2988 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2988 0x2988 seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2987 2987 fiu_fill_mode_src 0 ; Flow J 0x2983 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2983 0x2983 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2988 2988 fiu_fill_mode_src 0 ; Flow J 0x2983 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2983 0x2983 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2989 2989 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 298a 298a fiu_fill_mode_src 0 ; Flow J cc=True 0x2992 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2992 0x2992 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 298b 298b fiu_load_oreg 1 hold_oreg; Flow J 0x298f fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 298f 0x298f typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 298c 298c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 298d 298d seq_b_timing 1 Latch Condition; Flow J cc=True 0x2994 seq_br_type 1 Branch True seq_branch_adr 2994 0x2994 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 298e 298e fiu_fill_mode_src 0 ; Flow J 0x298f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 298f 0x298f typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 298f 298f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2990 2990 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2991 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2991 0x2991 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2991 2991 ioc_load_wdr 0 ; Flow J 0x2999 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2999 0x2999 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2992 2992 fiu_fill_mode_src 0 ; Flow J cc=True 0x2999 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2999 0x2999 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2993 2993 fiu_fill_mode_src 0 ; Flow J 0x2996 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2996 0x2996 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 2994 2994 fiu_fill_mode_src 0 ; Flow J cc=True 0x2999 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2999 0x2999 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2995 2995 fiu_fill_mode_src 0 ; Flow J 0x2996 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2996 0x2996 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 2996 2996 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2997 2997 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 2998 2998 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2991 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2991 0x2991 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2999 2999 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2973 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2973 0x2973 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 299a 299a fiu_mem_start 4 continue; Flow J cc=False 0x29a6 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29a6 0x29a6 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 299b 299b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 299c 299c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29a5 0x29a5 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 299d 299d fiu_load_oreg 1 hold_oreg; Flow J 0x299e fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 299e 0x299e typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 299e 299e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 299f 299f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a2 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29a2 0x29a2 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a0 29a0 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 29a1 29a1 fiu_mem_start 2 start-rd; Flow C 0x32fc seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc 29a2 29a2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29a4 0x29a4 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29a3 29a3 fiu_load_oreg 1 hold_oreg; Flow J 0x299e fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 299e 0x299e typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a4 29a4 ioc_load_wdr 0 ; Flow J 0x2973 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29a5 29a5 ioc_load_wdr 0 ; Flow J 0x2973 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29a6 29a6 fiu_load_var 1 hold_var; Flow J cc=False 0x29b0 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29b0 0x29b0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29a7 29a7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29a8 29a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 29a9 29a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29ad fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29ad 0x29ad typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29aa 29aa fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2a82 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29ab 29ab fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29ac 29ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x29a9 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a9 0x29a9 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29ad 29ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29ae 29ae fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 29af 29af ioc_load_wdr 0 ; Flow J 0x2973 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29b0 29b0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29b1 29b1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29b2 29b2 ioc_load_wdr 0 ; Flow J 0x2973 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29b3 ; -------------------------------------------------------------------------------------- 29b3 ; Comes from: 29b3 ; 10cf C from color 0x10bf 29b3 ; 12d0 C from color 0x098a 29b3 ; 16ee C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 29b3 ; 17c5 C from color MACRO_Execute_Any,Set_Constraint 29b3 ; 17cd C True from color MACRO_Execute_Any,Set_Constraint 29b3 ; -------------------------------------------------------------------------------------- 29b3 29b3 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29b8 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 29b8 0x29b8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29b4 29b4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2a2c fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a2c 0x2a2c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29b5 29b5 seq_br_type 5 Call True; Flow C cc=True 0x2a2c seq_branch_adr 2a2c 0x2a2c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29b6 29b6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29b7 29b7 ioc_fiubs 0 fiu ; Flow J 0x2a2c seq_br_type 3 Unconditional Branch seq_branch_adr 2a2c 0x2a2c val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29b8 29b8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29b9 29b9 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_en_micro 0 typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 29ba 29ba fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x29c0 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29c0 0x29c0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29bb 29bb fiu_fill_mode_src 0 ; Flow J cc=False 0x29bd fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29bd 0x29bd seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29bc 29bc fiu_fill_mode_src 0 ; Flow J 0x29c2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c2 0x29c2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29bd 29bd fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29be 29be fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29bf 29bf fiu_load_var 1 hold_var; Flow J 0x29c2 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29c2 0x29c2 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29c0 29c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29c1 29c1 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x29c2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c2 0x29c2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29c2 29c2 ioc_load_wdr 0 ; Flow J cc=True 0x29cf ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29cf 0x29cf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 29c3 29c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29c6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29c6 0x29c6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 29c4 29c4 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 29c5 29c5 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 29c6 29c6 <default> 29c7 29c7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 29c8 29c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator 29c9 29c9 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29ca 29ca fiu_fill_mode_src 0 ; Flow J cc=False 0x29cc fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29cc 0x29cc seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29cb 29cb fiu_fill_mode_src 0 ; Flow J 0x29c2 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c2 0x29c2 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29cc 29cc fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29cd 29cd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29ce 29ce fiu_load_var 1 hold_var; Flow J 0x29c2 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29c2 0x29c2 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29cf 29cf fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 29d0 29d0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x29d3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29d3 0x29d3 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 29d1 29d1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2a2c seq_br_type 0 Branch False seq_branch_adr 2a2c 0x2a2c seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29d2 29d2 seq_br_type 3 Unconditional Branch; Flow J 0x29d4 seq_branch_adr 29d4 0x29d4 29d3 29d3 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x2a2c seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a2c 0x2a2c seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29d4 29d4 seq_br_type 5 Call True; Flow C cc=True 0x2a2c seq_branch_adr 2a2c 0x2a2c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 0 PASS_A 29d5 29d5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val typ_b_adr 09 GP09 val_b_adr 09 GP09 29d6 29d6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29d7 29d7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 29d8 29d8 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x29de fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29de 0x29de typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29d9 29d9 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 29da 29da fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 29db 29db typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29dc 29dc fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29dd 29dd fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x29df fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 29df 0x29df typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 29de 29de fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 29df 0x29df seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 17 LOOP_COUNTER typ_b_adr 32 TR02:12 typ_frame 2 29df 29df fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 29e0 29e0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 29e1 29e1 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29e2 29e2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x29ef seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29ef 0x29ef seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e3 29e3 fiu_mem_start 2 start-rd; Flow J cc=False 0x29e6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29e6 0x29e6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 29e4 29e4 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 29e5 29e5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x29f1 seq_br_type 3 Unconditional Branch seq_branch_adr 29f1 0x29f1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e6 29e6 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 29e7 29e7 fiu_tivi_src c mar_0xc; Flow J cc=False 0x29f1 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29f1 0x29f1 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e8 29e8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e9 29e9 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 29ea 29ea fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 29eb 29eb fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS 29ec 29ec ioc_tvbs 1 typ+fiu; Flow J cc=True 0x29ee seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29ee 0x29ee seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 29ed 29ed seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_mux_sel 2 ALU 29ee 29ee seq_br_type 3 Unconditional Branch; Flow J 0x29f1 seq_branch_adr 29f1 0x29f1 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29ef 29ef ioc_tvbs 2 fiu+val; Flow J 0x29f1 seq_br_type 3 Unconditional Branch seq_branch_adr 29f1 0x29f1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 29f0 29f0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a02 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a02 0x2a02 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29f1 29f1 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29f6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29f6 0x29f6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 09 GP09 29f2 29f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x29f0 seq_br_type 0 Branch False seq_branch_adr 29f0 0x29f0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29f3 29f3 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 29f4 29f4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 29f5 29f5 seq_br_type 3 Unconditional Branch; Flow J 0x29f0 seq_branch_adr 29f0 0x29f0 29f6 29f6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29f7 29f7 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 29f8 0x29f8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 29f8 29f8 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS 29f9 29f9 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 29fa 29fa <default> 29fb 29fb fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 29fc 29fc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a02 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a02 0x2a02 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 29fd 29fd fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 29fe 0x29fe seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 29fe 29fe seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x29fc seq_br_type 0 Branch False seq_branch_adr 29fc 0x29fc seq_cond_sel 67 REFRESH_MACRO_EVENT 29ff 29ff seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 2a00 2a00 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a01 2a01 seq_br_type 3 Unconditional Branch; Flow J 0x29fc seq_branch_adr 29fc 0x29fc 2a02 ; -------------------------------------------------------------------------------------- 2a02 ; Comes from: 2a02 ; 29f0 C True from color 0x0000 2a02 ; 29fc C True from color 0x0000 2a02 ; -------------------------------------------------------------------------------------- 2a02 2a02 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a03 2a03 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a19 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a19 0x2a19 typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2a04 2a04 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2a05 2a05 ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a06 2a06 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a07 2a07 seq_br_type 3 Unconditional Branch; Flow J 0x2a0b seq_branch_adr 2a0b 0x2a0b val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a08 2a08 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a12 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a12 0x2a12 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a09 2a09 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a0a 2a0a val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a0b 2a0b fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a0c 2a0c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2a12 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2a12 0x2a12 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2a0d 2a0d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a1c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a1c 0x2a1c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2a0e 2a0e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2a08 seq_br_type 0 Branch False seq_branch_adr 2a08 0x2a08 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a0f 2a0f seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 2a10 2a10 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a11 2a11 seq_br_type 3 Unconditional Branch; Flow J 0x2a08 seq_branch_adr 2a08 0x2a08 2a12 ; -------------------------------------------------------------------------------------- 2a12 ; Comes from: 2a12 ; 2a08 C from color 0x2a02 2a12 ; 2a0c C from color 0x2a02 2a12 ; 2a23 C from color 0x2a02 2a12 ; -------------------------------------------------------------------------------------- 2a12 2a12 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a15 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a15 0x2a15 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a13 2a13 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a18 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a18 0x2a18 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a14 ; -------------------------------------------------------------------------------------- 2a14 ; Comes from: 2a14 ; 2a1b C from color 0x2a02 2a14 ; -------------------------------------------------------------------------------------- 2a14 2a14 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 2a15 2a15 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a16 2a16 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a17 2a17 fiu_load_var 1 hold_var; Flow J cc=False 0x2a14 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a14 0x2a14 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a18 2a18 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 2a19 2a19 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1a PASS_B 2a1a 2a1a ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a1b 2a1b fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x2a14 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a14 0x2a14 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 2a1c 2a1c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a26 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a26 0x2a26 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a1d 2a1d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a1e 2a1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2a1f 2a1f fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a20 2a20 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 2a21 2a21 fiu_fill_mode_src 0 ; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2a22 2a22 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a23 2a23 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a12 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a12 0x2a12 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a24 2a24 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a20 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a20 0x2a20 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a25 2a25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a26 2a26 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a29 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a29 0x2a29 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 2a27 2a27 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a28 2a28 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a29 2a29 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a2a 2a2a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a2b 2a2b fiu_load_var 1 hold_var; Flow J 0x2a28 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a28 0x2a28 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a2c ; -------------------------------------------------------------------------------------- 2a2c ; Comes from: 2a2c ; 10c8 C from color 0x10a8 2a2c ; 10e7 C from color 0x10d4 2a2c ; 10fa C from color 0x10d5 2a2c ; 1225 C from color 0x10d4 2a2c ; 1235 C from color 0x11ff 2a2c ; 12b9 C from color 0x125d 2a2c ; 12e5 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2a2c ; 12f0 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 2a2c ; 139b C from color 0x139a 2a2c ; 13bb C from color 0x13ba 2a2c ; 140d C from color 0x140a 2a2c ; 173f C from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 2a2c ; 291f C from color MACRO_Execute_Any,Structure_Clear 2a2c ; -------------------------------------------------------------------------------------- 2a2c 2a2c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 2a2d 2a2d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a33 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a33 0x2a33 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2a2e 2a2e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2a30 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a30 0x2a30 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a2f 2a2f fiu_fill_mode_src 0 ; Flow J 0x2a5b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a5b 0x2a5b typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a30 2a30 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a31 2a31 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a32 2a32 fiu_load_var 1 hold_var; Flow J 0x2a5b fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a5b 0x2a5b seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a33 2a33 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2a42 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a42 0x2a42 typ_a_adr 14 ZEROS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a34 2a34 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a40 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a40 0x2a40 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2a35 2a35 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a5b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a5b 0x2a5b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a36 2a36 fiu_load_oreg 1 hold_oreg; Flow J 0x2a37 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a37 0x2a37 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a37 2a37 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a3e fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a3e 0x2a3e seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a38 2a38 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2a3f 0x2a3f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a39 2a39 fiu_mem_start 4 continue; Flow J cc=True 0x2a5b fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2a5b 0x2a5b seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR04:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2a3a 2a3a fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a3b 2a3b seq_en_micro 0 2a3c 2a3c fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2a5b ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2a5b 0x2a5b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 7 INC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 2a3d 2a3d fiu_mem_start 3 start-wr; Flow J 0x2a2c ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2a2c 0x2a2c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a3e 2a3e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a39 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2a39 0x2a39 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a3f 2a3f fiu_mem_start 2 start-rd; Flow J 0x2a2c ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a2c 0x2a2c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 0 PASS_A 2a40 2a40 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a41 2a41 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a37 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a37 0x2a37 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a42 2a42 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a44 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a44 0x2a44 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a43 2a43 fiu_load_oreg 1 hold_oreg; Flow J 0x2a45 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a45 0x2a45 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a44 2a44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a45 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a45 0x2a45 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a45 2a45 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a47 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a47 0x2a47 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a46 2a46 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a48 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a48 0x2a48 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a47 2a47 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a48 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a48 0x2a48 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a48 2a48 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a3f fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a3f 0x2a3f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2a49 2a49 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2a39 fiu_mem_start 7 start_wr_if_true fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a39 0x2a39 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR06:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 6 2a4a 2a4a fiu_mem_start 3 start-wr; Flow J cc=True 0x2a4f seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a4f 0x2a4f seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 2a4b 2a4b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_alu_func 1c DEC_A val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a4c 2a4c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a3d fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 2a3d 0x2a3d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a4d 2a4d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a4e 2a4e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 2a4f 2a4f fiu_mem_start 4 continue seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a50 2a50 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a51 2a51 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a52 2a52 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a53 2a53 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a54 2a54 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a55 2a55 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a56 2a56 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a57 2a57 fiu_mem_start 4 continue; Flow J cc=False 0x2a5b seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a58 2a58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a59 2a59 seq_br_type 4 Call False; Flow C cc=False 0x329a seq_branch_adr 329a 0x329a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 34 VR02:14 val_frame 2 2a5a 2a5a fiu_mem_start 3 start-wr; Flow J cc=True 0x2a50 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a50 0x2a50 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a5b 2a5b ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a5c 2a5c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2a60 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a60 0x2a60 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 13 ? typ_a_adr 26 TR05:06 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2a5d 2a5d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a61 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a61 0x2a61 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2a5e 2a5e fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a60 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a60 0x2a60 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 3e ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2a5f 2a5f seq_br_type 3 Unconditional Branch; Flow J 0x2a5e seq_branch_adr 2a5e 0x2a5e val_rand 1 INC_LOOP_COUNTER 2a60 2a60 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a62 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2a62 0x2a62 seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2a61 2a61 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 2a62 2a62 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a63 2a63 fiu_mem_start d start_physical_rd; Flow J 0x2a64 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a64 0x2a64 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a64 2a64 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1c TR1d:03 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1c VR1d:03 val_c_mux_sel 2 ALU val_frame 1d 2a65 2a65 fiu_mem_start d start_physical_rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a66 2a66 seq_en_micro 0 typ_a_adr 2b TR04:0b typ_alu_func 7 INC_A typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 2b VR04:0b val_alu_func 1 A_PLUS_B val_b_adr 2a VR04:0a val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a67 2a67 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR1d:02 typ_c_source 0 FIU_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a68 2a68 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR1d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR1d:02 val_c_mux_sel 2 ALU val_frame 1d 2a69 2a69 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6a 2a6a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2a6b 2a6b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6c 2a6c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 2b VR04:0b val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a6d 2a6d fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a6e 2a6e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 0d fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a6f 2a6f fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a70 2a70 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a71 2a71 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 32 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a72 2a72 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a73 2a73 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a74 2a74 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a75 2a75 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 0f fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a76 2a76 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a77 2a77 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a78 2a78 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 8 read and clear rtc ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a79 2a79 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a7a 2a7a ioc_tvbs 1 typ+fiu; Flow J 0x2a7c seq_br_type 3 Unconditional Branch seq_branch_adr 2a7c 0x2a7c seq_en_micro 0 val_a_adr 35 VR04:15 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0a VR04:15 val_c_mux_sel 2 ALU val_frame 4 2a7b 2a7b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2a7c 2a7c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2a7b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a7b 0x2a7b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2a7d 2a7d seq_b_timing 1 Latch Condition; Flow J cc=True 0x2a83 seq_br_type 1 Branch True seq_branch_adr 2a83 0x2a83 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 2a7e 2a7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a80 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a80 0x2a80 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a7f 2a7f fiu_mem_start 18 acknowledge_refresh; Flow J 0x2a81 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2a81 0x2a81 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2a80 2a80 seq_br_type 3 Unconditional Branch; Flow J 0x2a81 seq_branch_adr 2a81 0x2a81 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2a81 2a81 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2a82 ; -------------------------------------------------------------------------------------- 2a82 ; Comes from: 2a82 ; 0245 C from color 0x0245 2a82 ; 0274 C from color 0x0274 2a82 ; 031f C True from color MACRO_Action_Name_Partner 2a82 ; 0568 C True from color 0x0567 2a82 ; 058f C True from color 0x058d 2a82 ; 0596 C from color 0x0573 2a82 ; 05af C True from color 0x05af 2a82 ; 05c8 C True from color 0x05a7 2a82 ; 06b6 C True from color 0x06b6 2a82 ; 06d7 C True from color 0x06d2 2a82 ; 0718 C True from color 0x0717 2a82 ; 07ac C True from color 0x07ab 2a82 ; 07b5 C from color 0x07b5 2a82 ; 07e8 C from color 0x07e8 2a82 ; 0851 C True from color 0x0820 2a82 ; 085f C True from color 0x0820 2a82 ; 0869 C from color 0x0820 2a82 ; 086f C True from color 0x0820 2a82 ; 08ff C from color 0x0127 2a82 ; 090d C True from color 0x0905 2a82 ; 0ad9 C True from color 0x0ac2 2a82 ; 0b8c C True from color 0x0b83 2a82 ; 0b94 C from color 0x0b93 2a82 ; 0ba7 C from color 0x0b93 2a82 ; 0ce7 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 2a82 ; 0d01 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 2a82 ; 0d6d C True from color 0x0d34 2a82 ; 0d97 C True from color 0x0d92 2a82 ; 0efe C True from color 0x0ef8 2a82 ; 0f90 C from color 0x0ef8 2a82 ; 0fc8 C from color 0x0ef8 2a82 ; 0fd2 C True from color 0x0fd0 2a82 ; 0fd9 C True from color 0x0fd0 2a82 ; 0fe9 C from color 0x0fd0 2a82 ; 0ff8 C True from color 0x0fd0 2a82 ; 107b C True from color 0x0ef8 2a82 ; 107e C True from color 0x0ef8 2a82 ; 1088 C True from color 0x0ef8 2a82 ; 1319 C from color 0x1314 2a82 ; 1326 C True from color 0x1314 2a82 ; 13f5 C from color MACRO_Declare_Variable_Array,With_Constraint 2a82 ; 1416 C True from color 0x140f 2a82 ; 16c5 C True from color 0x16c5 2a82 ; 1714 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a82 ; 1716 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a82 ; 171f C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2a82 ; 1864 C from color MACRO_Execute_Vector,Greater_Equal 2a82 ; 194a C from color MACRO_Execute_Vector,Complement 2a82 ; 1c53 C from color 0x1c53 2a82 ; 1c87 C True from color MACRO_Execute_Array,Subarray 2a82 ; 1e9b C True from color MACRO_Declare_Type_Record,Incomplete 2a82 ; 1eba C True from color MACRO_Complete_Type_Record,By_Renaming 2a82 ; 1ec8 C True from color MACRO_Complete_Type_Record,By_Renaming 2a82 ; 1fed C True from color MACRO_Complete_Type_Array,By_Constraining 2a82 ; 204a C from color 0x2010 2a82 ; 20f0 C from color 0x2010 2a82 ; 218b C from color MACRO_Declare_Type_Array,Constrained 2a82 ; 2215 C True from color 0x2003 2a82 ; 2229 C True from color 0x2226 2a82 ; 2241 C True from color 0x2226 2a82 ; 2256 C from color 0x1b7c 2a82 ; 225c C True from color 0x1b7c 2a82 ; 22a6 C from color 0x22a6 2a82 ; 22b6 C True from color 0x09a6 2a82 ; 22f9 C True from color MACRO_Declare_Type_Array,Incomplete 2a82 ; 22fb C True from color MACRO_Declare_Type_Array,Incomplete 2a82 ; 231a C True from color MACRO_Complete_Type_Array,By_Component_Completion 2a82 ; 237e C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a82 ; 2382 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a82 ; 238c C from color 0x238c 2a82 ; 2391 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2a82 ; 23ab C from color 0x23ab 2a82 ; 23ed C from color 0x23ed 2a82 ; 243a C from color 0x243a 2a82 ; 2450 C from color 0x2450 2a82 ; 24de C from color 0x24d8 2a82 ; 24f0 C from color 0x2488 2a82 ; 250e C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a82 ; 2518 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a82 ; 251e C True from color 0x251e 2a82 ; 2527 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2a82 ; 254d C True from color MACRO_Complete_Type_Variant_Record,By_Defining 2a82 ; 259a C True from color MACRO_Complete_Type_Variant_Record,By_Defining 2a82 ; 25da C from color 0x25da 2a82 ; 25dc C from color 0x25dc 2a82 ; 2636 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 2a82 ; 264d C True from color 0x263a 2a82 ; 2652 C True from color 0x263a 2a82 ; 2662 C True from color MACRO_Declare_Type_Variant_Record,Defined 2a82 ; 268e C True from color 0x268e 2a82 ; 26a7 C True from color MACRO_Declare_Type_Variant_Record,Defined 2a82 ; 26ff C True from color 0x26fa 2a82 ; 2704 C True from color 0x26fa 2a82 ; 2717 C from color 0x2717 2a82 ; 2899 C True from color MACRO_Execute_Float,Exponentiate 2a82 ; 28a3 C True from color MACRO_Execute_Float,Exponentiate 2a82 ; 2a0f C from color 0x2a02 2a82 ; 2a21 C True from color 0x2a02 2a82 ; 2ab4 C from color 0x0127 2a82 ; 2d28 C True from color 0x2d1f 2a82 ; 2dcd C from color 0x2dcd 2a82 ; 2eed C True from color 0x2ee5 2a82 ; 2f74 C from color 0x2f73 2a82 ; 3356 C from color MACRO_Action_Accept_Activation 2a82 ; 337d C True from color 0x3378 2a82 ; 33da C True from color 0x0f05 2a82 ; 3424 C True from color 0x0d34 2a82 ; 342f C from color 0x0d34 2a82 ; 3437 C from color 0x0d34 2a82 ; 343c C from color 0x0d34 2a82 ; 34d2 C True from color 0x34d2 2a82 ; 368f C True from color 0x05a7 2a82 ; 3739 C from color 0x3738 2a82 ; 37e1 C from color 0x37dc 2a82 ; 37f3 C from color 0x37dc 2a82 ; 389d C from color 0x2abd 2a82 ; 3b79 C True from color 0x3b49 2a82 ; 3b8e C from color 0x3b8b 2a82 ; -------------------------------------------------------------------------------------- 2a82 2a82 fiu_mem_start d start_physical_rd; Flow J 0x139 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0139 0x0139 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 2a83 2a83 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a85 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a85 0x2a85 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a84 2a84 fiu_mem_start 18 acknowledge_refresh; Flow J 0x2a86 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2a86 0x2a86 seq_en_micro 0 2a85 2a85 seq_br_type 3 Unconditional Branch; Flow J 0x2a86 seq_branch_adr 2a86 0x2a86 seq_en_micro 0 2a86 2a86 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2a87 2a87 seq_en_micro 0 typ_a_adr 23 TR1d:03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 23 VR1d:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1d 2a88 2a88 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 22 VR1d:02 val_alu_func 1a PASS_B val_b_adr 21 VR1d:01 val_frame 1d 2a89 2a89 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src b type_frame ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 25 TR1d:05 typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_frame 1d val_rand 9 PASS_A_HIGH 2a8a 2a8a fiu_len_fill_lit 72 zero-fill 0x32; Flow J cc=True 0x18c fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018c 0x018c seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a8b 2a8b fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0x2ab8 fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2ab8 0x2ab8 seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2a8c 2a8c fiu_fill_mode_src 0 ; Flow J 0x2a8d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2a8d 0x2a8d seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2a8d 2a8d fiu_fill_mode_src 0 ; Flow J 0x2a8e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a8e 0x2a8e seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2a8e 2a8e fiu_mem_start d start_physical_rd seq_en_micro 0 2a8f 2a8f ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2a92 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a92 0x2a92 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR1d:07 val_c_mux_sel 2 ALU val_frame 1d 2a90 2a90 fiu_mem_start e start_physical_wr; Flow J cc=False 0x2a9a fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2a9a 0x2a9a seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a91 2a91 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a92 2a92 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2a9a ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 2a9a 0x2a9a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR1d:0d val_alu_func 19 X_XOR_B val_b_adr 2f VR1d:0f val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a93 2a93 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a94 2a94 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2a95 2a95 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a98 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a98 0x2a98 seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 2a96 2a96 fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=True 0x18d fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018d 0x018d seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d 2a97 2a97 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2a98 2a98 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 2a99 2a99 fiu_mem_start e start_physical_wr; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 1d 2a9a 2a9a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 2a VR1d:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2a9b 2a9b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_frame 1d 2a9c 2a9c fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 2a9d 2a9d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS 2a9e 2a9e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2a9f 2a9f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 5d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 14 VR1d:0b val_c_mux_sel 2 ALU val_frame 1d 2aa0 2aa0 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR1d:0d val_c_adr 15 VR1d:0a val_frame 1d 2aa1 2aa1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2aa2 2aa2 fiu_len_fill_lit 48 zero-fill 0x8 fiu_load_tar 1 hold_tar fiu_offs_lit 03 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 25 VR08:05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 2aa3 2aa3 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2d VR12:0d val_frame 12 2aa4 2aa4 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2aa7 seq_br_type 1 Branch True seq_branch_adr 2aa7 0x2aa7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 2aa5 2aa5 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2aa6 2aa6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2aa9 fiu_load_var 1 hold_var fiu_offs_lit 1b fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2aa9 0x2aa9 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2aa7 2aa7 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2aa8 2aa8 ioc_tvbs 2 fiu+val; Flow J 0x2aa9 seq_br_type 3 Unconditional Branch seq_branch_adr 2aa9 0x2aa9 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2aa9 2aa9 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2aad fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2aad 0x2aad seq_en_micro 0 typ_a_adr 13 LOOP_REG val_a_adr 2d VR06:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2aaa 2aaa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 30 VR02:10 val_frame 2 2aab 2aab fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 2aac 2aac ioc_tvbs 3 fiu+fiu; Flow J 0x2ab0 seq_br_type 3 Unconditional Branch seq_branch_adr 2ab0 0x2ab0 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2aad 2aad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2aae 2aae fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 27 TR01:07 typ_frame 1 val_b_adr 27 VR01:07 val_frame 1 2aaf 2aaf ioc_tvbs 3 fiu+fiu; Flow J 0x2ab0 seq_br_type 3 Unconditional Branch seq_branch_adr 2ab0 0x2ab0 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR01:07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR01:07 val_c_mux_sel 2 ALU val_frame 1 2ab0 2ab0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ab2 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2ab2 0x2ab2 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2c TR1d:0c typ_b_adr 27 TR1d:07 typ_frame 1d 2ab1 2ab1 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 21 TR1d:01 typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_frame 1d typ_rand 5 CHECK_CLASS_B_LIT 2ab2 2ab2 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 26 TR1d:06 typ_frame 1d val_a_adr 27 VR1d:07 val_b_adr 26 VR1d:06 val_frame 1d 2ab3 2ab3 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x18e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 018e 0x018e seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 0 PASS_A typ_b_adr 25 TR1d:05 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 2b VR1d:0b val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 1d 2ab4 2ab4 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 0 PASS_A typ_c_adr 16 TR1d:09 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 0 PASS_A val_c_adr 16 VR1d:09 val_c_mux_sel 2 ALU val_frame 1d 2ab5 2ab5 seq_en_micro 0 typ_a_adr 29 TR1d:09 typ_alu_func 0 PASS_A typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 29 VR1d:09 val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_mux_sel 2 ALU val_frame 1d 2ab6 2ab6 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x18e fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 018e 0x018e seq_en_micro 0 val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2ab7 ; -------------------------------------------------------------------------------------- 2ab7 ; Comes from: 2ab7 ; 0189 C True from color 0x0127 2ab7 ; -------------------------------------------------------------------------------------- 2ab7 2ab7 fiu_mem_start 18 acknowledge_refresh; Flow R fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR1d:01 typ_frame 1d val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2ab8 2ab8 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a8d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2ab9 2ab9 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a8e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2a8e 0x2a8e seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 1c DEC_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2aba 2aba seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 2abb 2abb seq_br_type 2 Push (branch address); Flow J 0x2abc seq_branch_adr 01d1 0x01d1 seq_en_micro 0 2abc 2abc fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x8aa fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 08aa 0x08aa seq_en_micro 0 val_c_adr 10 VR1d:0f val_c_source 0 FIU_BUS val_frame 1d 2abd ; -------------------------------------------------------------------------------------- 2abd ; Comes from: 2abd ; 061b C from color 0x0000 2abd ; 067e C from color 0x066a 2abd ; -------------------------------------------------------------------------------------- 2abd 2abd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR11:14 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 02 GP02 2abe 2abe ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2abf 2abf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2ac3 fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ac3 0x2ac3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ac0 2ac0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2adb fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2adb 0x2adb typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ac1 2ac1 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2ace fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ace 0x2ace seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 04 GP04 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 24 VR05:04 val_frame 5 2ac2 2ac2 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_b_adr 04 GP04 2ac3 2ac3 fiu_mem_start 11 start_tag_query; Flow C cc=False 0x20a seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ac4 2ac4 seq_br_type 7 Unconditional Call; Flow C 0x34f2 seq_branch_adr 34f2 0x34f2 seq_en_micro 0 2ac5 2ac5 ioc_tvbs 8 typ+mem; Flow J cc=True 0x2ac8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ac8 0x2ac8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2ac6 2ac6 fiu_mem_start 2 start-rd; Flow C 0x348d fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 348d 0x348d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2ac7 2ac7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2ac8 2ac8 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2ac9 2ac9 ioc_load_wdr 0 typ_b_adr 20 TR05:00 typ_frame 5 val_b_adr 39 VR02:19 val_frame 2 2aca 2aca fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2acb 2acb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 2acc 2acc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 2acd 2acd ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2ace 2ace fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2acf 2acf <default> 2ad0 2ad0 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 2ad1 2ad1 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 3e VR06:1e val_frame 6 2ad2 2ad2 fiu_mem_start 3 start-wr; Flow J cc=False 0x2ad6 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2ad6 0x2ad6 val_a_adr 3e VR06:1e val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2ad3 2ad3 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2ad4 2ad4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ad5 2ad5 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 2ad6 2ad6 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 2ad7 2ad7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2ad8 2ad8 <default> 2ad9 2ad9 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2ada 2ada ioc_fiubs 0 fiu ; Flow J 0x2ad4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2ad4 0x2ad4 val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2adb ; -------------------------------------------------------------------------------------- 2adb ; Comes from: 2adb ; 2ac0 C False from color 0x2abd 2adb ; -------------------------------------------------------------------------------------- 2adb 2adb fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2adc 2adc fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x2ae0 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ae0 0x2ae0 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_frame 2 2add 2add fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2ade 2ade ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2adf 2adf fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2ae1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 2ae1 0x2ae1 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2ae0 2ae0 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2ae1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ae1 0x2ae1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ae1 2ae1 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2ae2 2ae2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 2ae3 2ae3 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2ae4 2ae4 ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2ae5 2ae5 seq_br_type a Unconditional Return; Flow R 2ae6 ; -------------------------------------------------------------------------------------- 2ae6 ; 0x03d5 Declare_Type Access,Defined 2ae6 ; -------------------------------------------------------------------------------------- 2ae6 MACRO_Declare_Type_Access,Defined: 2ae6 2ae6 dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2ae6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ae7 2ae7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2ae8 2ae8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af6 0x2af6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ae9 2ae9 <halt> ; Flow R 2aea ; -------------------------------------------------------------------------------------- 2aea ; 0x03d6 Declare_Type Access,Defined,Visible 2aea ; -------------------------------------------------------------------------------------- 2aea MACRO_Declare_Type_Access,Defined,Visible: 2aea 2aea dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2aea seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2aeb 2aeb fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 2aec 2aec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2aed 2aed fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af6 0x2af6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2aee ; -------------------------------------------------------------------------------------- 2aee ; 0x03d3 Declare_Type Access,Defined,Accesses_Protected 2aee ; -------------------------------------------------------------------------------------- 2aee MACRO_Declare_Type_Access,Defined,Accesses_Protected: 2aee 2aee dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2aee fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2aef 2aef fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2af0 2af0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af6 0x2af6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2af1 2af1 <halt> ; Flow R 2af2 ; -------------------------------------------------------------------------------------- 2af2 ; 0x03d4 Declare_Type Access,Defined,Visible,Accesses_Protected 2af2 ; -------------------------------------------------------------------------------------- 2af2 MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected: 2af2 2af2 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2af2 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2af3 2af3 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 2af4 2af4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2af5 2af5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2af6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2af6 0x2af6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2af6 2af6 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2af7 2af7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b15 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b15 0x2b15 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2af8 2af8 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b03 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b03 0x2b03 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 09 GP09 typ_b_adr 03 GP03 val_b_adr 3a VR02:1a val_frame 2 2af9 2af9 fiu_mem_start 4 continue; Flow J cc=True 0x2afb ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2afb 0x2afb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2afa 2afa fiu_load_var 1 hold_var; Flow J 0x2afc fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2afc 0x2afc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2afb 2afb fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2afc 2afc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP 2afd 2afd fiu_fill_mode_src 0 ; Flow C 0x34fb fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fb 0x34fb typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2afe 2afe ioc_load_wdr 0 ; Flow C cc=True 0x2b00 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2b00 0x2b00 typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA 2aff 2aff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b00 ; -------------------------------------------------------------------------------------- 2b00 ; Comes from: 2b00 ; 2afe C True from color 0x2af9 2b00 ; -------------------------------------------------------------------------------------- 2b00 2b00 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2b01 2b01 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 2b02 2b02 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_b_adr 09 GP09 2b03 ; -------------------------------------------------------------------------------------- 2b03 ; Comes from: 2b03 ; 2af8 C #0x0 from color MACRO_Declare_Type_Access,Defined 2b03 ; -------------------------------------------------------------------------------------- 2b03 2b03 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b04 2b04 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b05 2b05 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b06 2b06 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b07 2b07 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b08 2b08 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b09 2b09 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0a 2b0a fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b0b 2b0b fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b0c 2b0c seq_br_type 3 Unconditional Branch; Flow J 0x2b13 seq_branch_adr 2b13 0x2b13 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b0d 2b0d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0e 2b0e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b0f 2b0f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b10 2b10 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b14 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b14 0x2b14 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b11 2b11 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b14 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b14 0x2b14 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b12 2b12 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b14 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b14 0x2b14 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b13 2b13 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b14 2b14 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 2b15 2b15 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b18 0x2b18 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 3a VR02:1a val_frame 2 2b16 2b16 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b17 2b17 fiu_load_var 1 hold_var; Flow J 0x2afc fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2afc 0x2afc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2b18 ; -------------------------------------------------------------------------------------- 2b18 ; Comes from: 2b18 ; 2b15 C #0x0 from color MACRO_Declare_Type_Access,Defined 2b18 ; -------------------------------------------------------------------------------------- 2b18 2b18 seq_br_type 3 Unconditional Branch; Flow J 0x2b28 seq_branch_adr 2b28 0x2b28 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b19 2b19 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b1a 2b1a fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b1b 2b1b fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2a fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2a 0x2b2a typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b1c 2b1c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b1d 2b1d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b1e 2b1e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b1f 2b1f fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2a fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2a 0x2b2a typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b20 2b20 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2c fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2c 0x2b2c typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b21 2b21 seq_br_type 3 Unconditional Branch; Flow J 0x2b2b seq_branch_adr 2b2b 0x2b2b typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b22 2b22 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b23 2b23 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b24 2b24 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b25 2b25 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2d fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2d 0x2b2d typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b26 2b26 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2d fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2d 0x2b2d typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b27 2b27 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b2d fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2d 0x2b2d typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b28 2b28 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b29 2b29 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b2a 2b2a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b2b 2b2b fiu_mem_start 7 start_wr_if_true; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b2c 0x2b2c typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b2c 2b2c seq_br_type 3 Unconditional Branch; Flow J 0x2b2e seq_branch_adr 2b2e 0x2b2e typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b2d 2b2d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2b2a seq_br_type 1 Branch True seq_branch_adr 2b2a 0x2b2a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b2e 2b2e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b2f 2b2f fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b30 2b30 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2b31 2b31 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 2b32 2b32 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b33 2b33 <halt> ; Flow R 2b34 ; -------------------------------------------------------------------------------------- 2b34 ; 0x03ce Declare_Type Access,Incomplete 2b34 ; -------------------------------------------------------------------------------------- 2b34 MACRO_Declare_Type_Access,Incomplete: 2b34 2b34 dispatch_brk_class 4 ; Flow J 0x2b3c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b34 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3c 0x2b3c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b35 2b35 <halt> ; Flow R 2b36 ; -------------------------------------------------------------------------------------- 2b36 ; 0x03cf Declare_Type Access,Incomplete,Visible 2b36 ; -------------------------------------------------------------------------------------- 2b36 MACRO_Declare_Type_Access,Incomplete,Visible: 2b36 2b36 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b36 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b37 2b37 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b3c fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3c 0x2b3c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b38 ; -------------------------------------------------------------------------------------- 2b38 ; 0x03cc Declare_Type Access,Incomplete,Accesses_Protected 2b38 ; -------------------------------------------------------------------------------------- 2b38 MACRO_Declare_Type_Access,Incomplete,Accesses_Protected: 2b38 2b38 dispatch_brk_class 4 ; Flow J 0x2b3c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b38 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3c 0x2b3c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b39 2b39 <halt> ; Flow R 2b3a ; -------------------------------------------------------------------------------------- 2b3a ; 0x03cd Declare_Type Access,Incomplete,Visible,Accesses_Protected 2b3a ; -------------------------------------------------------------------------------------- 2b3a MACRO_Declare_Type_Access,Incomplete,Visible,Accesses_Protected: 2b3a 2b3a dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b3a seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b3b 2b3b fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b3c fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b3c 0x2b3c typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b3c 2b3c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b3d 2b3d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2b3e 2b3e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 2b3f 2b3f fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2b40 2b40 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b41 2b41 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2b42 2b42 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2b43 2b43 <halt> ; Flow R 2b44 ; -------------------------------------------------------------------------------------- 2b44 ; 0x038e Declare_Type Package,Defined 2b44 ; -------------------------------------------------------------------------------------- 2b44 MACRO_Declare_Type_Package,Defined: 2b44 2b44 dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b44 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 22 VR06:02 val_frame 6 2b45 ; -------------------------------------------------------------------------------------- 2b45 ; Comes from: 2b45 ; 2b5f C from color MACRO_Declare_Type_Task,Incomplete 2b45 ; 2b66 C from color 0x2b4f 2b45 ; -------------------------------------------------------------------------------------- 2b45 2b45 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2b46 ; -------------------------------------------------------------------------------------- 2b46 ; 0x038c Declare_Type Package,Defined,Not_Elaborated 2b46 ; -------------------------------------------------------------------------------------- 2b46 MACRO_Declare_Type_Package,Defined,Not_Elaborated: 2b46 2b46 dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b46 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 39 VR02:19 val_frame 2 2b47 2b47 fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False ; Flow J cc=True 0x2b56 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b56 0x2b56 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b48 ; -------------------------------------------------------------------------------------- 2b48 ; 0x038f Declare_Type Package,Defined,Visible 2b48 ; -------------------------------------------------------------------------------------- 2b48 MACRO_Declare_Type_Package,Defined,Visible: 2b48 2b48 dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b48 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 22 VR06:02 val_frame 6 2b49 2b49 fiu_mem_start 4 continue; Flow J 0x2b4b ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b4b 0x2b4b typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b4a ; -------------------------------------------------------------------------------------- 2b4a ; 0x038d Declare_Type Package,Defined,Visible,Not_Elaborated 2b4a ; -------------------------------------------------------------------------------------- 2b4a MACRO_Declare_Type_Package,Defined,Visible,Not_Elaborated: 2b4a 2b4a dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 39 VR02:19 val_frame 2 2b4b 2b4b ioc_load_wdr 0 ; Flow J 0x2b4d ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b4d 0x2b4d seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 03 GP03 2b4c ; -------------------------------------------------------------------------------------- 2b4c ; 0x037d Declare_Type Task,Defined 2b4c ; -------------------------------------------------------------------------------------- 2b4c MACRO_Declare_Type_Task,Defined: 2b4c 2b4c dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4c fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 27 VR06:07 val_frame 6 2b4d 2b4d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b4e ; -------------------------------------------------------------------------------------- 2b4e ; 0x037e Declare_Type Task,Defined,Visible 2b4e ; -------------------------------------------------------------------------------------- 2b4e MACRO_Declare_Type_Task,Defined,Visible: 2b4e 2b4e dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b4e fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 27 VR06:07 val_frame 6 2b4f 2b4f ioc_load_wdr 0 ; Flow J 0x2b51 seq_br_type 3 Unconditional Branch seq_branch_adr 2b51 0x2b51 typ_b_adr 01 GP01 val_b_adr 01 GP01 2b50 ; -------------------------------------------------------------------------------------- 2b50 ; 0x037a Declare_Type Task,Defined,Not_Elaborated 2b50 ; -------------------------------------------------------------------------------------- 2b50 MACRO_Declare_Type_Task,Defined,Not_Elaborated: 2b50 2b50 dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b50 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b51 2b51 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2b52 ; -------------------------------------------------------------------------------------- 2b52 ; 0x037b Declare_Type Task,Defined,Visible,Not_Elaborated 2b52 ; -------------------------------------------------------------------------------------- 2b52 MACRO_Declare_Type_Task,Defined,Visible,Not_Elaborated: 2b52 2b52 dispatch_brk_class 4 ; Flow J 0x2b53 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b52 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b53 0x2b53 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b53 2b53 seq_br_type 2 Push (branch address); Flow J 0x2b54 seq_branch_adr 3277 0x3277 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 11 2b54 2b54 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b47 fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b47 0x2b47 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b55 2b55 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b56 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b56 0x2b56 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b56 2b56 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 10 TOP 2b57 2b57 fiu_mem_start 4 continue; Flow J 0x2b49 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b49 0x2b49 typ_a_adr 3e TR06:1e typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR06:09 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b58 ; -------------------------------------------------------------------------------------- 2b58 ; 0x0377 Declare_Type Task,Incomplete 2b58 ; -------------------------------------------------------------------------------------- 2b58 MACRO_Declare_Type_Task,Incomplete: 2b58 2b58 dispatch_brk_class 4 ; Flow J 0x2b5b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b58 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b5b 0x2b5b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b59 2b59 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2b5a ; -------------------------------------------------------------------------------------- 2b5a ; 0x0378 Declare_Type Task,Incomplete,Visible 2b5a ; -------------------------------------------------------------------------------------- 2b5a MACRO_Declare_Type_Task,Incomplete,Visible: 2b5a 2b5a dispatch_brk_class 4 ; Flow J 0x2b5b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b5a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b5b 0x2b5b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b5b 2b5b ioc_fiubs 1 val ; Flow J 0x2b5c seq_br_type 2 Push (branch address) seq_branch_adr 3277 0x3277 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b5c 2b5c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b5e fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b5e 0x2b5e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 2b5d 2b5d fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b5f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b5f 0x2b5f typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b5e 2b5e fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b5f 0x2b5f typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b5f 2b5f fiu_mem_start 3 start-wr; Flow C 0x2b45 fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2b45 0x2b45 typ_a_adr 32 TR02:12 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b60 2b60 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b61 2b61 ioc_load_wdr 0 ; Flow J 0x2b59 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b59 0x2b59 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b62 ; -------------------------------------------------------------------------------------- 2b62 ; 0x0374 Complete_Type Task,By_Renaming 2b62 ; -------------------------------------------------------------------------------------- 2b62 MACRO_Complete_Type_Task,By_Renaming: 2b62 2b62 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b62 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2b63 2b63 fiu_mem_start 4 continue ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b64 2b64 fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR 2b65 2b65 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b66 2b66 fiu_mem_start 3 start-wr; Flow C 0x2b45 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2b45 0x2b45 seq_random 02 ? typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 2b67 2b67 fiu_mem_start 4 continue; Flow J 0x2b4f ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b4f 0x2b4f typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 2b68 ; -------------------------------------------------------------------------------------- 2b68 ; 0x009c Action Load_Dynamic 2b68 ; -------------------------------------------------------------------------------------- 2b68 MACRO_Action_Load_Dynamic: 2b68 2b68 dispatch_brk_class 8 ; Flow C 0x2c6e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b68 seq_br_type 7 Unconditional Call seq_branch_adr 2c6e 0x2c6e typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2b69 2b69 fiu_mem_start 2 start-rd 2b6a ; -------------------------------------------------------------------------------------- 2b6a ; 0xe000-0xffff Load llvl,ldelta 2b6a ; -------------------------------------------------------------------------------------- 2b6a MACRO_Load_llvl,ldelta: 2b6a 2b6a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2b6a 2b6b 2b6b fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b6c 2b6c fiu_load_var 1 hold_var; Flow J cc=True 0x2b6d ; Flow J cc=#0x0 0x2b6e fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2b6e 0x2b6e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 6 2b6d 2b6d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b76 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b76 0x2b76 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b6e 2b6e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b6f 2b6f seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 2b70 2b70 seq_br_type 3 Unconditional Branch; Flow J 0x2b77 seq_branch_adr 2b77 0x2b77 2b71 2b71 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b72 2b72 fiu_mem_start 6 start_rd_if_false; Flow J 0x2b78 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2b78 0x2b78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2b73 2b73 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b76 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b76 0x2b76 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b74 2b74 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2b76 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b76 0x2b76 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b75 2b75 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 2b76 2b76 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2b77 2b77 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b78 2b78 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2b80 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b80 0x2b80 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2b79 2b79 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2b7a 2b7a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2b7c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2b7c 0x2b7c seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR05:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 2b7b 2b7b fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2b7e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2b7e 0x2b7e seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b7c 2b7c fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2b7d 2b7d fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2b7e 0x2b7e seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b7e 2b7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b7f 0x2b7f seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2b7f 2b7f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2b80 2b80 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b81 0x2b81 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b81 2b81 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2b82 ; -------------------------------------------------------------------------------------- 2b82 ; 0x00d8 Load_Top At_Offset_0 2b82 ; -------------------------------------------------------------------------------------- 2b82 MACRO_Load_Top_At_Offset_0: 2b82 2b82 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b82 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b83 2b83 <halt> ; Flow R 2b84 ; -------------------------------------------------------------------------------------- 2b84 ; 0x00d9 Load_Top At_Offset_1 2b84 ; -------------------------------------------------------------------------------------- 2b84 MACRO_Load_Top_At_Offset_1: 2b84 2b84 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b84 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b85 2b85 <halt> ; Flow R 2b86 ; -------------------------------------------------------------------------------------- 2b86 ; 0x00da Load_Top At_Offset_2 2b86 ; -------------------------------------------------------------------------------------- 2b86 MACRO_Load_Top_At_Offset_2: 2b86 2b86 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b86 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b87 2b87 <halt> ; Flow R 2b88 ; -------------------------------------------------------------------------------------- 2b88 ; 0x00db Load_Top At_Offset_3 2b88 ; -------------------------------------------------------------------------------------- 2b88 MACRO_Load_Top_At_Offset_3: 2b88 2b88 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2b88 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1d TOP - 3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b89 2b89 <halt> ; Flow R 2b8a ; -------------------------------------------------------------------------------------- 2b8a ; 0x00dc Load_Top At_Offset_4 2b8a ; -------------------------------------------------------------------------------------- 2b8a MACRO_Load_Top_At_Offset_4: 2b8a 2b8a dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2b8a fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1c TOP - 4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1c TOP - 4 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8b 2b8b <halt> ; Flow R 2b8c ; -------------------------------------------------------------------------------------- 2b8c ; 0x00dd Load_Top At_Offset_5 2b8c ; -------------------------------------------------------------------------------------- 2b8c MACRO_Load_Top_At_Offset_5: 2b8c 2b8c dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 2b8c fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1b TOP - 5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1b TOP - 5 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8d 2b8d <halt> ; Flow R 2b8e ; -------------------------------------------------------------------------------------- 2b8e ; 0x00de Load_Top At_Offset_6 2b8e ; -------------------------------------------------------------------------------------- 2b8e MACRO_Load_Top_At_Offset_6: 2b8e 2b8e dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b6c dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2b8e fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b6c 0x2b6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1a TOP - 6 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1a TOP - 6 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b8f 2b8f <halt> ; Flow R 2b90 ; -------------------------------------------------------------------------------------- 2b90 ; 0x00e0 Load_Encached eon 2b90 ; -------------------------------------------------------------------------------------- 2b90 MACRO_Load_Encached_eon: 2b90 2b90 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b90 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR0b:00 typ_alu_func 15 NOT_B typ_b_adr 20 TR0b:00 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 20 VR0b:00 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b91 2b91 <halt> ; Flow R 2b92 ; -------------------------------------------------------------------------------------- 2b92 ; 0x00e1 Load_Encached eon 2b92 ; -------------------------------------------------------------------------------------- 2b92 MACRO_Load_Encached_eon: 2b92 2b92 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b92 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR0b:01 typ_alu_func 15 NOT_B typ_b_adr 21 TR0b:01 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 21 VR0b:01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b93 2b93 <halt> ; Flow R 2b94 ; -------------------------------------------------------------------------------------- 2b94 ; 0x00e2 Load_Encached eon 2b94 ; -------------------------------------------------------------------------------------- 2b94 MACRO_Load_Encached_eon: 2b94 2b94 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b94 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 22 TR0b:02 typ_alu_func 15 NOT_B typ_b_adr 22 TR0b:02 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 22 VR0b:02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b95 2b95 <halt> ; Flow R 2b96 ; -------------------------------------------------------------------------------------- 2b96 ; 0x00e3 Load_Encached eon 2b96 ; -------------------------------------------------------------------------------------- 2b96 MACRO_Load_Encached_eon: 2b96 2b96 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b96 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 23 TR0b:03 typ_alu_func 15 NOT_B typ_b_adr 23 TR0b:03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 23 VR0b:03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b97 2b97 <halt> ; Flow R 2b98 ; -------------------------------------------------------------------------------------- 2b98 ; 0x00e4 Load_Encached eon 2b98 ; -------------------------------------------------------------------------------------- 2b98 MACRO_Load_Encached_eon: 2b98 2b98 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b98 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 24 TR0b:04 typ_alu_func 15 NOT_B typ_b_adr 24 TR0b:04 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 24 VR0b:04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b99 2b99 <halt> ; Flow R 2b9a ; -------------------------------------------------------------------------------------- 2b9a ; 0x00e5 Load_Encached eon 2b9a ; -------------------------------------------------------------------------------------- 2b9a MACRO_Load_Encached_eon: 2b9a 2b9a dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9a fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 25 TR0b:05 typ_alu_func 15 NOT_B typ_b_adr 25 TR0b:05 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 25 VR0b:05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9b 2b9b <halt> ; Flow R 2b9c ; -------------------------------------------------------------------------------------- 2b9c ; 0x00e6 Load_Encached eon 2b9c ; -------------------------------------------------------------------------------------- 2b9c MACRO_Load_Encached_eon: 2b9c 2b9c dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 26 TR0b:06 typ_alu_func 15 NOT_B typ_b_adr 26 TR0b:06 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 26 VR0b:06 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9d 2b9d <halt> ; Flow R 2b9e ; -------------------------------------------------------------------------------------- 2b9e ; 0x00e7 Load_Encached eon 2b9e ; -------------------------------------------------------------------------------------- 2b9e MACRO_Load_Encached_eon: 2b9e 2b9e dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b9e fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 27 TR0b:07 typ_alu_func 15 NOT_B typ_b_adr 27 TR0b:07 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 27 VR0b:07 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2b9f 2b9f <halt> ; Flow R 2ba0 ; -------------------------------------------------------------------------------------- 2ba0 ; 0x00e8 Load_Encached eon 2ba0 ; -------------------------------------------------------------------------------------- 2ba0 MACRO_Load_Encached_eon: 2ba0 2ba0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR0b:08 typ_alu_func 15 NOT_B typ_b_adr 28 TR0b:08 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 28 VR0b:08 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba1 2ba1 <halt> ; Flow R 2ba2 ; -------------------------------------------------------------------------------------- 2ba2 ; 0x00e9 Load_Encached eon 2ba2 ; -------------------------------------------------------------------------------------- 2ba2 MACRO_Load_Encached_eon: 2ba2 2ba2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 29 TR0b:09 typ_alu_func 15 NOT_B typ_b_adr 29 TR0b:09 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 29 VR0b:09 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba3 2ba3 <halt> ; Flow R 2ba4 ; -------------------------------------------------------------------------------------- 2ba4 ; 0x00ea Load_Encached eon 2ba4 ; -------------------------------------------------------------------------------------- 2ba4 MACRO_Load_Encached_eon: 2ba4 2ba4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR0b:0a typ_alu_func 15 NOT_B typ_b_adr 2a TR0b:0a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2a VR0b:0a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba5 2ba5 <halt> ; Flow R 2ba6 ; -------------------------------------------------------------------------------------- 2ba6 ; 0x00eb Load_Encached eon 2ba6 ; -------------------------------------------------------------------------------------- 2ba6 MACRO_Load_Encached_eon: 2ba6 2ba6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2b TR0b:0b typ_alu_func 15 NOT_B typ_b_adr 2b TR0b:0b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2b VR0b:0b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba7 2ba7 <halt> ; Flow R 2ba8 ; -------------------------------------------------------------------------------------- 2ba8 ; 0x00ec Load_Encached eon 2ba8 ; -------------------------------------------------------------------------------------- 2ba8 MACRO_Load_Encached_eon: 2ba8 2ba8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ba8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2c TR0b:0c typ_alu_func 15 NOT_B typ_b_adr 2c TR0b:0c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2c VR0b:0c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2ba9 2ba9 <halt> ; Flow R 2baa ; -------------------------------------------------------------------------------------- 2baa ; 0x00ed Load_Encached eon 2baa ; -------------------------------------------------------------------------------------- 2baa MACRO_Load_Encached_eon: 2baa 2baa dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2baa fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR0b:0d typ_alu_func 15 NOT_B typ_b_adr 2d TR0b:0d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2d VR0b:0d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bab 2bab <halt> ; Flow R 2bac ; -------------------------------------------------------------------------------------- 2bac ; 0x00ee Load_Encached eon 2bac ; -------------------------------------------------------------------------------------- 2bac MACRO_Load_Encached_eon: 2bac 2bac dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bac fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2e TR0b:0e typ_alu_func 15 NOT_B typ_b_adr 2e TR0b:0e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR0b:0e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bad 2bad <halt> ; Flow R 2bae ; -------------------------------------------------------------------------------------- 2bae ; 0x00ef Load_Encached eon 2bae ; -------------------------------------------------------------------------------------- 2bae MACRO_Load_Encached_eon: 2bae 2bae dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bae fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2f TR0b:0f typ_alu_func 15 NOT_B typ_b_adr 2f TR0b:0f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR0b:0f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2baf 2baf <halt> ; Flow R 2bb0 ; -------------------------------------------------------------------------------------- 2bb0 ; 0x00f0 Load_Encached eon 2bb0 ; -------------------------------------------------------------------------------------- 2bb0 MACRO_Load_Encached_eon: 2bb0 2bb0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 30 TR0b:10 typ_alu_func 15 NOT_B typ_b_adr 30 TR0b:10 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR0b:10 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb1 2bb1 <halt> ; Flow R 2bb2 ; -------------------------------------------------------------------------------------- 2bb2 ; 0x00f1 Load_Encached eon 2bb2 ; -------------------------------------------------------------------------------------- 2bb2 MACRO_Load_Encached_eon: 2bb2 2bb2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 31 TR0b:11 typ_alu_func 15 NOT_B typ_b_adr 31 TR0b:11 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 31 VR0b:11 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb3 2bb3 <halt> ; Flow R 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 ; 0x00f2 Load_Encached eon 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 MACRO_Load_Encached_eon: 2bb4 2bb4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 32 TR0b:12 typ_alu_func 15 NOT_B typ_b_adr 32 TR0b:12 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 32 VR0b:12 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb5 2bb5 <halt> ; Flow R 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 ; 0x00f3 Load_Encached eon 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 MACRO_Load_Encached_eon: 2bb6 2bb6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 33 TR0b:13 typ_alu_func 15 NOT_B typ_b_adr 33 TR0b:13 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 33 VR0b:13 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb7 2bb7 <halt> ; Flow R 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 ; 0x00f4 Load_Encached eon 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 MACRO_Load_Encached_eon: 2bb8 2bb8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bb8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 34 TR0b:14 typ_alu_func 15 NOT_B typ_b_adr 34 TR0b:14 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 34 VR0b:14 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bb9 2bb9 <halt> ; Flow R 2bba ; -------------------------------------------------------------------------------------- 2bba ; 0x00f5 Load_Encached eon 2bba ; -------------------------------------------------------------------------------------- 2bba MACRO_Load_Encached_eon: 2bba 2bba dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bba fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 35 TR0b:15 typ_alu_func 15 NOT_B typ_b_adr 35 TR0b:15 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 35 VR0b:15 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbb 2bbb <halt> ; Flow R 2bbc ; -------------------------------------------------------------------------------------- 2bbc ; 0x00f6 Load_Encached eon 2bbc ; -------------------------------------------------------------------------------------- 2bbc MACRO_Load_Encached_eon: 2bbc 2bbc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR0b:16 typ_alu_func 15 NOT_B typ_b_adr 36 TR0b:16 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 36 VR0b:16 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbd 2bbd <halt> ; Flow R 2bbe ; -------------------------------------------------------------------------------------- 2bbe ; 0x00f7 Load_Encached eon 2bbe ; -------------------------------------------------------------------------------------- 2bbe MACRO_Load_Encached_eon: 2bbe 2bbe dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR0b:17 typ_alu_func 15 NOT_B typ_b_adr 37 TR0b:17 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR0b:17 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bbf 2bbf <halt> ; Flow R 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 ; 0x00f8 Load_Encached eon 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 MACRO_Load_Encached_eon: 2bc0 2bc0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR0b:18 typ_alu_func 15 NOT_B typ_b_adr 38 TR0b:18 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR0b:18 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc1 2bc1 <halt> ; Flow R 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 ; 0x00f9 Load_Encached eon 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 MACRO_Load_Encached_eon: 2bc2 2bc2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR0b:19 typ_alu_func 15 NOT_B typ_b_adr 39 TR0b:19 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR0b:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc3 2bc3 <halt> ; Flow R 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 ; 0x00fa Load_Encached eon 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 MACRO_Load_Encached_eon: 2bc4 2bc4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3a TR0b:1a typ_alu_func 15 NOT_B typ_b_adr 3a TR0b:1a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3a VR0b:1a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc5 2bc5 <halt> ; Flow R 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 ; 0x00fb Load_Encached eon 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 MACRO_Load_Encached_eon: 2bc6 2bc6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3b TR0b:1b typ_alu_func 15 NOT_B typ_b_adr 3b TR0b:1b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR0b:1b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc7 2bc7 <halt> ; Flow R 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 ; 0x00fc Load_Encached eon 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 MACRO_Load_Encached_eon: 2bc8 2bc8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3c TR0b:1c typ_alu_func 15 NOT_B typ_b_adr 3c TR0b:1c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3c VR0b:1c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc9 2bc9 <halt> ; Flow R 2bca ; -------------------------------------------------------------------------------------- 2bca ; 0x00fd Load_Encached eon 2bca ; -------------------------------------------------------------------------------------- 2bca MACRO_Load_Encached_eon: 2bca 2bca dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bca fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR0b:1d typ_alu_func 15 NOT_B typ_b_adr 3d TR0b:1d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3d VR0b:1d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcb 2bcb <halt> ; Flow R 2bcc ; -------------------------------------------------------------------------------------- 2bcc ; 0x00fe Load_Encached eon 2bcc ; -------------------------------------------------------------------------------------- 2bcc MACRO_Load_Encached_eon: 2bcc 2bcc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2bcf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bcc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR0b:1e typ_alu_func 15 NOT_B typ_b_adr 3e TR0b:1e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3e VR0b:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcd 2bcd <halt> ; Flow R 2bce ; -------------------------------------------------------------------------------------- 2bce ; 0x00ff Load_Encached eon 2bce ; -------------------------------------------------------------------------------------- 2bce MACRO_Load_Encached_eon: 2bce 2bce dispatch_brk_class 4 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bce fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2bcf 0x2bcf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3f TR0b:1f typ_alu_func 15 NOT_B typ_b_adr 3f TR0b:1f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR0b:1f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcf 2bcf seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 ; 0x1b00-0x1bff Execute Package,Field_Read,fieldnum 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 MACRO_Execute_Package,Field_Read,fieldnum: 2bd0 2bd0 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2bd0 dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2bd1 2bd1 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_random 17 force type bus receivers ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2bd2 0x2bd2 seq_cond_sel 79 IOC.PFR seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bd2 2bd2 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2bdd seq_br_type 0 Branch False seq_branch_adr 2bdd 0x2bdd seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2bd3 2bd3 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2b78 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2b78 0x2b78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2bd4 2bd4 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2b80 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 2b80 0x2b80 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 0 PASS_A 2bd5 2bd5 seq_br_type 1 Branch True; Flow J cc=True 0x2b6d seq_branch_adr 2b6d 0x2b6d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 2bd6 2bd6 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 2bd7 2bd7 <halt> ; Flow R 2bd8 ; -------------------------------------------------------------------------------------- 2bd8 ; 0x0098 Execute Package,Field_Read_Dynamic 2bd8 ; -------------------------------------------------------------------------------------- 2bd8 MACRO_Execute_Package,Field_Read_Dynamic: 2bd8 2bd8 dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2bd8 fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2bd9 2bd9 fiu_mem_start 2 start-rd; Flow C cc=True 0x32ac ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2bda 2bda ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2bdb 2bdb fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bdc 0x2bdc seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bdc 2bdc ioc_tvbs 2 fiu+val; Flow J 0x2bd3 seq_br_type 3 Unconditional Branch seq_branch_adr 2bd3 0x2bd3 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2bdd 2bdd fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32a8 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2bde 2bde seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 2bdf 2bdf seq_br_type 4 Call False; Flow C cc=False 0x326c seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR1b:0d val_frame 1b 2be0 2be0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be4 seq_br_type 1 Branch True seq_branch_adr 2be4 0x2be4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 1f TOP - 1 typ_frame 1 val_a_adr 26 VR12:06 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 12 2be1 2be1 ioc_fiubs 1 val ; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 2be2 2be2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2be6 seq_br_type 1 Branch True seq_branch_adr 2be6 0x2be6 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 10 NOT_A val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 2be3 2be3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2be4 2be4 ioc_fiubs 1 val ; Flow J cc=False 0x2be2 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2be2 0x2be2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1b val_a_adr 17 LOOP_COUNTER 2be5 2be5 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 2be6 2be6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326c seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2be7 2be7 seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 2be8 ; -------------------------------------------------------------------------------------- 2be8 ; 0x009a Action Call_Dynamic 2be8 ; -------------------------------------------------------------------------------------- 2be8 MACRO_Action_Call_Dynamic: 2be8 2be8 dispatch_brk_class 6 ; Flow C 0x2c6e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2be8 seq_br_type 7 Unconditional Call seq_branch_adr 2c6e 0x2c6e typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2be9 2be9 fiu_mem_start 2 start-rd; Flow J cc=True 0x2bf2 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2bf2 MACRO_Call_llvl,ldelta 2bea ; -------------------------------------------------------------------------------------- 2bea ; 0x8200-0x9fff Call llvl,ldelta 2bea ; -------------------------------------------------------------------------------------- 2bea MACRO_Call_llvl,ldelta: 2bea 2bea dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2bea fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2beb 2beb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2bed fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2bed 0x2bed seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 50 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2bec 2bec fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c05 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c05 0x2c05 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bed 2bed fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c38 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c38 0x2c38 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A 2bee 2bee seq_br_type 2 Push (branch address); Flow J 0x2bef seq_branch_adr 2c05 0x2c05 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2bef 2bef fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c3d fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c3d 0x2c3d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf0 2bf0 fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c35 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c35 0x2c35 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bf1 2bf1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2bf2 ; -------------------------------------------------------------------------------------- 2bf2 ; 0x8000-0x81ff Call llvl,ldelta 2bf2 ; -------------------------------------------------------------------------------------- 2bf2 MACRO_Call_llvl,ldelta: 2bf2 2bf2 dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2bf2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 14 ZEROS typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2bf3 2bf3 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a5 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf4 2bf4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 37 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2bf5 2bf5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2c35 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c35 0x2c35 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bf6 2bf6 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c05 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c05 0x2c05 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bf7 2bf7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2bf1 seq_br_type 3 Unconditional Branch seq_branch_adr 2bf1 0x2bf1 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2bf8 ; -------------------------------------------------------------------------------------- 2bf8 ; 0x1800-0x18ff Execute Package,Field_Execute,fieldnum 2bf8 ; -------------------------------------------------------------------------------------- 2bf8 MACRO_Execute_Package,Field_Execute,fieldnum: 2bf8 2bf8 dispatch_brk_class 6 ; Flow J cc=True 0x3b94 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2bf8 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3b94 0x3b94 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 0a ? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 18 NOT_A_AND_B val_b_adr 22 VR11:02 val_frame 11 2bf9 2bf9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2bfb fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2bfb 0x2bfb seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 4a Load_current_lex+? typ_a_adr 20 TR16:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2bfa 2bfa fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c05 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c05 0x2c05 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2bfb 2bfb seq_br_type 0 Branch False; Flow J cc=False 0x2c00 seq_branch_adr 2c00 0x2c00 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 val_c_adr 3e GP01 2bfc 2bfc fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c39 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c39 0x2c39 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 2bfd 2bfd seq_br_type 2 Push (branch address); Flow J 0x2bfe seq_branch_adr 2c05 0x2c05 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2bfe 2bfe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c3d fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c3d 0x2c3d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2bff 2bff fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c35 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c35 0x2c35 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c00 2c00 seq_br_type 1 Branch True; Flow J cc=True 0x2c39 seq_branch_adr 2c39 0x2c39 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_frame 10 2c01 2c01 ioc_load_wdr 0 ; Flow J 0x2c39 seq_br_type 3 Unconditional Branch seq_branch_adr 2c39 0x2c39 typ_b_adr 29 TR05:09 typ_frame 5 val_b_adr 01 GP01 2c02 ; -------------------------------------------------------------------------------------- 2c02 ; 0x0096 Execute Package,Field_Execute_Dynamic 2c02 ; -------------------------------------------------------------------------------------- 2c02 MACRO_Execute_Package,Field_Execute_Dynamic: 2c02 2c02 dispatch_brk_class 6 ; Flow C cc=False 0x32ac dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c02 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c03 2c03 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a5 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2c04 2c04 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2bf9 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2bf9 0x2bf9 seq_int_reads 5 RESOLVE RAM seq_random 0a ? 2c05 2c05 ioc_fiubs 0 fiu ; Flow J cc=False 0x2c07 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c07 0x2c07 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 2d Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c06 2c06 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x2bf1 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bf1 0x2bf1 seq_cond_sel 4f SEQ.uE_field_number_error seq_random 54 Load_save_offset+Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c07 2c07 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2c27 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2c27 0x2c27 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c08 ; -------------------------------------------------------------------------------------- 2c08 ; 0x1c00-0x1cff Execute_Immediate Run_Utility,uimmediate 2c08 ; -------------------------------------------------------------------------------------- 2c08 MACRO_Execute_Immediate_Run_Utility,uimmediate: 2c08 2c08 dispatch_brk_class 6 ; Flow C cc=True 0x32a5 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_uadr 2c08 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2c09 2c09 fiu_tivi_src 4 fiu_var; Flow J cc=False 0x32a5 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c0a 2c0a fiu_load_tar 1 hold_tar; Flow J cc=True 0x2c23 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c23 0x2c23 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 2d TR1b:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 2c0b 2c0b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4c Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 2c0c 2c0c fiu_load_tar 1 hold_tar; Flow J cc=False 0x2c1b fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c1b 0x2c1b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2c0d 2c0d fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c0e 2c0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c18 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c18 0x2c18 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c0f 2c0f ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c10 2c10 fiu_load_var 1 hold_var; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2c11 0x2c11 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c11 2c11 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2c12 2c12 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 2c13 2c13 fiu_len_fill_lit 4c zero-fill 0xc; Flow R cc=False ; Flow J cc=True 0x32fc fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 32fc 0x32fc seq_random 04 Load_save_offset+? typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 21 TOP - 0x2 val_c_source 0 FIU_BUS 2c14 ; -------------------------------------------------------------------------------------- 2c14 ; 0x0127 Execute Any,Run_Initialization_Utility 2c14 ; -------------------------------------------------------------------------------------- 2c14 MACRO_Execute_Any,Run_Initialization_Utility: 2c14 2c14 dispatch_brk_class 6 ; Flow C cc=True 0x32a5 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2c14 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c15 2c15 seq_br_type 0 Branch False; Flow J cc=False 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 2c16 2c16 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2c17 0x2c17 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR05:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 2c17 2c17 fiu_mem_start 2 start-rd; Flow J 0x2c09 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c09 0x2c09 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 2c18 2c18 ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c19 2c19 fiu_load_var 1 hold_var; Flow C cc=True 0x2c11 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c11 0x2c11 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c1a 2c1a fiu_mem_start 2 start-rd; Flow J 0x2c27 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c27 0x2c27 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2c1b 2c1b fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c1c 2c1c ioc_fiubs 0 fiu typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c1d 2c1d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2c1e 2c1e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 10 TOP typ_c_adr 3d GP02 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c1f 2c1f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 1d TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2c20 2c20 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2c21 2c21 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2c11 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c11 0x2c11 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c22 2c22 fiu_mem_start 2 start-rd; Flow J 0x2c27 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c27 0x2c27 seq_random 15 ? typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE 2c23 2c23 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 2c24 0x2c24 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL 2c24 2c24 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2c25 2c25 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2c26 2c26 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c27 2c27 seq_br_type 3 Unconditional Branch; Flow J 0x2bf7 seq_branch_adr 2bf7 0x2bf7 2c28 ; -------------------------------------------------------------------------------------- 2c28 ; 0x00c5 Action Set_Block_Start 2c28 ; -------------------------------------------------------------------------------------- 2c28 MACRO_Action_Set_Block_Start: 2c28 2c28 dispatch_brk_class 8 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2c28 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c29 2c29 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_mdr 1 hold_mdr fiu_offs_lit 54 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2c2a 2c2a fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c2b fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2bf7 0x2bf7 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2c2b 2c2b fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_random 16 ? typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_c_adr 1d VR02:02 val_c_source 0 FIU_BUS val_frame 2 2c2c 2c2c fiu_mem_start 2 start-rd; Flow J 0x32fc ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 32fc 0x32fc seq_random 02 ? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2c2d ; -------------------------------------------------------------------------------------- 2c2d ; Comes from: 2c2d ; 2c35 C from color 0x0000 2c2d ; 2c39 C from color 0x0000 2c2d ; 2c3e C from color 0x0000 2c2d ; -------------------------------------------------------------------------------------- 2c2d 2c2d fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2c2e 2c2e ioc_fiubs 1 val seq_random 41 Load_control_pred+? val_a_adr 3e VR02:1e val_frame 2 2c2f 2c2f fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 2c30 2c30 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3e ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c31 2c31 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_random 6c Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2c32 2c32 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 2c33 2c33 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c34 2c34 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2c35 2c35 fiu_load_var 1 hold_var; Flow C 0x2c2d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2d 0x2c2d seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c36 2c36 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c37 2c37 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2c38 2c38 seq_br_type 3 Unconditional Branch; Flow J 0x2c35 seq_branch_adr 2c35 0x2c35 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c39 2c39 fiu_load_var 1 hold_var; Flow C 0x2c2d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2d 0x2c2d seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c3a 2c3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c3b 2c3b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277 seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_frame 2 2c3c 2c3c seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 2c3d 2c3d ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2c3e 2c3e fiu_load_var 1 hold_var; Flow C 0x2c2d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c2d 0x2c2d seq_en_micro 0 seq_random 0a ? val_a_adr 3e VR02:1e val_frame 2 2c3f 2c3f fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 2c40 2c40 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_b_adr 16 CSA/VAL_BUS 2c41 2c41 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? val_a_adr 05 GP05 2c42 2c42 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c43 2c43 <halt> ; Flow R 2c44 ; -------------------------------------------------------------------------------------- 2c44 ; 0x1d00-0x1dff Execute_Immediate Reference_Lex_1,uimmediate 2c44 ; -------------------------------------------------------------------------------------- 2c44 MACRO_Execute_Immediate_Reference_Lex_1,uimmediate: 2c44 2c44 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2c44 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME 2c45 2c45 fiu_mem_start 2 start-rd; Flow J 0x2c48 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c48 0x2c48 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2c46 ; -------------------------------------------------------------------------------------- 2c46 ; 0x0099 Action Reference_Dynamic 2c46 ; -------------------------------------------------------------------------------------- 2c46 MACRO_Action_Reference_Dynamic: 2c46 2c46 dispatch_brk_class 4 ; Flow C 0x2c6e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c46 seq_br_type 7 Unconditional Call seq_branch_adr 2c6e 0x2c6e typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2c47 2c47 fiu_mem_start 2 start-rd; Flow J cc=True 0x2c56 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c56 MACRO_Reference_zdelta 2c48 2c48 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 32 TR05:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2c49 2c49 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4a 0x2c4a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 1c ? typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c4a 2c4a fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4b 0x2c4b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2c4b 2c4b seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x2c4d seq_br_type f Unconditional Case Call seq_branch_adr 2c4d 0x2c4d seq_en_micro 0 2c4c 2c4c seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 2c4d ; -------------------------------------------------------------------------------------- 2c4d ; Comes from: 2c4d ; 2c4b C #0x0 from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2c4d ; -------------------------------------------------------------------------------------- 2c4d 2c4d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c4e 2c4e seq_br_type a Unconditional Return; Flow R 2c4f 2c4f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c50 2c50 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c51 2c51 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c52 2c52 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2c4c ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c4c 0x2c4c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL 2c53 2c53 seq_br_type a Unconditional Return; Flow R 2c54 2c54 seq_br_type a Unconditional Return; Flow R 2c55 2c55 <halt> ; Flow R 2c56 ; -------------------------------------------------------------------------------------- 2c56 ; 0xa000-0xa1ff Reference zdelta 2c56 ; -------------------------------------------------------------------------------------- 2c56 MACRO_Reference_zdelta: 2c56 2c56 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2c56 2c57 2c57 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c58 0x2c58 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 1c ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c58 2c58 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 2c59 2c59 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 2c5a ; -------------------------------------------------------------------------------------- 2c5a ; 0x1900-0x19ff Execute Package,Field_Reference,fieldnum 2c5a ; -------------------------------------------------------------------------------------- 2c5a MACRO_Execute_Package,Field_Reference,fieldnum: 2c5a 2c5a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2c5a dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c5b 2c5b fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c5c 2c5c fiu_len_fill_lit 01 sign-fill 0x1; Flow J cc=True 0x2c5d ; Flow J cc=#0x0 0x2c5e fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2c5e 0x2c5e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c5d 2c5d seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c5e 2c5e fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c5f 2c5f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c60 2c60 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c61 2c61 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 32 TR05:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c62 2c62 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c63 2c63 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c64 2c64 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c66 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c66 0x2c66 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c65 2c65 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c66 2c66 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2c67 2c67 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2c68 0x2c68 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2c68 2c68 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c69 2c69 <halt> ; Flow R 2c6a ; -------------------------------------------------------------------------------------- 2c6a ; 0x0095 Execute Package,Field_Reference_Dynamic 2c6a ; -------------------------------------------------------------------------------------- 2c6a MACRO_Execute_Package,Field_Reference_Dynamic: 2c6a 2c6a dispatch_brk_class 8 ; Flow C cc=True 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c6a fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2c6b 2c6b fiu_mem_start 2 start-rd; Flow C cc=True 0x32ac ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c6c 2c6c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 1f TOP - 1 val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c6d 2c6d fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2c5c fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2c5c 0x2c5c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c6e ; -------------------------------------------------------------------------------------- 2c6e ; Comes from: 2c6e ; 1c98 C from color 0x0000 2c6e ; 2b68 C from color 0x0000 2c6e ; 2be8 C from color 0x0000 2c6e ; 2c46 C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2c6e ; -------------------------------------------------------------------------------------- 2c6e 2c6e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x2c74 fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2c74 0x2c74 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c6f 2c6f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32ac fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2c70 2c70 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x2c73 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2c73 0x2c73 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 2c71 2c71 val_rand 2 DEC_LOOP_COUNTER 2c72 2c72 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2c71 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2c71 0x2c71 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2c73 2c73 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2c74 2c74 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32ac fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2c75 2c75 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c73 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2c73 0x2c73 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c76 2c76 ioc_adrbs 1 val ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 0 PASS_A 2c77 2c77 <halt> ; Flow R 2c78 ; -------------------------------------------------------------------------------------- 2c78 ; 0x1100-0x11ff Execute Select,Member_Write,fieldnum 2c78 ; -------------------------------------------------------------------------------------- 2c78 MACRO_Execute_Select,Member_Write,fieldnum: 2c78 2c78 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2c78 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 2c79 2c79 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2c8c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c8c 0x2c8c seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2c7a 2c7a fiu_mem_start 2 start-rd; Flow C cc=False 0x32ac ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c7b 2c7b seq_br_type 4 Call False; Flow C cc=False 0x3274 seq_branch_adr 3274 0x3274 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR06:16 val_frame 6 2c7c 2c7c fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=False 0x2c84 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c84 0x2c84 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2c7d 2c7d fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 2c7e 2c7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3274 fiu_offs_lit 07 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c7f 2c7f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS 2c80 2c80 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2c81 2c81 fiu_mem_start 3 start-wr; Flow C cc=False 0x3274 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 3274 0x3274 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c82 2c82 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 2c83 2c83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c84 ; -------------------------------------------------------------------------------------- 2c84 ; Comes from: 2c84 ; 2c7c C False from color MACRO_Execute_Select,Member_Write,fieldnum 2c84 ; -------------------------------------------------------------------------------------- 2c84 2c84 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL 2c85 2c85 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 2c86 2c86 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c87 2c87 fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x3274 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c88 2c88 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 19 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2c89 2c89 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2c8a 2c8a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2c8b 0x2c8b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2c8b 2c8b seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 2c8c 2c8c fiu_mem_start 2 start-rd; Flow C cc=False 0x32ac ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c8d 2c8d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2c7c seq_br_type 0 Branch False seq_branch_adr 2c7c 0x2c7c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 2c8e 2c8e seq_br_type 7 Unconditional Call; Flow C 0x3274 seq_branch_adr 3274 0x3274 2c8f 2c8f <halt> ; Flow R 2c90 ; -------------------------------------------------------------------------------------- 2c90 ; 0x1000-0x10ff Execute Select,Guard_Write,fieldnum 2c90 ; -------------------------------------------------------------------------------------- 2c90 MACRO_Execute_Select,Guard_Write,fieldnum: 2c90 2c90 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2c90 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2c91 2c91 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2c92 2c92 fiu_mem_start 2 start-rd; Flow C cc=False 0x32ac ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32ac 0x32ac seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2c93 2c93 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2c97 seq_br_type 1 Branch True seq_branch_adr 2c97 0x2c97 typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2c94 2c94 fiu_mem_start 7 start_wr_if_true ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 3a TR06:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c95 2c95 ioc_load_wdr 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2c96 2c96 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c97 2c97 fiu_mem_start 3 start-wr; Flow J 0x2c95 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2c95 0x2c95 typ_a_adr 3a TR06:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c98 ; -------------------------------------------------------------------------------------- 2c98 ; 0x013d Execute Select,Timed_Duration_Write 2c98 ; -------------------------------------------------------------------------------------- 2c98 MACRO_Execute_Select,Timed_Duration_Write: 2c98 2c98 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2c98 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2c99 2c99 ioc_fiubs 2 typ ; Flow C cc=False 0x32b0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32b0 0x32b0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c9a 2c9a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_b_adr 3a TR07:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B 2c9b 2c9b ioc_load_wdr 0 ; Flow J cc=True 0x2c9d ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c9d 0x2c9d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_frame 7 val_a_adr 25 VR07:05 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_frame 7 2c9c 2c9c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2c9d 2c9d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ac seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 2 PUSH_CSA typ_frame 7 2c9e 2c9e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326c seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 1a PASS_B val_b_adr 10 TOP 2c9f 2c9f fiu_mem_start 3 start-wr; Flow J 0x2c9b ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c9b 0x2c9b typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 2ca0 ; -------------------------------------------------------------------------------------- 2ca0 ; 0x013e Execute Select,Timed_Guard_Write 2ca0 ; -------------------------------------------------------------------------------------- 2ca0 MACRO_Execute_Select,Timed_Guard_Write: 2ca0 2ca0 dispatch_brk_class 8 ; Flow C cc=False 0x32b0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ca0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32b0 0x32b0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ca1 2ca1 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2ca2 2ca2 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2ca3 2ca3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2ca4 ; -------------------------------------------------------------------------------------- 2ca4 ; 0x013c Execute Select,Terminate_Guard_Write 2ca4 ; -------------------------------------------------------------------------------------- 2ca4 MACRO_Execute_Select,Terminate_Guard_Write: 2ca4 2ca4 dispatch_brk_class 8 ; Flow C cc=False 0x32b0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ca4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32b0 0x32b0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ca5 2ca5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2ca6 2ca6 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2ca7 2ca7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2ca8 ; -------------------------------------------------------------------------------------- 2ca8 ; 0x029f Declare_Subprogram For_Call,subp 2ca8 ; -------------------------------------------------------------------------------------- 2ca8 MACRO_Declare_Subprogram_For_Call,subp: 2ca8 2ca8 dispatch_brk_class 4 ; Flow J 0x2ca9 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ca8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2ca9 2ca9 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2caa ; -------------------------------------------------------------------------------------- 2caa ; 0x029e Declare_Subprogram For_Call,Unelaborated,subp 2caa ; -------------------------------------------------------------------------------------- 2caa MACRO_Declare_Subprogram_For_Call,Unelaborated,subp: 2caa 2caa dispatch_brk_class 4 ; Flow J 0x2cab dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2caa fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cab 2cab fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cac ; -------------------------------------------------------------------------------------- 2cac ; 0x029d Declare_Subprogram For_Outer_Call,subp 2cac ; -------------------------------------------------------------------------------------- 2cac MACRO_Declare_Subprogram_For_Outer_Call,subp: 2cac 2cac dispatch_brk_class 4 ; Flow J 0x2cad dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cad 2cad fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR07:10 val_frame 7 2cae ; -------------------------------------------------------------------------------------- 2cae ; 0x029c Declare_Subprogram For_Outer_Call,Visible,subp 2cae ; -------------------------------------------------------------------------------------- 2cae MACRO_Declare_Subprogram_For_Outer_Call,Visible,subp: 2cae 2cae dispatch_brk_class 4 ; Flow J 0x2caf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2caf 2caf fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR07:0b val_frame 7 2cb0 ; -------------------------------------------------------------------------------------- 2cb0 ; 0x029b Declare_Subprogram For_Outer_Call,Unelaborated,subp 2cb0 ; -------------------------------------------------------------------------------------- 2cb0 MACRO_Declare_Subprogram_For_Outer_Call,Unelaborated,subp: 2cb0 2cb0 dispatch_brk_class 4 ; Flow J 0x2cb1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cb0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cb1 2cb1 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_frame 5 2cb2 ; -------------------------------------------------------------------------------------- 2cb2 ; 0x029a Declare_Subprogram For_Outer_Call,Visible,Unelaborated,subp 2cb2 ; -------------------------------------------------------------------------------------- 2cb2 MACRO_Declare_Subprogram_For_Outer_Call,Visible,Unelaborated,subp: 2cb2 2cb2 dispatch_brk_class 4 ; Flow J 0x2cb3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cb2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2cb4 0x2cb4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cb3 2cb3 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2cb7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2cb7 0x2cb7 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR07:0a val_frame 7 2cb4 2cb4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2cb5 0x2cb5 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cb5 2cb5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32aa seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cb6 2cb6 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 2cb7 2cb7 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE 2cb8 2cb8 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2cb9 2cb9 <halt> ; Flow R 2cba ; -------------------------------------------------------------------------------------- 2cba ; 0x0299 Declare_Subprogram For_Accept,subp 2cba ; -------------------------------------------------------------------------------------- 2cba MACRO_Declare_Subprogram_For_Accept,subp: 2cba 2cba dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cba fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 2cbb 2cbb fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x32aa fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 2cbc 2cbc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2cbd 2cbd fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cbe ; -------------------------------------------------------------------------------------- 2cbe ; 0x02ab Declare_Subprogram For_Call,With_Address 2cbe ; -------------------------------------------------------------------------------------- 2cbe MACRO_Declare_Subprogram_For_Call,With_Address: 2cbe 2cbe dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cbe fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cbf 2cbf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccb fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccb 0x2ccb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc0 ; -------------------------------------------------------------------------------------- 2cc0 ; 0x02aa Declare_Subprogram For_Call,Visible,With_Address 2cc0 ; -------------------------------------------------------------------------------------- 2cc0 MACRO_Declare_Subprogram_For_Call,Visible,With_Address: 2cc0 2cc0 dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc1 2cc1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cca fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cca 0x2cca seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 ; 0x02a9 Declare_Subprogram For_Call,Unelaborated,With_Address 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 MACRO_Declare_Subprogram_For_Call,Unelaborated,With_Address: 2cc2 2cc2 dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc3 2cc3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccb fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccb 0x2ccb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc4 ; -------------------------------------------------------------------------------------- 2cc4 ; 0x02a8 Declare_Subprogram For_Call,Visible,Unelaborated,With_Address 2cc4 ; -------------------------------------------------------------------------------------- 2cc4 MACRO_Declare_Subprogram_For_Call,Visible,Unelaborated,With_Address: 2cc4 2cc4 dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cc5 2cc5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cca fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cca 0x2cca seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2a TR05:0a typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cc6 ; -------------------------------------------------------------------------------------- 2cc6 ; 0x02a5 Declare_Subprogram For_Outer_Call,With_Address 2cc6 ; -------------------------------------------------------------------------------------- 2cc6 MACRO_Declare_Subprogram_For_Outer_Call,With_Address: 2cc6 2cc6 dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc6 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2cc7 2cc7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ccb fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2ccb 0x2ccb seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2cc8 ; -------------------------------------------------------------------------------------- 2cc8 ; 0x02a4 Declare_Subprogram For_Outer_Call,Visible,With_Address 2cc8 ; -------------------------------------------------------------------------------------- 2cc8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,With_Address: 2cc8 2cc8 dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cc8 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2cc9 2cc9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cca fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cca 0x2cca seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2cca 2cca seq_br_type 4 Call False; Flow C cc=False 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2ccb 2ccb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2ccc 0x2ccc seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ccc 2ccc seq_br_type 3 Unconditional Branch; Flow J 0x32aa seq_branch_adr 32aa 0x32aa typ_csa_cntl 3 POP_CSA 2ccd 2ccd <halt> ; Flow R 2cce ; -------------------------------------------------------------------------------------- 2cce ; 0x02a2 Declare_Subprogram For_Accept,With_Address 2cce ; -------------------------------------------------------------------------------------- 2cce MACRO_Declare_Subprogram_For_Accept,With_Address: 2cce 2cce dispatch_brk_class 4 ; Flow J cc=True 0x32aa dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2cce fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32aa 0x32aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2ccf 2ccf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32aa fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cd0 2cd0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd1 2cd1 fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cd2 ; -------------------------------------------------------------------------------------- 2cd2 ; 0x02a0 Declare_Subprogram Null_Subprogram 2cd2 ; -------------------------------------------------------------------------------------- 2cd2 MACRO_Declare_Subprogram_Null_Subprogram: 2cd2 2cd2 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cd2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 38 TR06:18 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2cd3 2cd3 <halt> ; Flow R 2cd4 ; -------------------------------------------------------------------------------------- 2cd4 ; 0x00c7 Action Elaborate_Subprogram 2cd4 ; -------------------------------------------------------------------------------------- 2cd4 MACRO_Action_Elaborate_Subprogram: 2cd4 2cd4 dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cd4 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 2cd5 2cd5 fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd6 2cd6 ioc_load_wdr 0 seq_random 02 ? 2cd7 2cd7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2cd8 ; -------------------------------------------------------------------------------------- 2cd8 ; 0x00c6 Action Check_Subprogram_Elaborated 2cd8 ; -------------------------------------------------------------------------------------- 2cd8 MACRO_Action_Check_Subprogram_Elaborated: 2cd8 2cd8 dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cd8 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 2cd9 2cd9 seq_br_type 2 Push (branch address); Flow J 0x2cda seq_branch_adr 3277 0x3277 2cda 2cda fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2cdb 0x2cdb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 2cdb 2cdb seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2cdc 2cdc fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2cdd 2cdd fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cde 2cde ioc_load_wdr 0 ; Flow J 0x2d16 seq_br_type 3 Unconditional Branch seq_branch_adr 2d16 0x2d16 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2cdf ; -------------------------------------------------------------------------------------- 2cdf ; Comes from: 2cdf ; 2cf5 C from color 0x2cf4 2cdf ; -------------------------------------------------------------------------------------- 2cdf 2cdf fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2ce0 2ce0 ioc_tvbs 5 seq+seq; Flow J cc=False 0x2cf2 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2cf2 0x2cf2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 2ce1 2ce1 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2ce2 2ce2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2ce5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ce5 0x2ce5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f 2ce3 2ce3 fiu_mem_start 2 start-rd; Flow C 0x2ced ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ced 0x2ced seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 2ce4 2ce4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 2ce5 2ce5 fiu_mem_start 2 start-rd; Flow C 0x2ce4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ce4 0x2ce4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2ce6 2ce6 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2a82 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 2ce7 2ce7 fiu_mem_start 2 start-rd; Flow C 0x2ced ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ced 0x2ced seq_en_micro 0 typ_a_adr 25 TR12:05 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 2ce8 2ce8 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2ce3 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ce3 0x2ce3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 2ce9 2ce9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 2cea 2cea seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2ce3 seq_br_type 0 Branch False seq_branch_adr 2ce3 0x2ce3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 2ceb 2ceb ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 2 INC_A_PLUS_B typ_b_adr 34 TR12:14 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f 2cec 2cec fiu_mem_start 2 start-rd; Flow J 0x2ce4 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2ce4 0x2ce4 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2ced 2ced seq_en_micro 0 2cee 2cee seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2cef 0x2cef seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2cef 2cef seq_en_micro 0 seq_random 06 Pop_stack+? 2cf0 2cf0 seq_br_type 7 Unconditional Call; Flow C 0x2cf2 seq_branch_adr 2cf2 0x2cf2 seq_en_micro 0 2cf1 2cf1 seq_br_type 3 Unconditional Branch; Flow J 0x2ce1 seq_branch_adr 2ce1 0x2ce1 val_c_adr 30 GP0f 2cf2 ; -------------------------------------------------------------------------------------- 2cf2 ; Comes from: 2cf2 ; 2cdc C from color ML_break_class 2cf2 ; 2cf9 C from color 0x2cf9 2cf2 ; 2cfb C from color 0x2cfb 2cf2 ; 2cfe C from color 0x2cfe 2cf2 ; 2cff C from color 0x2cfe 2cf2 ; 2d01 C from color 0x2cf4 2cf2 ; 2d0e C from color ML_break_class 2cf2 ; 2d12 C from color 0x2d11 2cf2 ; 2d3d C from color ML_break_class 2cf2 ; 2d41 C from color ML_break_class 2cf2 ; 2d44 C from color 0x2d43 2cf2 ; -------------------------------------------------------------------------------------- 2cf2 2cf2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2cf3 0x2cf3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 2cf3 ; -------------------------------------------------------------------------------------- 2cf3 ; Comes from: 2cf3 ; 2d04 C True from color ML_break_class 2cf3 ; 2d07 C True from color ML_break_class 2cf3 ; -------------------------------------------------------------------------------------- 2cf3 2cf3 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32b3 seq_branch_adr 32b3 0x32b3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2cf4 2cf4 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_b_adr 1f TOP - 1 2cf5 2cf5 fiu_mem_start 2 start-rd; Flow C 0x2cdf ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2cf6 2cf6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d31 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d31 0x2d31 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2cf7 2cf7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 25 TR00:05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2cf8 2cf8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 24 TR00:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2cf9 2cf9 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2cfa 2cfa fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 2cfb 2cfb fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2cfc 2cfc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2cfd 2cfd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2cfe 2cfe fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 9 val_rand a PASS_B_HIGH 2cff 2cff fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d00 2d00 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2d01 2d01 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2d02 2d02 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d31 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d31 0x2d31 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d03 2d03 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_frame 4 val_rand a PASS_B_HIGH 2d04 2d04 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2cf3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2cf3 0x2cf3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d05 2d05 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d15 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d15 0x2d15 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d06 2d06 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 15 NOT_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d07 2d07 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2cf3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2cf3 0x2cf3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d08 2d08 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 16 CSA/VAL_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 16 CSA/VAL_BUS 2d09 2d09 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2d0a 2d0a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2d0b 2d0b fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x2d0d fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d0d 0x2d0d typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 2d0c 2d0c ioc_tvbs 3 fiu+fiu; Flow J 0x2d16 seq_br_type 3 Unconditional Branch seq_branch_adr 2d16 0x2d16 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2d0d 2d0d fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2d15 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d15 0x2d15 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d0e 2d0e fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 32 VR05:12 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2d0f 2d0f fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d10 2d10 ioc_load_wdr 0 ; Flow J 0x2d16 seq_br_type 3 Unconditional Branch seq_branch_adr 2d16 0x2d16 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 2d11 2d11 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a5 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 37 VR05:17 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 5 2d12 2d12 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2cf2 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_b_adr 24 VR11:04 val_frame 11 2d13 2d13 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2d14 2d14 fiu_mem_start 3 start-wr; Flow C cc=True 0x32ab ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ab 0x32ab seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 28 TR06:08 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2d15 2d15 ioc_load_wdr 0 ; Flow J 0x2d16 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d16 0x2d16 2d16 2d16 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2d17 2d17 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d18 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2d1d 0x2d1d seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 2d18 2d18 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2d1b seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d1b 0x2d1b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2d19 2d19 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2cf3 seq_br_type 9 Return False seq_branch_adr 2cf3 0x2cf3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d1a 2d1a seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 2d1b 2d1b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2d1a ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d1a 0x2d1a seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2d1c 2d1c seq_br_type 7 Unconditional Call; Flow C 0x2cdf seq_branch_adr 2cdf 0x2cdf seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2d1d 2d1d fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d1b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2d1b 0x2d1b seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 2d1e 2d1e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d1f 2d1f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d20 2d20 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2d29 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2d29 0x2d29 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_frame 2 2d21 2d21 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d29 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d29 0x2d29 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR07:03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2d22 2d22 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d23 2d23 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2d24 2d24 ioc_fiubs 0 fiu ; Flow J cc=False 0x2d2a ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d2a 0x2d2a seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 6 A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2d25 2d25 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d2a ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d2a 0x2d2a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 2d26 2d26 fiu_vmux_sel 1 fill value; Flow J 0x2d23 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d23 0x2d23 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d27 2d27 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d28 2d28 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d29 2d29 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2d27 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 10 fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d27 0x2d27 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 2d2a 2d2a fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 30 TR00:10 typ_alu_func 0 PASS_A typ_c_adr 0f TR00:10 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 2d2b 2d2b <halt> ; Flow R 2d2c ; -------------------------------------------------------------------------------------- 2d2c ; 0x006b Action Query_Break_Address 2d2c ; -------------------------------------------------------------------------------------- 2d2c MACRO_Action_Query_Break_Address: 2d2c 2d2c dispatch_brk_class 0 ; Flow C 0x2d33 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d2c fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d33 0x2d33 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d2d 2d2d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1d 2d2e ; -------------------------------------------------------------------------------------- 2d2e ; 0x006d Action Query_Break_Cause 2d2e ; -------------------------------------------------------------------------------------- 2d2e MACRO_Action_Query_Break_Cause: 2d2e 2d2e dispatch_brk_class 0 ; Flow J 0x2d2f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d2e fiu_len_fill_lit 42 zero-fill 0x2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 7d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d2f 0x2d2f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d2f 2d2f ioc_tvbs 5 seq+seq; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d30 2d30 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d31 2d31 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d32 ; -------------------------------------------------------------------------------------- 2d32 ; 0x006c Action Query_Break_Mask 2d32 ; -------------------------------------------------------------------------------------- 2d32 MACRO_Action_Query_Break_Mask: 2d32 2d32 dispatch_brk_class 0 ; Flow J 0x2d2f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d32 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d2f 0x2d2f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d33 ; -------------------------------------------------------------------------------------- 2d33 ; Comes from: 2d33 ; 2d2c C from color MACRO_Action_Query_Break_Address 2d33 ; 2d34 C from color ML_break_class 2d33 ; -------------------------------------------------------------------------------------- 2d33 2d33 ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d34 ; -------------------------------------------------------------------------------------- 2d34 ; 0x006a Action Alter_Break_Mask 2d34 ; -------------------------------------------------------------------------------------- 2d34 MACRO_Action_Alter_Break_Mask: 2d34 2d34 dispatch_brk_class 0 ; Flow C 0x2d33 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2d34 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d33 0x2d33 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d35 2d35 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 2d36 2d36 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d15 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d15 0x2d15 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d37 2d37 <halt> ; Flow R 2d38 ; -------------------------------------------------------------------------------------- 2d38 ; 0x006f Action Break_Unconditional 2d38 ; -------------------------------------------------------------------------------------- 2d38 MACRO_Action_Break_Unconditional: 2d38 2d38 dispatch_brk_class 0 dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2d38 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 3e VR03:1e val_frame 3 2d39 2d39 fiu_load_tar 1 hold_tar; Flow J 0x14a fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d3a 2d3a fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d3b 2d3b ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 16 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d3c 2d3c ioc_tvbs 2 fiu+val; Flow J cc=True 0x2d48 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d48 0x2d48 typ_a_adr 2e TR06:0e typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 2d3d 2d3d fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 28 TR06:08 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d3e 2d3e fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2d47 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d47 0x2d47 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d3f 2d3f seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_en_micro 0 2d40 2d40 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2d39 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d39 0x2d39 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2d41 2d41 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d42 2d42 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2d43 2d43 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d44 2d44 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d45 2d45 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d46 2d46 ioc_load_wdr 0 ; Flow J 0x2d39 seq_br_type 3 Unconditional Branch seq_branch_adr 2d39 0x2d39 seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d47 2d47 seq_br_type 0 Branch False; Flow J cc=False 0x2dba seq_branch_adr 2dba 0x2dba seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 16 val_b_adr 39 VR02:19 val_frame 2 2d48 2d48 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 0a ? typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 30 VR02:10 val_frame 2 2d49 2d49 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 34 VR02:14 val_frame 2 2d4a 2d4a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 02 ? 2d4b 2d4b seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2d4c 2d4c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 03 GP03 2d4d 2d4d fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2d4e 2d4e ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 3 seq_random 25 Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d4f 2d4f fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d51 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d51 0x2d51 seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2d50 2d50 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d51 seq_br_type 3 Unconditional Branch seq_branch_adr 2d51 0x2d51 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2d51 2d51 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2d52 2d52 seq_br_type 3 Unconditional Branch; Flow J 0x2dba seq_branch_adr 2dba 0x2dba seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 39 VR02:19 val_frame 2 2d53 ; -------------------------------------------------------------------------------------- 2d53 ; Comes from: 2d53 ; 0148 C True from color ML_break_class 2d53 ; -------------------------------------------------------------------------------------- 2d53 2d53 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION 2d54 2d54 ioc_tvbs 5 seq+seq; Flow J cc=True 0x2d55 ; Flow J cc=#0x0 0x2d55 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2d55 0x2d55 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d55 2d55 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2d56 2d56 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d57 2d57 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d58 2d58 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d59 2d59 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5a 2d5a ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5b 2d5b ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5c 2d5c ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5d 2d5d ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d5e 2d5e fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d5f 2d5f fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d60 2d60 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d61 2d61 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d62 2d62 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d63 2d63 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d64 2d64 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 2d65 2d65 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 38 TR00:18 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 38 VR00:18 2d66 2d66 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 37 TR00:17 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 37 VR00:17 2d67 2d67 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 36 TR00:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 36 VR00:16 2d68 2d68 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR00:15 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 35 VR00:15 2d69 2d69 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 34 TR00:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 34 VR00:14 2d6a 2d6a fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 33 TR00:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 33 VR00:13 2d6b 2d6b fiu_tivi_src 4 fiu_var; Flow J cc=True 0x2d6e ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d6e 0x2d6e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR00:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 32 VR00:12 2d6c 2d6c fiu_tivi_src 4 fiu_var; Flow J cc=False 0x2dba ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2dba 0x2dba seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 31 TR00:11 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 31 VR00:11 val_c_adr 3b GP04 2d6d 2d6d seq_br_type 3 Unconditional Branch; Flow J 0x14a seq_branch_adr 014a 0x014a seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 04 GP04 2d6e 2d6e seq_br_type 3 Unconditional Branch; Flow J 0x2d6d seq_branch_adr 2d6d 0x2d6d seq_en_micro 0 val_c_adr 3b GP04 2d6f 2d6f <halt> ; Flow R 2d70 ; -------------------------------------------------------------------------------------- 2d70 ; 0x006e Action Exit_Break 2d70 ; -------------------------------------------------------------------------------------- 2d70 MACRO_Action_Exit_Break: 2d70 2d70 dispatch_brk_class 0 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2d70 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2d71 2d71 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_mar_cntl e LOAD_MAR_CONTROL 2d72 2d72 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d73 2d73 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d74 2d74 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2d75 2d75 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d76 2d76 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_lex_adr 2 seq_random 0b ? typ_a_adr 14 ZEROS val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2d77 2d77 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 2d78 2d78 ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2d79 2d79 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_b_adr 01 GP01 2d7a 2d7a fiu_mem_start 2 start-rd; Flow J 0x2dda seq_br_type 3 Unconditional Branch seq_branch_adr 2dda MACRO_Exit_Subprogram_topoffset,>R seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 14 Load_save_offset+? 2d7b ; -------------------------------------------------------------------------------------- 2d7b ; Comes from: 2d7b ; 2d9c C from color MACRO_Action_Query_Frame 2d7b ; 2dac C from color ML_break_class 2d7b ; -------------------------------------------------------------------------------------- 2d7b 2d7b ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 3a VR02:1a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d7c 2d7c fiu_load_tar 1 hold_tar; Flow J cc=True 0x2d80 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d80 0x2d80 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 5 RESOLVE RAM typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 2d7d 2d7d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2cdf fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2d7e 2d7e ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2d8d seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d8d 0x2d8d seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2d7f 2d7f seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d80 2d80 fiu_mem_start 2 start-rd; Flow C 0x2cf2 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cf2 0x2cf2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2d81 2d81 seq_br_type 1 Branch True; Flow J cc=True 0x2d84 seq_branch_adr 2d84 0x2d84 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2d82 2d82 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2d83 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 2d8d 0x2d8d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d83 2d83 fiu_mem_start 2 start-rd; Flow J 0x2cdf ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2cdf 0x2cdf seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2d84 2d84 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d85 2d85 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d86 2d86 fiu_mem_start 2 start-rd; Flow C 0x2cdf ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 2d87 2d87 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2d88 2d88 fiu_mem_start 2 start-rd; Flow C 0x2cdf ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2d89 2d89 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d8a 2d8a fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2d8b 2d8b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 2d8c 2d8c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d8d 2d8d fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d92 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2d92 0x2d92 seq_cond_sel 56 SEQ.LATCHED_COND typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d8e 2d8e ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2d7f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d7f 0x2d7f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3e VR02:1e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2d8f 2d8f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2d90 2d90 fiu_mem_start 2 start-rd; Flow C 0x2cdf ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d91 2d91 seq_br_type 3 Unconditional Branch; Flow J 0x2d8d seq_branch_adr 2d8d 0x2d8d seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2d92 2d92 fiu_len_fill_lit 13 sign-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand a PASS_B_HIGH 2d93 2d93 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2d7f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d7f 0x2d7f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2d94 2d94 seq_br_type 7 Unconditional Call; Flow C 0x2cdf seq_branch_adr 2cdf 0x2cdf seq_en_micro 0 2d95 2d95 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2cdf fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2d96 2d96 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2d99 seq_br_type 0 Branch False seq_branch_adr 2d99 0x2d99 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d97 2d97 fiu_mem_start 2 start-rd; Flow C 0x2cdf ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2cdf 0x2cdf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_frame 4 2d98 2d98 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2d99 0x2d99 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2d99 2d99 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2d9a ; -------------------------------------------------------------------------------------- 2d9a ; Comes from: 2d9a ; 2d9e C from color MACRO_Action_Query_Frame 2d9a ; 2dbf C from color 0x2dbd 2d9a ; 2dc3 C from color 0x2dbd 2d9a ; -------------------------------------------------------------------------------------- 2d9a 2d9a seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 2d9b 2d9b <halt> ; Flow R 2d9c ; -------------------------------------------------------------------------------------- 2d9c ; 0x0069 Action Query_Frame 2d9c ; -------------------------------------------------------------------------------------- 2d9c MACRO_Action_Query_Frame: 2d9c 2d9c dispatch_brk_class 0 ; Flow C 0x2d7b dispatch_csa_free 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2d9c seq_br_type 7 Unconditional Call seq_branch_adr 2d7b 0x2d7b 2d9d 2d9d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2da5 seq_br_type 1 Branch True seq_branch_adr 2da5 0x2da5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2d9e 2d9e ioc_fiubs 1 val ; Flow C 0x2d9a seq_br_type 7 Unconditional Call seq_branch_adr 2d9a 0x2d9a typ_a_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 2d9f 2d9f seq_b_timing 1 Latch Condition; Flow J cc=False 0x2da6 seq_br_type 0 Branch False seq_branch_adr 2da6 0x2da6 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2da0 2da0 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2da1 2da1 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 11 2da2 2da2 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR07:00 val_alu_func 1e A_AND_B val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 7 2da3 2da3 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 28 VR07:08 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU val_frame 7 2da4 2da4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU val_frame 6 2da5 2da5 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2da6 2da6 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2da7 2da7 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2da8 2da8 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2da9 2da9 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 2daa 2daa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 2dab 2dab <halt> ; Flow R 2dac ; -------------------------------------------------------------------------------------- 2dac ; 0x0068 Action Establish_Frame 2dac ; -------------------------------------------------------------------------------------- 2dac MACRO_Action_Establish_Frame: 2dac 2dac dispatch_brk_class 0 ; Flow C 0x2d7b dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2dac seq_br_type 7 Unconditional Call seq_branch_adr 2d7b 0x2d7b 2dad 2dad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2dbb seq_br_type 1 Branch True seq_branch_adr 2dbb 0x2dbb seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2dae 2dae ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2daf 2daf typ_a_adr 29 TR05:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2db0 2db0 val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2db1 2db1 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 2db2 2db2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 2 INC_A_PLUS_B val_b_adr 07 GP07 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2db3 2db3 seq_en_micro 0 seq_random 02 ? typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2db4 2db4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2db5 2db5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 06 GP06 2db6 2db6 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2db7 2db7 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 2d Load_ibuff+? typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2db8 2db8 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dba fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2dba 0x2dba seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2db9 2db9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dba seq_br_type 3 Unconditional Branch seq_branch_adr 2dba 0x2dba seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2dba 2dba fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2dbb 2dbb seq_random 02 ? typ_csa_cntl 3 POP_CSA 2dbc 2dbc seq_br_type 3 Unconditional Branch; Flow J 0x2d16 seq_branch_adr 2d16 0x2d16 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2dbd 2dbd ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2dbe 2dbe ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP 2dbf 2dbf ioc_fiubs 2 typ ; Flow C 0x2d9a seq_br_type 7 Unconditional Call seq_branch_adr 2d9a 0x2d9a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 2dc0 2dc0 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dcb ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dcb 0x2dcb seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 2dc1 2dc1 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2dc2 2dc2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2dd0 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2dd0 0x2dd0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2dc3 2dc3 seq_br_type 7 Unconditional Call; Flow C 0x2d9a seq_branch_adr 2d9a 0x2d9a 2dc4 2dc4 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dcb ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dcb 0x2dcb seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 2dc5 2dc5 ioc_fiubs 1 val ; Flow J cc=True 0x2dcb seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dcb 0x2dcb seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_rand 9 PASS_A_HIGH 2dc6 2dc6 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dcb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dcb 0x2dcb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2dc7 2dc7 fiu_mem_start 2 start-rd; Flow C 0x336b ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 336b 0x336b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2dc8 2dc8 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2dcc ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dcc 0x2dcc seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 07 GP07 typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dc9 2dc9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2dcd seq_br_type 5 Call True seq_branch_adr 2dcd 0x2dcd seq_cond_sel 67 REFRESH_MACRO_EVENT 2dca 2dca fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dc7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2dc7 0x2dc7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 2dcb 2dcb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2dcc 2dcc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 20 VR07:00 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 2dcd ; -------------------------------------------------------------------------------------- 2dcd ; Comes from: 2dcd ; 2dc9 C True from color 0x2dbd 2dcd ; -------------------------------------------------------------------------------------- 2dcd 2dcd seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2dce 2dce fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dcf 2dcf seq_br_type a Unconditional Return; Flow R 2dd0 2dd0 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2dd1 2dd1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2dc7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2dc7 0x2dc7 typ_b_adr 08 GP08 2dd2 2dd2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2dd3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2dd3 0x2dd3 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 2dd3 2dd3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2dd6 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2dd6 0x2dd6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 2dd4 2dd4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 2dd5 2dd5 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x2dd8 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2dd8 0x2dd8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2dd6 2dd6 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2dd7 2dd7 fiu_fill_mode_src 0 ; Flow J 0x2dd5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2dd5 0x2dd5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2dd8 2dd8 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32c3 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32c3 0x32c3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2dd9 2dd9 <halt> ; Flow R 2dda ; -------------------------------------------------------------------------------------- 2dda ; 0x4500-0x45ff Exit_Subprogram topoffset,>R 2dda ; -------------------------------------------------------------------------------------- 2dda MACRO_Exit_Subprogram_topoffset,>R: 2dda 2dda dispatch_brk_class 6 ; Flow J cc=False 0x2f4a dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2dda fiu_mem_start 9 start_continue_if_true fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4a 0x2f4a seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2ddb 2ddb ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ddc 2ddc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2de0 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2de0 0x2de0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2ddd 2ddd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2de5 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de5 0x2de5 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2dde 2dde ioc_fiubs 2 typ ; Flow J cc=False 0x2de3 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2de3 0x2de3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2ddf 2ddf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER 2de0 2de0 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2de1 2de1 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2de7 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de7 0x2de7 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2de2 2de2 ioc_fiubs 0 fiu ; Flow J 0x2e81 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2de3 2de3 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2de4 2de4 fiu_tivi_src 4 fiu_var; Flow J 0x2e84 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2e84 0x2e84 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR02:19 val_b_adr 39 VR02:19 val_frame 2 2de5 2de5 fiu_load_var 1 hold_var; Flow C 0x2deb fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2deb 0x2deb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2de6 2de6 seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad 2de7 2de7 seq_br_type 7 Unconditional Call; Flow C 0x2deb seq_branch_adr 2deb 0x2deb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2de8 2de8 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2de9 2de9 fiu_load_tar 1 hold_tar; Flow J 0x2dea fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32ad 0x32ad seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2dea 2dea seq_br_type 3 Unconditional Branch; Flow J 0x2e81 seq_branch_adr 2e81 0x2e81 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2deb 2deb ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2dec 2dec fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2ded 2ded fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2df5 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2df5 0x2df5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2dee 2dee seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2def 2def seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2df0 2df0 seq_b_timing 0 Early Condition; Flow J cc=False 0x2df0 seq_br_type 0 Branch False seq_branch_adr 2df0 0x2df0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA val_rand 2 DEC_LOOP_COUNTER 2df1 2df1 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2df2 2df2 ioc_fiubs 2 typ ; Flow C 0x32fc seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 0c TR18:13 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 18 2df3 2df3 ioc_tvbs 5 seq+seq; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2df4 0x2df4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 2df4 2df4 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_c_lit 0 typ_frame 1f 2df5 2df5 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 2df6 2df6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2df7 2df7 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2df8 2df8 ioc_adrbs 2 typ ; Flow J cc=True 0x2df1 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2df1 0x2df1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2df9 2df9 seq_br_type 3 Unconditional Branch; Flow J 0x2df0 seq_branch_adr 2df0 0x2df0 seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 2dfa ; -------------------------------------------------------------------------------------- 2dfa ; 0x00cc Action Pop_Block 2dfa ; -------------------------------------------------------------------------------------- 2dfa MACRO_Action_Pop_Block: 2dfa 2dfa dispatch_brk_class 6 ; Flow J cc=False 0x2f4a dispatch_csa_valid 0 dispatch_ignore 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2dfa fiu_mem_start 9 start_continue_if_true ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4a 0x2f4a seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 2dfb 2dfb ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2dfc 2dfc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2dff fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2dff 0x2dff seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2dfd 2dfd fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 2dfe 2dfe ioc_fiubs 2 typ ; Flow J 0x2ddf seq_br_type 3 Unconditional Branch seq_branch_adr 2ddf 0x2ddf seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2dff 2dff fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2e00 2e00 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2e01 2e01 ioc_fiubs 2 typ ; Flow J 0x2e81 seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? 2e02 ; -------------------------------------------------------------------------------------- 2e02 ; 0x4300-0x43ff Exit_Subprogram From_Utility,>R,topoffset 2e02 ; -------------------------------------------------------------------------------------- 2e02 MACRO_Exit_Subprogram_From_Utility,>R,topoffset: 2e02 2e02 dispatch_brk_class 6 ; Flow C cc=False 0x32ad dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2e02 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e03 2e03 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2e08 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e08 0x2e08 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e04 2e04 ioc_adrbs 3 seq ; Flow J 0x2e05 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2ddf 0x2ddf seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_a_adr 14 ZEROS typ_csa_cntl 1 START_POP_DOWN val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e05 2e05 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e0e fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e0e 0x2e0e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e06 2e06 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2de5 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de5 0x2de5 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2e07 2e07 ioc_fiubs 2 typ ; Flow R cc=True ; Flow J cc=False 0x2de3 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 2de3 0x2de3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? 2e08 2e08 fiu_mem_start 2 start-rd; Flow J 0x2e09 ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2ddf 0x2ddf val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e09 2e09 typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e0a 2e0a fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2e0b 2e0b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2e7d fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7d 0x2e7d seq_random 02 ? typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_b_adr 02 GP02 2e0c 2e0c ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_csa_cntl 1 START_POP_DOWN 2e0d 2e0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e06 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2e06 0x2e06 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_b_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 02 GP02 2e0e 2e0e ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e0f 2e0f fiu_load_var 1 hold_var; Flow J cc=True 0x2de5 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2de5 0x2de5 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 2e10 2e10 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e11 2e11 fiu_tivi_src 2 tar_fiu; Flow J 0x2e81 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 2e12 ; -------------------------------------------------------------------------------------- 2e12 ; 0x4400-0x44ff Exit_Subprogram With_Result,>R,topoffset 2e12 ; -------------------------------------------------------------------------------------- 2e12 MACRO_Exit_Subprogram_With_Result,>R,topoffset: 2e12 2e12 dispatch_brk_class 6 ; Flow J cc=False 0x2f4d dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e12 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4d 0x2f4d seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e13 2e13 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x2f8a fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2f8a 0x2f8a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e14 2e14 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e19 fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e19 0x2e19 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e15 2e15 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e33 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e33 0x2e33 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e16 2e16 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e2d fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e2d 0x2e2d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e17 2e17 ioc_fiubs 2 typ ; Flow J cc=False 0x2e38 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e38 0x2e38 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e18 2e18 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e19 2e19 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e24 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e24 0x2e24 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e1a 2e1a seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e1b 2e1b seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e1c 2e1c seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e1d 2e1d fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e24 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e24 0x2e24 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e1e 2e1e seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e1f 2e1f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2e21 seq_br_type 1 Branch True seq_branch_adr 2e21 0x2e21 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e20 2e20 seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e21 2e21 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e24 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e24 0x2e24 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 03 GP03 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e22 ; -------------------------------------------------------------------------------------- 2e22 ; 0x00ca Action Exit_Nullary_Function,>R 2e22 ; -------------------------------------------------------------------------------------- 2e22 MACRO_Action_Exit_Nullary_Function,>R: 2e22 2e22 dispatch_brk_class 6 ; Flow J cc=False 0x2f4d dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2e22 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4d 0x2f4d seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e23 2e23 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e14 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e14 0x2e14 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_c_adr 3e GP01 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2e24 2e24 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e2a fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e2a 0x2e2a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e25 2e25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e26 2e26 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e27 2e27 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f 2e28 2e28 seq_br_type 7 Unconditional Call; Flow C 0x2deb seq_branch_adr 2deb 0x2deb seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e29 2e29 seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad 2e2a 2e2a fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e2b 2e2b fiu_load_var 1 hold_var; Flow J 0x2e2c fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2de8 0x2de8 seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 2e2c 2e2c seq_br_type 3 Unconditional Branch; Flow J 0x2deb seq_branch_adr 2deb 0x2deb seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e2d 2e2d ioc_fiubs 2 typ ; Flow J cc=False 0x2e2f ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e2f 0x2e2f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e2e 2e2e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e32 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e32 0x2e32 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e2f 2e2f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e30 2e30 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e32 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e32 0x2e32 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 15 ? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e31 2e31 seq_br_type 3 Unconditional Branch; Flow J 0x2e84 seq_branch_adr 2e84 0x2e84 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e32 2e32 seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e33 2e33 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e34 2e34 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e36 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 2e36 0x2e36 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 2e35 2e35 ioc_fiubs 2 typ ; Flow J 0x2e81 seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e36 2e36 ioc_fiubs 2 typ ; Flow C 0x2e81 seq_br_type 7 Unconditional Call seq_branch_adr 2e81 0x2e81 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e37 2e37 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e32 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e32 0x2e32 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e38 2e38 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e39 2e39 seq_br_type 3 Unconditional Branch; Flow J 0x2e84 seq_branch_adr 2e84 0x2e84 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 03 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e3a ; -------------------------------------------------------------------------------------- 2e3a ; 0x00cb Action Pop_Block_With_Result 2e3a ; -------------------------------------------------------------------------------------- 2e3a MACRO_Action_Pop_Block_With_Result: 2e3a 2e3a dispatch_brk_class 6 ; Flow J cc=False 0x2f4d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2e3a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f4d 0x2f4d seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 2b ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e3b 2e3b seq_random 14 Load_save_offset+? typ_c_adr 3e GP01 val_c_adr 3c GP03 2e3c 2e3c fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e3d 2e3d fiu_mem_start 4 continue; Flow J cc=True 0x2e3e ; Flow J cc=#0x0 0x2e3e ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2e3e 0x2e3e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 62 ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e3e 2e3e fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e46 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e46 0x2e46 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e3f 2e3f seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e40 2e40 seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e41 2e41 seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e42 2e42 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e46 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e46 0x2e46 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e43 2e43 seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e44 2e44 seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e45 2e45 seq_br_type 3 Unconditional Branch; Flow J 0x2e4d seq_branch_adr 2e4d 0x2e4d 2e46 2e46 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e50 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e50 0x2e50 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e47 2e47 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e4a fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e4a 0x2e4a seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e48 2e48 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e49 2e49 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e4a 2e4a ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e4b 2e4b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e4c 0x2e4c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e4c 2e4c seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e4d 2e4d ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2e4e 2e4e seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 2e4f 2e4f seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 seq_int_reads 0 TYP VAL BUS seq_random 4f ? typ_b_adr 05 GP05 val_b_adr 05 GP05 2e50 2e50 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e51 2e51 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e4a ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2e4a 0x2e4a seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e52 2e52 ioc_fiubs 2 typ ; Flow J 0x2e81 seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e53 2e53 <halt> ; Flow R 2e54 ; -------------------------------------------------------------------------------------- 2e54 ; 0x4200-0x42ff Exit_Subprogram From_Utility,With_Result,>R,topoffset 2e54 ; -------------------------------------------------------------------------------------- 2e54 MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset: 2e54 2e54 dispatch_brk_class 6 ; Flow C cc=False 0x32ad dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e54 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e55 2e55 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2f8c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2f8c 0x2f8c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame b typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e56 2e56 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2e78 fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e78 0x2e78 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2e57 2e57 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e59 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e59 0x2e59 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e58 2e58 seq_br_type 3 Unconditional Branch; Flow J 0x2e24 seq_branch_adr 2e24 0x2e24 seq_en_micro 0 2e59 ; -------------------------------------------------------------------------------------- 2e59 ; Comes from: 2e59 ; 2e57 C #0x0 from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2e59 ; -------------------------------------------------------------------------------------- 2e59 2e59 ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e61 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e61 0x2e61 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e5a 2e5a seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e5b 2e5b ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e66 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e66 0x2e66 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e5c 2e5c seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e5d 2e5d ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e61 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e61 0x2e61 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e5e 2e5e seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e5f 2e5f seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e60 2e60 seq_br_type 3 Unconditional Branch; Flow J 0x2e86 seq_branch_adr 2e86 0x2e86 2e61 2e61 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e63 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e63 0x2e63 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e62 2e62 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e17 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e17 0x2e17 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e63 2e63 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e64 2e64 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 2e65 2e65 seq_br_type 3 Unconditional Branch; Flow J 0x2e81 seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2e66 2e66 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e6c fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e6c 0x2e6c seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e67 2e67 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_latch 1 seq_random 57 Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e68 2e68 ioc_fiubs 2 typ ; Flow J cc=False 0x2e74 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e74 0x2e74 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e69 2e69 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2e6a 0x2e6a seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 2e6a 2e6a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2e6b 0x2e6b seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2e6b 2e6b seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e6c 2e6c ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e6d 2e6d ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e6e 2e6e fiu_load_var 1 hold_var; Flow J cc=True 0x2e70 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e70 0x2e70 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS 2e6f 2e6f seq_br_type 3 Unconditional Branch; Flow J 0x2e81 seq_branch_adr 2e81 0x2e81 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e70 2e70 ioc_tvbs 1 typ+fiu; Flow J 0x2e81 seq_br_type 3 Unconditional Branch seq_branch_adr 2e81 0x2e81 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2e71 2e71 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 2e72 2e72 ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e73 2e73 seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad 2e74 2e74 seq_br_type 2 Push (branch address); Flow J 0x2e75 seq_branch_adr 2e71 0x2e71 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2e75 2e75 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e77 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e77 0x2e77 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e76 2e76 seq_br_type 3 Unconditional Branch; Flow J 0x2e84 seq_branch_adr 2e84 0x2e84 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e77 2e77 fiu_tivi_src 2 tar_fiu; Flow J 0x2e84 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e84 0x2e84 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2e78 2e78 fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e79 2e79 typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 2e7a 2e7a fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2e7b 2e7b fiu_load_var 1 hold_var; Flow C cc=False 0x2e7d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7d 0x2e7d seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2e7c 2e7c fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e57 fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e57 0x2e57 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e7d ; -------------------------------------------------------------------------------------- 2e7d ; Comes from: 2e7d ; 2e0b C False from color 0x0000 2e7d ; 2e7b C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2e7d ; 2f08 C False from color 0x2f04 2e7d ; -------------------------------------------------------------------------------------- 2e7d 2e7d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e7e 2e7e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e7f 2e7f fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2e80 2e80 ioc_load_wdr 0 ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_b_adr 03 GP03 2e81 2e81 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e82 2e82 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e83 2e83 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e84 2e84 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e85 0x2e85 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2e85 2e85 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2e86 2e86 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2e87 2e87 ioc_adrbs 2 typ ; Flow J 0x2e88 seq_br_type 2 Push (branch address) seq_branch_adr 32a6 0x32a6 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2e88 2e88 ioc_fiubs 2 typ ; Flow J 0x2f96 seq_br_type 3 Unconditional Branch seq_branch_adr 2f96 0x2f96 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 2e89 2e89 <halt> ; Flow R 2e8a ; -------------------------------------------------------------------------------------- 2e8a ; 0x0100 Execute Exception,Raise,>R 2e8a ; -------------------------------------------------------------------------------------- 2e8a MACRO_Execute_Exception,Raise,>R: 2e8a 2e8a dispatch_brk_class 8 ; Flow J cc=False 0x2ebe dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e8a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2ebe 0x2ebe seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e8b 2e8b fiu_mem_start 2 start-rd; Flow J cc=True 0x2eaa ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2eaa 0x2eaa seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2e8c 2e8c fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e8d 2e8d ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e8e 2e8e fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2ea2 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea2 0x2ea2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e8f 2e8f fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2e90 2e90 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e91 2e91 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ea7 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea7 0x2ea7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e92 2e92 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2ea0 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea0 0x2ea0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2e93 2e93 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2e94 2e94 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ea0 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea0 0x2ea0 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e95 2e95 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2ea0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ea0 0x2ea0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 2e96 2e96 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2e97 2e97 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e99 ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2e99 0x2e99 seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2e98 2e98 seq_br_type 3 Unconditional Branch; Flow J 0x2e9a seq_branch_adr 2e9a 0x2e9a val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2e99 2e99 seq_br_type 3 Unconditional Branch; Flow J 0x2e9a seq_branch_adr 2e9a 0x2e9a val_a_adr 27 VR05:07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2e9a 2e9a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2e9b 2e9b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 03 GP03 2e9c 2e9c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e9d 2e9d ioc_tvbs 3 fiu+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 2e9e 2e9e fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2e9f 0x2e9f seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e9f 2e9f seq_br_type 3 Unconditional Branch; Flow J 0x2e83 seq_branch_adr 2e83 0x2e83 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 59 ? val_b_adr 04 GP04 2ea0 2ea0 seq_br_type 2 Push (branch address); Flow J 0x2ea1 seq_branch_adr 2e98 0x2e98 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ea1 2ea1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2e99 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e99 0x2e99 seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ea2 2ea2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2ea3 2ea3 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ea4 2ea4 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ea5 2ea5 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ea6 2ea6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e91 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2e91 0x2e91 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2ea7 2ea7 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ea8 2ea8 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e90 seq_br_type 1 Branch True seq_branch_adr 2e90 0x2e90 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_rand 0 NO_OP 2ea9 2ea9 seq_br_type 3 Unconditional Branch; Flow J 0x2ea0 seq_branch_adr 2ea0 0x2ea0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eaa 2eaa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 2eab 2eab fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 01 GP01 2eac 2eac fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2ead fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2ead 0x2ead seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 03 ? typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ead ; -------------------------------------------------------------------------------------- 2ead ; Comes from: 2ead ; 2eac C #0x0 from color 0x0000 2ead ; -------------------------------------------------------------------------------------- 2ead 2ead fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2eb1 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb1 0x2eb1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2eae 2eae fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2eb6 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2eaf 2eaf ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2ebb seq_br_type 3 Unconditional Branch seq_branch_adr 2ebb 0x2ebb seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2eb0 2eb0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eb1 2eb1 fiu_load_var 1 hold_var; Flow C cc=True 0x2eb5 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2eb5 0x2eb5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 28 TR12:08 typ_frame 12 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 2eb2 2eb2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2eb4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2eb4 0x2eb4 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eb3 2eb3 ioc_fiubs 0 fiu ; Flow C 0x3915 seq_br_type 7 Unconditional Call seq_branch_adr 3915 0x3915 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 26 VR05:06 val_frame 5 2eb4 2eb4 ioc_fiubs 0 fiu ; Flow C 0x3915 seq_br_type 7 Unconditional Call seq_branch_adr 3915 0x3915 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 27 VR05:07 val_frame 5 2eb5 2eb5 seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 9 2eb6 2eb6 fiu_mem_start 4 continue typ_a_adr 31 TR08:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR 2eb7 2eb7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eb8 2eb8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2eba seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2eba 0x2eba typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2eb9 2eb9 seq_br_type 7 Unconditional Call; Flow C 0x3959 seq_branch_adr 3959 0x3959 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 26 VR05:06 val_frame 5 2eba 2eba seq_br_type 7 Unconditional Call; Flow C 0x3959 seq_branch_adr 3959 0x3959 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 27 VR05:07 val_frame 5 2ebb 2ebb seq_b_timing 1 Latch Condition; Flow J cc=True 0x2ebd seq_br_type 1 Branch True seq_branch_adr 2ebd 0x2ebd 2ebc 2ebc seq_br_type 3 Unconditional Branch; Flow J 0x2e85 seq_branch_adr 2e85 0x2e85 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 26 VR05:06 val_frame 5 2ebd 2ebd seq_br_type 3 Unconditional Branch; Flow J 0x2e85 seq_branch_adr 2e85 0x2e85 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 27 VR05:07 val_frame 5 2ebe 2ebe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ee5 seq_br_type 5 Call True seq_branch_adr 2ee5 0x2ee5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ebf 2ebf ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2eaa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2eaa 0x2eaa seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2ec0 2ec0 fiu_load_var 1 hold_var; Flow J cc=True 0x2f01 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f01 0x2f01 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2ec1 2ec1 ioc_load_wdr 0 ; Flow J cc=False 0x2f4a ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2f4a 0x2f4a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2ec2 2ec2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f60 seq_br_type 1 Branch True seq_branch_adr 2f60 0x2f60 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 38 GP07 typ_frame 2 2ec3 2ec3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2ec4 2ec4 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR09:11 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 9 2ec5 2ec5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2ec6 2ec6 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 2ec7 2ec7 fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 38 GP07 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ec8 2ec8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2ec9 2ec9 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2edb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2edb 0x2edb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2eca 2eca fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ecb 2ecb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ecc 2ecc fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x2ee0 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2ee0 0x2ee0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ecd 2ecd fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2ed8 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed8 0x2ed8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2ece 2ece seq_b_timing 1 Latch Condition; Flow J cc=True 0x2ed8 seq_br_type 1 Branch True seq_branch_adr 2ed8 0x2ed8 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2ecf 2ecf fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ed9 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed9 0x2ed9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ed0 2ed0 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2ed9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ed9 0x2ed9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2ed1 2ed1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 30 TR09:10 typ_csa_cntl 1 START_POP_DOWN typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ed2 2ed2 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 37 GP08 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 07 GP07 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2ed3 2ed3 fiu_mem_start 2 start-rd; Flow J cc=True 0x2ed5 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ed5 0x2ed5 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2ed4 2ed4 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2ed6 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2ed6 0x2ed6 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 26 VR05:06 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2ed5 2ed5 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2ed6 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2ed6 0x2ed6 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 27 VR05:07 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2ed6 2ed6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 2ed7 2ed7 ioc_adrbs 1 val ; Flow J 0x2f0a ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f0a 0x2f0a seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 2ed8 2ed8 seq_br_type 3 Unconditional Branch; Flow J 0x2ed9 seq_branch_adr 2ed9 0x2ed9 typ_c_adr 1d TR02:02 typ_frame 2 2ed9 2ed9 fiu_load_var 1 hold_var; Flow J 0x2eda fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2ed4 0x2ed4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 30 TR09:10 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2eda 2eda fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2ed5 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ed5 0x2ed5 seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2edb 2edb fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2edc 2edc ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2edd 2edd fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ede 2ede fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2edf 2edf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ecc fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2ecc 0x2ecc val_b_adr 22 VR02:02 val_frame 2 2ee0 2ee0 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2ee1 2ee1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ee3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 2ee3 0x2ee3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_b_adr 22 VR02:02 val_frame 2 2ee2 2ee2 fiu_mem_start 2 start-rd; Flow J 0x2ecb seq_br_type 3 Unconditional Branch seq_branch_adr 2ecb 0x2ecb seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 2ee3 2ee3 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 2ee4 2ee4 ioc_tvbs 1 typ+fiu; Flow J 0x2ed9 seq_br_type 3 Unconditional Branch seq_branch_adr 2ed9 0x2ed9 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_c_adr 1d TR02:02 typ_frame 2 2ee5 ; -------------------------------------------------------------------------------------- 2ee5 ; Comes from: 2ee5 ; 2ebe C True from color 0x0000 2ee5 ; -------------------------------------------------------------------------------------- 2ee5 2ee5 fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2ee6 2ee6 fiu_mem_start 2 start-rd; Flow C 0x3345 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2ee7 2ee7 fiu_load_var 1 hold_var; Flow J cc=True 0x2ee8 ; Flow J cc=#0x0 0x2ee9 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 2ee9 0x2ee9 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2ee8 2ee8 fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ee9 2ee9 seq_br_type 3 Unconditional Branch; Flow J 0x2ef1 seq_branch_adr 2ef1 0x2ef1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2eea 2eea seq_br_type 3 Unconditional Branch; Flow J 0x2ef1 seq_branch_adr 2ef1 0x2ef1 typ_a_adr 14 ZEROS typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2eeb 2eeb seq_br_type 3 Unconditional Branch; Flow J 0x2eed seq_branch_adr 2eed 0x2eed seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2eec 2eec seq_br_type 3 Unconditional Branch; Flow J 0x2eed seq_branch_adr 2eed 0x2eed seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2eed 2eed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 2eee 2eee seq_b_timing 1 Latch Condition; Flow J cc=True 0x2ee8 seq_br_type 1 Branch True seq_branch_adr 2ee8 0x2ee8 2eef 2eef seq_br_type 2 Push (branch address); Flow J 0x2ef0 seq_branch_adr 2ee7 0x2ee7 2ef0 2ef0 fiu_load_oreg 1 hold_oreg; Flow J 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 335a 0x335a seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 2ef1 2ef1 fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2ef2 2ef2 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f00 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f00 0x2f00 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2ef3 2ef3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR09:13 val_frame 9 2ef4 2ef4 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2f00 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f00 0x2f00 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 2ef5 2ef5 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2f00 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f00 0x2f00 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR05:01 val_frame 5 2ef6 2ef6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f00 seq_br_type 1 Branch True seq_branch_adr 2f00 0x2f00 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR08:05 typ_frame 8 2ef7 2ef7 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x2efd ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2efd 0x2efd typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2ef8 2ef8 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2ef9 2ef9 seq_br_type 2 Push (branch address); Flow J 0x2efa seq_branch_adr 0282 0x0282 2efa 2efa fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 5 val_rand a PASS_B_HIGH 2efb 2efb ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 2e TR02:0e typ_frame 2 2efc 2efc seq_br_type 3 Unconditional Branch; Flow J 0x2eed seq_branch_adr 2eed 0x2eed seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2efd 2efd fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 2f TR11:0f typ_frame 11 2efe 2efe fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2eff 2eff ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f00 2f00 seq_br_type 3 Unconditional Branch; Flow J 0x2eed seq_branch_adr 2eed 0x2eed seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f01 2f01 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2f04 seq_br_type 5 Call True seq_branch_adr 2f04 0x2f04 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 2f02 2f02 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL 2f03 2f03 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2e8d fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2e8d 0x2e8d seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f04 ; -------------------------------------------------------------------------------------- 2f04 ; Comes from: 2f04 ; 2f01 C True from color 0x0000 2f04 ; -------------------------------------------------------------------------------------- 2f04 2f04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f05 2f05 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f06 2f06 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f07 2f07 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2f08 2f08 fiu_load_var 1 hold_var; Flow C cc=False 0x2e7d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2e7d 0x2e7d seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2f09 2f09 seq_br_type a Unconditional Return; Flow R 2f0a 2f0a ioc_fiubs 1 val ; Flow J cc=True 0x2f0c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f0c 0x2f0c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f0b 2f0b fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2f0c 2f0c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f0d 2f0d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 36 TR02:16 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 2f0e 2f0e fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2f3e fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f3e 0x2f3e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f0f 2f0f fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3e GP01 2f10 2f10 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f11 fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 2 Push (branch address) seq_branch_adr 2e83 0x2e83 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2f11 2f11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f35 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f35 0x2f35 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f12 2f12 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2f13 2f13 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1f typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 2f14 2f14 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2f15 2f15 ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 2f16 2f16 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2f47 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f47 0x2f47 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f17 2f17 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2f29 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f29 0x2f29 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f18 2f18 fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f19 2f19 ioc_adrbs 1 val ; Flow J cc=False 0x2f29 seq_br_type 0 Branch False seq_branch_adr 2f29 0x2f29 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f1a 2f1a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f29 fiu_load_mdr 1 hold_mdr fiu_offs_lit 44 fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f29 0x2f29 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f1b 2f1b fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x32fc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 01 GP01 2f1c 2f1c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f1d 2f1d fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2f2e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f2e 0x2f2e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f1e 2f1e ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f1f 2f1f fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f20 2f20 seq_br_type 1 Branch True; Flow J cc=True 0x2f43 seq_branch_adr 2f43 0x2f43 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 2f21 2f21 <default> 2f22 2f22 seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2f23 2f23 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 2f24 2f24 ioc_adrbs 2 typ ; Flow C 0x6b7 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f25 2f25 fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f26 2f26 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2f27 0x2f27 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f27 2f27 seq_br_type 7 Unconditional Call; Flow C 0x33ba seq_branch_adr 33ba 0x33ba 2f28 2f28 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f29 2f29 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f2a 2f2a fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 01 GP01 2f2b 2f2b ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f2c 2f2c fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2f1e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2f1e 0x2f1e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f2d 2f2d seq_br_type 3 Unconditional Branch; Flow J 0x2f2e seq_branch_adr 2f2e 0x2f2e 2f2e 2f2e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 20 TR08:00 typ_c_adr 39 GP06 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 39 GP06 val_frame 4 val_rand 9 PASS_A_HIGH 2f2f 2f2f ioc_load_wdr 0 ; Flow J cc=True 0x2f32 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f32 0x2f32 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2f30 2f30 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f34 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f34 0x2f34 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 37 TR06:17 typ_frame 6 val_a_adr 2e VR06:0e val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f31 2f31 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f34 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f34 0x2f34 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f32 2f32 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f34 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f34 0x2f34 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 23 VR06:03 val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f33 2f33 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f34 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f34 0x2f34 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f34 2f34 ioc_fiubs 1 val ; Flow J 0x2f1f ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f1f 0x2f1f typ_b_adr 06 GP06 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f35 2f35 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 01 GP01 typ_c_adr 30 GP0f 2f36 2f36 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2f3a ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f3a 0x2f3a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 2f37 2f37 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f38 2f38 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2f43 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2f43 0x2f43 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f39 2f39 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f3a 2f3a fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 2f3b 2f3b fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f3c 2f3c fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f3d 2f3d ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f3e 2f3e fiu_load_var 1 hold_var fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f3f 2f3f fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2f40 0x2f40 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2f40 2f40 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 2f41 2f41 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f42 2f42 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f0f fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f0f 0x2f0f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f43 ; -------------------------------------------------------------------------------------- 2f43 ; Comes from: 2f43 ; 2f38 C True from color 0x2ec7 2f43 ; -------------------------------------------------------------------------------------- 2f43 2f43 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 11 val_rand a PASS_B_HIGH 2f44 2f44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 2f45 2f45 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f46 2f46 ioc_load_wdr 0 ; Flow J 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2f47 2f47 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f48 2f48 fiu_mem_start 2 start-rd; Flow J cc=True 0x2f15 seq_br_type 1 Branch True seq_branch_adr 2f15 0x2f15 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f49 2f49 ioc_fiubs 2 typ ; Flow J 0x2f29 seq_br_type 3 Unconditional Branch seq_branch_adr 2f29 0x2f29 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f4a 2f4a fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2f4b fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f64 0x2f64 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f4b 2f4b fiu_mem_start 2 start-rd; Flow J cc=True 0x3369 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3369 0x3369 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f4c 2f4c seq_br_type 7 Unconditional Call; Flow C 0x32ad seq_branch_adr 32ad 0x32ad 2f4d 2f4d fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2f4e fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f64 0x2f64 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f4e 2f4e fiu_mem_start 2 start-rd; Flow J cc=True 0x3369 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3369 0x3369 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f4f 2f4f seq_br_type 4 Call False; Flow C cc=False 0x32ad seq_branch_adr 32ad 0x32ad seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2f50 2f50 fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f51 2f51 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT 2f52 2f52 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2f64 seq_br_type 0 Branch False seq_branch_adr 2f64 0x2f64 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 10 TOP 2f53 2f53 seq_br_type 3 Unconditional Branch; Flow J 0x2f64 seq_branch_adr 2f64 0x2f64 2f54 2f54 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f55 2f55 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f5d seq_br_type 1 Branch True seq_branch_adr 2f5d 0x2f5d seq_cond_sel 67 REFRESH_MACRO_EVENT 2f56 2f56 fiu_mem_start 2 start-rd; Flow J cc=True 0x2f5b ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f5b 0x2f5b seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_frame 9 val_rand 9 PASS_A_HIGH 2f57 2f57 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f58 2f58 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand 9 PASS_A_HIGH 2f59 2f59 ioc_fiubs 0 fiu ; Flow C cc=True 0x32a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 2f5a 2f5a seq_b_timing 1 Latch Condition; Flow J cc=False 0x2f54 seq_br_type 0 Branch False seq_branch_adr 2f54 0x2f54 2f5b 2f5b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2f5c 2f5c seq_br_type 3 Unconditional Branch; Flow J 0x2f64 seq_branch_adr 2f64 0x2f64 2f5d 2f5d seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f5e 2f5e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2f5f 2f5f seq_br_type 3 Unconditional Branch; Flow J 0x2f56 seq_branch_adr 2f56 0x2f56 2f60 2f60 seq_br_type 2 Push (branch address); Flow J 0x2f61 seq_branch_adr 2f64 0x2f64 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 2f61 2f61 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3369 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3369 0x3369 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f62 2f62 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2f63 2f63 fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f64 2f64 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2f69 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f69 0x2f69 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2f65 2f65 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 2f66 2f66 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2f67 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 2f63 0x2f63 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 2f67 2f67 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f68 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f68 2f68 ioc_tvbs 1 typ+fiu; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f69 2f69 fiu_mem_start 2 start-rd; Flow C 0x3345 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f6a 2f6a fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2f70 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2f70 0x2f70 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f6b 2f6b ioc_fiubs 2 typ ; Flow J 0x2f6c seq_br_type 3 Unconditional Branch seq_branch_adr 2f6c 0x2f6c val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f6c 2f6c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f79 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f79 0x2f79 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 2f6d 2f6d fiu_load_oreg 1 hold_oreg; Flow C 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335a 0x335a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 2f6e 2f6e fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2f70 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2f70 0x2f70 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f6f 2f6f ioc_fiubs 2 typ ; Flow J 0x2f6c seq_br_type 3 Unconditional Branch seq_branch_adr 2f6c 0x2f6c val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f70 2f70 seq_br_type 3 Unconditional Branch; Flow J 0x2f76 seq_branch_adr 2f76 0x2f76 2f71 2f71 seq_br_type 3 Unconditional Branch; Flow J 0x2f76 seq_branch_adr 2f76 0x2f76 2f72 2f72 fiu_mem_start 2 start-rd; Flow J 0x3455 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3455 0x3455 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2f73 2f73 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2f7c fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2f7c 0x2f7c seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2f74 2f74 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 2f75 2f75 seq_br_type 3 Unconditional Branch; Flow J 0x2f7c seq_branch_adr 2f7c 0x2f7c 2f76 2f76 seq_br_type 2 Push (branch address); Flow J 0x2f77 seq_branch_adr 2f6c 0x2f6c 2f77 2f77 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 2f78 2f78 ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f79 2f79 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2f7a 2f7a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2f7b 2f7b ioc_load_wdr 0 ; Flow J 0x2e85 seq_br_type 3 Unconditional Branch seq_branch_adr 2e85 0x2e85 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2f7c 2f7c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f7d 2f7d ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f7e 2f7e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f7f 2f7f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2f80 2f80 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f89 seq_br_type 1 Branch True seq_branch_adr 2f89 0x2f89 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 2f81 2f81 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 2f82 2f82 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2f84 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2f84 0x2f84 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2f83 2f83 fiu_fill_mode_src 0 ; Flow J 0x2f86 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f86 0x2f86 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f84 2f84 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2f85 2f85 fiu_fill_mode_src 0 ; Flow J 0x2f86 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f86 0x2f86 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f86 2f86 ioc_fiubs 2 typ ; Flow J 0x2f87 seq_br_type 2 Push (branch address) seq_branch_adr 2f80 0x2f80 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f87 2f87 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 2f88 2f88 ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f89 2f89 seq_br_type 3 Unconditional Branch; Flow J 0x2f6c seq_branch_adr 2f6c 0x2f6c typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2f8a 2f8a fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2f8b 2f8b fiu_mem_start 5 start_rd_if_true; Flow R cc=True ; Flow J cc=False 0x32ad ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 32ad 0x32ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f8c ; -------------------------------------------------------------------------------------- 2f8c ; Comes from: 2f8c ; 2e55 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2f8c ; -------------------------------------------------------------------------------------- 2f8c 2f8c fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2f8d 2f8d seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32ad seq_br_type 8 Return True seq_branch_adr 32ad 0x32ad seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 2f8e ; -------------------------------------------------------------------------------------- 2f8e ; 0x4100-0x41ff End_Rendezvous >R,parmcnt 2f8e ; -------------------------------------------------------------------------------------- 2f8e MACRO_End_Rendezvous_>R,parmcnt: 2f8e 2f8e dispatch_brk_class 5 ; Flow C 0x337d dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 2f8e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d seq_int_reads 5 RESOLVE RAM typ_a_adr 2f TR05:0f typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 2e VR05:0e val_frame 5 2f8f 2f8f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2f90 2f90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f60 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f60 0x2f60 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 2f91 2f91 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x2f94 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f94 0x2f94 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2f92 2f92 ioc_fiubs 2 typ ; Flow C cc=False 0x32ad ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 2f93 2f93 ioc_adrbs 1 val ; Flow J 0x3730 seq_br_type 3 Unconditional Branch seq_branch_adr 3730 0x3730 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f94 2f94 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x32ad seq_br_type 4 Call False seq_branch_adr 32ad 0x32ad seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2f95 2f95 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2f96 2f96 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? 2f97 2f97 seq_random 6a ? 2f98 2f98 seq_lex_adr 3 seq_random 6a ? 2f99 2f99 seq_br_type a Unconditional Return; Flow R seq_lex_adr 2 seq_random 0b ? 2f9a ; -------------------------------------------------------------------------------------- 2f9a ; 0x027f Execute Discrete,Equal 2f9a ; -------------------------------------------------------------------------------------- 2f9a MACRO_Execute_Discrete,Equal: 2f9a 2f9a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2f9a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2f9b 2f9b <halt> ; Flow R 2f9c ; -------------------------------------------------------------------------------------- 2f9c ; 0x0f00-0x0fff Execute_Immediate Equal,uimmediate 2f9c ; -------------------------------------------------------------------------------------- 2f9c MACRO_Execute_Immediate_Equal,uimmediate: 2f9c 2f9c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2f9c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2f9d 2f9d <halt> ; Flow R 2f9e ; -------------------------------------------------------------------------------------- 2f9e ; 0x027e Execute Discrete,Not_Equal 2f9e ; -------------------------------------------------------------------------------------- 2f9e MACRO_Execute_Discrete,Not_Equal: 2f9e 2f9e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2f9e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2f9f 2f9f <halt> ; Flow R 2fa0 ; -------------------------------------------------------------------------------------- 2fa0 ; 0x0e00-0x0eff Execute_Immediate Not_Equal,uimmediate 2fa0 ; -------------------------------------------------------------------------------------- 2fa0 MACRO_Execute_Immediate_Not_Equal,uimmediate: 2fa0 2fa0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fa0 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fa1 2fa1 <halt> ; Flow R 2fa2 ; -------------------------------------------------------------------------------------- 2fa2 ; 0x027d Execute Discrete,Greater 2fa2 ; -------------------------------------------------------------------------------------- 2fa2 MACRO_Execute_Discrete,Greater: 2fa2 2fa2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa2 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa3 2fa3 <halt> ; Flow R 2fa4 ; -------------------------------------------------------------------------------------- 2fa4 ; 0x027c Execute Discrete,Less 2fa4 ; -------------------------------------------------------------------------------------- 2fa4 MACRO_Execute_Discrete,Less: 2fa4 2fa4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa4 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa5 2fa5 <halt> ; Flow R 2fa6 ; -------------------------------------------------------------------------------------- 2fa6 ; 0x0d00-0x0dff Execute_Immediate Less,uimmediate 2fa6 ; -------------------------------------------------------------------------------------- 2fa6 MACRO_Execute_Immediate_Less,uimmediate: 2fa6 2fa6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fa6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fa7 2fa7 <halt> ; Flow R 2fa8 ; -------------------------------------------------------------------------------------- 2fa8 ; 0x027b Execute Discrete,Greater_Equal 2fa8 ; -------------------------------------------------------------------------------------- 2fa8 MACRO_Execute_Discrete,Greater_Equal: 2fa8 2fa8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fa8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fa9 2fa9 <halt> ; Flow R 2faa ; -------------------------------------------------------------------------------------- 2faa ; 0x0c00-0x0cff Execute_Immediate Greater_Equal,uimmediate 2faa ; -------------------------------------------------------------------------------------- 2faa MACRO_Execute_Immediate_Greater_Equal,uimmediate: 2faa 2faa dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 2faa ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fab 2fab fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fac ; -------------------------------------------------------------------------------------- 2fac ; 0x027a Execute Discrete,Less_Equal 2fac ; -------------------------------------------------------------------------------------- 2fac MACRO_Execute_Discrete,Less_Equal: 2fac 2fac dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fac fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fad 2fad <halt> ; Flow R 2fae ; -------------------------------------------------------------------------------------- 2fae ; 0x0279 Execute Discrete,And 2fae ; -------------------------------------------------------------------------------------- 2fae MACRO_Execute_Discrete,And: 2fae 2fae dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fae fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2faf 2faf <halt> ; Flow R 2fb0 ; -------------------------------------------------------------------------------------- 2fb0 ; 0x0278 Execute Discrete,Or 2fb0 ; -------------------------------------------------------------------------------------- 2fb0 MACRO_Execute_Discrete,Or: 2fb0 2fb0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fb0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fb1 2fb1 <halt> ; Flow R 2fb2 ; -------------------------------------------------------------------------------------- 2fb2 ; 0x0277 Execute Discrete,Xor 2fb2 ; -------------------------------------------------------------------------------------- 2fb2 MACRO_Execute_Discrete,Xor: 2fb2 2fb2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fb2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fb3 2fb3 <halt> ; Flow R 2fb4 ; -------------------------------------------------------------------------------------- 2fb4 ; 0x0276 Execute Discrete,Complement 2fb4 ; -------------------------------------------------------------------------------------- 2fb4 MACRO_Execute_Discrete,Complement: 2fb4 2fb4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fb4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 10 NOT_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fb5 2fb5 <halt> ; Flow R 2fb6 ; -------------------------------------------------------------------------------------- 2fb6 ; 0x0275 Execute Discrete,Unary_Minus 2fb6 ; -------------------------------------------------------------------------------------- 2fb6 MACRO_Execute_Discrete,Unary_Minus: 2fb6 2fb6 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fb6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fb7 0x2fb7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fb7 2fb7 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2fb8 ; -------------------------------------------------------------------------------------- 2fb8 ; 0x0274 Execute Discrete,Absolute_Value 2fb8 ; -------------------------------------------------------------------------------------- 2fb8 MACRO_Execute_Discrete,Absolute_Value: 2fb8 2fb8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fb8 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 2fb9 2fb9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fb7 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fb7 0x2fb7 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fba ; -------------------------------------------------------------------------------------- 2fba ; 0x0273 Execute Discrete,Plus 2fba ; -------------------------------------------------------------------------------------- 2fba MACRO_Execute_Discrete,Plus: 2fba 2fba dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fba fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fbb 0x2fbb seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fbb 2fbb seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2fbc ; -------------------------------------------------------------------------------------- 2fbc ; 0x0a00-0x0a7f Execute_Immediate Plus,s8 2fbc ; -------------------------------------------------------------------------------------- 2fbc MACRO_Execute_Immediate_Plus,s8: 2fbc 2fbc dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2fbc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fbd 0x2fbd seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fbd 2fbd seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2fbe ; -------------------------------------------------------------------------------------- 2fbe ; 0x0272 Execute Discrete,Minus 2fbe ; -------------------------------------------------------------------------------------- 2fbe MACRO_Execute_Discrete,Minus: 2fbe 2fbe dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fbe fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fbf 0x2fbf seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fbf 2fbf seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 ; 0x0a80-0x0aff Execute_Immediate Plus,s8 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 MACRO_Execute_Immediate_Plus,s8: 2fc0 2fc0 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2fc0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fc1 0x2fc1 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 30 VR02:10 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fc1 2fc1 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 2fc2 ; -------------------------------------------------------------------------------------- 2fc2 ; 0x026c Execute Discrete,Minimum 2fc2 ; -------------------------------------------------------------------------------------- 2fc2 MACRO_Execute_Discrete,Minimum: 2fc2 2fc2 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fc2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2fc3 2fc3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fc4 ; -------------------------------------------------------------------------------------- 2fc4 ; 0x026b Execute Discrete,Maximum 2fc4 ; -------------------------------------------------------------------------------------- 2fc4 MACRO_Execute_Discrete,Maximum: 2fc4 2fc4 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fc4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2fc5 2fc5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fc6 ; -------------------------------------------------------------------------------------- 2fc6 ; 0x026a Execute Discrete,First 2fc6 ; -------------------------------------------------------------------------------------- 2fc6 MACRO_Execute_Discrete,First: 2fc6 2fc6 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fc6 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fc7 2fc7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fc8 ; -------------------------------------------------------------------------------------- 2fc8 ; 0x0269 Execute Discrete,Last 2fc8 ; -------------------------------------------------------------------------------------- 2fc8 MACRO_Execute_Discrete,Last: 2fc8 2fc8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fc8 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fc9 2fc9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fca ; -------------------------------------------------------------------------------------- 2fca ; 0x0268 Execute Discrete,Successor 2fca ; -------------------------------------------------------------------------------------- 2fca MACRO_Execute_Discrete,Successor: 2fca 2fca dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fca fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2fcb 2fcb ioc_fiubs 1 val ; Flow C cc=True 0x326c ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fcc 2fcc fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fcd 0x2fcd seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fcd 2fcd fiu_mem_start 2 start-rd; Flow J 0x2fce ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2fce 0x2fce seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2fce 2fce <default> 2fcf 2fcf fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2fd0 2fd0 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2fd1 2fd1 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c seq_en_micro 0 seq_random 02 ? 2fd2 ; -------------------------------------------------------------------------------------- 2fd2 ; 0x0267 Execute Discrete,Predecessor 2fd2 ; -------------------------------------------------------------------------------------- 2fd2 MACRO_Execute_Discrete,Predecessor: 2fd2 2fd2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fd2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2fd3 2fd3 ioc_fiubs 1 val ; Flow C cc=True 0x326c ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fd4 2fd4 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fd5 0x2fd5 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fd5 2fd5 fiu_mem_start 2 start-rd; Flow J 0x2fce ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2fce 0x2fce seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2fd6 ; -------------------------------------------------------------------------------------- 2fd6 ; 0x0b00-0x0bff Execute_Immediate Case_Compare,uimmediate 2fd6 ; -------------------------------------------------------------------------------------- 2fd6 MACRO_Execute_Immediate_Case_Compare,uimmediate: 2fd6 2fd6 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_uadr 2fd6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fd7 2fd7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 ; 0x0249 Execute Discrete,Case_In_Range 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 MACRO_Execute_Discrete,Case_In_Range: 2fd8 2fd8 dispatch_brk_class 8 ; Flow J cc=True 0x2fd7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fd8 seq_br_type 1 Branch True seq_branch_adr 2fd7 0x2fd7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fd9 2fd9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fda ; -------------------------------------------------------------------------------------- 2fda ; 0x0266 Execute Discrete,Bounds 2fda ; -------------------------------------------------------------------------------------- 2fda MACRO_Execute_Discrete,Bounds: 2fda 2fda dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fda dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fdb 2fdb ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2fdc 2fdc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fdd 2fdd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2fde ; -------------------------------------------------------------------------------------- 2fde ; 0x0265 Execute Discrete,Reverse_Bounds 2fde ; -------------------------------------------------------------------------------------- 2fde MACRO_Execute_Discrete,Reverse_Bounds: 2fde 2fde dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fde dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2fdf 2fdf ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2fdd seq_br_type 3 Unconditional Branch seq_branch_adr 2fdd 0x2fdd seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 ; 0x0264 Execute Discrete,Below_Bound 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 MACRO_Execute_Discrete,Below_Bound: 2fe0 2fe0 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe0 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fe1 0x2fe1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2fe1 2fe1 seq_br_type 3 Unconditional Branch; Flow J 0x2fe3 seq_branch_adr 2fe3 0x2fe3 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 ; 0x0263 Execute Discrete,Above_Bound 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 MACRO_Execute_Discrete,Above_Bound: 2fe2 2fe2 dispatch_brk_class 8 ; Flow R cc=True ; Flow J cc=False 0x2fe1 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe2 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fe1 0x2fe1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2fe3 2fe3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 ; 0x0262 Execute Discrete,In_Range 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 MACRO_Execute_Discrete,In_Range: 2fe4 2fe4 dispatch_brk_class 8 ; Flow J cc=True 0x2fa8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fe4 seq_br_type 1 Branch True seq_branch_adr 2fa8 MACRO_Execute_Discrete,Greater_Equal seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fe5 2fe5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 ; 0x0261 Execute Discrete,Not_In_Range 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 MACRO_Execute_Discrete,Not_In_Range: 2fe6 2fe6 dispatch_brk_class 8 ; Flow J cc=True 0x2fa4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2fe6 seq_br_type 1 Branch True seq_branch_adr 2fa4 MACRO_Execute_Discrete,Less seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 2fe7 2fe7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 ; 0x0260 Execute Discrete,In_Type 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 MACRO_Execute_Discrete,In_Type: 2fe8 2fe8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fe8 dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_frame 2 2fe9 2fe9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2feb fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2feb 0x2feb seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 2fea ; -------------------------------------------------------------------------------------- 2fea ; 0x025f Execute Discrete,Not_In_Type 2fea ; -------------------------------------------------------------------------------------- 2fea MACRO_Execute_Discrete,Not_In_Type: 2fea 2fea dispatch_brk_class 8 ; Flow J 0x2fe9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fea dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2fe9 0x2fe9 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2feb 2feb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2fec ; -------------------------------------------------------------------------------------- 2fec ; 0x025e Execute Discrete,Convert 2fec ; -------------------------------------------------------------------------------------- 2fec MACRO_Execute_Discrete,Convert: 2fec 2fec dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2fec dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 2fed 2fed fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fee 0x2fee seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2fee 2fee fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2fef 2fef fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 2ff0 2ff0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326c seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff1 2ff1 seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 2ff2 ; -------------------------------------------------------------------------------------- 2ff2 ; 0x025d Execute Discrete,Bounds_Check 2ff2 ; -------------------------------------------------------------------------------------- 2ff2 MACRO_Execute_Discrete,Bounds_Check: 2ff2 2ff2 dispatch_brk_class 8 ; Flow J 0x2ff3 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff2 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2ff5 0x2ff5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2ff3 2ff3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ff4 0x2ff4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff4 2ff4 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fd1 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2fd1 0x2fd1 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 2ff5 2ff5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 2ff6 ; -------------------------------------------------------------------------------------- 2ff6 ; 0x025c Execute Discrete,ReverseBounds_Check 2ff6 ; -------------------------------------------------------------------------------------- 2ff6 MACRO_Execute_Discrete,ReverseBounds_Check: 2ff6 2ff6 dispatch_brk_class 8 ; Flow J 0x2ff7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff6 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2ff5 0x2ff5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 2ff7 2ff7 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x2ff4 seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ff4 0x2ff4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 ; 0x025b Execute Discrete,Check_In_Type 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 MACRO_Execute_Discrete,Check_In_Type: 2ff8 2ff8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff8 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 2ff9 2ff9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fee ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fee 0x2fee seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2ffa ; -------------------------------------------------------------------------------------- 2ffa ; 0x0248 Execute Discrete,Check_In_Integer 2ffa ; -------------------------------------------------------------------------------------- 2ffa MACRO_Execute_Discrete,Check_In_Integer: 2ffa 2ffa dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2ffa fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 2ffb 0x2ffb seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 2ffb 2ffb fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3276 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3276 0x3276 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 2ffc ; -------------------------------------------------------------------------------------- 2ffc ; 0x025a Execute Discrete,Write_Unchecked 2ffc ; -------------------------------------------------------------------------------------- 2ffc MACRO_Execute_Discrete,Write_Unchecked: 2ffc 2ffc dispatch_brk_class 2 ; Flow C cc=False 0x32a5 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ffc fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a5 0x32a5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2ffd 2ffd typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 2ffe 2ffe fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3277 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2fff 2fff fiu_fill_mode_src 0 ; Flow J cc=False 0x3001 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3001 0x3001 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 3000 3000 fiu_fill_mode_src 0 ; Flow J 0x3004 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3004 0x3004 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3001 3001 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3002 3002 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3003 3003 fiu_load_var 1 hold_var; Flow J 0x3004 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3004 0x3004 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3004 3004 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 3005 3005 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3006 ; -------------------------------------------------------------------------------------- 3006 ; 0x0259 Execute Discrete,Test_And_Set_Previous 3006 ; -------------------------------------------------------------------------------------- 3006 MACRO_Execute_Discrete,Test_And_Set_Previous: 3006 3006 dispatch_brk_class 8 ; Flow J cc=True 0x300f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3006 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 300f 0x300f seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 3007 3007 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 3008 3008 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 3009 3009 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 300a 300a fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 300b 300b fiu_load_var 1 hold_var; Flow J cc=True 0x300d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 300d 0x300d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 300c 300c fiu_mem_start 3 start-wr; Flow J cc=True 0x300d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300d 0x300d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 300d 300d ioc_load_wdr 0 ; Flow J 0x3023 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3023 0x3023 seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 300e ; -------------------------------------------------------------------------------------- 300e ; 0x0258 Execute Discrete,Test_And_Set_Next 300e ; -------------------------------------------------------------------------------------- 300e MACRO_Execute_Discrete,Test_And_Set_Next: 300e 300e dispatch_brk_class 8 ; Flow J cc=False 0x3007 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 300e fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 3007 0x3007 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 300f 300f fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3010 3010 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x3277 fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 3011 3011 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3012 3012 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3017 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3017 0x3017 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3013 3013 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3014 3014 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x300d seq_br_type 1 Branch True seq_branch_adr 300d 0x300d seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3015 3015 fiu_fill_mode_src 0 ; Flow J cc=True 0x300d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300d 0x300d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3016 3016 fiu_fill_mode_src 0 ; Flow J 0x300d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 300d 0x300d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3017 3017 fiu_load_var 1 hold_var; Flow J cc=True 0x301d fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 301d 0x301d seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3018 3018 seq_br_type 7 Unconditional Call; Flow C 0x3075 seq_branch_adr 3075 0x3075 3019 3019 <default> 301a 301a fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 301b 301b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 301c 301c fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 301d 301d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 301e 301e typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 301f 301f fiu_fill_mode_src 0 ; Flow J cc=True 0x300d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 300d 0x300d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3020 3020 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first 3021 3021 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3022 3022 fiu_load_var 1 hold_var; Flow J 0x300d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 300d 0x300d seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3023 3023 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3024 ; -------------------------------------------------------------------------------------- 3024 ; 0x0256 Execute Discrete,Instruction_Read 3024 ; -------------------------------------------------------------------------------------- 3024 MACRO_Execute_Discrete,Instruction_Read: 3024 3024 dispatch_brk_class 8 ; Flow C 0x32fc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3024 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_frame 6 3025 3025 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3026 ; -------------------------------------------------------------------------------------- 3026 ; 0x0255 Execute Discrete,Partial_Plus 3026 ; -------------------------------------------------------------------------------------- 3026 MACRO_Execute_Discrete,Partial_Plus: 3026 3026 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3026 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 3027 3027 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3029 seq_br_type 1 Branch True seq_branch_adr 3029 0x3029 typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 3028 3028 seq_br_type 3 Unconditional Branch; Flow J 0x302a seq_branch_adr 302a 0x302a seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3029 3029 seq_br_type 3 Unconditional Branch; Flow J 0x302a seq_branch_adr 302a 0x302a seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 302a 302a seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 302b 302b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 302c ; -------------------------------------------------------------------------------------- 302c ; 0x0254 Execute Discrete,Partial_Minus 302c ; -------------------------------------------------------------------------------------- 302c MACRO_Execute_Discrete,Partial_Minus: 302c 302c dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 302c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 302d 302d seq_b_timing 1 Latch Condition; Flow J cc=True 0x302f seq_br_type 1 Branch True seq_branch_adr 302f 0x302f typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 302e 302e seq_br_type 3 Unconditional Branch; Flow J 0x302a seq_branch_adr 302a 0x302a seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 302f 302f seq_br_type 3 Unconditional Branch; Flow J 0x302a seq_branch_adr 302a 0x302a seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3030 ; -------------------------------------------------------------------------------------- 3030 ; 0x0253 Execute Discrete,Binary_Scale 3030 ; -------------------------------------------------------------------------------------- 3030 MACRO_Execute_Discrete,Binary_Scale: 3030 3030 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3030 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3031 3031 fiu_tivi_src 6 fiu_fiu; Flow J cc=True 0x3036 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3036 0x3036 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3032 3032 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3033 0x3033 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 3033 3033 ioc_tvbs 2 fiu+val; Flow J cc=False 0x3035 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3035 0x3035 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_rand 5 COUNT_ZEROS 3034 3034 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3035 0x3035 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3035 3035 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2fb7 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2fb7 0x2fb7 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 3036 3036 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3037 0x3037 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR11:12 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 11 3037 3037 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3039 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3039 0x3039 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 02 ? val_alu_func 6 A_MINUS_B val_b_adr 32 VR11:12 val_frame 11 3038 3038 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 3039 3039 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 303a ; -------------------------------------------------------------------------------------- 303a ; 0x09c0-0x09ff Execute_Immediate Binary_Scale,limitedneg 303a ; -------------------------------------------------------------------------------------- 303a MACRO_Execute_Immediate_Binary_Scale,limitedneg: 303a 303a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 303a fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR02:10 val_frame 2 val_rand 6 IMMEDIATE_OP 303b 303b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 303c 0x303c seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 303c 303c fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value 303d 303d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 303e ; -------------------------------------------------------------------------------------- 303e ; 0x0900-0x093f Execute_Immediate Binary_Scale,limitedpos 303e ; -------------------------------------------------------------------------------------- 303e MACRO_Execute_Immediate_Binary_Scale,limitedpos: 303e 303e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 303e fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 303f 303f fiu_tivi_src 6 fiu_fiu; Flow J cc=False 0x3033 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3033 0x3033 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3040 3040 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x3033 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3033 0x3033 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3041 3041 <halt> ; Flow R 3042 ; -------------------------------------------------------------------------------------- 3042 ; 0x0252 Execute Discrete,Arithmetic_Shift 3042 ; -------------------------------------------------------------------------------------- 3042 MACRO_Execute_Discrete,Arithmetic_Shift: 3042 3042 dispatch_brk_class 8 ; Flow J cc=True 0x3045 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3042 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3045 0x3045 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3043 3043 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 39 VR02:19 val_frame 2 3044 3044 fiu_len_fill_lit 7e zero-fill 0x3e; Flow R cc=True ; Flow J cc=False 0x2fd1 fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3045 3045 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd1 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3046 ; -------------------------------------------------------------------------------------- 3046 ; 0x0251 Execute Discrete,Logical_Shift 3046 ; -------------------------------------------------------------------------------------- 3046 MACRO_Execute_Discrete,Logical_Shift: 3046 3046 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3046 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3047 3047 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd1 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3048 ; -------------------------------------------------------------------------------------- 3048 ; 0x0940-0x097f Execute_Immediate Logical_Shift,limitedneg 3048 ; 0x0980-0x09bf Execute_Immediate Logical_Shift,limitedpos 3048 ; -------------------------------------------------------------------------------------- 3048 MACRO_Execute_Immediate_Logical_Shift,limitedneg: 3048 MACRO_Execute_Immediate_Logical_Shift,limitedpos: 3048 3048 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 3048 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 3049 3049 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 304a ; -------------------------------------------------------------------------------------- 304a ; 0x0250 Execute Discrete,Rotate 304a ; -------------------------------------------------------------------------------------- 304a MACRO_Execute_Discrete,Rotate: 304a 304a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 304a fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 304b 304b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd1 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 304c ; -------------------------------------------------------------------------------------- 304c ; 0x024f Execute Discrete,Insert_Bits 304c ; -------------------------------------------------------------------------------------- 304c MACRO_Execute_Discrete,Insert_Bits: 304c 304c dispatch_brk_class 8 ; Flow C cc=True 0x326c dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 304c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 304d 304d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x326c fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 304e 304e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 304f 304f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2fd1 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3050 ; -------------------------------------------------------------------------------------- 3050 ; 0x024e Execute Discrete,Extract_Bits 3050 ; -------------------------------------------------------------------------------------- 3050 MACRO_Execute_Discrete,Extract_Bits: 3050 3050 dispatch_brk_class 8 ; Flow J cc=True 0x3054 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3050 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3054 0x3054 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3051 3051 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x326c fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3052 3052 fiu_fill_mode_src 0 ; Flow C cc=True 0x326c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3053 3053 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2fd1 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2fd1 0x2fd1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3054 3054 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x3052 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3052 0x3052 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3055 3055 seq_br_type 7 Unconditional Call; Flow C 0x326c seq_branch_adr 326c 0x326c seq_en_micro 0 seq_random 02 ? 3056 ; -------------------------------------------------------------------------------------- 3056 ; 0x024d Execute Discrete,Count_Nonzero_Bits 3056 ; -------------------------------------------------------------------------------------- 3056 MACRO_Execute_Discrete,Count_Nonzero_Bits: 3056 3056 dispatch_brk_class 8 ; Flow J cc=True 0x306b dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3056 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 306b 0x306b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3057 3057 fiu_len_fill_lit 7d zero-fill 0x3d fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER 3058 3058 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3059 3059 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 305a 305a fiu_fill_mode_src 0 ; Flow J cc=True 0x305b ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_mux_sel 2 ALU 305b 305b fiu_fill_mode_src 0 ; Flow J cc=True 0x305c ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3e VR03:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 val_rand 2 DEC_LOOP_COUNTER 305c 305c fiu_fill_mode_src 0 ; Flow J cc=True 0x305d ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 305d 305d fiu_fill_mode_src 0 ; Flow J cc=True 0x305e ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 305e 305e fiu_fill_mode_src 0 ; Flow J cc=True 0x305f ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 305f 305f fiu_fill_mode_src 0 ; Flow J cc=True 0x3060 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3060 3060 fiu_fill_mode_src 0 ; Flow J cc=True 0x3061 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3061 3061 fiu_fill_mode_src 0 ; Flow J cc=True 0x3062 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3062 3062 fiu_fill_mode_src 0 ; Flow J cc=True 0x3063 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3063 3063 fiu_fill_mode_src 0 ; Flow J cc=True 0x3064 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3064 3064 fiu_fill_mode_src 0 ; Flow J cc=True 0x3065 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3065 3065 fiu_fill_mode_src 0 ; Flow J cc=True 0x3066 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3066 3066 fiu_fill_mode_src 0 ; Flow J cc=True 0x3067 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3067 3067 fiu_fill_mode_src 0 ; Flow J cc=True 0x3068 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3068 3068 fiu_fill_mode_src 0 ; Flow J cc=True 0x3069 ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3069 3069 fiu_fill_mode_src 0 ; Flow J cc=True 0x306a ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306a 306a fiu_fill_mode_src 0 ; Flow J cc=True 0x306b ; Flow J cc=#0x0 0x305b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 305b 0x305b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 306b 306b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 306c ; -------------------------------------------------------------------------------------- 306c ; 0x024c Execute Discrete,Count_Leading_Zeros 306c ; -------------------------------------------------------------------------------------- 306c MACRO_Execute_Discrete,Count_Leading_Zeros: 306c 306c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 306c typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 306d 306d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 306e ; -------------------------------------------------------------------------------------- 306e ; 0x024b Execute Discrete,Count_Trailing_Zeros 306e ; -------------------------------------------------------------------------------------- 306e MACRO_Execute_Discrete,Count_Trailing_Zeros: 306e 306e dispatch_brk_class 8 ; Flow J cc=True 0x3071 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 306e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3071 0x3071 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 306f 306f val_a_adr 10 TOP val_alu_func 1e A_AND_B val_rand 5 COUNT_ZEROS 3070 3070 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3071 3071 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 3072 ; -------------------------------------------------------------------------------------- 3072 ; 0x024a Execute Discrete,Is_Unsigned 3072 ; -------------------------------------------------------------------------------------- 3072 MACRO_Execute_Discrete,Is_Unsigned: 3072 3072 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3072 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_b_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 3073 3073 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3074 3074 fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3075 ; -------------------------------------------------------------------------------------- 3075 ; Comes from: 3075 ; 0888 C False from color 0x0000 3075 ; 088c C False from color 0x0000 3075 ; 0969 C False from color MACRO_0966_QQUnknown_InMicrocode 3075 ; 0975 C False from color 0x0000 3075 ; 09d8 C False from color MACRO_Execute_Any,Size 3075 ; 09e1 C False from color 0x09df 3075 ; 09ee C False from color MACRO_Execute_Any,Size 3075 ; 0b1f C False from color 0x0000 3075 ; 0c23 C False from color MACRO_Execute_Heap_Access,Element_Type 3075 ; 0c61 C False from color 0x0000 3075 ; 0c93 C False from color 0x0000 3075 ; 0caf C False from color MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head 3075 ; 0cda C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3075 ; 0ce1 C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3075 ; 0cfa C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3075 ; 0cfe C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 3075 ; 0d09 C False from color MACRO_Execute_Vector,Hash 3075 ; 0d1b C False from color MACRO_Execute_Vector,Hash 3075 ; 0d1d C False from color MACRO_Execute_Vector,Hash 3075 ; 0d24 C False from color MACRO_Execute_Vector,Hash 3075 ; 0d2b C False from color 0x0000 3075 ; 134b C False from color 0x0000 3075 ; 1350 C False from color 0x134e 3075 ; 1367 C False from color 0x0000 3075 ; 143f C False from color 0x09aa 3075 ; 1441 C False from color 0x09aa 3075 ; 1453 C False from color 0x09aa 3075 ; 1455 C False from color 0x09aa 3075 ; 146a C False from color 0x0000 3075 ; 146e C False from color 0x0000 3075 ; 147d C False from color MACRO_Execute_Matrix,Length 3075 ; 148a C False from color 0x1484 3075 ; 1493 C False from color 0x1484 3075 ; 14db C False from color 0x14d5 3075 ; 14de C False from color 0x14d5 3075 ; 1521 C False from color 0x0000 3075 ; 1533 C False from color 0x152f 3075 ; 1540 C False from color 0x152f 3075 ; 156f C False from color 0x1567 3075 ; 1572 C False from color 0x1567 3075 ; 1574 C False from color 0x1567 3075 ; 15dd C False from color 0x0000 3075 ; 15f2 C False from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 3075 ; 1600 C False from color 0x0000 3075 ; 1603 C False from color 0x0000 3075 ; 160a C False from color 0x0000 3075 ; 162a C False from color 0x0000 3075 ; 1635 C False from color 0x0000 3075 ; 163c C False from color 0x0000 3075 ; 1641 C False from color 0x0000 3075 ; 164e C False from color 0x0000 3075 ; 165a C False from color 0x0000 3075 ; 1660 C False from color 0x0000 3075 ; 1665 C False from color 0x0000 3075 ; 166f C False from color 0x0000 3075 ; 16a9 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 3075 ; 16c9 C False from color 0x16c5 3075 ; 16da C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3075 ; 16e2 C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3075 ; 16ea C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 3075 ; 16fd C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3075 ; 175a C False from color MACRO_Execute_Variant_Record,Read_Variant 3075 ; 17cb C False from color MACRO_Execute_Any,Set_Constraint 3075 ; 17d6 C False from color MACRO_Execute_Record,Field_Read,fieldnum 3075 ; 181f C False from color 0x09a9 3075 ; 182b C False from color 0x09a9 3075 ; 1844 C False from color MACRO_Execute_Vector,Greater_Equal 3075 ; 184e C False from color MACRO_Execute_Vector,Greater_Equal 3075 ; 1859 C False from color MACRO_Execute_Vector,Greater_Equal 3075 ; 1862 C False from color MACRO_Execute_Vector,Greater_Equal 3075 ; 1869 C False from color MACRO_Execute_Vector,First 3075 ; 1870 C False from color MACRO_Execute_Vector,First 3075 ; 1882 C False from color MACRO_Execute_Vector,First 3075 ; 188e C False from color MACRO_Execute_Vector,Reverse_Bounds 3075 ; 189d C False from color MACRO_Execute_Vector,Reverse_Bounds 3075 ; 18aa C False from color MACRO_Execute_Vector,Field_Read 3075 ; 18ba C False from color MACRO_Execute_Vector,Field_Read 3075 ; 18d3 C False from color 0x0000 3075 ; 18ee C False from color MACRO_Execute_Vector,Field_Reference 3075 ; 18fc C False from color MACRO_Execute_Vector,And 3075 ; 1905 C False from color MACRO_Execute_Vector,And 3075 ; 1917 C False from color MACRO_Execute_Vector,And 3075 ; 1931 C False from color 0x0000 3075 ; 1933 C False from color 0x0000 3075 ; 193e C False from color MACRO_Execute_Vector,Complement 3075 ; 1953 C False from color MACRO_Execute_Vector,Complement 3075 ; 195d C False from color MACRO_Execute_Vector,Complement 3075 ; 1980 C False from color MACRO_Execute_Vector,Slice_Read 3075 ; 19a8 C False from color MACRO_Execute_Vector,Slice_Write 3075 ; 19b1 C False from color MACRO_Execute_Vector,Slice_Write 3075 ; 19cb C False from color 0x19c8 3075 ; 19d3 C False from color MACRO_Execute_Vector,Catenate 3075 ; 19de C False from color MACRO_Execute_Vector,Catenate 3075 ; 19fd C False from color MACRO_Execute_Vector,Catenate 3075 ; 1a2a C False from color 0x0000 3075 ; 1a4a C False from color 0x0000 3075 ; 1a53 C False from color 0x1a4d 3075 ; 1a66 C False from color 0x1a63 3075 ; 1aa8 C False from color 0x1aa5 3075 ; 1ae3 C False from color MACRO_Execute_Access,Element_Type 3075 ; 1b51 C False from color 0x09a6 3075 ; 1b5b C False from color 0x1b58 3075 ; 1b88 C False from color 0x1b7e 3075 ; 1b8e C False from color 0x1b7e 3075 ; 1c26 C False from color 0x1c25 3075 ; 1c5f C False from color 0x0000 3075 ; 1c63 C False from color 0x0000 3075 ; 1c6c C False from color MACRO_Execute_Array,Field_Read 3075 ; 1df9 C False from color 0x0000 3075 ; 1e04 C False from color 0x0000 3075 ; 1e1a C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e1e C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e24 C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e28 C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e3a C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e3d C False from color MACRO_Execute_Matrix,Structure_Write 3075 ; 1e70 C False from color 0x0000 3075 ; 1ef3 C False from color 0x0000 3075 ; 2288 C False from color 0x2280 3075 ; 22a3 C False from color 0x0000 3075 ; 22b8 C False from color 0x09a6 3075 ; 22be C False from color 0x09a6 3075 ; 22c3 C False from color 0x0000 3075 ; 245a C False from color 0x0000 3075 ; 2468 C False from color 0x0000 3075 ; 2470 C False from color 0x0000 3075 ; 24b2 C False from color 0x2488 3075 ; 24bf C False from color 0x2488 3075 ; 24db C False from color 0x24d8 3075 ; 24ee C False from color 0x2488 3075 ; 24f8 C False from color 0x2488 3075 ; 24ff C False from color 0x2488 3075 ; 2701 C False from color 0x26fa 3075 ; 2703 C False from color 0x26fa 3075 ; 2931 C False from color 0x292d 3075 ; 2939 C False from color 0x2937 3075 ; 295e C False from color 0x295c 3075 ; 2b7c C False from color 0x0000 3075 ; 2dd6 C False from color 0x0000 3075 ; 3018 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 3075 ; 35ef C False from color 0x0000 3075 ; 35fa C False from color 0x0000 3075 ; 3600 C False from color 0x35fe 3075 ; -------------------------------------------------------------------------------------- 3075 3075 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3076 0x3076 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3076 3076 fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3077 3077 fiu_load_var 1 hold_var; Flow J 0x3074 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3074 0x3074 3078 3078 fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3079 ; -------------------------------------------------------------------------------------- 3079 ; Comes from: 3079 ; 0791 C False from color 0x0767 3079 ; 0ab0 C False from color 0x0000 3079 ; 0c13 C False from color 0x0c05 3079 ; 0c9b C False from color 0x0000 3079 ; 0ca4 C False from color 0x0000 3079 ; 0d36 C False from color 0x0d34 3079 ; 1150 C False from color 0x110d 3079 ; 12ea C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3079 ; 1322 C False from color 0x1314 3079 ; 137d C False from color MACRO_Declare_Variable_Array,With_Constraint 3079 ; 13c0 C False from color MACRO_Declare_Variable_Array,With_Constraint 3079 ; 13d5 C False from color MACRO_Declare_Variable_Array,With_Constraint 3079 ; 13e1 C False from color MACRO_Declare_Variable_Array,With_Constraint 3079 ; 1407 C False from color MACRO_Declare_Variable_Array,With_Constraint 3079 ; 1426 C False from color 0x140f 3079 ; 1431 C False from color 0x140f 3079 ; 1728 C False from color 0x1725 3079 ; 1ad3 C False from color 0x0000 3079 ; 1d66 C False from color 0x0000 3079 ; 1d7b C False from color 0x1d28 3079 ; 1d99 C False from color 0x1d28 3079 ; 1da1 C False from color 0x1d28 3079 ; 1ef5 C False from color 0x0000 3079 ; 2901 C False from color MACRO_Execute_Float,Write_Unchecked 3079 ; 296a C False from color 0x0000 3079 ; 29bd C False from color 0x0000 3079 ; 29cc C False from color 0x0000 3079 ; 2a15 C False from color 0x2a12 3079 ; 2a29 C False from color 0x2a02 3079 ; 2a30 C False from color 0x0000 3079 ; 3001 C False from color MACRO_Execute_Discrete,Write_Unchecked 3079 ; 35a6 C False from color 0x35a1 3079 ; 392a C False from color 0x062d 3079 ; -------------------------------------------------------------------------------------- 3079 3079 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x307d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 307d 0x307d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl 1 RESTORE_RDR val_c_adr 30 GP0f 307a 307a fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x307e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 307e 0x307e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 307b 307b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 307c 307c ioc_adrbs 1 val ; Flow R cc=True ; Flow J cc=False 0x307e seq_br_type 8 Return True seq_branch_adr 307e 0x307e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 307d 307d fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 307e 307e fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A val_b_adr 0f GP0f 307f 307f fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3080 3080 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc 3081 3081 fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3082 3082 fiu_fill_mode_src 0 ; Flow J 0x3078 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3078 0x3078 3083 3083 <halt> ; Flow R 3084 ; -------------------------------------------------------------------------------------- 3084 ; 0x03e6 Declare_Type Float,Defined,Visible 3084 ; -------------------------------------------------------------------------------------- 3084 MACRO_Declare_Type_Float,Defined,Visible: 3084 3084 dispatch_brk_class 4 ; Flow C 0x3087 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3084 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3087 0x3087 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3085 3085 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32a8 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 36 TR08:16 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 3086 3086 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 3087 ; -------------------------------------------------------------------------------------- 3087 ; Comes from: 3087 ; 3084 C from color MACRO_Declare_Type_Float,Defined,Visible 3087 ; 308a C from color MACRO_Declare_Type_Float,Defined,Visible 3087 ; -------------------------------------------------------------------------------------- 3087 3087 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a5 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_frame 1c val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3088 3088 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_alu_func 1 A_PLUS_B val_b_adr 29 VR09:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 3089 3089 fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 308a ; -------------------------------------------------------------------------------------- 308a ; 0x03e5 Declare_Type Float,Defined 308a ; -------------------------------------------------------------------------------------- 308a MACRO_Declare_Type_Float,Defined: 308a 308a dispatch_brk_class 4 ; Flow C 0x3087 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 308a fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3087 0x3087 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 308b 308b fiu_tivi_src 4 fiu_var; Flow J 0x3086 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3086 0x3086 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 31 TR02:11 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 308c ; -------------------------------------------------------------------------------------- 308c ; Comes from: 308c ; 3098 C from color 0x0000 308c ; -------------------------------------------------------------------------------------- 308c 308c fiu_load_tar 1 hold_tar; Flow C 0x3090 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3090 0x3090 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_rand 8 SPARE_0x08 308d 308d ioc_tvbs 2 fiu+val; Flow C 0x3091 seq_br_type 0 Branch False seq_branch_adr 3091 0x3091 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 308e 308e fiu_mem_start 3 start-wr; Flow J cc=False 0x3095 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3095 0x3095 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 308f 308f fiu_mem_start 4 continue; Flow C 0x3092 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3092 0x3092 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3090 ; -------------------------------------------------------------------------------------- 3090 ; Comes from: 3090 ; 308c C from color 0x308c 3090 ; -------------------------------------------------------------------------------------- 3090 3090 ioc_tvbs 2 fiu+val; Flow J cc=False 0x308e seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 308e 0x308e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 3091 ; -------------------------------------------------------------------------------------- 3091 ; Comes from: 3091 ; 308d C from color 0x308d 3091 ; -------------------------------------------------------------------------------------- 3091 3091 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 3092 3092 fiu_mem_start 3 start-wr; Flow J cc=False 0x3094 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3094 0x3094 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3093 3093 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326c seq_br_type 8 Return True seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 3094 3094 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326c seq_br_type 8 Return True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 3095 3095 fiu_mem_start 4 continue; Flow C 0x3092 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3092 0x3092 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3096 ; -------------------------------------------------------------------------------------- 3096 ; Comes from: 3096 ; 309a C from color MACRO_Declare_Type_Float,Constrained,Visible 3096 ; 309e C from color 0x309d 3096 ; -------------------------------------------------------------------------------------- 3096 3096 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3097 3097 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 3098 3098 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x308c seq_br_type 7 Unconditional Call seq_branch_adr 308c 0x308c seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3099 3099 fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x3277 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3277 0x3277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 309a ; -------------------------------------------------------------------------------------- 309a ; 0x03e4 Declare_Type Float,Constrained,Visible 309a ; -------------------------------------------------------------------------------------- 309a MACRO_Declare_Type_Float,Constrained,Visible: 309a 309a dispatch_brk_class 4 ; Flow C 0x3096 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 309a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3096 0x3096 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 309b 309b fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32a8 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 309c 309c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR08:18 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 309d 309d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR05:1d typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 309e ; -------------------------------------------------------------------------------------- 309e ; 0x03e3 Declare_Type Float,Constrained 309e ; -------------------------------------------------------------------------------------- 309e MACRO_Declare_Type_Float,Constrained: 309e 309e dispatch_brk_class 4 ; Flow C 0x3096 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 309e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3096 0x3096 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 309f 309f fiu_tivi_src 4 fiu_var; Flow J 0x309d ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 309d 0x309d seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30a0 ; -------------------------------------------------------------------------------------- 30a0 ; 0x03e1 Declare_Type Float,Incomplete,Visible 30a0 ; -------------------------------------------------------------------------------------- 30a0 MACRO_Declare_Type_Float,Incomplete,Visible: 30a0 30a0 dispatch_brk_class 4 ; Flow C 0x30a3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30a0 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30a3 0x30a3 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30a1 30a1 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32a8 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3a TR08:1a typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30a2 30a2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30a3 ; -------------------------------------------------------------------------------------- 30a3 ; Comes from: 30a3 ; 30a0 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30a3 ; 30a6 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30a3 ; -------------------------------------------------------------------------------------- 30a3 30a3 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30a4 30a4 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 2a VR09:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 30a5 30a5 fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 30a6 ; -------------------------------------------------------------------------------------- 30a6 ; 0x03e0 Declare_Type Float,Incomplete 30a6 ; -------------------------------------------------------------------------------------- 30a6 MACRO_Declare_Type_Float,Incomplete: 30a6 30a6 dispatch_brk_class 4 ; Flow C 0x30a3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30a6 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30a3 0x30a3 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30a7 30a7 fiu_tivi_src 4 fiu_var; Flow J 0x30a2 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30a2 0x30a2 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3b TR08:1b typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30a8 ; -------------------------------------------------------------------------------------- 30a8 ; 0x03de Complete_Type Float,By_Defining 30a8 ; -------------------------------------------------------------------------------------- 30a8 MACRO_Complete_Type_Float,By_Defining: 30a8 30a8 dispatch_brk_class 4 ; Flow C cc=True 0x32a5 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30a9 30a9 seq_br_type 2 Push (branch address); Flow J 0x30aa seq_branch_adr 32a7 0x32a7 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_frame 8 typ_rand 8 SPARE_0x08 30aa 30aa fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x30bd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 30bd 0x30bd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 30ab 30ab fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 30ac ; -------------------------------------------------------------------------------------- 30ac ; 0x03dd Complete_Type Float,By_Renaming 30ac ; -------------------------------------------------------------------------------------- 30ac MACRO_Complete_Type_Float,By_Renaming: 30ac 30ac dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30ac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30ad 30ad fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 30ae 30ae fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30af 30af fiu_load_var 1 hold_var; Flow C cc=True 0x3277 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30b0 30b0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30b1 30b1 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR06:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 30b2 30b2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 30b3 30b3 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x3277 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 30b4 30b4 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert typ_mar_cntl 6 INCREMENT_MAR 30b5 30b5 fiu_mem_start 4 continue; Flow J 0x30bf ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 30bf 0x30bf typ_mar_cntl 6 INCREMENT_MAR 30b6 ; -------------------------------------------------------------------------------------- 30b6 ; 0x03dc Complete_Type Float,By_Constraining 30b6 ; -------------------------------------------------------------------------------------- 30b6 MACRO_Complete_Type_Float,By_Constraining: 30b6 30b6 dispatch_brk_class 4 ; Flow C 0x32fc dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30b6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1d TOP - 3 val_b_adr 1e TOP - 2 30b7 30b7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 30b8 30b8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30b9 30b9 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32a7 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR 30ba 30ba fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x30c0 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 30c0 0x30c0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30bb 30bb ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 30bc 30bc fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3277 0x3277 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30bd 30bd fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 21 TR06:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30be 30be fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 30bf 30bf ioc_load_wdr 0 ; Flow J 0x30ab seq_br_type 3 Unconditional Branch seq_branch_adr 30ab 0x30ab typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 30c0 ; -------------------------------------------------------------------------------------- 30c0 ; Comes from: 30c0 ; 30ba C from color MACRO_Complete_Type_Float,By_Defining 30c0 ; -------------------------------------------------------------------------------------- 30c0 30c0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x30c4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c4 0x30c4 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30c1 30c1 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30c5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 30c5 0x30c5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30c2 30c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x30c9 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c9 0x30c9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30c3 30c3 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30c6 seq_branch_adr 30c6 0x30c6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 30c4 30c4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30c2 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30c2 0x30c2 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30c5 30c5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 30c6 30c6 fiu_mem_start 2 start-rd; Flow J cc=False 0x30c8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c8 0x30c8 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30c7 30c7 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x326c seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 30c8 30c8 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x326c seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 30c9 30c9 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30c6 seq_branch_adr 30c6 0x30c6 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 30ca ; -------------------------------------------------------------------------------------- 30ca ; 0x03d9 Declare_Variable Float,Visible 30ca ; -------------------------------------------------------------------------------------- 30ca MACRO_Declare_Variable_Float,Visible: 30ca 30ca dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30ca seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 30cb 30cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR08:16 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30cc ; -------------------------------------------------------------------------------------- 30cc ; 0x03da Declare_Variable Float 30cc ; -------------------------------------------------------------------------------------- 30cc MACRO_Declare_Variable_Float: 30cc 30cc dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30cc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR09:17 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30cd 30cd <halt> ; Flow R 30ce ; -------------------------------------------------------------------------------------- 30ce ; 0x03d8 Declare_Variable Float,Duplicate 30ce ; -------------------------------------------------------------------------------------- 30ce MACRO_Declare_Variable_Float,Duplicate: 30ce 30ce dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30ce fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 30cf 30cf <halt> ; Flow R 30d0 ; -------------------------------------------------------------------------------------- 30d0 ; 0x02bf Declare_Variable Float,With_Value,With_Constraint 30d0 ; -------------------------------------------------------------------------------------- 30d0 MACRO_Declare_Variable_Float,With_Value,With_Constraint: 30d0 30d0 dispatch_brk_class 4 ; Flow J cc=True 0x30d6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 30d0 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 30d6 0x30d6 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30d1 30d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x326c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30d2 ; -------------------------------------------------------------------------------------- 30d2 ; 0x03df Declare_Variable Float,With_Value 30d2 ; -------------------------------------------------------------------------------------- 30d2 MACRO_Declare_Variable_Float,With_Value: 30d2 30d2 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30d2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 30d3 0x30d3 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 30d3 30d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 30d4 ; -------------------------------------------------------------------------------------- 30d4 ; 0x02be Declare_Variable Float,Visible,With_Value,With_Constraint 30d4 ; -------------------------------------------------------------------------------------- 30d4 MACRO_Declare_Variable_Float,Visible,With_Value,With_Constraint: 30d4 30d4 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 30d4 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 30d5 30d5 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30d1 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30d1 0x30d1 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30d6 30d6 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 326c 0x326c seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 30d7 30d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x326c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 326c 0x326c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30d8 ; -------------------------------------------------------------------------------------- 30d8 ; 0x03db Declare_Variable Float,Visible,With_Value 30d8 ; -------------------------------------------------------------------------------------- 30d8 MACRO_Declare_Variable_Float,Visible,With_Value: 30d8 30d8 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30d8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 30d9 30d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 30da ; -------------------------------------------------------------------------------------- 30da ; Comes from: 30da ; 30e8 C from color 0x30e3 30da ; 30ec C from color 0x30e3 30da ; 30f0 C from color 0x30e3 30da ; 30f2 C from color 0x30e3 30da ; -------------------------------------------------------------------------------------- 30da 30da fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x30df fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30df 0x30df seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 typ_a_adr 35 TR02:15 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 30db 30db fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x30e1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30e1 0x30e1 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_b_adr 10 TOP 30dc 30dc fiu_tivi_src c mar_0xc; Flow J cc=False 0x30de ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30de 0x30de typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 30dd 30dd val_alu_func 15 NOT_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 30de 30de fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x32a5 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1c val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30df 30df fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a5 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_b_adr 10 TOP 30e0 30e0 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 30e1 30e1 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a5 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30e2 30e2 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 30e3 30e3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 30e4 30e4 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30e5 30e5 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32a7 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30e6 30e6 seq_br_type 4 Call False; Flow C cc=False 0x32aa seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 30e7 30e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 30e8 ; -------------------------------------------------------------------------------------- 30e8 ; 0x03fe Declare_Type Discrete,Defined,Visible 30e8 ; -------------------------------------------------------------------------------------- 30e8 MACRO_Declare_Type_Discrete,Defined,Visible: 30e8 30e8 dispatch_brk_class 4 ; Flow C 0x30da dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30e8 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30da 0x30da seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30e9 30e9 fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30ea 30ea fiu_mem_start 4 continue; Flow C cc=False 0x32a8 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 30eb 30eb fiu_tivi_src 4 fiu_var; Flow J 0x30e7 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e7 0x30e7 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30ec ; -------------------------------------------------------------------------------------- 30ec ; 0x03fd Declare_Type Discrete,Defined 30ec ; -------------------------------------------------------------------------------------- 30ec MACRO_Declare_Type_Discrete,Defined: 30ec 30ec dispatch_brk_class 4 ; Flow C 0x30da dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30ec fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30da 0x30da seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30ed 30ed fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30ee 30ee fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 30ef 30ef fiu_tivi_src 4 fiu_var; Flow J 0x30e7 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e7 0x30e7 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 30f0 ; -------------------------------------------------------------------------------------- 30f0 ; 0x03fb Declare_Type Discrete,Defined,Visible,With_Size 30f0 ; -------------------------------------------------------------------------------------- 30f0 MACRO_Declare_Type_Discrete,Defined,Visible,With_Size: 30f0 30f0 dispatch_brk_class 4 ; Flow C 0x30da dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30f0 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30da 0x30da seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30f1 30f1 ioc_tvbs 1 typ+fiu; Flow J 0x30e3 seq_br_type 3 Unconditional Branch seq_branch_adr 30e3 0x30e3 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30f2 ; -------------------------------------------------------------------------------------- 30f2 ; 0x03fa Declare_Type Discrete,Defined,With_Size 30f2 ; -------------------------------------------------------------------------------------- 30f2 MACRO_Declare_Type_Discrete,Defined,With_Size: 30f2 30f2 dispatch_brk_class 4 ; Flow C 0x30da dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30f2 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30da 0x30da seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30f3 30f3 ioc_tvbs 1 typ+fiu; Flow J 0x30e3 seq_br_type 3 Unconditional Branch seq_branch_adr 30e3 0x30e3 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30f4 ; -------------------------------------------------------------------------------------- 30f4 ; 0x03f9 Declare_Type Discrete,Constrained,Visible 30f4 ; -------------------------------------------------------------------------------------- 30f4 MACRO_Declare_Type_Discrete,Constrained,Visible: 30f4 30f4 dispatch_brk_class 4 ; Flow J 0x30f5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30f4 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 30f5 30f5 fiu_mem_start 4 continue; Flow J cc=False 0x30fb ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 30fb 0x30fb seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 30f6 30f6 fiu_mem_start 4 continue; Flow J cc=True 0x30f9 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 30f9 0x30f9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30f7 30f7 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 30f8 30f8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x3108 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3108 0x3108 seq_en_micro 0 typ_a_adr 26 TR06:06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30f9 30f9 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 30fa 30fa fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x3108 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3108 0x3108 seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 30fb 30fb ioc_fiubs 1 val ; Flow R cc=False ; Flow J cc=True 0x3104 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 3104 0x3104 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30fc ; -------------------------------------------------------------------------------------- 30fc ; 0x03f8 Declare_Type Discrete,Constrained 30fc ; -------------------------------------------------------------------------------------- 30fc MACRO_Declare_Type_Discrete,Constrained: 30fc 30fc dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30fc fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 30fd 30fd fiu_mem_start 4 continue; Flow J cc=False 0x3103 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3103 0x3103 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 30fe 30fe fiu_mem_start 4 continue; Flow J cc=True 0x3101 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3101 0x3101 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30ff 30ff ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3100 3100 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3108 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3108 0x3108 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3101 3101 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3102 3102 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3108 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3108 0x3108 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3103 3103 ioc_load_wdr 0 ; Flow J 0x3104 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3104 0x3104 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3104 3104 fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3105 3105 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3106 3106 fiu_mem_start 4 continue; Flow J cc=False 0x310a ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 310a 0x310a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3107 3107 seq_br_type 3 Unconditional Branch; Flow J 0x3276 seq_branch_adr 3276 0x3276 3108 3108 fiu_load_tar 1 hold_tar; Flow C cc=False 0x326c fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3109 3109 fiu_mem_start 4 continue; Flow C cc=False 0x326c ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 310a 310a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 310b 310b fiu_load_oreg 1 hold_oreg fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 310c 310c fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 310d ; -------------------------------------------------------------------------------------- 310d ; Comes from: 310d ; 311c C from color MACRO_Declare_Type_InMicrocode,Discrete 310d ; 3122 C from color MACRO_Declare_Type_InMicrocode,Discrete 310d ; -------------------------------------------------------------------------------------- 310d 310d fiu_mem_start 4 continue; Flow J cc=False 0x3115 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3115 0x3115 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 310e 310e fiu_mem_start 4 continue; Flow J cc=True 0x3111 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3111 0x3111 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 310f 310f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3110 3110 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3113 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3113 0x3113 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3111 3111 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3112 3112 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3113 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3113 0x3113 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3113 3113 fiu_load_tar 1 hold_tar; Flow C cc=False 0x326c fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3114 3114 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x326c ioc_tvbs 3 fiu+fiu seq_br_type 8 Return True seq_branch_adr 326c 0x326c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3115 3115 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3116 3116 fiu_mem_start 2 start-rd; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3117 3117 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x3276 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3118 3118 fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x3276 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3276 0x3276 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3119 3119 <halt> ; Flow R 311a ; -------------------------------------------------------------------------------------- 311a ; 0x03fc Declare_Type InMicrocode,Discrete 311a ; -------------------------------------------------------------------------------------- 311a MACRO_Declare_Type_InMicrocode,Discrete: 311a 311a dispatch_brk_class 0 ; Flow C cc=False 0x32aa dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 311a fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 311b 311b ioc_fiubs 1 val ; Flow C cc=False 0x32a8 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 311c 311c fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x310d fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 310d 0x310d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 311d 311d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x311e fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 311e 0x311e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 311e 311e fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x32a7 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 311f 311f fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 3120 ; -------------------------------------------------------------------------------------- 3120 ; 0x03f7 Declare_Type InMicrocode,Discrete 3120 ; -------------------------------------------------------------------------------------- 3120 MACRO_Declare_Type_InMicrocode,Discrete: 3120 3120 dispatch_brk_class 0 ; Flow C cc=False 0x32aa dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3120 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 3121 3121 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3122 3122 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x310d fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 310d 0x310d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 3123 3123 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x311e fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 311e 0x311e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 3124 3124 fiu_mem_start 4 continue; Flow J 0x3127 seq_br_type 3 Unconditional Branch seq_branch_adr 3127 0x3127 typ_a_adr 24 TR09:04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 3125 3125 <halt> ; Flow R 3126 ; -------------------------------------------------------------------------------------- 3126 ; 0x03f5 Declare_Variable Discrete,Incomplete 3126 ; -------------------------------------------------------------------------------------- 3126 MACRO_Declare_Variable_Discrete,Incomplete: 3126 3126 dispatch_brk_class 4 ; Flow J 0x3129 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3126 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3129 0x3129 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3127 3127 fiu_mem_start 4 continue; Flow J 0x312b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 312b 0x312b seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 3128 ; -------------------------------------------------------------------------------------- 3128 ; 0x03f2 Declare_Variable Discrete,Incomplete,Unsigned 3128 ; -------------------------------------------------------------------------------------- 3128 MACRO_Declare_Variable_Discrete,Incomplete,Unsigned: 3128 3128 dispatch_brk_class 4 ; Flow J 0x3129 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3128 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3129 0x3129 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 3129 3129 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3124 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3124 0x3124 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 312a ; -------------------------------------------------------------------------------------- 312a ; 0x03f6 Declare_Variable Discrete,Incomplete,Visible 312a ; -------------------------------------------------------------------------------------- 312a MACRO_Declare_Variable_Discrete,Incomplete,Visible: 312a 312a dispatch_brk_class 4 ; Flow J 0x312d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 312a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312d 0x312d seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 312b 312b fiu_tivi_src 4 fiu_var; Flow J 0x30e7 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30e7 0x30e7 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_b_adr 30 VR02:10 val_frame 2 312c ; -------------------------------------------------------------------------------------- 312c ; 0x03f3 Declare_Variable Discrete,Incomplete,Visible,Unsigned 312c ; -------------------------------------------------------------------------------------- 312c MACRO_Declare_Variable_Discrete,Incomplete,Visible,Unsigned: 312c 312c dispatch_brk_class 4 ; Flow J 0x312d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 312c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 312d 0x312d seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 312d 312d fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 312e 312e fiu_mem_start 4 continue; Flow J 0x312f seq_br_type 2 Push (branch address) seq_branch_adr 32a8 0x32a8 typ_a_adr 21 TR08:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 312f 312f fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x312b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 9 Return False seq_branch_adr 312b 0x312b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 3130 ; -------------------------------------------------------------------------------------- 3130 ; 0x03ef Complete_Type Discrete,By_Defining 3130 ; -------------------------------------------------------------------------------------- 3130 MACRO_Complete_Type_Discrete,By_Defining: 3130 3130 dispatch_brk_class 4 ; Flow J 0x3131 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3130 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32a5 0x32a5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3131 3131 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3137 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3137 0x3137 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 5 COUNT_ZEROS 3132 3132 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3138 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3138 0x3138 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 1f TOP - 1 val_a_adr 15 ZERO_COUNTER val_b_adr 1f TOP - 1 3133 3133 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3135 seq_br_type 0 Branch False seq_branch_adr 3135 0x3135 val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 3134 3134 val_alu_func 15 NOT_B val_b_adr 1d TOP - 3 val_rand 5 COUNT_ZEROS 3135 3135 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3136 3136 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3139 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3139 0x3139 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3137 3137 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3139 ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3139 0x3139 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 28 VR06:08 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3138 3138 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a5 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 2a VR06:0a val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3139 3139 ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_rand 8 SPARE_0x08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 313a 313a fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x32a7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 313b 313b fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 24 TR09:04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR 313c 313c fiu_mem_start 4 continue; Flow J 0x313d ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 313d 0x313d typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 313d 313d fiu_tivi_src 4 fiu_var; Flow J 0x3163 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3163 0x3163 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_b_adr 10 TOP 313e ; -------------------------------------------------------------------------------------- 313e ; 0x03ee Complete_Type Discrete,By_Renaming 313e ; -------------------------------------------------------------------------------------- 313e MACRO_Complete_Type_Discrete,By_Renaming: 313e 313e dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 313e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 313f 313f fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3140 3140 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 3141 3141 fiu_load_var 1 hold_var; Flow C cc=True 0x3277 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3142 3142 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3143 3143 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3144 3144 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B 3145 3145 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 02 GP02 typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 3146 3146 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x3277 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 3147 3147 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3148 3148 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 3149 3149 ioc_load_wdr 0 ; Flow J 0x3163 seq_br_type 3 Unconditional Branch seq_branch_adr 3163 0x3163 typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 314a ; -------------------------------------------------------------------------------------- 314a ; 0x03ed Complete_Type Discrete,By_Constraining 314a ; -------------------------------------------------------------------------------------- 314a MACRO_Complete_Type_Discrete,By_Constraining: 314a 314a dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 314a fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 314b 314b fiu_load_tar 1 hold_tar; Flow J cc=True 0x3158 fiu_tivi_src 8 type_var ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3158 0x3158 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 314c 314c fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 314d 314d seq_b_timing 1 Latch Condition; Flow J cc=True 0x3150 seq_br_type 1 Branch True seq_branch_adr 3150 0x3150 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 314e 314e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3151 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3151 0x3151 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 314f 314f fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3152 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3152 0x3152 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3150 3150 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 01 GP01 val_rand 5 COUNT_ZEROS 3151 3151 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3152 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3152 0x3152 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3152 3152 fiu_mem_start 4 continue; Flow C cc=False 0x32a7 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1d TOP - 3 3153 3153 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3277 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS 3154 3154 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x326c seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3155 3155 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3156 3156 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3157 3157 fiu_mem_start 4 continue; Flow J 0x313d ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 313d 0x313d typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 3158 3158 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3159 3159 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 315a 315a fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 315b 315b fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32a7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 28 VR06:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 315c 315c ioc_fiubs 1 val ; Flow J 0x315d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3155 0x3155 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 315d 315d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3277 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 315e 315e ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3276 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3276 0x3276 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 315f 315f <halt> ; Flow R 3160 ; -------------------------------------------------------------------------------------- 3160 ; 0x03ea Declare_Variable Discrete,Visible 3160 ; -------------------------------------------------------------------------------------- 3160 MACRO_Declare_Variable_Discrete,Visible: 3160 3160 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3160 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3161 3161 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3162 ; -------------------------------------------------------------------------------------- 3162 ; 0x03eb Declare_Variable Discrete 3162 ; -------------------------------------------------------------------------------------- 3162 MACRO_Declare_Variable_Discrete: 3162 3162 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3162 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3163 3163 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3164 ; -------------------------------------------------------------------------------------- 3164 ; 0x03e9 Declare_Variable Discrete,Duplicate 3164 ; -------------------------------------------------------------------------------------- 3164 MACRO_Declare_Variable_Discrete,Duplicate: 3164 3164 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3164 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3165 ; -------------------------------------------------------------------------------------- 3165 ; Comes from: 3165 ; 3176 C from color MACRO_Execute_Immediate_Set_Value,uimmediate 3165 ; -------------------------------------------------------------------------------------- 3165 3165 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3166 ; -------------------------------------------------------------------------------------- 3166 ; 0x0600-0x06ff Execute_Immediate Set_Value_Unchecked,uimmediate 3166 ; -------------------------------------------------------------------------------------- 3166 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 3166 3166 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_uadr 3166 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 3167 ; -------------------------------------------------------------------------------------- 3167 ; Comes from: 3167 ; 3168 C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 3167 ; -------------------------------------------------------------------------------------- 3167 3167 seq_br_type a Unconditional Return; Flow R typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 3168 ; -------------------------------------------------------------------------------------- 3168 ; 0x0700-0x07ff Execute_Immediate Set_Value,uimmediate 3168 ; -------------------------------------------------------------------------------------- 3168 MACRO_Execute_Immediate_Set_Value,uimmediate: 3168 3168 dispatch_brk_class 4 ; Flow C cc=True 0x3167 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3168 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3167 0x3167 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3169 3169 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316a 0x316a seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 316a 316a fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 316b 316b fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x3277 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 316c 316c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x326c seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 316d 316d seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 316e ; -------------------------------------------------------------------------------------- 316e ; 0x0400-0x04ff Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 316e ; -------------------------------------------------------------------------------------- 316e MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 316e 316e dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_uadr 316e ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 316f 316f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 3170 ; -------------------------------------------------------------------------------------- 3170 ; 0x0500-0x05ff Execute_Immediate Set_Value_Visible,uimmediate 3170 ; -------------------------------------------------------------------------------------- 3170 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 3170 3170 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3170 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 3171 3171 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3177 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3177 0x3177 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 3172 ; -------------------------------------------------------------------------------------- 3172 ; 0x03ec Declare_Variable Discrete,With_Value,With_Constraint 3172 ; -------------------------------------------------------------------------------------- 3172 MACRO_Declare_Variable_Discrete,With_Value,With_Constraint: 3172 3172 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3172 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3173 3173 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x316a fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316a 0x316a seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3174 ; -------------------------------------------------------------------------------------- 3174 ; 0x03f1 Declare_Variable Discrete,With_Value 3174 ; -------------------------------------------------------------------------------------- 3174 MACRO_Declare_Variable_Discrete,With_Value: 3174 3174 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3174 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3175 0x3175 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 3175 3175 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 3176 ; -------------------------------------------------------------------------------------- 3176 ; 0x03e8 Declare_Variable Discrete,Visible,With_Value,With_Constraint 3176 ; -------------------------------------------------------------------------------------- 3176 MACRO_Declare_Variable_Discrete,Visible,With_Value,With_Constraint: 3176 3176 dispatch_brk_class 4 ; Flow C 0x3165 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3176 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3165 0x3165 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3177 3177 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x316a fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 316a 0x316a seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3178 ; -------------------------------------------------------------------------------------- 3178 ; 0x03f0 Declare_Variable Discrete,Visible,With_Value 3178 ; -------------------------------------------------------------------------------------- 3178 MACRO_Declare_Variable_Discrete,Visible,With_Value: 3178 3178 dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3178 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 3179 3179 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 317a ; -------------------------------------------------------------------------------------- 317a ; 0x03ad Declare_Type Heap_Access,Defined 317a ; -------------------------------------------------------------------------------------- 317a MACRO_Declare_Type_Heap_Access,Defined: 317a 317a dispatch_brk_class 4 ; Flow J cc=False 0x317f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 317a fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 317f 0x317f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 317b 317b seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 317c ; -------------------------------------------------------------------------------------- 317c ; 0x03ae Declare_Type Heap_Access,Defined,Visible 317c ; -------------------------------------------------------------------------------------- 317c MACRO_Declare_Type_Heap_Access,Defined,Visible: 317c 317c dispatch_brk_class 4 ; Flow C cc=False 0x32a8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 317c seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 317d 317d fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x317f ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 317f 0x317f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3a VR07:1a val_frame 7 317e 317e seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 317f 317f fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 29 VR06:09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 3180 3180 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c 3181 3181 ioc_adrbs 2 typ ; Flow C cc=#0x0 0x3188 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3188 0x3188 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 3182 3182 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 38 TR11:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3183 3183 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 10 TOP 3184 3184 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 3185 3185 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 39 VR02:19 val_frame 2 3186 3186 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 3187 3187 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 3188 ; -------------------------------------------------------------------------------------- 3188 ; Comes from: 3188 ; 3181 C #0x0 from color MACRO_Declare_Type_Heap_Access,Defined 3188 ; -------------------------------------------------------------------------------------- 3188 3188 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x318e seq_br_type 9 Return False seq_branch_adr 318e 0x318e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 3189 3189 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x318e seq_br_type 9 Return False seq_branch_adr 318e 0x318e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318a 318a seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x318e seq_br_type 9 Return False seq_branch_adr 318e 0x318e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318b 318b seq_br_type 3 Unconditional Branch; Flow J 0x318c seq_branch_adr 318c 0x318c typ_c_adr 3b GP04 318c 318c seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 318d 318d seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 318e 0x318e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 318e 318e seq_br_type a Unconditional Return; Flow R typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 318f 318f <halt> ; Flow R 3190 ; -------------------------------------------------------------------------------------- 3190 ; 0x03a8 Declare_Type Heap_Access,Incomplete 3190 ; -------------------------------------------------------------------------------------- 3190 MACRO_Declare_Type_Heap_Access,Incomplete: 3190 3190 dispatch_brk_class 4 ; Flow J 0x3191 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3190 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3191 0x3191 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3191 3191 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x319e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 319e 0x319e typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR06:09 val_frame 6 3192 ; -------------------------------------------------------------------------------------- 3192 ; 0x03a9 Declare_Type Heap_Access,Incomplete,Visible 3192 ; -------------------------------------------------------------------------------------- 3192 MACRO_Declare_Type_Heap_Access,Incomplete,Visible: 3192 3192 dispatch_brk_class 4 ; Flow J cc=True 0x3191 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3192 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3191 0x3191 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3193 3193 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 3194 ; -------------------------------------------------------------------------------------- 3194 ; 0x03a5 Declare_Type Heap_Access,Incomplete,Values_Relative 3194 ; -------------------------------------------------------------------------------------- 3194 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative: 3194 3194 dispatch_brk_class 4 ; Flow J 0x3195 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3194 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3195 0x3195 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3195 3195 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x319e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 319e 0x319e typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR11:11 val_frame 11 3196 ; -------------------------------------------------------------------------------------- 3196 ; 0x03a6 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative 3196 ; -------------------------------------------------------------------------------------- 3196 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative: 3196 3196 dispatch_brk_class 4 ; Flow J cc=True 0x3195 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3196 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3195 0x3195 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3197 3197 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 3198 ; -------------------------------------------------------------------------------------- 3198 ; 0x03a4 Declare_Type Heap_Access,Incomplete,Values_Relative,With_Size 3198 ; -------------------------------------------------------------------------------------- 3198 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative,With_Size: 3198 3198 dispatch_brk_class 4 ; Flow J 0x3199 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3198 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3199 0x3199 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3199 3199 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a7 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 319a 319a fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x319e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_br_type 1 Branch True seq_branch_adr 319e 0x319e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 319b 319b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 319c ; -------------------------------------------------------------------------------------- 319c ; 0x03a7 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative,With_Size 319c ; -------------------------------------------------------------------------------------- 319c MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative,With_Size: 319c 319c dispatch_brk_class 4 ; Flow J cc=True 0x3199 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 319c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3199 0x3199 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 319d 319d seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 319e 319e fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 3b TR02:1b typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 319f 319f fiu_mem_start 4 continue ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 31a0 31a0 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 2c TR07:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 31a1 31a1 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 31a2 31a2 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 31a3 31a3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 31a4 ; -------------------------------------------------------------------------------------- 31a4 ; Comes from: 31a4 ; 31ae C False from color 0x0000 31a4 ; 31c2 C False from color 0x0000 31a4 ; 31d7 C False from color MACRO_Execute_Discrete,Remainder 31a4 ; 31e5 C False from color MACRO_Execute_Discrete,Remainder 31a4 ; 31f6 C False from color MACRO_Execute_Discrete,Remainder 31a4 ; 3202 C False from color MACRO_Execute_Discrete,Remainder 31a4 ; -------------------------------------------------------------------------------------- 31a4 31a4 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x31a4 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31a5 31a5 <halt> ; Flow R 31a6 ; -------------------------------------------------------------------------------------- 31a6 ; 0x0270 Execute Discrete,Divide 31a6 ; -------------------------------------------------------------------------------------- 31a6 MACRO_Execute_Discrete,Divide: 31a6 31a6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31a6 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31a7 31a7 fiu_load_var 1 hold_var; Flow J cc=True 0x31b6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31b6 0x31b6 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31a8 31a8 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31b1 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31b1 0x31b1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31a9 31a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31ab fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31ab 0x31ab seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31aa 31aa fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 31ab 31ab ioc_fiubs 1 val ; Flow J cc=False 0x31ae ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31ae 0x31ae typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31ac 31ac fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31ad 31ad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ae 31ae ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31a4 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31af 31af fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31b0 31b0 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31b1 31b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b2 31b2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31b3 31b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31ab fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31ab 0x31ab seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31b4 31b4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 31b5 31b5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 30 VR02:10 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 31b6 31b6 fiu_vmux_sel 1 fill value; Flow J cc=True 0x31ba ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31ba 0x31ba seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b7 31b7 fiu_load_var 1 hold_var; Flow J cc=True 0x31b2 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31b2 0x31b2 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b8 31b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31b9 31b9 fiu_load_oreg 1 hold_oreg; Flow J 0x31a9 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 31a9 0x31a9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31ba 31ba fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 31bb 0x31bb seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31bb 31bb seq_br_type 7 Unconditional Call; Flow C 0x3276 seq_branch_adr 3276 0x3276 seq_en_micro 0 seq_random 02 ? 31bc ; -------------------------------------------------------------------------------------- 31bc ; 0x0140 Execute Discrete,Divide_And_Scale 31bc ; -------------------------------------------------------------------------------------- 31bc MACRO_Execute_Discrete,Divide_And_Scale: 31bc 31bc dispatch_brk_class 8 ; Flow C cc=False 0x31c5 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 31bc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 31c5 0x31c5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31bd 31bd fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31c7 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 31c7 0x31c7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31be 31be fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 31bf 31bf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER 31c0 31c0 ioc_fiubs 0 fiu ; Flow J cc=True 0x31c9 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31c9 0x31c9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 31c1 31c1 fiu_load_var 1 hold_var; Flow J cc=True 0x31cd fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31cd 0x31cd seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_frame 2 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 31c2 31c2 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31a4 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31c3 31c3 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31cc fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31cc 0x31cc seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 31c4 31c4 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3276 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3276 0x3276 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31c5 ; -------------------------------------------------------------------------------------- 31c5 ; Comes from: 31c5 ; 31bc C False from color 0x0000 31c5 ; -------------------------------------------------------------------------------------- 31c5 31c5 seq_br_type 4 Call False; Flow C cc=False 0x3275 seq_branch_adr 3275 0x3275 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31c6 31c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA val_b_adr 01 GP01 31c7 ; -------------------------------------------------------------------------------------- 31c7 ; Comes from: 31c7 ; 31bd C False from color 0x0000 31c7 ; -------------------------------------------------------------------------------------- 31c7 31c7 seq_br_type 1 Branch True; Flow J cc=True 0x31c6 seq_branch_adr 31c6 0x31c6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31c8 31c8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31c9 31c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 31ca 31ca fiu_fill_mode_src 0 ; Flow J cc=True 0x31cd fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31cd 0x31cd seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 31cb 31cb fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31c4 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31c4 0x31c4 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 31cc 31cc fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3276 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3276 0x3276 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31cd 31cd fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3276 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3276 0x3276 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ce ; -------------------------------------------------------------------------------------- 31ce ; 0x026f Execute Discrete,Remainder 31ce ; -------------------------------------------------------------------------------------- 31ce MACRO_Execute_Discrete,Remainder: 31ce 31ce dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31ce ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31cf 31cf fiu_load_var 1 hold_var; Flow J cc=False 0x31dd fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31dd 0x31dd seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d0 31d0 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31d3 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d3 0x31d3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31d1 31d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d2 31d2 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31d3 31d3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31d6 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d6 0x31d6 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31d4 31d4 seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 31d5 31d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31d6 31d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x31dc seq_br_type 1 Branch True seq_branch_adr 31dc 0x31dc seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31d7 31d7 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a4 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31d8 31d8 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31d9 31d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31db fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31db 0x31db seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31da 31da fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 31db 31db fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31dc 31dc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31dd 31dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3208 seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31de 31de fiu_load_var 1 hold_var; Flow J cc=True 0x31e0 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e0 0x31e0 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31df 31df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e0 31e0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31e1 31e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31e4 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e4 0x31e4 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31e2 31e2 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 31e3 0x31e3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 31e3 31e3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 31e4 31e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x31ea seq_br_type 1 Branch True seq_branch_adr 31ea 0x31ea seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31e5 31e5 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a4 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31e6 31e6 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31e7 31e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31e9 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31e9 0x31e9 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31e8 31e8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 31e9 31e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ea 31ea val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31eb 31eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ec ; -------------------------------------------------------------------------------------- 31ec ; 0x026e Execute Discrete,Modulo 31ec ; -------------------------------------------------------------------------------------- 31ec MACRO_Execute_Discrete,Modulo: 31ec 31ec dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31ec ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ed 31ed fiu_load_var 1 hold_var; Flow J cc=False 0x31fb fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31fb 0x31fb seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ee 31ee fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31d3 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31d3 0x31d3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31ef 31ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275 seq_br_type 5 Call True seq_branch_adr 3275 0x3275 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31f0 31f0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31f1 31f1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31f5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31f5 0x31f5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31f2 31f2 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 31f3 31f3 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 31f4 0x31f4 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31f4 31f4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 31f5 31f5 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 31f6 31f6 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a4 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31f7 31f7 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3208 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 31f8 31f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x31fa fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 31fa 0x31fa seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31f9 31f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3208 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 31fa 31fa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31fb 31fb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3208 seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31fc 31fc fiu_load_var 1 hold_var; Flow J cc=False 0x31df fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31df 0x31df seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31fd 31fd fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31fe 31fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3201 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3201 0x3201 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 31ff 31ff fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3200 0x3200 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3200 3200 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 3201 3201 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3207 seq_br_type 1 Branch True seq_branch_adr 3207 0x3207 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3202 3202 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31a4 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31a4 0x31a4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 3203 3203 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3208 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 3204 3204 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3206 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3206 0x3206 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3205 3205 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3208 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 3206 3206 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3207 3207 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3208 3208 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3209 0x3209 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 3209 3209 seq_br_type 7 Unconditional Call; Flow C 0x3275 seq_branch_adr 3275 0x3275 seq_en_micro 0 seq_random 02 ? 320a ; -------------------------------------------------------------------------------------- 320a ; 0x7800-0x7fff Jump pcrel,>J 320a ; -------------------------------------------------------------------------------------- 320a MACRO_Jump_pcrel,>J: 320a 320a dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 320a 320b 320b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x321a seq_br_type 3 Unconditional Branch seq_branch_adr 321a 0x321a seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? 320c ; -------------------------------------------------------------------------------------- 320c ; 0x7000-0x77ff Jump_Nonzero pcrel,>JC 320c ; -------------------------------------------------------------------------------------- 320c MACRO_Jump_Nonzero_pcrel,>JC: 320c 320c dispatch_brk_class 1 ; Flow J 0x320f dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 320c seq_br_type 3 Unconditional Branch seq_branch_adr 320f 0x320f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 320d 320d <halt> ; Flow R 320e ; -------------------------------------------------------------------------------------- 320e ; 0x6800-0x6fff Jump_Zero pcrel,>JC 320e ; -------------------------------------------------------------------------------------- 320e MACRO_Jump_Zero_pcrel,>JC: 320e 320e dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 320e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 320f 320f fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3210 0x3210 seq_int_reads 0 TYP VAL BUS seq_random 40 Load_ibuff+Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3210 3210 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3211 0x3211 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 3211 3211 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3212 ; -------------------------------------------------------------------------------------- 3212 ; 0x4600-0x47ff Jump_Case case_max 3212 ; -------------------------------------------------------------------------------------- 3212 MACRO_Jump_Case_case_max: 3212 3212 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_uadr 3212 fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3d VR02:1d val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 3213 3213 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3214 3214 fiu_tivi_src c mar_0xc; Flow J cc=False 0x3219 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3219 0x3219 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3215 3215 ioc_tvbs 1 typ+fiu; Flow C 0x326d seq_br_type 7 Unconditional Call seq_branch_adr 326d 0x326d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 2 PUSH_CSA 3216 ; -------------------------------------------------------------------------------------- 3216 ; 0x00a7 Action Jump_Extended,abs,>J 3216 ; -------------------------------------------------------------------------------------- 3216 MACRO_Action_Jump_Extended,abs,>J: 3216 3216 dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3216 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3217 3217 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3218 3218 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? 3219 3219 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 321a 321a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 321b 321b <halt> ; Flow R 321c ; -------------------------------------------------------------------------------------- 321c ; 0x00a5 Action Jump_Nonzero_Extended,abs,>JC 321c ; -------------------------------------------------------------------------------------- 321c MACRO_Action_Jump_Nonzero_Extended,abs,>JC: 321c 321c dispatch_brk_class 1 ; Flow J 0x321f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 321c fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 321f 0x321f seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 321d 321d <halt> ; Flow R 321e ; -------------------------------------------------------------------------------------- 321e ; 0x00a6 Action Jump_Zero_Extended,abs,>JC 321e ; -------------------------------------------------------------------------------------- 321e MACRO_Action_Jump_Zero_Extended,abs,>JC: 321e 321e dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 321e fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 321f 321f fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3217 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3217 0x3217 seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3220 3220 seq_br_type 1 Branch True; Flow J cc=True 0x3219 seq_branch_adr 3219 0x3219 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 16 ? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 3221 3221 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3222 ; -------------------------------------------------------------------------------------- 3222 ; 0x009f Action Jump_Dynamic 3222 ; -------------------------------------------------------------------------------------- 3222 MACRO_Action_Jump_Dynamic: 3222 3222 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3222 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 3223 3223 fiu_tivi_src c mar_0xc; Flow J 0x3219 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3219 0x3219 seq_int_reads 0 TYP VAL BUS seq_random 59 ? 3224 ; -------------------------------------------------------------------------------------- 3224 ; 0x009d Action Jump_Nonzero_Dynamic 3224 ; -------------------------------------------------------------------------------------- 3224 MACRO_Action_Jump_Nonzero_Dynamic: 3224 3224 dispatch_brk_class 1 ; Flow J cc=False 0x3229 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3224 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 3229 0x3229 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3225 3225 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3219 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3219 0x3219 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 3226 3226 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3227 3227 <halt> ; Flow R 3228 ; -------------------------------------------------------------------------------------- 3228 ; 0x009e Action Jump_Zero_Dynamic 3228 ; -------------------------------------------------------------------------------------- 3228 MACRO_Action_Jump_Zero_Dynamic: 3228 3228 dispatch_brk_class 1 ; Flow J cc=True 0x3225 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3228 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3225 0x3225 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3229 3229 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3226 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3226 0x3226 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 322a ; -------------------------------------------------------------------------------------- 322a ; 0x3e00-0x3fff Loop_Increasing pcrelneg,>JC 322a ; -------------------------------------------------------------------------------------- 322a MACRO_Loop_Increasing_pcrelneg,>JC: 322a 322a dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 322a fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 322b 322b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x322d fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 322d 0x322d seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 322c 322c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 322d 322d fiu_tivi_src c mar_0xc; Flow J 0x3219 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3219 0x3219 seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 322e ; -------------------------------------------------------------------------------------- 322e ; 0x3600-0x37ff Loop_Decreasing pcrelneg,>JC 322e ; -------------------------------------------------------------------------------------- 322e MACRO_Loop_Decreasing_pcrelneg,>JC: 322e 322e dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 322e fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 322f 322f fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3231 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3231 0x3231 seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 3230 3230 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3231 3231 fiu_tivi_src c mar_0xc; Flow J 0x3219 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3219 0x3219 seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 3232 ; -------------------------------------------------------------------------------------- 3232 ; 0x00a4 Action Loop_Increasing_Extended,abs,>JC 3232 ; -------------------------------------------------------------------------------------- 3232 MACRO_Action_Loop_Increasing_Extended,abs,>JC: 3232 3232 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3232 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3233 3233 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3234 3234 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 3235 3235 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x322d fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 322d 0x322d seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 3236 3236 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3237 3237 <halt> ; Flow R 3238 ; -------------------------------------------------------------------------------------- 3238 ; 0x00a3 Action Loop_Decreasing_Extended,abs,>JC 3238 ; -------------------------------------------------------------------------------------- 3238 MACRO_Action_Loop_Decreasing_Extended,abs,>JC: 3238 3238 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3238 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3239 3239 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 323a 323a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 323b 323b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3231 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3231 0x3231 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 323c 323c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 323d ; -------------------------------------------------------------------------------------- 323d ; Comes from: 323d ; 0a7f C from color 0x0a74 323d ; 0a93 C from color 0x0a88 323d ; 0aa6 C from color 0x0a9c 323d ; 1209 C from color 0x10bf 323d ; 120d C from color 0x10d4 323d ; 122a C from color 0x11ff 323d ; 1437 C from color 0x09aa 323d ; 14ef C from color 0x14ef 323d ; 169c C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 323d ; 1743 C from color 0x09ac 323d ; 17a1 C from color 0x0a30 323d ; 17af C from color 0x0a7a 323d ; 17b3 C from color 0x0a8e 323d ; 17b7 C from color MACRO_Execute_Variant_Record,Check_In_Type 323d ; 17bd C from color 0x0aa2 323d ; 1815 C from color 0x1815 323d ; 1819 C from color 0x09a9 323d ; 19ba C from color 0x19b7 323d ; 1ac1 C from color 0x0a9f 323d ; 1b43 C from color 0x09a6 323d ; 1bd1 C from color 0x0a9e 323d ; 1db1 C from color 0x1d37 323d ; 1e40 C False from color MACRO_Execute_Matrix,Structure_Write 323d ; 1e44 C False from color MACRO_Execute_Matrix,Structure_Write 323d ; 1e79 C from color 0x1e79 323d ; 239c C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 323d ; 23b0 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 323d ; 2488 C from color 0x2488 323d ; 2492 C from color 0x2488 323d ; -------------------------------------------------------------------------------------- 323d 323d seq_en_micro 0 typ_c_adr 36 GP09 323e 323e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3277 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 323f 323f ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3240 0x3240 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3240 3240 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3277 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3241 3241 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3242 ; -------------------------------------------------------------------------------------- 3242 ; Comes from: 3242 ; 0503 C from color 0x04fa 3242 ; 1f73 C from color 0x1f69 3242 ; 2200 C from color 0x21f6 3242 ; -------------------------------------------------------------------------------------- 3242 3242 seq_en_micro 0 typ_c_adr 36 GP09 3243 3243 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3247 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3247 0x3247 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3244 3244 ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3245 0x3245 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3245 3245 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3247 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3247 0x3247 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3246 3246 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3247 3247 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3277 seq_br_type 9 Return False seq_branch_adr 3277 0x3277 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0c GP0c 3248 ; -------------------------------------------------------------------------------------- 3248 ; 0x0001-0x0006 Illegal - 3248 ; 0x0009-0x000f Illegal - 3248 ; -------------------------------------------------------------------------------------- 3248 MACRO_Illegal_-: 3248 3248 dispatch_brk_class f ; Flow C 0x32ab dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3248 seq_br_type 7 Unconditional Call seq_branch_adr 32ab 0x32ab 3249 3249 <halt> ; Flow R 324a ; -------------------------------------------------------------------------------------- 324a ; 0x0007 Action Break_Optional 324a ; -------------------------------------------------------------------------------------- 324a MACRO_Action_Break_Optional: 324a 324a dispatch_brk_class 7 ; Flow R dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 324a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 324b 324b <halt> ; Flow R 324c ; -------------------------------------------------------------------------------------- 324c ; 0x0107 Execute Exception,Get_Name 324c ; -------------------------------------------------------------------------------------- 324c MACRO_Execute_Exception,Get_Name: 324c 324c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 324c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 1c ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 324d 324d <halt> ; Flow R 324e ; -------------------------------------------------------------------------------------- 324e ; 0x0106 Execute Exception,Address 324e ; -------------------------------------------------------------------------------------- 324e MACRO_Execute_Exception,Address: 324e 324e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 324e fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 324f 324f fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value val_alu_func 1e A_AND_B val_b_adr 37 VR0d:17 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame d 3250 3250 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3251 3251 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3253 seq_br_type 1 Branch True seq_branch_adr 3253 0x3253 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3252 3252 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 3253 3253 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3254 ; -------------------------------------------------------------------------------------- 3254 ; 0x010e Execute Exception,Is_Constraint_Error 3254 ; -------------------------------------------------------------------------------------- 3254 MACRO_Execute_Exception,Is_Constraint_Error: 3254 3254 dispatch_brk_class 8 ; Flow J 0x3255 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3254 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3252 0x3252 typ_alu_func 1a PASS_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2d VR1b:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 1b 3255 3255 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3251 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3251 0x3251 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2c VR08:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3256 ; -------------------------------------------------------------------------------------- 3256 ; 0x010d Execute Exception,Is_Numeric_Error 3256 ; -------------------------------------------------------------------------------------- 3256 MACRO_Execute_Exception,Is_Numeric_Error: 3256 3256 dispatch_brk_class 8 ; Flow J 0x3257 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3256 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3252 0x3252 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 35 VR08:15 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 3257 3257 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3251 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3251 0x3251 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2d VR08:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3258 ; -------------------------------------------------------------------------------------- 3258 ; 0x010c Execute Exception,Is_Program_Error 3258 ; -------------------------------------------------------------------------------------- 3258 MACRO_Execute_Exception,Is_Program_Error: 3258 3258 dispatch_brk_class 8 ; Flow J 0x3259 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3258 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3252 0x3252 typ_alu_func 1a PASS_B typ_b_adr 30 TR11:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 3259 3259 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3251 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3251 0x3251 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2e VR08:0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325a ; -------------------------------------------------------------------------------------- 325a ; 0x010b Execute Exception,Is_Storage_Error 325a ; -------------------------------------------------------------------------------------- 325a MACRO_Execute_Exception,Is_Storage_Error: 325a 325a dispatch_brk_class 8 ; Flow J 0x325b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3252 0x3252 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 36 VR08:16 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 325b 325b ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3251 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3251 0x3251 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2f VR08:0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325c ; -------------------------------------------------------------------------------------- 325c ; 0x010a Execute Exception,Is_Tasking_Error 325c ; -------------------------------------------------------------------------------------- 325c MACRO_Execute_Exception,Is_Tasking_Error: 325c 325c dispatch_brk_class 8 ; Flow J 0x325d dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3252 0x3252 typ_alu_func 1a PASS_B typ_b_adr 2d TR08:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 37 VR08:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 325d 325d ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3251 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3251 0x3251 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 30 VR08:10 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 325e ; -------------------------------------------------------------------------------------- 325e ; 0x0109 Execute Exception,Is_Instruction_Error 325e ; -------------------------------------------------------------------------------------- 325e MACRO_Execute_Exception,Is_Instruction_Error: 325e 325e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 325e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 325f 325f ioc_fiubs 0 fiu ; Flow J 0x3251 seq_br_type 3 Unconditional Branch seq_branch_adr 3251 0x3251 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3260 ; -------------------------------------------------------------------------------------- 3260 ; 0x010f Execute Exception,Equal 3260 ; -------------------------------------------------------------------------------------- 3260 MACRO_Execute_Exception,Equal: 3260 3260 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3260 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 3261 3261 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 3262 ; -------------------------------------------------------------------------------------- 3262 ; 0x0257 Execute Discrete,Raise,>R 3262 ; -------------------------------------------------------------------------------------- 3262 MACRO_Execute_Discrete,Raise,>R: 3262 3262 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3262 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 3263 3263 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3264 3264 seq_br_type 7 Unconditional Call; Flow C 0x32c4 seq_branch_adr 32c4 0x32c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 3265 3265 <halt> ; Flow R 3266 ; -------------------------------------------------------------------------------------- 3266 ; 0x0800-0x08ff Execute_Immediate Raise,uimmediate,>R 3266 ; -------------------------------------------------------------------------------------- 3266 MACRO_Execute_Immediate_Raise,uimmediate,>R: 3266 3266 dispatch_brk_class 1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 3266 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3267 3267 ioc_fiubs 1 val ; Flow C 0x32c4 seq_br_type 7 Unconditional Call seq_branch_adr 32c4 0x32c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 3268 ; -------------------------------------------------------------------------------------- 3268 ; Comes from: 3268 ; 397e C from color 0x3972 3268 ; -------------------------------------------------------------------------------------- 3268 3268 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3269 3269 ioc_fiubs 1 val ; Flow J 0x32c4 seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 326a ; -------------------------------------------------------------------------------------- 326a ; Comes from: 326a ; 0342 C from color MACRO_Action_Increase_Priority 326a ; 1d2f C from color 0x1d2f 326a ; 1d31 C from color 0x1d31 326a ; -------------------------------------------------------------------------------------- 326a 326a fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR09:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 326b 326b fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 326c ; -------------------------------------------------------------------------------------- 326c ; Comes from: 326c ; 0328 C True from color MACRO_Action_Set_Priority 326c ; 090a C True from color 0x0905 326c ; 0e41 C False from color 0x0d34 326c ; 0e43 C False from color 0x0d34 326c ; 0e59 C True from color 0x0e59 326c ; 0ee3 C True from color 0x0ee3 326c ; 112d C False from color 0x110d 326c ; 1138 C False from color 0x110d 326c ; 113b C True from color 0x110d 326c ; 1d74 C from color 0x1d28 326c ; 1d84 C True from color 0x1d28 326c ; 1d85 C from color 0x1d28 326c ; 2375 C True from color 0x236f 326c ; 2417 C True from color 0x2413 326c ; 2825 C from color 0x0a29 326c ; 293e C False from color MACRO_Action_Push_String_Extended,pse 326c ; 2c9e C True from color MACRO_Execute_Select,Timed_Duration_Write 326c ; 2fcb C True from color MACRO_Execute_Any,Convert 326c ; 2fd1 C from color MACRO_Execute_Any,Convert 326c ; 2fd3 C True from color MACRO_Execute_Any,Convert 326c ; 2ff0 C False from color MACRO_Execute_Any,Convert 326c ; 304c C True from color MACRO_Execute_Any,Convert 326c ; 304d C True from color MACRO_Execute_Any,Convert 326c ; 3051 C True from color MACRO_Execute_Any,Convert 326c ; 3052 C True from color MACRO_Execute_Any,Convert 326c ; 3055 C from color MACRO_Execute_Any,Convert 326c ; 316c C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 326c ; 35d4 C False from color 0x35c5 326c ; 35d9 C False from color 0x35d9 326c ; -------------------------------------------------------------------------------------- 326c 326c fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 326d ; -------------------------------------------------------------------------------------- 326d ; Comes from: 326d ; 3215 C from color MACRO_Execute_Discrete,Remainder 326d ; -------------------------------------------------------------------------------------- 326d 326d fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 326e 326e fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 326f ; -------------------------------------------------------------------------------------- 326f ; Comes from: 326f ; 0c1e C True from color MACRO_Execute_Heap_Access,Element_Type 326f ; 0c2e C True from color MACRO_Execute_Heap_Access,All_Reference 326f ; 1ade C True from color MACRO_Execute_Access,Element_Type 326f ; 1aee C True from color MACRO_Execute_Access,All_Reference 326f ; -------------------------------------------------------------------------------------- 326f 326f fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 3270 ; -------------------------------------------------------------------------------------- 3270 ; Comes from: 3270 ; 0508 C from color 0x04fa 3270 ; 0c4c C from color 0x0a33 3270 ; 1145 C False from color 0x110d 3270 ; 1173 C True from color 0x111b 3270 ; 1177 C from color 0x111b 3270 ; 117a C True from color 0x111b 3270 ; 117b C True from color 0x111b 3270 ; 1193 C False from color 0x111b 3270 ; 11b8 C from color 0x111b 3270 ; 11bd C False from color 0x111b 3270 ; 11c7 C False from color 0x111b 3270 ; 1212 C False from color 0x10d4 3270 ; 1216 C from color 0x10d4 3270 ; 1237 C True from color 0x11ff 3270 ; 127a C False from color 0x10d4 3270 ; 12a5 C True from color 0x125d 3270 ; 12a6 C True from color 0x125d 3270 ; 1381 C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 1382 C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 13a7 C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 13a8 C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 13cc C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 13cd C False from color MACRO_Declare_Variable_Array,With_Constraint 3270 ; 1417 C True from color 0x140f 3270 ; 141a C True from color 0x140f 3270 ; 1429 C True from color 0x140f 3270 ; 14b9 C from color 0x0aa0 3270 ; 1534 C True from color 0x152f 3270 ; 153b C True from color 0x152f 3270 ; 1544 C True from color 0x152f 3270 ; 154c C True from color 0x152f 3270 ; 15e7 C True from color MACRO_Execute_Matrix,Subarray 3270 ; 15ea C True from color MACRO_Execute_Matrix,Subarray 3270 ; 16b2 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 3270 ; 1711 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3270 ; 1712 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 3270 ; 18b0 C True from color MACRO_Execute_Vector,Field_Read 3270 ; 18b9 C from color MACRO_Execute_Vector,Field_Read 3270 ; 18be C True from color MACRO_Execute_Vector,Field_Read 3270 ; 18c0 C True from color MACRO_Execute_Vector,Field_Read 3270 ; 18e2 C from color MACRO_Execute_Vector,Field_Reference 3270 ; 18ec C False from color MACRO_Execute_Vector,Field_Reference 3270 ; 18f2 C False from color MACRO_Execute_Vector,Field_Reference 3270 ; 196b C False from color MACRO_Execute_Vector,Slice_Read 3270 ; 196c C True from color MACRO_Execute_Vector,Slice_Read 3270 ; 199a C False from color MACRO_Execute_Vector,Slice_Write 3270 ; 199b C True from color MACRO_Execute_Vector,Slice_Write 3270 ; 19e8 C True from color MACRO_Execute_Vector,Catenate 3270 ; 1a5b C True from color 0x0a2d 3270 ; 1a9d C from color 0x0a2d 3270 ; 1aba C from color 0x0a9f 3270 ; 1abc C False from color 0x0a9f 3270 ; 1ac0 C from color 0x0a9f 3270 ; 1b0b C from color 0x0a31 3270 ; 1bc6 C from color 0x0a9e 3270 ; 1bc9 C from color 0x0a9e 3270 ; 1bcd C from color 0x0a9e 3270 ; 1bd0 C from color 0x0a9e 3270 ; 1c89 C True from color MACRO_Execute_Array,Subarray 3270 ; 1d90 C from color 0x1d28 3270 ; 1f78 C from color 0x1f69 3270 ; 1f8e C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1f92 C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1fad C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1fb1 C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1fb6 C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1fc3 C False from color 0x1fc3 3270 ; 1ff0 C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 1ff1 C True from color MACRO_Complete_Type_Array,By_Constraining 3270 ; 2149 C True from color MACRO_Declare_Type_Array,Constrained 3270 ; 214d C True from color MACRO_Declare_Type_Array,Constrained 3270 ; 2152 C True from color MACRO_Declare_Type_Array,Constrained 3270 ; 215f C True from color 0x215f 3270 ; 218f C True from color MACRO_Declare_Type_Array,Constrained 3270 ; 2190 C True from color MACRO_Declare_Type_Array,Constrained 3270 ; 2205 C from color 0x21f6 3270 ; -------------------------------------------------------------------------------------- 3270 3270 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3271 ; -------------------------------------------------------------------------------------- 3271 ; Comes from: 3271 ; 190d C True from color MACRO_Execute_Vector,And 3271 ; 19a0 C True from color MACRO_Execute_Vector,Slice_Write 3271 ; 19af C True from color MACRO_Execute_Vector,Slice_Write 3271 ; 19b3 C True from color MACRO_Execute_Vector,Slice_Write 3271 ; 19c3 C True from color MACRO_Execute_Vector,Slice_Reference 3271 ; 19c5 C True from color MACRO_Execute_Vector,Slice_Reference 3271 ; 1e45 C False from color MACRO_Execute_Matrix,Structure_Write 3271 ; 1e46 C False from color MACRO_Execute_Matrix,Structure_Write 3271 ; -------------------------------------------------------------------------------------- 3271 3271 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3272 ; -------------------------------------------------------------------------------------- 3272 ; Comes from: 3272 ; 0c4b C True from color 0x0a33 3272 ; 116c C from color 0x1169 3272 ; 131e C True from color 0x1314 3272 ; 179f C False from color 0x0a30 3272 ; 17ba C from color MACRO_Execute_Variant_Record,Check_In_Type 3272 ; 17bf C True from color 0x0aa2 3272 ; 1b0a C True from color 0x0a31 3272 ; 1d8f C True from color 0x1d28 3272 ; 24f6 C from color 0x2488 3272 ; -------------------------------------------------------------------------------------- 3272 3272 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3273 ; -------------------------------------------------------------------------------------- 3273 ; Comes from: 3273 ; 1144 C True from color 0x110d 3273 ; 12de C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3273 ; 12e0 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3273 ; -------------------------------------------------------------------------------------- 3273 3273 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR05:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3274 ; -------------------------------------------------------------------------------------- 3274 ; Comes from: 3274 ; 2c7b C False from color MACRO_Execute_Select,Member_Write,fieldnum 3274 ; 2c7e C True from color MACRO_Execute_Select,Member_Write,fieldnum 3274 ; 2c81 C False from color 0x2c80 3274 ; 2c87 C True from color MACRO_Execute_Select,Member_Write,fieldnum 3274 ; 2c8b C from color MACRO_Execute_Select,Member_Write,fieldnum 3274 ; 2c8e C from color MACRO_Execute_Select,Member_Write,fieldnum 3274 ; 3821 C True from color 0x37ff 3274 ; -------------------------------------------------------------------------------------- 3274 3274 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3275 ; -------------------------------------------------------------------------------------- 3275 ; Comes from: 3275 ; 28ae C True from color MACRO_Execute_Float,Exponentiate 3275 ; 31c5 C False from color 0x31c5 3275 ; 31d1 C True from color MACRO_Execute_Discrete,Remainder 3275 ; 31df C True from color MACRO_Execute_Discrete,Remainder 3275 ; 31ef C True from color MACRO_Execute_Discrete,Remainder 3275 ; 3209 C from color MACRO_Execute_Discrete,Remainder 3275 ; -------------------------------------------------------------------------------------- 3275 3275 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3276 ; -------------------------------------------------------------------------------------- 3276 ; Comes from: 3276 ; 112e C from color 0x110d 3276 ; 1139 C from color 0x110d 3276 ; 113a C True from color 0x110d 3276 ; 113c C from color 0x110d 3276 ; 201a C False from color 0x2010 3276 ; 201b C False from color 0x2010 3276 ; 2035 C False from color 0x2010 3276 ; 2036 C False from color 0x2010 3276 ; 204d C False from color 0x2010 3276 ; 204e C False from color 0x2010 3276 ; 2088 C False from color 0x2010 3276 ; 2089 C False from color 0x2010 3276 ; 20be C False from color 0x2010 3276 ; 20bf C False from color 0x2010 3276 ; 20d3 C False from color 0x2010 3276 ; 20f3 C False from color 0x2010 3276 ; 20f4 C False from color 0x2010 3276 ; 27e3 C False from color 0x27e3 3276 ; 2830 C True from color 0x0a29 3276 ; 2880 C True from color MACRO_Execute_Float,Times 3276 ; 28a7 C from color MACRO_Execute_Float,Exponentiate 3276 ; 28ba C True from color MACRO_Execute_Float,Exponentiate 3276 ; 28bb C True from color MACRO_Execute_Float,Exponentiate 3276 ; 28c0 C False from color MACRO_Execute_Float,Exponentiate 3276 ; 28ca C True from color MACRO_Execute_Float,Exponentiate 3276 ; 28e1 C from color MACRO_Execute_Float,Truncate_To_Discrete 3276 ; 2fb7 C from color MACRO_Execute_Discrete,Unary_Minus 3276 ; 2fbb C from color MACRO_Execute_Discrete,Plus 3276 ; 2fbd C from color MACRO_Execute_Discrete,Plus 3276 ; 2fbf C from color MACRO_Execute_Discrete,Plus 3276 ; 2fc1 C from color MACRO_Execute_Discrete,Plus 3276 ; 2ff1 C from color MACRO_Execute_Any,Convert 3276 ; 316d C from color MACRO_Execute_Immediate_Set_Value,uimmediate 3276 ; -------------------------------------------------------------------------------------- 3276 3276 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR07:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3277 ; -------------------------------------------------------------------------------------- 3277 ; Comes from: 3277 ; 0221 C False from color MACRO_Action_Accept_Activation 3277 ; 0224 C False from color MACRO_Action_Accept_Activation 3277 ; 09ce C from color MACRO_Execute_Any,Size 3277 ; 09d2 C from color MACRO_Execute_Any,Size 3277 ; 09e3 C True from color MACRO_Execute_Any,Size 3277 ; 0a16 C True from color MACRO_Execute_Any,Make_Root_Type 3277 ; 0a1b C True from color MACRO_Execute_Any,Make_Root_Type 3277 ; 0a6c C True from color 0x0a4e 3277 ; 0c10 C True from color 0x0c05 3277 ; 109d C from color 0x1097 3277 ; 10a4 C from color 0x1097 3277 ; 119b C True from color 0x1198 3277 ; 11ca C True from color 0x111b 3277 ; 12ca C True from color 0x098a 3277 ; 12d8 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 3277 ; 1310 C True from color MACRO_Declare_Variable_Variant_Record,Duplicate 3277 ; 1392 C True from color MACRO_Declare_Variable_Array,With_Constraint 3277 ; 13b5 C True from color MACRO_Declare_Variable_Array,With_Constraint 3277 ; 1434 C False from color MACRO_Declare_Variable_Array,With_Constraint 3277 ; 1449 C True from color 0x09aa 3277 ; 145d C True from color 0x09aa 3277 ; 17aa C True from color 0x17a9 3277 ; 17ac C True from color 0x17a9 3277 ; 17e8 C from color MACRO_Execute_Record,Field_Type,fieldnum 3277 ; 17ec C from color MACRO_Execute_Record,Field_Type_Dynamic 3277 ; 1809 C True from color 0x0a2f 3277 ; 180b C True from color 0x0a2f 3277 ; 1825 C True from color 0x09a9 3277 ; 1831 C True from color 0x09a9 3277 ; 19d8 C True from color MACRO_Execute_Vector,Catenate 3277 ; 1a5c C True from color 0x0a2d 3277 ; 1a74 C True from color 0x0a2d 3277 ; 1a76 C True from color 0x0a2d 3277 ; 1a8a C True from color 0x0a2d 3277 ; 1b4e C True from color 0x09a6 3277 ; 1b5f C True from color 0x09a6 3277 ; 1b61 C True from color 0x09a6 3277 ; 1c2c C True from color 0x1c25 3277 ; 1e92 C False from color MACRO_Declare_Type_Record,Defined 3277 ; 1e94 C False from color MACRO_Declare_Type_Record,Defined 3277 ; 1ea0 C False from color MACRO_Declare_Type_Record,Incomplete 3277 ; 1ea4 C True from color MACRO_Complete_Type_Record,By_Defining 3277 ; 1eb2 C True from color MACRO_Complete_Type_Record,By_Renaming 3277 ; 1eb7 C True from color MACRO_Complete_Type_Record,By_Renaming 3277 ; 1ee7 C True from color MACRO_Declare_Variable_Record,Duplicate 3277 ; 1f52 C False from color MACRO_Declare_Type_Access,Constrained 3277 ; 1f56 C False from color MACRO_Declare_Type_Access,Constrained 3277 ; 1f5b C True from color MACRO_Declare_Type_Access,Constrained 3277 ; 1f83 C from color MACRO_Complete_Type_Array,By_Constraining 3277 ; 1f99 C from color 0x1f97 3277 ; 1f9d C from color 0x1f9c 3277 ; 200d C True from color MACRO_Complete_Type_Array,By_Defining 3277 ; 209a C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 3277 ; 20a2 C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 3277 ; 20cc C True from color 0x2010 3277 ; 2112 C False from color MACRO_Declare_Type_Array,Defined,Visible 3277 ; 2116 C from color 0x2010 3277 ; 211b C from color 0x2010 3277 ; 211c C False from color 0x2010 3277 ; 2120 C from color 0x2010 3277 ; 2135 C from color 0x2133 3277 ; 2139 C from color 0x2138 3277 ; 21ae C False from color MACRO_Declare_Type_Array,Constrained 3277 ; 21b0 C False from color MACRO_Declare_Type_Array,Constrained 3277 ; 21b6 C False from color MACRO_Declare_Type_Array,Constrained 3277 ; 21b8 C False from color MACRO_Declare_Type_Array,Constrained 3277 ; 21d8 C True from color 0x2003 3277 ; 21e8 C True from color 0x2003 3277 ; 220a C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 3277 ; 220c C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 3277 ; 2214 C from color 0x2003 3277 ; 2304 C False from color MACRO_Declare_Type_Array,Incomplete 3277 ; 2308 C False from color MACRO_Declare_Type_Array,Incomplete 3277 ; 2313 C True from color MACRO_Complete_Type_Array,By_Component_Completion 3277 ; 2331 C True from color MACRO_Complete_Type_Array,By_Renaming 3277 ; 2333 C True from color MACRO_Complete_Type_Array,By_Renaming 3277 ; 239b C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3277 ; 23c4 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3277 ; 23c6 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 3277 ; 23f0 C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 3277 ; 23f5 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 3277 ; 2502 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3277 ; 2517 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3277 ; 2520 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 3277 ; 252f C True from color MACRO_Complete_Type_Variant_Record,By_Defining 3277 ; 25e6 C from color 0x25df 3277 ; 262b C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 3277 ; 2630 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 3277 ; 263a C False from color 0x263a 3277 ; 2651 C True from color 0x263a 3277 ; 26e1 C from color 0x26e0 3277 ; 2747 C False from color MACRO_Declare_Variable_Entry 3277 ; 274b C False from color MACRO_Declare_Variable_Entry 3277 ; 28fe C True from color MACRO_Execute_Float,Write_Unchecked 3277 ; 2cb6 C from color MACRO_Declare_Subprogram_For_Call,subp 3277 ; 2fcf C True from color MACRO_Execute_Any,Convert 3277 ; 2fef C True from color MACRO_Execute_Any,Convert 3277 ; 2ffe C True from color MACRO_Execute_Discrete,Write_Unchecked 3277 ; 3010 C True from color MACRO_Execute_Discrete,Test_And_Set_Previous 3277 ; 30af C True from color MACRO_Complete_Type_Float,By_Defining 3277 ; 30b3 C True from color MACRO_Complete_Type_Float,By_Defining 3277 ; 30bb C True from color MACRO_Complete_Type_Float,By_Defining 3277 ; 30bc C True from color MACRO_Complete_Type_Float,By_Defining 3277 ; 316b C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 3277 ; -------------------------------------------------------------------------------------- 3277 3277 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR08:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 3278 3278 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR05:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3279 3279 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR06:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 327a ; -------------------------------------------------------------------------------------- 327a ; Comes from: 327a ; 0f21 C True from color 0x0ef8 327a ; -------------------------------------------------------------------------------------- 327a 327a fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 05 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 327b 327b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3770 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 0 Branch False seq_branch_adr 3770 0x3770 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 20 VR0d:00 val_frame d 327c 327c ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 327d 327d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x327f seq_br_type 1 Branch True seq_branch_adr 327f 0x327f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 3b TR05:1b typ_frame 5 327e 327e seq_br_type 3 Unconditional Branch; Flow J 0x327d seq_branch_adr 327d 0x327d seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand 0 NO_OP 327f 327f fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 3280 3280 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 3281 3281 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3282 3282 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 14 ZEROS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 3283 3283 ioc_tvbs 2 fiu+val; Flow J cc=True 0x328a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 328a 0x328a seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3284 3284 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3285 3285 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6a ? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 2a TR08:0a typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 8 typ_rand 6 CHECK_CLASS_A_??_B 3286 3286 ioc_fiubs 2 typ ; Flow J cc=True 0x328c seq_br_type 1 Branch True seq_branch_adr 328c 0x328c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 3287 3287 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 3288 3288 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 3289 3289 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x32ef fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32ef 0x32ef seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 328a 328a ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 3e TR09:1e typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 9 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 328b 328b seq_br_type 3 Unconditional Branch; Flow J 0x32c6 seq_branch_adr 32c6 0x32c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_csa_cntl 7 FINISH_POP_DOWN 328c 328c fiu_load_tar 1 hold_tar; Flow C cc=False 0x3296 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3296 0x3296 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 328d 328d fiu_mem_start 4 continue ioc_tvbs 2 fiu+val seq_random 0a ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 328e 328e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 328f 328f ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3290 3290 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 3291 3291 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3292 3292 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3293 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 328c 0x328c seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 3293 3293 ioc_fiubs 2 typ ; Flow J cc=True 0x328a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 328a 0x328a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 0f Load_control_top+? typ_a_adr 02 GP02 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3294 3294 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3287 seq_br_type 0 Branch False seq_branch_adr 3287 0x3287 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 val_b_adr 03 GP03 3295 3295 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 3296 ; -------------------------------------------------------------------------------------- 3296 ; Comes from: 3296 ; 328c C False from color 0x0000 3296 ; -------------------------------------------------------------------------------------- 3296 3296 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3297 3297 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3298 3298 seq_br_type 3 Unconditional Branch; Flow J 0x327f seq_branch_adr 327f 0x327f typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3299 ; -------------------------------------------------------------------------------------- 3299 ; Comes from: 3299 ; 0f31 C True from color 0x0ef8 3299 ; 2042 C True from color 0x2010 3299 ; 20e8 C True from color 0x2010 3299 ; -------------------------------------------------------------------------------------- 3299 3299 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR06:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 329a ; -------------------------------------------------------------------------------------- 329a ; Comes from: 329a ; 0f44 C True from color 0x0ef8 329a ; 12c9 C False from color 0x098a 329a ; 12cf C from color 0x098a 329a ; 12d7 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 329a ; 12e4 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 329a ; 130f C False from color MACRO_Declare_Variable_Variant_Record,Duplicate 329a ; 1391 C from color MACRO_Declare_Variable_Array,With_Constraint 329a ; 1398 C False from color 0x1397 329a ; 13e6 C from color MACRO_Declare_Variable_Array,With_Constraint 329a ; 13ea C False from color MACRO_Declare_Variable_Array,With_Constraint 329a ; 13f3 C False from color MACRO_Declare_Variable_Array,With_Constraint 329a ; 1406 C from color MACRO_Declare_Variable_Array,With_Constraint 329a ; 140c C from color 0x140a 329a ; 17ab C from color 0x17a9 329a ; 180a C from color 0x0a2f 329a ; 196a C False from color MACRO_Execute_Vector,Slice_Read 329a ; 1977 C from color MACRO_Execute_Vector,Slice_Read 329a ; 197b C False from color MACRO_Execute_Vector,Slice_Read 329a ; 1985 C False from color MACRO_Execute_Vector,Slice_Read 329a ; 1a5f C False from color 0x0a2d 329a ; 1a79 C False from color 0x0a2d 329a ; 1a7b C False from color 0x0a2d 329a ; 1a91 C False from color 0x0a2d 329a ; 1c34 C False from color 0x1c25 329a ; 1c35 C False from color 0x1c25 329a ; 1ee8 C False from color MACRO_Declare_Variable_Record,Duplicate 329a ; 272c C True from color 0x26fa 329a ; 2737 C True from color 0x26fa 329a ; -------------------------------------------------------------------------------------- 329a 329a fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR06:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 329b 329b fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR07:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 329c ; -------------------------------------------------------------------------------------- 329c ; Comes from: 329c ; 0f3a C True from color 0x0ef8 329c ; -------------------------------------------------------------------------------------- 329c 329c fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR07:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 329d 329d fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR07:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 329e ; -------------------------------------------------------------------------------------- 329e ; Comes from: 329e ; 3517 C from color 0x3517 329e ; -------------------------------------------------------------------------------------- 329e 329e fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR09:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 329f 329f fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR13:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 32a0 ; -------------------------------------------------------------------------------------- 32a0 ; Comes from: 32a0 ; 10d2 C from color 0x10d2 32a0 ; 11c0 C False from color 0x111b 32a0 ; 11cb C False from color 0x111b 32a0 ; 1230 C False from color 0x11ff 32a0 ; 12ce C True from color 0x098a 32a0 ; 12e3 C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a0 ; 138a C from color MACRO_Declare_Variable_Array,With_Constraint 32a0 ; 13d4 C from color MACRO_Declare_Variable_Array,With_Constraint 32a0 ; 1405 C True from color MACRO_Declare_Variable_Array,With_Constraint 32a0 ; 140b C True from color 0x140a 32a0 ; -------------------------------------------------------------------------------------- 32a0 32a0 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a1 32a1 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR08:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32a2 ; -------------------------------------------------------------------------------------- 32a2 ; Comes from: 32a2 ; 0215 C True from color MACRO_Action_Accept_Activation 32a2 ; 0217 C True from color MACRO_Action_Accept_Activation 32a2 ; 022c C True from color MACRO_Action_Signal_Activated 32a2 ; 0230 C from color MACRO_Action_Signal_Activated 32a2 ; 3946 C True from color 0x0913 32a2 ; 3952 C True from color 0x06b6 32a2 ; 3964 C False from color 0x03fa 32a2 ; -------------------------------------------------------------------------------------- 32a2 32a2 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a3 32a3 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR09:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a4 32a4 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32a5 ; -------------------------------------------------------------------------------------- 32a5 ; Comes from: 32a5 ; 01a9 C from color UE_CLASS 32a5 ; 054f C True from color MACRO_Action_Pop_Auxiliary 32a5 ; 055a C False from color MACRO_Action_Pop_Auxiliary_Range 32a5 ; 090c C True from color 0x0905 32a5 ; 0917 C True from color 0x0917 32a5 ; 0950 C True from color MACRO_Execute_Module,Is_Callable 32a5 ; 095e C True from color MACRO_Execute_Module,Is_Callable 32a5 ; 096d C from color MACRO_0966_QQUnknown_InMicrocode 32a5 ; 0981 C from color MACRO_Declare_Variable_Any 32a5 ; 0991 C from color MACRO_Declare_Variable_Any,Visible 32a5 ; 09a3 C from color MACRO_Execute_Any,Equal 32a5 ; 09a6 C from color 0x09a6 32a5 ; 09a7 C from color 0x09a6 32a5 ; 09b3 C from color MACRO_Execute_Any,Not_Equal 32a5 ; 09b6 C from color 0x09a6 32a5 ; 09b7 C from color 0x09a6 32a5 ; 09c8 C True from color MACRO_Execute_Any,Address_Of_Type 32a5 ; 09cb C True from color MACRO_Execute_Any,Size 32a5 ; 09f6 C True from color MACRO_Execute_Any,Change_Utility 32a5 ; 09f8 C False from color MACRO_Execute_Any,Change_Utility 32a5 ; 09fa C True from color MACRO_Execute_Any,Change_Utility 32a5 ; 0a01 C from color MACRO_Execute_Any,Make_Visible 32a5 ; 0a03 C from color MACRO_Execute_Any,Make_Visible 32a5 ; 0a08 C from color MACRO_Execute_Any,Make_Visible 32a5 ; 0a14 C True from color MACRO_Execute_Any,Make_Root_Type 32a5 ; 0a15 C False from color MACRO_Execute_Any,Make_Root_Type 32a5 ; 0a1d C from color 0x0a1d 32a5 ; 0a20 C True from color MACRO_Execute_Any,Is_Value 32a5 ; 0a22 C True from color MACRO_Execute_Any,Is_Scalar 32a5 ; 0a27 C from color MACRO_Execute_Any,Convert 32a5 ; 0a39 C from color MACRO_Execute_Any,Convert 32a5 ; 0a4b C True from color MACRO_Execute_Any,Convert_Unchecked 32a5 ; 0a4f C from color 0x0a4e 32a5 ; 0a5c C True from color 0x0a4e 32a5 ; 0a71 C from color 0x0a4e 32a5 ; 0a85 C from color 0x0a4e 32a5 ; 0a99 C from color MACRO_Execute_Any,Convert 32a5 ; 0ab6 C True from color MACRO_Execute_Any,Structure_Query 32a5 ; 0c0d C False from color 0x0c05 32a5 ; 0c0e C False from color 0x0c05 32a5 ; 0e45 C False from color 0x0d34 32a5 ; 0e46 C False from color 0x0d34 32a5 ; 0e6d C False from color 0x0d34 32a5 ; 0e6e C False from color 0x0d34 32a5 ; 12c6 C False from color 0x098a 32a5 ; 12d2 C False from color 0x098a 32a5 ; 12d4 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a5 ; 130a C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a5 ; 130c C False from color MACRO_Declare_Variable_Variant_Record,Duplicate 32a5 ; 17d0 C from color MACRO_Execute_Any,Set_Constraint 32a5 ; 1e81 C True from color MACRO_Declare_Type_Record,Defined 32a5 ; 1ea3 C True from color MACRO_Complete_Type_Record,By_Defining 32a5 ; 1ee4 C False from color MACRO_Declare_Variable_Record,Duplicate 32a5 ; 2009 C True from color MACRO_Complete_Type_Array,By_Defining 32a5 ; 200e C True from color MACRO_Complete_Type_Array,By_Defining 32a5 ; 2024 C True from color 0x2010 32a5 ; 205b C True from color 0x2010 32a5 ; 206a C True from color MACRO_Declare_Type_Array,Defined_Incomplete 32a5 ; 2092 C True from color 0x2010 32a5 ; 209b C True from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 32a5 ; 209e C True from color 0x209d 32a5 ; 20a3 C True from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 32a5 ; 20ca C True from color MACRO_Declare_Type_Array,Defined 32a5 ; 20de C True from color 0x2010 32a5 ; 2101 C True from color 0x2010 32a5 ; 2104 C True from color 0x2010 32a5 ; 2113 C True from color MACRO_Declare_Type_Array,Defined,Visible 32a5 ; 2118 C True from color MACRO_Declare_Type_Array,Defined,Bounds_With_Object 32a5 ; 211d C True from color 0x2010 32a5 ; 21bf C True from color 0x2003 32a5 ; 21c0 C True from color 0x2003 32a5 ; 230a C True from color MACRO_Complete_Type_Array,By_Component_Completion 32a5 ; 232d C True from color MACRO_Complete_Type_Array,By_Renaming 32a5 ; 2536 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a5 ; 2573 C False from color MACRO_Complete_Type_Variant_Record,By_Defining 32a5 ; 2574 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a5 ; 263e C True from color 0x263a 32a5 ; 2644 C True from color 0x263a 32a5 ; 26b9 C True from color 0x26b6 32a5 ; 26de C True from color 0x26b6 32a5 ; 28fc C False from color MACRO_Execute_Float,Write_Unchecked 32a5 ; 2ae6 C True from color MACRO_Declare_Type_Access,Defined 32a5 ; 2aeb C True from color MACRO_Declare_Type_Access,Defined 32a5 ; 2aee C True from color MACRO_Declare_Type_Access,Defined 32a5 ; 2af3 C True from color MACRO_Declare_Type_Access,Defined 32a5 ; 2afc C True from color 0x2af9 32a5 ; 2b2f C True from color 0x2b1b 32a5 ; 2c4c C from color 0x2c4c 32a5 ; 2c59 C from color 0x2c59 32a5 ; 2c5d C from color 0x2c59 32a5 ; 2c65 C from color 0x2c59 32a5 ; 2c6a C True from color 0x2c59 32a5 ; 2cd4 C True from color MACRO_Action_Elaborate_Subprogram 32a5 ; 2cd8 C True from color MACRO_Action_Check_Subprogram_Elaborated 32a5 ; 2d11 C True from color 0x2d11 32a5 ; 2ffc C False from color MACRO_Execute_Discrete,Write_Unchecked 32a5 ; 3087 C True from color 0x3087 32a5 ; 30a8 C True from color MACRO_Complete_Type_Float,By_Defining 32a5 ; 317b C from color MACRO_Declare_Type_Heap_Access,Defined 32a5 ; 317e C from color MACRO_Declare_Type_Heap_Access,Defined 32a5 ; 3183 C True from color 0x3182 32a5 ; 3211 C from color MACRO_Execute_Discrete,Remainder 32a5 ; 3221 C from color MACRO_Execute_Discrete,Remainder 32a5 ; 3226 C from color MACRO_Execute_Discrete,Remainder 32a5 ; -------------------------------------------------------------------------------------- 32a5 32a5 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32a6 32a6 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32a7 ; -------------------------------------------------------------------------------------- 32a7 ; Comes from: 32a7 ; 04bb C from color 0x04bb 32a7 ; 0501 C False from color 0x04fa 32a7 ; 0515 C from color 0x0515 32a7 ; 09f7 C False from color MACRO_Execute_Any,Change_Utility 32a7 ; 09f9 C False from color MACRO_Execute_Any,Change_Utility 32a7 ; 0c1d C from color MACRO_Execute_Heap_Access,Element_Type 32a7 ; 0c39 C from color 0x0a7c 32a7 ; 0cf0 C True from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32a7 ; 109b C True from color 0x1097 32a7 ; 10a2 C True from color 0x1097 32a7 ; 10ca C False from color 0x10bf 32a7 ; 115a C True from color 0x1115 32a7 ; 1160 C True from color 0x1116 32a7 ; 1170 C True from color 0x111a 32a7 ; 11b3 C True from color 0x111b 32a7 ; 11e4 C from color 0x11e4 32a7 ; 11e8 C from color 0x11e8 32a7 ; 11ec C from color 0x11ec 32a7 ; 11f0 C from color 0x11f0 32a7 ; 11f1 C from color 0x11f0 32a7 ; 11f2 C from color 0x11f0 32a7 ; 11f3 C from color 0x11f0 32a7 ; 11f4 C from color 0x11f0 32a7 ; 11f8 C from color 0x10bf 32a7 ; 11f9 C from color 0x10bf 32a7 ; 1205 C True from color 0x10bf 32a7 ; 1207 C True from color 0x10bf 32a7 ; 1208 C False from color 0x10bf 32a7 ; 124f C from color 0x124e 32a7 ; 1250 C from color 0x124e 32a7 ; 1251 C from color 0x124e 32a7 ; 1252 C from color 0x124e 32a7 ; 12da C True from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a7 ; 147f C True from color MACRO_Execute_Matrix,Length 32a7 ; 1495 C True from color 0x1484 32a7 ; 15e5 C True from color MACRO_Execute_Matrix,Subarray 32a7 ; 15e8 C True from color MACRO_Execute_Matrix,Subarray 32a7 ; 1695 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32a7 ; 16cf C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32a7 ; 16dd C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32a7 ; 16f5 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a7 ; 16f6 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a7 ; 16f7 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a7 ; 16f8 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a7 ; 1700 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a7 ; 172c C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 172d C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 172f C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 1730 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 1736 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 1738 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32a7 ; 175d C from color MACRO_Execute_Variant_Record,Read_Variant 32a7 ; 1770 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a7 ; 1771 C False from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a7 ; 1772 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a7 ; 1773 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32a7 ; 177c C True from color MACRO_Execute_Variant_Record,Reference_Makes_Copy 32a7 ; 1783 C True from color MACRO_Execute_Variant_Record,Structure_Query 32a7 ; 1784 C True from color MACRO_Execute_Variant_Record,Structure_Query 32a7 ; 1798 C True from color MACRO_Execute_Variant_Record,Component_Offset 32a7 ; 17ff C True from color 0x0a2f 32a7 ; 1add C from color MACRO_Execute_Access,Element_Type 32a7 ; 1af9 C from color 0x0a7b 32a7 ; 1b80 C True from color 0x1b7e 32a7 ; 1b8b C False from color 0x1b7e 32a7 ; 1c7f C True from color MACRO_Execute_Array,Subarray 32a7 ; 1c80 C True from color MACRO_Execute_Array,Subarray 32a7 ; 1c81 C False from color MACRO_Execute_Array,Subarray 32a7 ; 1e82 C True from color MACRO_Declare_Type_Record,Defined 32a7 ; 1e99 C True from color MACRO_Declare_Type_Record,Incomplete 32a7 ; 1ea6 C True from color MACRO_Complete_Type_Record,By_Defining 32a7 ; 1eb5 C True from color MACRO_Complete_Type_Record,By_Renaming 32a7 ; 1eb8 C True from color MACRO_Complete_Type_Record,By_Renaming 32a7 ; 1ec2 C from color MACRO_Complete_Type_Record,By_Renaming 32a7 ; 1f5d C True from color MACRO_Declare_Type_Access,Constrained 32a7 ; 1f71 C False from color 0x1f69 32a7 ; 1f7e C True from color MACRO_Complete_Type_Array,By_Constraining 32a7 ; 1f88 C from color MACRO_Complete_Type_Array,By_Constraining 32a7 ; 2008 C True from color MACRO_Complete_Type_Array,By_Defining 32a7 ; 2040 C True from color 0x2010 32a7 ; 207f C from color 0x2010 32a7 ; 2081 C from color 0x2010 32a7 ; 20b8 C from color 0x2010 32a7 ; 20ba C from color 0x2010 32a7 ; 20e6 C True from color 0x2010 32a7 ; 21bc C False from color 0x2003 32a7 ; 21cb C False from color 0x21c7 32a7 ; 21d2 C False from color 0x2003 32a7 ; 21e2 C False from color 0x2003 32a7 ; 21ea C True from color 0x2003 32a7 ; 21fe C True from color 0x21f6 32a7 ; 2211 C from color 0x2003 32a7 ; 22f1 C True from color MACRO_Declare_Type_Array,Incomplete 32a7 ; 22f3 C True from color MACRO_Declare_Type_Array,Incomplete 32a7 ; 2311 C from color MACRO_Complete_Type_Array,By_Component_Completion 32a7 ; 232c C True from color MACRO_Complete_Type_Array,By_Renaming 32a7 ; 2336 C True from color MACRO_Complete_Type_Array,By_Renaming 32a7 ; 234a C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 234b C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 234f C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 2350 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 23af C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 23c1 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 23c5 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 23f6 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32a7 ; 248c C True from color 0x2488 32a7 ; 248e C True from color 0x2488 32a7 ; 2496 C True from color 0x2488 32a7 ; 2532 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a7 ; 2534 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a7 ; 25b3 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 25b4 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a7 ; 262d C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a7 ; 262e C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a7 ; 2632 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a7 ; 263b C True from color 0x263a 32a7 ; 2642 C True from color 0x263a 32a7 ; 26ea C True from color 0x26e3 32a7 ; 2ae7 C False from color MACRO_Declare_Type_Access,Defined 32a7 ; 2aec C False from color MACRO_Declare_Type_Access,Defined 32a7 ; 2aef C False from color MACRO_Declare_Type_Access,Defined 32a7 ; 2af4 C False from color MACRO_Declare_Type_Access,Defined 32a7 ; 2af6 C True from color MACRO_Declare_Type_Access,Defined 32a7 ; 2b3c C False from color MACRO_Declare_Type_Access,Incomplete 32a7 ; 2b3d C True from color MACRO_Declare_Type_Access,Incomplete 32a7 ; 30b1 C False from color MACRO_Complete_Type_Float,By_Defining 32a7 ; 30b9 C False from color MACRO_Complete_Type_Float,By_Defining 32a7 ; 30e5 C False from color 0x30e3 32a7 ; 311e C False from color MACRO_Declare_Type_InMicrocode,Discrete 32a7 ; 318c C False from color 0x3188 32a7 ; 3199 C True from color MACRO_Declare_Type_Heap_Access,Incomplete 32a7 ; 319b C from color MACRO_Declare_Type_Heap_Access,Incomplete 32a7 ; -------------------------------------------------------------------------------------- 32a7 32a7 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR08:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32a8 ; -------------------------------------------------------------------------------------- 32a8 ; Comes from: 32a8 ; 099b C False from color 0x099b 32a8 ; 099d C False from color 0x099d 32a8 ; 09fe C False from color MACRO_Execute_Any,Make_Visible 32a8 ; 108e C False from color MACRO_Declare_Variable_Access,Visible 32a8 ; 1094 C False from color MACRO_Declare_Variable_Heap_Access,Visible 32a8 ; 1099 C False from color 0x1097 32a8 ; 10a0 C False from color 0x1097 32a8 ; 12c7 C False from color 0x098a 32a8 ; 12d5 C False from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32a8 ; 2aea C False from color MACRO_Declare_Type_Access,Defined 32a8 ; 2af2 C False from color MACRO_Declare_Type_Access,Defined 32a8 ; 2b36 C False from color MACRO_Declare_Type_Access,Incomplete 32a8 ; 2b3a C False from color MACRO_Declare_Type_Access,Incomplete 32a8 ; 2c68 C from color 0x2c59 32a8 ; 3085 C False from color MACRO_Declare_Type_Float,Defined,Visible 32a8 ; 309b C False from color MACRO_Declare_Type_Float,Constrained,Visible 32a8 ; 30a1 C False from color MACRO_Declare_Type_Float,Incomplete,Visible 32a8 ; 30ca C False from color 0x0993 32a8 ; 30d8 C False from color MACRO_Declare_Variable_Float,Visible,With_Value 32a8 ; 30e3 C False from color 0x30e3 32a8 ; 30ea C False from color 0x30e3 32a8 ; 311b C False from color MACRO_Declare_Type_InMicrocode,Discrete 32a8 ; 3160 C False from color MACRO_Declare_Variable_Any,Visible 32a8 ; 316e C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 32a8 ; 3170 C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 32a8 ; 3178 C False from color MACRO_Declare_Variable_Discrete,Visible,With_Value 32a8 ; 317c C False from color MACRO_Declare_Type_Heap_Access,Defined 32a8 ; 3193 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32a8 ; 3197 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32a8 ; 319d C from color MACRO_Declare_Type_Heap_Access,Incomplete 32a8 ; -------------------------------------------------------------------------------------- 32a8 32a8 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR08:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32a9 ; -------------------------------------------------------------------------------------- 32a9 ; Comes from: 32a9 ; 0a4c C from color MACRO_Execute_Any,Convert_Unchecked 32a9 ; 0a6a C False from color 0x0a4e 32a9 ; 0a6d C from color 0x0a4e 32a9 ; 1110 C from color 0x1110 32a9 ; 1698 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32a9 ; 1760 C False from color MACRO_Execute_Variant_Record,Indirects_Appended 32a9 ; 1761 C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32a9 ; 17f5 C True from color MACRO_Execute_Record,Structure_Write 32a9 ; 17f6 C True from color MACRO_Execute_Record,Structure_Write 32a9 ; 19b7 C True from color 0x19b7 32a9 ; 19b9 C from color 0x19b7 32a9 ; 1d2c C from color 0x1d2c 32a9 ; 1d2d C from color 0x1d2c 32a9 ; 1d3c C from color 0x1d3c 32a9 ; 1d4a C from color 0x1d4a 32a9 ; 1ea9 C False from color MACRO_Complete_Type_Record,By_Defining 32a9 ; 1eb6 C False from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1f7c C True from color MACRO_Complete_Type_Array,By_Constraining 32a9 ; 1f81 C True from color MACRO_Complete_Type_Array,By_Constraining 32a9 ; 2006 C True from color MACRO_Complete_Type_Array,By_Defining 32a9 ; 200c C True from color MACRO_Complete_Type_Array,By_Defining 32a9 ; 21bb C True from color 0x2003 32a9 ; 21d1 C True from color 0x2003 32a9 ; 21e1 C True from color 0x2003 32a9 ; 2208 C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32a9 ; 2213 C True from color 0x2003 32a9 ; 232a C True from color MACRO_Complete_Type_Array,By_Renaming 32a9 ; 2330 C True from color MACRO_Complete_Type_Array,By_Renaming 32a9 ; 23be C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23c3 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 2530 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a9 ; 2533 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a9 ; 2631 C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 2d2f C True from color 0x2cf4 32a9 ; -------------------------------------------------------------------------------------- 32a9 32a9 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR08:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32aa ; -------------------------------------------------------------------------------------- 32aa ; Comes from: 32aa ; 0907 C False from color 0x0905 32aa ; 10a9 C from color 0x10a8 32aa ; 10ad C from color 0x10a8 32aa ; 10b1 C from color 0x10a8 32aa ; 10b5 C from color 0x10a8 32aa ; 10df C False from color 0x10d4 32aa ; 117e C False from color 0x111b 32aa ; 1189 C from color 0x111b 32aa ; 1213 C False from color 0x10d4 32aa ; 1217 C False from color 0x10d4 32aa ; 121a C False from color 0x10d4 32aa ; 1242 C from color 0x1242 32aa ; 1246 C from color 0x1246 32aa ; 124a C from color 0x124a 32aa ; 124e C from color 0x124e 32aa ; 128a C False from color 0x10d4 32aa ; 129c C False from color 0x125d 32aa ; 12a0 C False from color 0x125d 32aa ; 12a3 C False from color 0x125d 32aa ; 12c3 C False from color 0x12c3 32aa ; 1374 C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 1378 C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 139f C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 13a3 C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 13c6 C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 13ca C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 13fb C False from color MACRO_Declare_Variable_Array,With_Constraint 32aa ; 1413 C False from color 0x140f 32aa ; 170e C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32aa ; 171b C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32aa ; 1970 C False from color MACRO_Execute_Vector,Slice_Read 32aa ; 1978 C False from color MACRO_Execute_Vector,Slice_Read 32aa ; 1984 C False from color MACRO_Execute_Vector,Slice_Read 32aa ; 1989 C False from color MACRO_Execute_Vector,Slice_Read 32aa ; 1990 C False from color MACRO_Execute_Vector,Slice_Read 32aa ; 19e3 C False from color MACRO_Execute_Vector,Catenate 32aa ; 19f6 C False from color MACRO_Execute_Vector,Catenate 32aa ; 1a05 C True from color MACRO_Execute_Vector,Catenate 32aa ; 1a7d C False from color 0x0a2d 32aa ; 1a84 C True from color 0x0a2d 32aa ; 1a86 C False from color 0x0a2d 32aa ; 20bb C True from color 0x2010 32aa ; 222a C False from color 0x2226 32aa ; 2236 C False from color 0x2226 32aa ; 2248 C False from color 0x2226 32aa ; 2249 C False from color 0x2226 32aa ; 2746 C False from color MACRO_Declare_Variable_Entry 32aa ; 2a0b C False from color 0x2a02 32aa ; 2a22 C False from color 0x2a02 32aa ; 2cb5 C True from color MACRO_Declare_Subprogram_For_Call,subp 32aa ; 2cbb C True from color MACRO_Declare_Subprogram_For_Accept,subp 32aa ; 30e6 C False from color 0x30e3 32aa ; 311a C False from color MACRO_Declare_Type_InMicrocode,Discrete 32aa ; 3120 C False from color MACRO_Declare_Type_InMicrocode,Discrete 32aa ; 3b19 C True from color 0x36e9 32aa ; 3b1b C True from color 0x36e9 32aa ; -------------------------------------------------------------------------------------- 32aa 32aa fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 37 VR12:17 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32ab ; -------------------------------------------------------------------------------------- 32ab ; Comes from: 32ab ; 01f8 C from color MACRO_01f8_QQUnknown_InMicrocode 32ab ; 2355 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ab ; 2398 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ab ; 239f C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32ab ; 23fb C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32ab ; 2420 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32ab ; 2506 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2507 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2508 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2509 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 250a C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2523 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2524 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2525 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32ab ; 2531 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2537 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 254b C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 254c C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 255d C True from color 0x255c 32ab ; 2575 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2576 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2578 C False from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2597 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2598 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 2599 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 259b C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 259c C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 259e C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32ab ; 264a C True from color 0x263a 32ab ; 2660 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 2661 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 266b C True from color 0x266a 32ab ; 26a4 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 26a5 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 26a6 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 26a8 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 26a9 C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 26ab C True from color MACRO_Declare_Type_Variant_Record,Defined 32ab ; 2d14 C True from color ML_break_class 32ab ; 3248 C from color MACRO_Illegal_- 32ab ; -------------------------------------------------------------------------------------- 32ab 32ab fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR08:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32ac ; -------------------------------------------------------------------------------------- 32ac ; Comes from: 32ac ; 0fa1 C True from color 0x0ef8 32ac ; 0fae C True from color 0x0ef8 32ac ; 0fb3 C True from color 0x0ef8 32ac ; 15f5 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 32ac ; 1648 C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 32ac ; 164a C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 32ac ; 1699 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ac ; 169f C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ac ; 16a4 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ac ; 16d2 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ac ; 16e5 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ac ; 16f4 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32ac ; 1765 C from color MACRO_Execute_Variant_Record,Indirects_Appended 32ac ; 1768 C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32ac ; 176c C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32ac ; 1796 C False from color MACRO_Execute_Variant_Record,Component_Offset 32ac ; 179a C from color MACRO_Execute_Variant_Record,Component_Offset 32ac ; 17c7 C from color MACRO_Execute_Any,Set_Constraint 32ac ; 17d2 C True from color MACRO_Execute_Record,Field_Read,fieldnum 32ac ; 17e2 C True from color MACRO_Execute_Record,Field_Reference,fieldnum 32ac ; 17ef C True from color 0x09ab 32ac ; 17fa C from color MACRO_Execute_Record,Structure_Write 32ac ; 17fc C False from color 0x0a2f 32ac ; 1801 C from color 0x0a2f 32ac ; 180f C True from color 0x180f 32ac ; 1810 C True from color 0x180f 32ac ; 1813 C from color 0x180f 32ac ; 1962 C True from color MACRO_Execute_Vector,Slice_Read 32ac ; 19b5 C True from color MACRO_Execute_Vector,Slice_Write 32ac ; 19c0 C True from color MACRO_Execute_Vector,Slice_Reference 32ac ; 24e4 C False from color 0x2488 32ac ; 2a61 C True from color ML_Resolve Reference 32ac ; 2c6b C True from color 0x2c59 32ac ; 2c6f C False from color 0x2c6e 32ac ; 2c74 C True from color 0x2c6e 32ac ; 2c7a C False from color MACRO_Execute_Select,Member_Write,fieldnum 32ac ; 2c8c C False from color MACRO_Execute_Select,Member_Write,fieldnum 32ac ; 2c92 C False from color MACRO_Execute_Select,Guard_Write,fieldnum 32ac ; 2c9d C True from color MACRO_Execute_Select,Timed_Duration_Write 32ac ; 35ac C True from color 0x35aa 32ac ; 35ae C from color 0x35aa 32ac ; 37d1 C True from color MACRO_Execute_Entry,Count 32ac ; 37d7 C True from color MACRO_Execute_Family,Count 32ac ; 38af C True from color 0x38ac 32ac ; -------------------------------------------------------------------------------------- 32ac 32ac fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR11:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32ad ; -------------------------------------------------------------------------------------- 32ad ; Comes from: 32ad ; 019a C from color UE_CHK_EXIT 32ad ; 01e2 C from color UE_NEW_PAK 32ad ; 2e54 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 32ad ; -------------------------------------------------------------------------------------- 32ad 32ad fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR11:0e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32ae ; -------------------------------------------------------------------------------------- 32ae ; Comes from: 32ae ; 01a2 C from color UE_FIELD_ERROR 32ae ; 1697 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 169a C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16b4 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16ba C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16bb C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16bf C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16c1 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32ae ; 16d1 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; 16d6 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; 16d7 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; 16de C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32ae ; -------------------------------------------------------------------------------------- 32ae 32ae fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR11:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32af ; -------------------------------------------------------------------------------------- 32af ; Comes from: 32af ; 0c56 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32af ; 0c57 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32af ; 1154 C False from color 0x1154 32af ; 1dac C False from color 0x1dac 32af ; 35b9 C from color 0x35b2 32af ; 35be C False from color 0x35bb 32af ; 35c0 C False from color 0x35bb 32af ; 35c1 C True from color 0x35bb 32af ; 35c5 C False from color 0x35c5 32af ; 35c6 C True from color 0x35c5 32af ; 35c7 C False from color 0x35c5 32af ; 35cd C from color 0x35c5 32af ; 35ce C False from color 0x35c5 32af ; 35cf C True from color 0x35c5 32af ; 35d0 C False from color 0x35c5 32af ; 35d3 C from color 0x35c5 32af ; -------------------------------------------------------------------------------------- 32af 32af fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR11:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32b0 ; -------------------------------------------------------------------------------------- 32b0 ; Comes from: 32b0 ; 03ab C True from color 0x0398 32b0 ; 2c99 C False from color MACRO_Execute_Select,Timed_Duration_Write 32b0 ; 2ca0 C False from color MACRO_Execute_Select,Timed_Guard_Write 32b0 ; 2ca4 C False from color MACRO_Execute_Select,Terminate_Guard_Write 32b0 ; -------------------------------------------------------------------------------------- 32b0 32b0 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR05:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32b1 32b1 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 32b2 32b2 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR09:10 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32b3 32b3 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR12:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32b4 ; -------------------------------------------------------------------------------------- 32b4 ; Comes from: 32b4 ; 0f54 C from color 0x0ef8 32b4 ; 0fa7 C False from color 0x0ef8 32b4 ; 0fac C from color 0x0ef8 32b4 ; -------------------------------------------------------------------------------------- 32b4 32b4 fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR18:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 32b5 32b5 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR18:10 typ_c_mux_sel 0 ALU typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0f VR18:10 val_c_mux_sel 2 ALU val_frame 18 32b6 32b6 ioc_adrbs 1 val ; Flow C 0x349b ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 32b7 32b7 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x32bb fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32bb 0x32bb seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 27 ? val_a_adr 22 VR02:02 val_frame 2 32b8 32b8 ioc_adrbs 1 val ; Flow C 0x349b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32b9 32b9 fiu_tivi_src 1 tar_val; Flow J cc=False 0x32bc ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 32bc 0x32bc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32ba 32ba seq_br_type 3 Unconditional Branch; Flow J 0x32c4 seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 32bb 32bb fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32bc 32bc fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR07:18 typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 32bd 32bd fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 14 ZEROS val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 32be 32be ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 02 GP02 32bf 32bf seq_br_type 3 Unconditional Branch; Flow J 0x32e1 seq_branch_adr 32e1 0x32e1 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32c0 ; -------------------------------------------------------------------------------------- 32c0 ; Comes from: 32c0 ; 0f7d C False from color 0x0ef8 32c0 ; -------------------------------------------------------------------------------------- 32c0 32c0 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR12:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32c1 ; -------------------------------------------------------------------------------------- 32c1 ; Comes from: 32c1 ; 1f4e C from color 0x1f4c 32c1 ; -------------------------------------------------------------------------------------- 32c1 32c1 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 32c2 32c2 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR12:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32c3 ; -------------------------------------------------------------------------------------- 32c3 ; Comes from: 32c3 ; 0b6f C False from color 0x0b6e 32c3 ; 0ce9 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32c3 ; 0d04 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32c3 ; 0e7a C False from color 0x0e78 32c3 ; 0e7b C True from color 0x0e78 32c3 ; 0e7d C False from color 0x0e78 32c3 ; -------------------------------------------------------------------------------------- 32c3 32c3 fiu_tivi_src 1 tar_val; Flow J 0x32c4 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c4 0x32c4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 39 VR09:19 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32c4 ; -------------------------------------------------------------------------------------- 32c4 ; Comes from: 32c4 ; 3264 C from color MACRO_Execute_Discrete,Raise,>R 32c4 ; -------------------------------------------------------------------------------------- 32c4 32c4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 32c5 32c5 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x32c7 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32c7 0x32c7 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32c6 32c6 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32c7 32c7 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 32c8 32c8 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32c9 32c9 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32ca 32ca fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x32da fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32da 0x32da typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 32cb 32cb fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 32cc 32cc fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x32e1 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32e1 0x32e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_lex_adr 2 seq_random 0b ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 32cd 32cd fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x32e1 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32e1 0x32e1 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 32ce 32ce fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x32e1 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32e1 0x32e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 32cf 32cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32e1 seq_br_type 1 Branch True seq_branch_adr 32e1 0x32e1 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 3e TR11:1e typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_frame 11 val_a_adr 38 VR02:18 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_frame 2 32d0 32d0 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 32d1 32d1 ioc_fiubs 2 typ ; Flow J cc=True 0x32d8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d8 0x32d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 06 GP06 val_alu_func 0 PASS_A 32d2 32d2 seq_en_micro 0 32d3 32d3 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x32d6 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32d6 0x32d6 seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 32d4 32d4 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f7 0x32f7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 32d5 32d5 seq_br_type 3 Unconditional Branch; Flow J 0x32ef seq_branch_adr 32ef 0x32ef 32d6 32d6 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f7 0x32f7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 32d7 32d7 seq_br_type 3 Unconditional Branch; Flow J 0x32ef seq_branch_adr 32ef 0x32ef 32d8 32d8 seq_en_micro 0 32d9 32d9 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x32e8 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32e8 0x32e8 seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 32da 32da seq_br_type 3 Unconditional Branch; Flow J 0x32e1 seq_branch_adr 32e1 0x32e1 seq_lex_adr 3 seq_random 6a ? val_c_adr 39 GP06 val_c_mux_sel 2 ALU 32db 32db seq_en_micro 0 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 32dc 32dc fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32dd 32dd ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 32de 32de fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_frame 2 32df 32df fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32e0 32e0 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x32cc fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 32cc 0x32cc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 32e1 32e1 fiu_load_tar 1 hold_tar; Flow J cc=True 0x32e7 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32e7 0x32e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 32e2 32e2 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x32e5 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32e5 0x32e5 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32e3 32e3 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f7 0x32f7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 32e4 32e4 seq_br_type 3 Unconditional Branch; Flow J 0x32ef seq_branch_adr 32ef 0x32ef 32e5 32e5 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f7 0x32f7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 32e6 32e6 seq_br_type 3 Unconditional Branch; Flow J 0x32ef seq_branch_adr 32ef 0x32ef 32e7 32e7 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32e8 32e8 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32f7 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f7 0x32f7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 32e9 32e9 seq_br_type 3 Unconditional Branch; Flow J 0x32ef seq_branch_adr 32ef 0x32ef 32ea ; -------------------------------------------------------------------------------------- 32ea ; 0x0101 Execute Exception,Reraise,>R 32ea ; -------------------------------------------------------------------------------------- 32ea MACRO_Execute_Exception,Reraise,>R: 32ea 32ea dispatch_brk_class 8 ; Flow J cc=True 0x32db dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 32ea fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_alu_func 13 ONES val_c_adr 39 GP06 val_c_mux_sel 2 ALU 32eb 32eb seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_frame 8 32ec 32ec fiu_mem_start 2 start-rd; Flow J cc=True 0x32ee ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 32ee 0x32ee typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 32ed 32ed ioc_fiubs 2 typ ; Flow J 0x32ef seq_br_type 3 Unconditional Branch seq_branch_adr 32ef 0x32ef seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 28 VR05:08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 32ee 32ee ioc_fiubs 2 typ ; Flow J 0x32ef seq_br_type 3 Unconditional Branch seq_branch_adr 32ef 0x32ef seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 29 VR05:09 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 32ef 32ef fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x32f2 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 32f2 0x32f2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 32f0 32f0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 32f1 32f1 ioc_tvbs 1 typ+fiu; Flow J 0x32f6 seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 32f2 32f2 fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 32f3 32f3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_random 15 ? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 32f4 32f4 ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 6e Load_break_mask+? 32f5 32f5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32f6 seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 32f6 32f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 32f7 ; -------------------------------------------------------------------------------------- 32f7 ; Comes from: 32f7 ; 32d4 C True from color 0x0000 32f7 ; 32d6 C True from color 0x0000 32f7 ; 32e3 C True from color 0x0000 32f7 ; 32e5 C True from color 0x0000 32f7 ; 32e8 C True from color 0x0000 32f7 ; -------------------------------------------------------------------------------------- 32f7 32f7 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 32f8 32f8 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 32f9 32f9 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL 32fa 32fa ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 32fb 32fb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 32fc ; -------------------------------------------------------------------------------------- 32fc ; Comes from: 32fc ; 0222 C from color MACRO_Action_Accept_Activation 32fc ; 0223 C from color MACRO_Action_Accept_Activation 32fc ; 026f C from color MACRO_Action_Accept_Activation 32fc ; 031a C from color MACRO_Action_Name_Partner 32fc ; 03d5 C from color 0x03d4 32fc ; 0402 C from color 0x03f0 32fc ; 067f C from color 0x066a 32fc ; 068a C from color 0x066a 32fc ; 090f C from color 0x0905 32fc ; 0911 C from color 0x0905 32fc ; 0913 C from color 0x0913 32fc ; 0961 C from color MACRO_Execute_Module,Is_Callable 32fc ; 0977 C from color MACRO_Execute_Module,Is_Callable 32fc ; 0a58 C from color 0x0a4e 32fc ; 0cea C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32fc ; 0d0c C from color MACRO_Execute_Vector,Hash 32fc ; 1175 C from color 0x111b 32fc ; 1317 C from color 0x1314 32fc ; 144a C from color 0x09aa 32fc ; 145e C from color 0x09aa 32fc ; 1482 C from color MACRO_Execute_Matrix,Length 32fc ; 1497 C from color 0x1484 32fc ; 14c0 C from color 0x0aa0 32fc ; 14c1 C from color 0x0aa0 32fc ; 14c5 C from color 0x0aa0 32fc ; 14c6 C from color 0x0aa0 32fc ; 14cd C from color 0x0aa0 32fc ; 14d2 C from color 0x0aa0 32fc ; 1750 C from color MACRO_Execute_Variant_Record,Is_Constrained_Object 32fc ; 1797 C from color MACRO_Execute_Variant_Record,Component_Offset 32fc ; 181b C from color 0x09a9 32fc ; 1827 C from color 0x09a9 32fc ; 1a80 C from color 0x0a2d 32fc ; 1b09 C from color 0x0a31 32fc ; 1b0d C from color 0x0a31 32fc ; 1b3f C from color MACRO_1b3e_QQUnknown_InMicrocode 32fc ; 1c85 C from color MACRO_Execute_Array,Subarray 32fc ; 1d73 C from color 0x1d28 32fc ; 1d8e C from color 0x1d28 32fc ; 1e11 C from color MACRO_Execute_Matrix,Structure_Write 32fc ; 1e2d C from color MACRO_Execute_Matrix,Structure_Write 32fc ; 1ebc C from color MACRO_Complete_Type_Record,By_Renaming 32fc ; 220b C from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32fc ; 2319 C from color MACRO_Complete_Type_Array,By_Component_Completion 32fc ; 2389 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fc ; 239d C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fc ; 23d2 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32fc ; 2415 C from color 0x2413 32fc ; 2416 C from color 0x2413 32fc ; 241c C from color 0x2413 32fc ; 244d C from color 0x2409 32fc ; 2516 C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32fc ; 252e C from color MACRO_Complete_Type_Variant_Record,By_Defining 32fc ; 2555 C from color 0x2553 32fc ; 2557 C from color 0x2553 32fc ; 2559 C from color 0x2553 32fc ; 262a C from color MACRO_Complete_Type_Variant_Record,By_Renaming 32fc ; 2637 C from color MACRO_Complete_Type_Variant_Record,By_Renaming 32fc ; 2650 C from color 0x263a 32fc ; 2678 C from color 0x2676 32fc ; 267a C from color 0x2676 32fc ; 267c C from color 0x2676 32fc ; 26f0 C from color 0x26e3 32fc ; 2b00 C from color 0x2b00 32fc ; 2cb7 C from color MACRO_Declare_Subprogram_For_Call,subp 32fc ; 2e7d C from color 0x2e7d 32fc ; 2f1b C from color 0x06b6 32fc ; 2f44 C from color 0x06b6 32fc ; 2fee C from color MACRO_Execute_Any,Convert 32fc ; 3007 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fc ; 3008 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fc ; 3009 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 32fc ; 3024 C from color MACRO_Execute_Discrete,Instruction_Read 32fc ; 3074 C from color 0x3074 32fc ; 3076 C from color 0x3074 32fc ; 3078 C from color 0x3078 32fc ; 307e C from color 0x3078 32fc ; 307f C from color 0x3078 32fc ; 3080 C from color 0x3078 32fc ; 3081 C from color 0x3078 32fc ; 30b0 C from color MACRO_Complete_Type_Float,By_Defining 32fc ; 30b6 C from color MACRO_Complete_Type_Float,By_Defining 32fc ; 316a C from color MACRO_Execute_Immediate_Set_Value,uimmediate 32fc ; 35af C from color 0x35aa 32fc ; 35cc C from color 0x35c5 32fc ; 35d5 C from color 0x35c5 32fc ; 35da C from color 0x35d9 32fc ; 3798 C from color 0x3794 32fc ; 3803 C from color 0x37fe 32fc ; 38b3 C from color 0x38b3 32fc ; 38d4 C from color 0x38c8 32fc ; 3912 C from color 0x390c 32fc ; 3931 C from color 0x062d 32fc ; 39af C from color 0x39ae 32fc ; 3a1d C from color 0x03fa 32fc ; 3a37 C from color 0x3a37 32fc ; -------------------------------------------------------------------------------------- 32fc 32fc seq_br_type a Unconditional Return; Flow R 32fd ; -------------------------------------------------------------------------------------- 32fd ; Comes from: 32fd ; 0754 C from color 0x0203 32fd ; 0ed0 C from color 0x0000 32fd ; 32b4 C from color 0x0000 32fd ; 32df C from color 0x0000 32fd ; 32f2 C from color 0x0000 32fd ; 3aac C from color 0x0000 32fd ; -------------------------------------------------------------------------------------- 32fd 32fd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 32fe 32fe fiu_tivi_src c mar_0xc; Flow J 0x3303 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3303 0x3303 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 32ff ; -------------------------------------------------------------------------------------- 32ff ; Comes from: 32ff ; 0b49 C from color 0x0000 32ff ; -------------------------------------------------------------------------------------- 32ff 32ff fiu_tivi_src c mar_0xc; Flow J 0x3300 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3303 0x3303 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3300 3300 fiu_mem_start 7 start_wr_if_true; Flow R cc=False fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 3301 0x3301 seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3301 3301 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 3302 3302 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3303 3303 fiu_mem_start 2 start-rd; Flow J 0x3304 ioc_adrbs 3 seq seq_br_type 2 Push (branch address) seq_branch_adr 330f 0x330f seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 26 TR11:06 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 3304 3304 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3365 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3365 0x3365 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3305 3305 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3334 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3334 0x3334 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3306 3306 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 3307 3307 fiu_mem_start 2 start-rd; Flow J 0x3308 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3313 0x3313 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 27 TR11:07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3308 3308 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3365 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3365 0x3365 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3309 3309 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3334 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3334 0x3334 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 330a 330a seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 330b 330b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x330c fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3316 0x3316 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 28 TR11:08 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 330c 330c fiu_tivi_src c mar_0xc; Flow J cc=True 0x3365 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3365 0x3365 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 330d 330d fiu_load_tar 1 hold_tar; Flow J cc=False 0x3334 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3334 0x3334 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 330e 330e seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 330f 330f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3321 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3321 0x3321 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3310 3310 ioc_adrbs 1 val ; Flow J cc=True 0x3312 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3312 0x3312 typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3311 3311 seq_b_timing 0 Early Condition; Flow J cc=True 0x3312 ; Flow J cc=#0x0 0x3319 seq_br_type b Case False seq_branch_adr 3319 0x3319 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3312 3312 seq_b_timing 0 Early Condition; Flow J cc=True 0x3313 ; Flow J cc=#0x0 0x3319 seq_br_type b Case False seq_branch_adr 3319 0x3319 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3313 3313 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3324 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3324 0x3324 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3314 3314 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3315 3315 seq_b_timing 0 Early Condition; Flow J cc=True 0x3316 ; Flow J cc=#0x0 0x3319 seq_br_type b Case False seq_branch_adr 3319 0x3319 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3316 3316 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3326 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3326 0x3326 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3317 3317 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3318 3318 seq_b_timing 0 Early Condition; Flow J cc=True 0x3319 ; Flow J cc=#0x0 0x3319 seq_br_type b Case False seq_branch_adr 3319 0x3319 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 3319 3319 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 331a 331a fiu_mem_start 3 start-wr; Flow J 0x331d ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 331d 0x331d seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 331b 331b fiu_mem_start 3 start-wr; Flow J 0x331e seq_br_type 3 Unconditional Branch seq_branch_adr 331e 0x331e seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 331c 331c seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 331d 331d ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 331e 331e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 07 GP07 val_a_adr 0f GP0f val_b_adr 05 GP05 331f 331f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3320 3320 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3321 3321 fiu_mem_start 2 start-rd; Flow J cc=True 0x3323 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3323 0x3323 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3322 3322 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3323 ; Flow J cc=#0x0 0x3328 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3328 0x3328 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 3323 3323 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3324 ; Flow J cc=#0x0 0x3328 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3328 0x3328 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2b TR11:0b typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3324 3324 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3325 3325 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3326 ; Flow J cc=#0x0 0x3328 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3328 0x3328 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR11:0c typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3326 3326 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3327 3327 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3328 ; Flow J cc=#0x0 0x3328 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3328 0x3328 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR11:0d typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3328 3328 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x332e fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3329 3329 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x332c fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 332c 0x332c typ_a_adr 04 GP04 332a 332a fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3331 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3331 0x3331 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 332b 332b seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 332c 332c fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_c_adr 3b GP04 332d 332d ioc_load_wdr 0 ; Flow J 0x332f seq_br_type 3 Unconditional Branch seq_branch_adr 332f 0x332f seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 332e 332e ioc_load_wdr 0 ; Flow J 0x332f ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 332f 0x332f seq_en_micro 0 val_b_adr 04 GP04 332f 332f fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3330 3330 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 07 GP07 val_b_adr 05 GP05 3331 3331 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 val_b_adr 05 GP05 3332 3332 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3333 3333 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3334 3334 ioc_adrbs 2 typ ; Flow J cc=True 0x3337 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3337 0x3337 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3335 3335 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3336 3336 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3339 fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3339 0x3339 seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 07 GP07 val_b_adr 07 GP07 3337 3337 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3338 3338 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3339 fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3339 0x3339 seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 29 TR11:09 typ_frame 11 val_b_adr 07 GP07 3339 3339 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 333a 333a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 3c TR02:1c typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 333b 333b ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 333c 333c seq_br_type a Unconditional Return; Flow R 333d ; -------------------------------------------------------------------------------------- 333d ; Comes from: 333d ; 0236 C from color 0x0000 333d ; -------------------------------------------------------------------------------------- 333d 333d fiu_tivi_src c mar_0xc; Flow C 0x3364 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3364 0x3364 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 333e 333e fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3348 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3348 0x3348 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 333f 333f fiu_load_oreg 1 hold_oreg; Flow J 0x3348 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3348 0x3348 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 3340 3340 fiu_mem_start 4 continue; Flow J 0x3341 seq_br_type 2 Push (branch address) seq_branch_adr 3346 0x3346 typ_mar_cntl 6 INCREMENT_MAR 3341 3341 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3342 3342 fiu_tivi_src c mar_0xc; Flow J cc=True 0x336e ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 336e 0x336e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 3343 3343 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 3344 3344 seq_br_type a Unconditional Return; Flow R 3345 ; -------------------------------------------------------------------------------------- 3345 ; Comes from: 3345 ; 024e C from color 0x0000 3345 ; 02c0 C from color 0x0000 3345 ; 2f69 C from color 0x0000 3345 ; 3870 C from color 0x0000 3345 ; -------------------------------------------------------------------------------------- 3345 3345 fiu_tivi_src c mar_0xc; Flow C 0x3364 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3364 0x3364 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3346 3346 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x335a fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 335a 0x335a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3347 3347 fiu_load_oreg 1 hold_oreg; Flow J 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 335a 0x335a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 3348 ; -------------------------------------------------------------------------------------- 3348 ; Comes from: 3348 ; 0239 C False from color 0x0000 3348 ; 0251 C False from color 0x0000 3348 ; -------------------------------------------------------------------------------------- 3348 3348 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 3349 3349 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 334a 334a ioc_fiubs 0 fiu ; Flow J cc=True 0x334b ; Flow J cc=#0x0 0x3350 seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3350 0x3350 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 334b 334b seq_b_timing 0 Early Condition; Flow J cc=True 0x334c ; Flow J cc=#0x0 0x334c seq_br_type b Case False seq_branch_adr 334c 0x334c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 334c 334c seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 334d 334d fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 334e 334e fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x334d fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 334d 0x334d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 334f 334f seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3350 3350 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3354 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3354 0x3354 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 3351 3351 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x3359 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3359 0x3359 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3352 3352 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x3358 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3358 0x3358 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3353 3353 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3354 3354 fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3355 0x3355 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3355 3355 fiu_mem_start 2 start-rd; Flow J cc=False 0x3348 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3348 0x3348 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3356 3356 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3357 3357 fiu_mem_start 2 start-rd; Flow J 0x3348 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3348 0x3348 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3358 3358 fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3359 0x3359 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3359 3359 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3354 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3354 0x3354 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 335a ; -------------------------------------------------------------------------------------- 335a ; Comes from: 335a ; 02c4 C from color 0x0000 335a ; 063a C from color 0x0000 335a ; 2f6d C from color 0x0000 335a ; 3874 C from color 0x0000 335a ; -------------------------------------------------------------------------------------- 335a 335a fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 335b 335b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 335c 335c seq_b_timing 0 Early Condition; Flow J cc=True 0x335d ; Flow J cc=#0x0 0x335d seq_br_type b Case False seq_branch_adr 335d 0x335d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 335d 335d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3361 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3361 0x3361 seq_en_micro 0 typ_a_adr 2e TR11:0e typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 335e 335e fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x3363 fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3363 0x3363 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 335f 335f fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3a fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3360 3360 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3361 3361 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False fiu_load_oreg 1 hold_oreg fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3362 0x3362 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3362 3362 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3363 3363 fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3364 ; -------------------------------------------------------------------------------------- 3364 ; Comes from: 3364 ; 333d C from color MACRO_Action_Accept_Activation 3364 ; 3345 C from color 0x2ee5 3364 ; -------------------------------------------------------------------------------------- 3364 3364 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3366 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3366 0x3366 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3365 3365 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x3277 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3277 0x3277 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3366 3366 ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3367 3367 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3368 3368 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3369 ; -------------------------------------------------------------------------------------- 3369 ; Comes from: 3369 ; 2ee5 C from color 0x2ee5 3369 ; 3934 C from color 0x03fa 3369 ; -------------------------------------------------------------------------------------- 3369 3369 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 336a 336a fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x336e fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 336e 0x336e typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 336b ; -------------------------------------------------------------------------------------- 336b ; Comes from: 336b ; 2dc7 C from color 0x2dbd 336b ; -------------------------------------------------------------------------------------- 336b 336b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 336c 336c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 336d 336d fiu_tivi_src c mar_0xc; Flow J 0x336e ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 336e 0x336e typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 336e 336e ioc_fiubs 2 typ typ_a_adr 06 GP06 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 336f 336f fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3370 3370 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3371 ; -------------------------------------------------------------------------------------- 3371 ; Comes from: 3371 ; 033e C from color 0x033e 3371 ; 2f22 C from color 0x06b6 3371 ; 393e C from color 0x0913 3371 ; 397a C from color 0x3972 3371 ; 3a6a C from color 0x3a6a 3371 ; -------------------------------------------------------------------------------------- 3371 3371 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3380 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3380 0x3380 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3372 3372 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a82 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3373 3373 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 3374 3374 fiu_len_fill_lit 6f zero-fill 0x2f; Flow C cc=True 0x337f fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 337f 0x337f seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 3375 3375 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x338a fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 338a 0x338a seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_frame 2 3376 3376 fiu_len_fill_lit 6b zero-fill 0x2b; Flow J cc=True 0x337c fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 337c 0x337c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3377 3377 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 3378 3378 fiu_mem_start 3 start-wr; Flow J cc=True 0x337a ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 337a 0x337a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 3379 3379 fiu_mem_start 4 continue; Flow J cc=False 0x3379 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3379 0x3379 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 337a 337a ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 337b 337b seq_br_type a Unconditional Return; Flow R 337c 337c ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 337d ; -------------------------------------------------------------------------------------- 337d ; Comes from: 337d ; 022a C from color MACRO_Action_Signal_Activated 337d ; 0233 C from color 0x0000 337d ; 0249 C from color 0x0000 337d ; 0278 C from color 0x0000 337d ; 036d C from color 0x0000 337d ; 055f C from color 0x0000 337d ; 069b C from color 0x0698 337d ; 0756 C from color 0x0203 337d ; 0add C from color 0x0add 337d ; 2f8e C from color 0x0000 337d ; 37b8 C from color 0x0000 337d ; 3828 C from color 0x0000 337d ; 3834 C from color 0x0000 337d ; 3850 C from color 0x0000 337d ; 38e2 C from color 0x0000 337d ; 39dc C from color 0x0000 337d ; 3a3a C from color 0x0000 337d ; 3a3e C from color 0x0000 337d ; 3aeb C from color 0x0000 337d ; 3af9 C from color 0x0000 337d ; 3b07 C from color 0x0000 337d ; 3b16 C from color MACRO_3b12_QQUnknown_InMicrocode 337d ; 3b25 C from color 0x0000 337d ; 3b33 C from color 0x0000 337d ; -------------------------------------------------------------------------------------- 337d 337d fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 337e 337e fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x3378 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 3378 0x3378 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 337f ; -------------------------------------------------------------------------------------- 337f ; Comes from: 337f ; 3374 C True from color 0x0000 337f ; -------------------------------------------------------------------------------------- 337f 337f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x364f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 364f 0x364f seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3c VR12:1c val_frame 12 3380 3380 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3381 3381 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3382 3382 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 3383 3383 ioc_load_wdr 0 ; Flow J 0x3384 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3384 0x3384 seq_en_micro 0 typ_b_adr 0e GP0e 3384 3384 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3372 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3372 0x3372 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3385 3385 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3386 3386 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3387 3387 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 3388 3388 ioc_load_wdr 0 ; Flow J 0x3389 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3389 0x3389 seq_en_micro 0 typ_b_adr 0e GP0e 3389 3389 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x338f fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 338f 0x338f seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 338a 338a fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 338b 338b fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 338c 338c fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 338d 338d ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x3378 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 3378 0x3378 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 24 VR02:04 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 338e 338e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3385 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3385 0x3385 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 338f 338f fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x2a82 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3390 3390 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 3391 3391 fiu_len_fill_lit 6f zero-fill 0x2f; Flow J 0x3375 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3375 0x3375 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 3392 ; -------------------------------------------------------------------------------------- 3392 ; Comes from: 3392 ; 0877 C from color 0x0821 3392 ; 2f25 C from color 0x06b6 3392 ; 371c C from color 0x371b 3392 ; 397c C from color 0x3972 3392 ; -------------------------------------------------------------------------------------- 3392 3392 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x33a6 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33a6 0x33a6 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 04 TR02:1b typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_c_adr 03 VR02:1c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3393 3393 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_random 6 load slice timer ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 42 Load_current_lex+Load_control_pred+? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3394 3394 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3395 3395 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 3396 3396 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x33a8 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 33a8 0x33a8 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3397 3397 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x33a3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33a3 0x33a3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 3398 3398 fiu_load_var 1 hold_var; Flow J cc=False 0x33b2 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b2 0x33b2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 3399 3399 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 28 LOOP_COUNTER typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 339a 339a fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x33b2 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b2 0x33b2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 339b 339b fiu_mem_start 2 start-rd; Flow J cc=False 0x339e ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 339e 0x339e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 6 339c 339c ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 339d 339d ioc_random c enable slice timer; Flow R cc=True ; Flow J cc=False 0x33b6 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 33b6 0x33b6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 339e 339e ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 339f 339f fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33b6 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33b6 0x33b6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 33a0 33a0 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 33a1 33a1 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33a2 33a2 ioc_random c enable slice timer; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33a3 33a3 ioc_adrbs 3 seq ; Flow J 0x33a4 seq_br_type 2 Push (branch address) seq_branch_adr 07e9 0x07e9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 1a TR02:05 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_c_adr 1a VR02:05 val_frame 2 33a4 33a4 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 33a5 33a5 ioc_random c enable slice timer; Flow R seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 33a6 33a6 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 33a7 33a7 fiu_mem_start 2 start-rd; Flow J 0x3392 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3392 0x3392 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 33a8 ; -------------------------------------------------------------------------------------- 33a8 ; Comes from: 33a8 ; 3396 C True from color 0x3395 33a8 ; -------------------------------------------------------------------------------------- 33a8 33a8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 33a9 0x33a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33a9 33a9 ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 39 VR02:19 val_frame 2 33aa 33aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x33ad fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33ad 0x33ad seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 33ab 33ab fiu_mem_start 2 start-rd; Flow R cc=True ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 33ac 0x33ac seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c val_a_adr 31 VR05:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 33ac 33ac fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33ad 33ad ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33ae 33ae fiu_mem_start 3 start-wr seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 0c GP0c typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 18 NOT_A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 33af 33af ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0c GP0c val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0c GP0c val_frame 9 33b0 33b0 fiu_mem_start 6 start_rd_if_false; Flow R cc=False ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 33b1 0x33b1 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33b1 33b1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33b2 33b2 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 33b3 33b3 seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 33b4 33b4 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 31 ? val_a_adr 0f GP0f 33b5 33b5 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 31 ? typ_b_adr 3b TR02:1b typ_frame 2 33b6 33b6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33b7 33b7 fiu_mem_start 4 continue seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 33b8 33b8 ioc_adrbs 3 seq ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33b9 33b9 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33ba ; -------------------------------------------------------------------------------------- 33ba ; Comes from: 33ba ; 0738 C from color 0x0738 33ba ; 2f27 C from color 0x06b6 33ba ; 397d C True from color 0x3972 33ba ; -------------------------------------------------------------------------------------- 33ba 33ba fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 40 SEQ.macro_restartable seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33bb 33bb seq_en_micro 0 33bc 33bc fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33c3 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33c3 0x33c3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 33bd 33bd seq_en_micro 0 33be 33be fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33c0 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33c0 0x33c0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 33bf 33bf fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3392 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 3392 0x3392 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33c0 33c0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 33c1 33c1 seq_en_micro 0 33c2 33c2 seq_br_type 3 Unconditional Branch; Flow J 0x33ba seq_branch_adr 33ba 0x33ba 33c3 33c3 ioc_adrbs 3 seq ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33c4 33c4 ioc_fiubs 2 typ ; Flow J cc=True 0x33ba seq_br_type 1 Branch True seq_branch_adr 33ba 0x33ba seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 33c5 33c5 seq_br_type 3 Unconditional Branch; Flow J 0x33ba seq_branch_adr 33ba 0x33ba seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 0f GP0f 33c6 ; -------------------------------------------------------------------------------------- 33c6 ; Comes from: 33c6 ; 33e1 C from color 0x0000 33c6 ; 33e5 C from color 0x0000 33c6 ; 3400 C from color 0x22cb 33c6 ; 3418 C from color 0x0000 33c6 ; 341c C from color 0x0000 33c6 ; -------------------------------------------------------------------------------------- 33c6 33c6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 33c7 ; -------------------------------------------------------------------------------------- 33c7 ; Comes from: 33c7 ; 0d3e C from color 0x0000 33c7 ; 0d51 C from color 0x0000 33c7 ; 0d83 C from color 0x0000 33c7 ; 0da9 C from color 0x0d9f 33c7 ; 0db8 C from color 0x0db1 33c7 ; 33e7 C from color 0x0000 33c7 ; 33e9 C from color 0x0000 33c7 ; 3409 C from color 0x22cb 33c7 ; 341e C from color 0x0000 33c7 ; 34b9 C from color 0x0000 33c7 ; 34c9 C from color 0x0000 33c7 ; -------------------------------------------------------------------------------------- 33c7 33c7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert ioc_tvbs 3 fiu+fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 33c8 33c8 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 33c9 33c9 ioc_tvbs 2 fiu+val; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 30 VR12:10 val_alu_func 18 NOT_A_AND_B val_b_adr 0b GP0b val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33ca 33ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0b GP0b val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 33cb 33cb fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 25 VR05:05 val_frame 5 33cc 33cc seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 33cd 33cd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x33d7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33d7 0x33d7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33ce 33ce fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 33cf 33cf fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0c GP0c typ_frame d typ_mar_cntl b LOAD_MAR_DATA 33d0 33d0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 33d1 33d1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 33d2 33d2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 33d3 33d3 fiu_load_tar 1 hold_tar; Flow C 0x34fa fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34fa 0x34fa seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0c GP0c typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_b_adr 0c GP0c 33d4 33d4 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33d5 33d5 fiu_mem_start 10 start_physical_tag_wr; Flow J 0x33d6 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 33da 0x33da seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 33d6 33d6 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34cb fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34cb 0x34cb seq_en_micro 0 val_b_adr 0b GP0b 33d7 33d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0xfd0 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 0fd0 0x0fd0 seq_en_micro 0 val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 33d8 33d8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x33c8 fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 33c8 0x33c8 seq_en_micro 0 val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 33d9 33d9 seq_b_timing 0 Early Condition; Flow C cc=True 0x104c seq_br_type 5 Call True seq_branch_adr 104c 0x104c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 33da 33da fiu_load_tar 1 hold_tar; Flow C cc=True 0x2a82 fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 0b GP0b val_frame d 33db 33db fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 23 VR0d:03 val_frame d 33dc ; -------------------------------------------------------------------------------------- 33dc ; Comes from: 33dc ; 33f3 C from color 0x0000 33dc ; 344e C from color 0x02c9 33dc ; 3469 C from color 0x0000 33dc ; 3470 C from color 0x3470 33dc ; 3491 C from color 0x0d34 33dc ; 34d3 C from color 0x34d2 33dc ; 34dc C from color 0x34dc 33dc ; -------------------------------------------------------------------------------------- 33dc 33dc seq_br_type a Unconditional Return; Flow R seq_en_micro 0 33dd ; -------------------------------------------------------------------------------------- 33dd ; Comes from: 33dd ; 33df C from color 0x0000 33dd ; 33ff C from color 0x22cb 33dd ; 3416 C from color 0x0000 33dd ; -------------------------------------------------------------------------------------- 33dd 33dd seq_en_micro 0 33de 33de fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 33df 33df seq_br_type 7 Unconditional Call; Flow C 0x33dd seq_branch_adr 33dd 0x33dd typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 33e0 33e0 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 33e1 33e1 fiu_mem_start 2 start-rd; Flow C 0x33c6 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c6 0x33c6 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33e2 33e2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x33df seq_br_type 0 Branch False seq_branch_adr 33df 0x33df seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 33e3 33e3 fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 33e4 33e4 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33e5 33e5 fiu_mem_start 2 start-rd; Flow C 0x33c6 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c6 0x33c6 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33e6 33e6 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 33e7 33e7 ioc_adrbs 1 val ; Flow C 0x33c7 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33c7 0x33c7 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 33e8 33e8 fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x33e0 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33e0 0x33e0 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 33e9 33e9 ioc_adrbs 1 val ; Flow C 0x33c7 seq_br_type 7 Unconditional Call seq_branch_adr 33c7 0x33c7 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 33ea 33ea fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x33f7 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33f7 0x33f7 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 33eb 33eb fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3a VR1b:1a val_frame 1b 33ec 33ec fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 3b TR1b:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR1b:1b val_frame 1b 33ed 33ed fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 28 TR05:08 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 33ee 33ee fiu_mem_start 4 continue; Flow J cc=False 0x33ee seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33ee 0x33ee seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT 33ef 33ef fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x33f2 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33f2 0x33f2 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 33f0 33f0 fiu_mem_start 3 start-wr; Flow J cc=True 0x33ee fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 33ee 0x33ee seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 33f1 33f1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 33f2 33f2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x33f6 seq_br_type 1 Branch True seq_branch_adr 33f6 0x33f6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 33f3 33f3 fiu_mem_start 2 start-rd; Flow C 0x33dc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 33f4 33f4 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 33f5 33f5 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 val_b_adr 0f GP0f 33f6 33f6 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 21 TR0d:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 33f7 33f7 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 33f8 33f8 seq_br_type 7 Unconditional Call; Flow C 0x34f9 seq_branch_adr 34f9 0x34f9 seq_en_micro 0 33f9 33f9 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33fa 33fa fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 33fb 33fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34d8 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34d8 0x34d8 seq_en_micro 0 val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 33fc 33fc ioc_adrbs 1 val ; Flow C 0x104c seq_br_type 7 Unconditional Call seq_branch_adr 104c 0x104c seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 33fd 33fd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 33fe 33fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x33e0 fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 33e0 0x33e0 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 33ff 33ff seq_br_type 7 Unconditional Call; Flow C 0x33dd seq_branch_adr 33dd 0x33dd typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3400 3400 fiu_mem_start 2 start-rd; Flow C 0x33c6 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33c6 0x33c6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_source 0 FIU_BUS val_frame d val_rand a PASS_B_HIGH 3401 3401 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x33ff seq_br_type 0 Branch False seq_branch_adr 33ff 0x33ff seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 3402 3402 fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 3403 3403 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3404 3404 fiu_mem_start 11 start_tag_query; Flow C 0x34f1 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f1 0x34f1 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3405 3405 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3409 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3409 0x3409 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3406 3406 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=False 0x3408 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 3408 0x3408 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0d GP0d typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3407 3407 ioc_load_wdr 0 ; Flow J 0x3408 seq_br_type 3 Unconditional Branch seq_branch_adr 3408 0x3408 seq_en_micro 0 val_b_adr 0d GP0d 3408 3408 fiu_mem_start 2 start-rd; Flow J 0x340c fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 340c 0x340c seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 3409 3409 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 340a 340a fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3400 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3400 0x3400 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 340b 340b fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 340c 340c fiu_mem_start 4 continue ioc_fiubs 0 fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d 340d 340d fiu_load_var 1 hold_var; Flow J cc=False 0x3414 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3414 0x3414 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 340e 340e ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 340f 340f seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 7 3410 3410 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 3411 3411 fiu_mem_start 9 start_continue_if_true; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 1 typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR12:14 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 12 3412 3412 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3413 3413 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_b_adr 22 VR0d:02 val_frame d 3414 3414 fiu_mem_start 11 start_tag_query; Flow C 0x3493 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3493 0x3493 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3415 3415 fiu_len_fill_reg_ctl 2 ; Flow J 0x3400 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3400 0x3400 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3416 3416 seq_br_type 7 Unconditional Call; Flow C 0x33dd seq_branch_adr 33dd 0x33dd typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3417 3417 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 3418 3418 fiu_mem_start 2 start-rd; Flow C 0x33c6 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c6 0x33c6 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3419 3419 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3416 seq_br_type 0 Branch False seq_branch_adr 3416 0x3416 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 341a 341a fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 341b 341b ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 341c 341c fiu_mem_start 2 start-rd; Flow C 0x33c6 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33c6 0x33c6 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 341d 341d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 341e 341e ioc_adrbs 1 val ; Flow C 0x33c7 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33c7 0x33c7 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 341f 341f fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3417 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3417 0x3417 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3420 3420 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR07:17 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3421 3421 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3422 3422 fiu_mem_start 4 continue; Flow J cc=False 0x3422 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3422 0x3422 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3423 3423 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x2a82 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3424 ; -------------------------------------------------------------------------------------- 3424 ; Comes from: 3424 ; 3457 C from color 0x02c9 3424 ; 3480 C from color 0x0f05 3424 ; 3486 C from color 0x0f05 3424 ; 3489 C from color 0x0f05 3424 ; -------------------------------------------------------------------------------------- 3424 3424 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2a82 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR02:13 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3425 3425 fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR02:13 val_alu_func 18 NOT_A_AND_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3426 3426 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3427 0x3427 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3427 3427 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3434 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3434 0x3434 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3b VR12:1b val_frame 12 3428 3428 seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 3429 3429 fiu_tivi_src 1 tar_val; Flow J cc=False 0x342e ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 342e 0x342e seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 342a 342a fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x342d fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 342d 0x342d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 342b 342b fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x342d ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 342d 0x342d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 342c 342c ioc_load_wdr 0 ; Flow J 0x342e seq_br_type 3 Unconditional Branch seq_branch_adr 342e 0x342e seq_en_micro 0 val_b_adr 0f GP0f 342d 342d ioc_load_wdr 0 ; Flow C 0x34d8 seq_br_type 7 Unconditional Call seq_branch_adr 34d8 0x34d8 seq_en_micro 0 val_b_adr 0f GP0f 342e 342e fiu_mem_start 11 start_tag_query; Flow J cc=False 0x3431 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3431 0x3431 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 4 RESTORE_MAR val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 342f 342f seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 3430 3430 fiu_mem_start 11 start_tag_query seq_en_micro 0 3431 3431 seq_br_type 1 Branch True; Flow J cc=True 0x3428 seq_branch_adr 3428 0x3428 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d 3432 3432 fiu_tivi_src 2 tar_fiu; Flow R cc=True ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3433 0x3433 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3433 3433 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3434 3434 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 3f TR06:1f typ_frame 6 val_a_adr 2c VR0d:0c val_b_adr 16 CSA/VAL_BUS val_frame d val_rand c START_MULTIPLY 3435 3435 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3447 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3447 0x3447 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3436 3436 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3439 seq_br_type 0 Branch False seq_branch_adr 3439 0x3439 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3437 3437 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 3438 3438 fiu_mem_start 14 start_name_query; Flow J 0x3436 seq_br_type 3 Unconditional Branch seq_branch_adr 3436 0x3436 seq_en_micro 0 3439 3439 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x3447 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3447 0x3447 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 4 343a 343a fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR05:11 typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 343b 343b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x343e fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 343e 0x343e seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS 343c 343c seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 343d 343d fiu_mem_start f start_physical_tag_rd; Flow J 0x343b seq_br_type 3 Unconditional Branch seq_branch_adr 343b 0x343b seq_en_micro 0 343e 343e fiu_mem_start 15 setup_tag_read; Flow J cc=False 0x3446 seq_br_type 0 Branch False seq_branch_adr 3446 0x3446 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 343f 343f fiu_len_fill_lit 5c zero-fill 0x1c; Flow J cc=False 0x3446 fiu_mem_start 15 setup_tag_read fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 3446 0x3446 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3440 3440 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3446 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 3446 0x3446 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f 3441 3441 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3443 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3443 0x3443 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3442 3442 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3446 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3446 0x3446 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0b GP0b typ_frame 1 3443 3443 ioc_load_wdr 0 ; Flow J cc=True 0x344a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 344a 0x344a seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 3444 3444 seq_br_type 0 Branch False; Flow J cc=False 0x3446 seq_branch_adr 3446 0x3446 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3445 3445 seq_br_type 5 Call True; Flow C cc=True 0x34d8 seq_branch_adr 34d8 0x34d8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 3446 3446 fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x343b fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 343b 0x343b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 31 TR05:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 6 A_MINUS_B val_b_adr 29 VR08:09 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 8 3447 3447 fiu_mem_start 14 start_name_query; Flow J cc=True 0x3436 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3436 0x3436 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3f VR06:1f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 3448 3448 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3449 0x3449 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3449 3449 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 344a 344a fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3445 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3445 0x3445 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 344b 344b ioc_load_wdr 0 ; Flow J 0x3446 seq_br_type 3 Unconditional Branch seq_branch_adr 3446 0x3446 seq_en_micro 0 val_b_adr 0f GP0f 344c 344c fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 344d ; -------------------------------------------------------------------------------------- 344d ; Comes from: 344d ; 3465 C True from color 0x0000 344d ; -------------------------------------------------------------------------------------- 344d 344d fiu_tivi_src c mar_0xc; Flow C 0x3628 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3628 0x3628 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 344e 344e fiu_mem_start 2 start-rd; Flow C 0x33dc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 344f 344f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3450 seq_br_type 2 Push (branch address) seq_branch_adr 344c 0x344c seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3450 3450 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3451 3451 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3454 seq_br_type 1 Branch True seq_branch_adr 3454 0x3454 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 3452 3452 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 3453 3453 ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0c GP0c val_b_adr 0c GP0c 3454 3454 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x362a fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 362a 0x362a seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 3455 3455 seq_en_micro 0 3456 3456 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3457 3457 fiu_load_oreg 1 hold_oreg; Flow C 0x3424 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3458 3458 fiu_tivi_src c mar_0xc; Flow R cc=False ; Flow J cc=True 0x344d ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 344d 0x344d seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3459 3459 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x345a fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 345a 0x345a typ_mar_cntl 6 INCREMENT_MAR 345a ; -------------------------------------------------------------------------------------- 345a ; Comes from: 345a ; 3464 C from color 0x0000 345a ; -------------------------------------------------------------------------------------- 345a 345a fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 345b 345b ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 345c 345c fiu_load_oreg 1 hold_oreg ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_frame d val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 345d 345d ioc_adrbs 2 typ ; Flow C 0x3424 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_a_adr 2c TR12:0c typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 345e 345e fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 345f 345f fiu_load_oreg 1 hold_oreg; Flow C 0x3424 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3460 3460 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3461 3461 fiu_load_oreg 1 hold_oreg; Flow C 0x3424 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3462 3462 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3463 3463 fiu_load_oreg 1 hold_oreg; Flow J 0x3424 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3464 3464 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x345a fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 345a 0x345a typ_mar_cntl 6 INCREMENT_MAR 3465 3465 fiu_tivi_src c mar_0xc; Flow C cc=True 0x344d ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 344d 0x344d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d val_rand a PASS_B_HIGH 3466 3466 ioc_adrbs 1 val ; Flow J 0x3467 seq_br_type 3 Unconditional Branch seq_branch_adr 3467 0x3467 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 3467 3467 fiu_mem_start 11 start_tag_query; Flow C 0x3493 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3493 0x3493 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 3468 3468 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x346c fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 346c 0x346c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 3 3469 3469 fiu_mem_start 2 start-rd; Flow C 0x33dc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 346a 346a fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 346b 346b ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 0b GP0b 346c 346c fiu_mem_start 2 start-rd; Flow J 0x346d ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 347a 0x347a seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 4 val_rand a PASS_B_HIGH 346d 346d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 36 TR07:16 typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 346e 346e fiu_len_fill_lit 48 zero-fill 0x8; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_b_adr 16 CSA/VAL_BUS 346f 346f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3470 3470 fiu_mem_start 2 start-rd; Flow C 0x33dc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 3471 3471 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3472 3472 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 1 typ_frame 1 val_b_adr 0c GP0c 3473 3473 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3474 3474 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 3475 3475 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 3476 3476 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3477 3477 fiu_mem_start 15 setup_tag_read fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR02:11 typ_frame 2 val_a_adr 2b VR12:0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3478 3478 ioc_tvbs a fiu+mem; Flow J cc=False 0x3496 seq_br_type 0 Branch False seq_branch_adr 3496 0x3496 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3479 3479 fiu_mem_start 10 start_physical_tag_wr; Flow J 0x349a seq_br_type 3 Unconditional Branch seq_branch_adr 349a 0x349a seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 347a 347a ioc_adrbs 1 val ; Flow J 0x3b71 seq_br_type 3 Unconditional Branch seq_branch_adr 3b71 0x3b71 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 347b ; -------------------------------------------------------------------------------------- 347b ; Comes from: 347b ; 027c C from color 0x0000 347b ; -------------------------------------------------------------------------------------- 347b 347b fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 347c 347c fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 347d 347d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d 347e 347e ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f 347f 347f ioc_tvbs 2 fiu+val; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 3480 3480 fiu_load_oreg 1 hold_oreg; Flow C 0x3424 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3481 3481 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 13 ONES typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d 3482 3482 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x34f2 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 34f2 0x34f2 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 3483 3483 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3499 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 3499 0x3499 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 3484 3484 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 3485 3485 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 3486 3486 fiu_load_oreg 1 hold_oreg; Flow C 0x3424 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3487 3487 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3488 3488 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR02:01 val_frame 2 3489 3489 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3424 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3424 0x3424 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 348a 348a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR0d:05 val_alu_func 1a PASS_B val_b_adr 0d GP0d val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d val_rand 9 PASS_A_HIGH 348b 348b fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR0d:04 val_frame d 348c 348c ioc_load_wdr 0 ; Flow J 0x33dc seq_br_type 3 Unconditional Branch seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 348d ; -------------------------------------------------------------------------------------- 348d ; Comes from: 348d ; 2ac6 C from color 0x2abd 348d ; -------------------------------------------------------------------------------------- 348d 348d fiu_mem_start 4 continue fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 348e 348e ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 348f 348f fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR07:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 3490 3490 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f 3491 3491 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3492 3492 fiu_load_oreg 1 hold_oreg; Flow J 0x3424 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3424 0x3424 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3493 ; -------------------------------------------------------------------------------------- 3493 ; Comes from: 3493 ; 027d C True from color 0x0000 3493 ; 0d9d C False from color 0x0000 3493 ; 0dad C from color 0x0d9f 3493 ; 3414 C from color 0x22cb 3493 ; 3467 C from color 0x0000 3493 ; -------------------------------------------------------------------------------------- 3493 3493 seq_br_type 7 Unconditional Call; Flow C 0x34f2 seq_branch_adr 34f2 0x34f2 seq_en_micro 0 3494 3494 fiu_mem_start 15 setup_tag_read; Flow R cc=False ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 3495 0x3495 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3495 3495 fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3496 3496 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3497 3497 ioc_load_wdr 0 ; Flow C 0x34d8 seq_br_type 7 Unconditional Call seq_branch_adr 34d8 0x34d8 seq_en_micro 0 val_b_adr 0f GP0f 3498 3498 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3499 ; -------------------------------------------------------------------------------------- 3499 ; Comes from: 3499 ; 3483 C True from color 0x0f05 3499 ; -------------------------------------------------------------------------------------- 3499 3499 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 349a 349a ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 0f GP0f 349b ; -------------------------------------------------------------------------------------- 349b ; Comes from: 349b ; 0305 C from color 0x0000 349b ; 0405 C from color 0x03f0 349b ; 05b8 C from color 0x05a7 349b ; 06e0 C from color 0x06ce 349b ; 0919 C from color 0x0000 349b ; 0959 C from color MACRO_Execute_Module,Is_Callable 349b ; 0963 C from color MACRO_Execute_Module,Is_Callable 349b ; 097a C from color MACRO_Execute_Module,Is_Callable 349b ; 0b6c C from color 0x0000 349b ; 0db1 C from color 0x0db1 349b ; 2d3f C from color ML_break_class 349b ; 2ea7 C from color 0x0000 349b ; 2ee0 C from color 0x2ec7 349b ; 2f47 C from color 0x06b6 349b ; 32b6 C from color 0x0000 349b ; 32b8 C from color 0x0000 349b ; 33c3 C from color 0x0000 349b ; 34bc C from color 0x0000 349b ; 3967 C from color 0x03fa 349b ; 39a8 C from color 0x0000 349b ; 39bd C from color 0x0000 349b ; 3a19 C from color 0x0000 349b ; 3a35 C from color 0x3a35 349b ; 3a66 C from color 0x0000 349b ; 3ad6 C from color 0x3ad5 349b ; 3b3f C from color 0x0000 349b ; -------------------------------------------------------------------------------------- 349b 349b fiu_mem_start 11 start_tag_query ioc_tvbs 3 fiu+fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 349c 349c fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 349d 349d seq_br_type 7 Unconditional Call; Flow C 0x34f3 seq_branch_adr 34f3 0x34f3 seq_en_micro 0 349e 349e fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x34a7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 34a7 0x34a7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 349f 349f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x34a0 ; Flow J cc=#0x0 0x34a0 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 34a0 0x34a0 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 34a0 34a0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 34a1 34a1 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34a2 34a2 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34a3 34a3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0xefa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 0efa 0x0efa seq_en_micro 0 val_c_adr 30 GP0f 34a4 34a4 fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34a5 34a5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 34a6 34a6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x349b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 349b 0x349b seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 23 VR0d:03 val_b_adr 21 VR0d:01 val_frame d 34a7 34a7 seq_b_timing 1 Latch Condition; Flow C cc=False 0xfb8 seq_br_type 4 Call False seq_branch_adr 0fb8 0x0fb8 seq_en_micro 0 34a8 34a8 fiu_len_fill_reg_ctl 2 ; Flow J 0x34a5 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34a5 0x34a5 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34a9 34a9 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34aa ; -------------------------------------------------------------------------------------- 34aa ; Comes from: 34aa ; 2f23 C from color 0x06b6 34aa ; 3667 C from color 0x0200 34aa ; 3930 C from color 0x062d 34aa ; 3a20 C from color 0x03fa 34aa ; -------------------------------------------------------------------------------------- 34aa 34aa seq_en_micro 0 34ab 34ab fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34ac ; -------------------------------------------------------------------------------------- 34ac ; Comes from: 34ac ; 2f43 C from color 0x06b6 34ac ; 3993 C from color 0x398b 34ac ; -------------------------------------------------------------------------------------- 34ac 34ac seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34ad 34ad seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 34ae 0x34ae seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34ae 34ae fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x34b1 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34b1 0x34b1 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34af 34af seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 34b0 34b0 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34b1 34b1 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34b2 34b2 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34b3 34b3 fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34b4 34b4 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34b5 34b5 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34a9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34a9 0x34a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34b6 34b6 fiu_mem_start 11 start_tag_query; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34b7 0x34b7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0b GP0b val_frame 5 34b7 34b7 seq_en_micro 0 34b8 34b8 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34a9 0x34a9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34b9 34b9 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 34ba 34ba fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34aa fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34aa 0x34aa seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34bb 34bb fiu_tivi_src c mar_0xc; Flow J 0x34bc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 34bc 0x34bc seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34bc 34bc seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_en_micro 0 34bd 34bd fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34bf fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 34bf 0x34bf seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34be ; -------------------------------------------------------------------------------------- 34be ; Comes from: 34be ; 0378 C from color 0x0377 34be ; 2ef1 C from color 0x2ee5 34be ; 2f0b C from color 0x2ec7 34be ; 393f C from color 0x0913 34be ; 395d C from color 0x03fa 34be ; -------------------------------------------------------------------------------------- 34be 34be seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34bf 34bf fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x34bb fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34bb 0x34bb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34c0 34c0 fiu_mem_start 6 start_rd_if_false; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 34c1 0x34c1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34c1 34c1 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34c2 34c2 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34c3 34c3 fiu_tivi_src c mar_0xc; Flow C 0x34f4 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f4 0x34f4 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34c4 34c4 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34c5 34c5 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34bc ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34bc 0x34bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34c6 34c6 fiu_mem_start 11 start_tag_query; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34c7 0x34c7 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 2d VR05:0d val_frame 5 34c7 34c7 seq_en_micro 0 34c8 34c8 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34bc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34bc 0x34bc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34c9 34c9 seq_br_type 7 Unconditional Call; Flow C 0x33c7 seq_branch_adr 33c7 0x33c7 seq_en_micro 0 34ca 34ca fiu_mem_start 6 start_rd_if_false; Flow R cc=False ; Flow J cc=True 0x34be fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34be 0x34be seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34cb ; -------------------------------------------------------------------------------------- 34cb ; Comes from: 34cb ; 08a7 C from color 0x08a5 34cb ; 0f8a C from color 0x0ef8 34cb ; -------------------------------------------------------------------------------------- 34cb 34cb fiu_mem_start f start_physical_tag_rd; Flow C 0x34e1 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 34e1 0x34e1 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 34cc ; -------------------------------------------------------------------------------------- 34cc ; Comes from: 34cc ; 0dd3 C from color 0x0000 34cc ; -------------------------------------------------------------------------------------- 34cc 34cc fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 21 VR11:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 34cd 34cd fiu_load_var 1 hold_var; Flow J cc=False 0x34cf fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 34cf 0x34cf seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_frame 3 34ce 34ce fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 34cf 34cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_source 0 FIU_BUS 34d0 34d0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 34d1 34d1 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 7 INC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 34d2 34d2 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x2a82 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 34d3 34d3 fiu_mem_start 2 start-rd; Flow C 0x33dc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 34d4 34d4 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 34d5 34d5 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 0d GP0d 34d6 34d6 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 34d7 34d7 fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0x34d9 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34d9 0x34d9 seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 34d8 ; -------------------------------------------------------------------------------------- 34d8 ; Comes from: 34d8 ; 0ff0 C from color 0x0ff0 34d8 ; 1021 C from color 0x0fd0 34d8 ; 1079 C from color 0x1079 34d8 ; 342d C from color 0x0d34 34d8 ; 3445 C True from color 0x0d34 34d8 ; -------------------------------------------------------------------------------------- 34d8 34d8 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x34df fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34df 0x34df seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 34d9 34d9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 34da 34da fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 34db 34db fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 34dc 34dc fiu_mem_start 2 start-rd; Flow C 0x33dc fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33dc 0x33dc seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 34dd 34dd fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 34de 34de ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 34df 34df seq_en_micro 0 typ_c_adr 1c TR0c:03 typ_frame c val_c_adr 1c VR0c:03 val_frame c 34e0 34e0 fiu_mem_start f start_physical_tag_rd; Flow J 0x34e2 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 34e2 0x34e2 seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 1d TR0c:02 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34e1 ; -------------------------------------------------------------------------------------- 34e1 ; Comes from: 34e1 ; 34cb C from color 0x0f05 34e1 ; -------------------------------------------------------------------------------------- 34e1 34e1 fiu_mem_start 15 setup_tag_read; Flow J 0x34e3 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34e3 0x34e3 seq_en_micro 0 typ_c_adr 1d TR0c:02 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 31 VR02:11 val_frame 2 34e2 34e2 fiu_mem_start 15 setup_tag_read seq_en_micro 0 34e3 34e3 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x34eb fiu_mem_start 15 setup_tag_read fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34eb 0x34eb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 29 VR0c:09 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 34e4 34e4 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x34eb fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34eb 0x34eb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 19 X_XOR_B val_b_adr 26 VR0c:06 val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 34e5 34e5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x34f0 seq_br_type 1 Branch True seq_branch_adr 34f0 0x34f0 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 34e6 34e6 fiu_mem_start 2 start-rd; Flow J 0x34e7 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 34ea 0x34ea seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 22 TR0c:02 typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 25 VR0c:05 val_frame c 34e7 34e7 seq_b_timing 0 Early Condition; Flow J cc=True 0x34ed seq_br_type 1 Branch True seq_branch_adr 34ed 0x34ed seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 34e8 34e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x34ec fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ec 0x34ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 28 VR0c:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 34e9 34e9 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34ea 34ea ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0c:04 typ_frame c val_b_adr 24 VR0c:04 val_frame c 34eb 34eb ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 23 TR0c:03 typ_frame c val_b_adr 23 VR0c:03 val_frame c 34ec 34ec fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 24 TR0c:04 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR0c:07 typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c 34ed 34ed fiu_tivi_src 1 tar_val; Flow J cc=True 0x34ef ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ef 0x34ef seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_source 0 FIU_BUS val_frame c val_rand 9 PASS_A_HIGH 34ee 34ee seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x34ec seq_br_type 1 Branch True seq_branch_adr 34ec 0x34ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 24 TR0c:04 typ_frame c val_a_adr 24 VR0c:04 val_alu_func 1c DEC_A val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 34ef 34ef fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34f0 34f0 seq_br_type 3 Unconditional Branch; Flow J 0x34eb seq_branch_adr 34eb 0x34eb seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR0c:02 typ_c_adr 1a TR0c:05 typ_c_mux_sel 0 ALU typ_frame c 34f1 ; -------------------------------------------------------------------------------------- 34f1 ; Comes from: 34f1 ; 0d53 C from color 0x0000 34f1 ; 0e01 C from color 0x0000 34f1 ; 0ea8 C from color 0x0000 34f1 ; 0ed6 C from color 0x0ed6 34f1 ; 1009 C from color 0x0fd0 34f1 ; 3404 C from color 0x22cb 34f1 ; -------------------------------------------------------------------------------------- 34f1 34f1 seq_en_micro 0 34f2 ; -------------------------------------------------------------------------------------- 34f2 ; Comes from: 34f2 ; 0f7a C from color 0x0ef8 34f2 ; 2ac4 C from color 0x2abd 34f2 ; 3482 C from color 0x0f05 34f2 ; 3493 C from color 0x3493 34f2 ; 3b5b C from color 0x3b5b 34f2 ; -------------------------------------------------------------------------------------- 34f2 34f2 seq_en_micro 0 34f3 ; -------------------------------------------------------------------------------------- 34f3 ; Comes from: 34f3 ; 084a C from color 0x0820 34f3 ; 0d43 C from color 0x0000 34f3 ; 0d87 C from color 0x0000 34f3 ; 0ef0 C from color 0x0000 34f3 ; 0f7e C from color 0x0ef8 34f3 ; 0fa3 C from color 0x0ef8 34f3 ; 0faf C from color 0x0ef8 34f3 ; 1031 C from color 0x0fd0 34f3 ; 1039 C from color 0x0fd0 34f3 ; 33cc C from color 0x0f05 34f3 ; 3428 C from color 0x0d34 34f3 ; 349d C from color 0x349b 34f3 ; -------------------------------------------------------------------------------------- 34f3 34f3 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34f4 ; -------------------------------------------------------------------------------------- 34f4 ; Comes from: 34f4 ; 101d C from color 0x0fd0 34f4 ; 105e C from color 0x0000 34f4 ; 33e3 C from color 0x0000 34f4 ; 3402 C from color 0x22cb 34f4 ; 341a C from color 0x0000 34f4 ; 34b3 C from color 0x0000 34f4 ; 34c3 C from color 0x0000 34f4 ; -------------------------------------------------------------------------------------- 34f4 34f4 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x34f7 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 34f7 0x34f7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34f5 34f5 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 34f6 34f6 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 34f7 34f7 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 34f8 34f8 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 34f9 ; -------------------------------------------------------------------------------------- 34f9 ; Comes from: 34f9 ; 33f8 C from color 0x0000 34f9 ; 39eb C from color 0x0000 34f9 ; 3a10 C from color 0x0000 34f9 ; -------------------------------------------------------------------------------------- 34f9 34f9 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34fa ; -------------------------------------------------------------------------------------- 34fa ; Comes from: 34fa ; 08e1 C from color 0x0127 34fa ; 0b86 C from color 0x0b83 34fa ; 0b89 C from color 0x0b83 34fa ; 0e0e C from color 0x0000 34fa ; 0f0b C from color 0x0000 34fa ; 0f9c C from color 0x0ef8 34fa ; 0ff6 C from color 0x0fd0 34fa ; 0ffc C from color 0x0fd0 34fa ; 1076 C from color 0x0ef8 34fa ; 107f C from color 0x0ef8 34fa ; 33d3 C from color 0x0f05 34fa ; -------------------------------------------------------------------------------------- 34fa 34fa fiu_mem_start 15 setup_tag_read; Flow R seq_br_type a Unconditional Return seq_en_micro 0 34fb ; -------------------------------------------------------------------------------------- 34fb ; Comes from: 34fb ; 2afd C from color 0x2af9 34fb ; -------------------------------------------------------------------------------------- 34fb 34fb fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x350f fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 350f 0x350f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 34fc 34fc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3504 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3504 0x3504 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 34fd 34fd ioc_fiubs 0 fiu ; Flow C cc=False 0x329a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 329a 0x329a seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 34fe 34fe val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 34ff 34ff fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x3505 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3505 0x3505 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 3500 3500 ioc_fiubs 0 fiu ; Flow J cc=False 0x3502 seq_br_type 0 Branch False seq_branch_adr 3502 0x3502 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 33 VR02:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 3501 3501 fiu_mem_start 3 start-wr; Flow J cc=True 0x3502 ; Flow J cc=#0x0 0x3507 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3507 0x3507 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3502 3502 ioc_fiubs 0 fiu 3503 3503 seq_b_timing 0 Early Condition; Flow J cc=True 0x3504 ; Flow J cc=#0x0 0x3507 seq_br_type b Case False seq_branch_adr 3507 0x3507 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3504 3504 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3505 3505 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3506 0x3506 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3506 3506 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a 3507 3507 ioc_load_wdr 0 ; Flow J 0x350e seq_br_type 3 Unconditional Branch seq_branch_adr 350e 0x350e typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 3508 3508 ioc_load_wdr 0 ; Flow J 0x350e seq_br_type 3 Unconditional Branch seq_branch_adr 350e 0x350e typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 3509 3509 ioc_load_wdr 0 ; Flow J 0x350e seq_br_type 3 Unconditional Branch seq_branch_adr 350e 0x350e typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 350a 350a seq_br_type 7 Unconditional Call; Flow C 0x330b seq_branch_adr 330b 0x330b seq_random 05 ? 350b 350b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_random 02 ? val_a_adr 06 GP06 350c 350c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 45 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR07:18 val_alu_func 1a PASS_B val_frame 7 350d 350d ioc_load_wdr 0 ; Flow J 0x350e ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 350e 0x350e typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 350e 350e fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 350f 350f fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x329a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329a 0x329a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_frame 2 3510 3510 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 3c TR07:1c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 3511 3511 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 39 TR02:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3512 3512 fiu_mem_start 3 start-wr; Flow J cc=True 0x3513 ; Flow J cc=#0x0 0x3507 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3507 0x3507 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3513 3513 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32aa fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3514 3514 ioc_fiubs 0 fiu ; Flow C cc=True 0x3518 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3518 0x3518 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3515 3515 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3516 0x3516 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 06 GP06 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3516 3516 seq_br_type 4 Call False; Flow C 0x329e seq_branch_adr 329e 0x329e seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 3517 3517 seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 9 Return False seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3518 ; -------------------------------------------------------------------------------------- 3518 ; Comes from: 3518 ; 3514 C True from color 0x0000 3518 ; -------------------------------------------------------------------------------------- 3518 3518 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x351e seq_br_type 1 Branch True seq_branch_adr 351e 0x351e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3519 3519 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 351a 351a typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 351b 351b typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 351c 351c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 351d 351d ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 351e 351e seq_br_type a Unconditional Return; Flow R val_a_adr 08 GP08 val_alu_func 7 INC_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 351f 351f typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3520 3520 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3521 3521 ioc_fiubs 0 fiu ; Flow J cc=True 0x3574 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3574 0x3574 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 3522 3522 seq_br_type 3 Unconditional Branch; Flow J 0x3524 seq_branch_adr 3524 0x3524 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3523 3523 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3575 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3575 0x3575 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_rand 9 PASS_A_HIGH 3524 3524 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0f GP0f 3525 3525 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x352c ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 352c 0x352c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 3526 3526 fiu_load_tar 1 hold_tar; Flow J cc=False 0x352f fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 352f 0x352f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3527 3527 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_b_adr 06 GP06 3528 3528 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3529 3529 fiu_length_src 0 length_register; Flow J cc=False 0x3541 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 3541 0x3541 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_c_adr 31 GP0e val_c_source 0 FIU_BUS 352a 352a seq_br_type 2 Push (branch address); Flow J 0x352b seq_branch_adr 3523 0x3523 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 352b 352b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 352c 352c fiu_load_var 1 hold_var; Flow J cc=False 0x3539 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3539 0x3539 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 352d 352d fiu_load_tar 1 hold_tar; Flow J cc=True 0x3527 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3527 0x3527 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 352e 352e seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 352f 352f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x3573 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3573 0x3573 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand 1 INC_LOOP_COUNTER 3530 3530 fiu_tivi_src 1 tar_val; Flow J cc=True 0x353d ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 353d 0x353d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3531 3531 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3532 3532 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3536 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3536 0x3536 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3533 3533 fiu_length_src 0 length_register; Flow J cc=False 0x353f fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 353f 0x353f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3534 3534 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x353f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 353f 0x353f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3535 3535 fiu_load_oreg 1 hold_oreg; Flow J 0x3527 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3527 0x3527 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0d GP0d 3536 3536 fiu_load_var 1 hold_var; Flow J cc=False 0x353f fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 353f 0x353f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3537 3537 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 3538 3538 fiu_length_src 0 length_register; Flow J 0x3534 fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 3534 0x3534 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3539 3539 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 353a 353a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x210 fiu_mem_start a start_continue_if_false fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 353b 353b ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 353c 353c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3531 seq_br_type 1 Branch True seq_branch_adr 3531 0x3531 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 353d 353d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 353e 353e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3520 seq_br_type 3 Unconditional Branch seq_branch_adr 3520 0x3520 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 353f 353f fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3540 3540 seq_br_type 3 Unconditional Branch; Flow J 0x3520 seq_branch_adr 3520 0x3520 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3541 3541 fiu_length_src 0 length_register; Flow J cc=True 0x354a fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 354a 0x354a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 3542 3542 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3543 3543 fiu_fill_mode_src 0 ; Flow J cc=False 0x3546 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3546 0x3546 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3544 3544 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3545 3545 ioc_load_wdr 0 ; Flow J 0x354c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 354c 0x354c seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3546 3546 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3547 3547 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3548 3548 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 3549 3549 ioc_load_wdr 0 ; Flow J 0x354c ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 354c 0x354c val_b_adr 0e GP0e 354a 354a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 354b 354b ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 354c 354c fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 354d 354d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 07 GP07 354e 354e fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 35 TR02:15 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f 354f 354f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3552 ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3552 0x3552 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 37 GP08 val_c_source 0 FIU_BUS 3550 3550 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA 3551 3551 ioc_load_wdr 0 ; Flow J 0x3556 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3556 0x3556 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 3552 3552 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 3553 3553 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3554 3554 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR 3555 3555 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 3556 3556 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3592 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3592 0x3592 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_b_adr 07 GP07 3557 3557 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 3558 3558 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_b_adr 06 GP06 3559 3559 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 355a 355a seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 13 355b 355b seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 355c 355c fiu_fill_mode_src 0 ; Flow J cc=True 0x3568 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3568 0x3568 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 355d 355d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 355e 355e fiu_fill_mode_src 0 ; Flow J cc=False 0x356a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 356a 0x356a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 355f 355f fiu_fill_mode_src 0 ; Flow C cc=False 0x3571 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3571 0x3571 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3560 3560 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3561 3561 fiu_mem_start 7 start_wr_if_true ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3562 3562 ioc_load_wdr 0 ; Flow J cc=True 0x3592 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3592 0x3592 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 val_b_adr 06 GP06 3563 3563 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3564 3564 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3565 3565 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3566 3566 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 3567 3567 fiu_fill_mode_src 0 ; Flow J 0x355d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 355d 0x355d val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3568 3568 seq_br_type 0 Branch False; Flow J cc=False 0x3592 seq_branch_adr 3592 0x3592 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 3569 3569 seq_br_type 3 Unconditional Branch; Flow J 0x3566 seq_branch_adr 3566 0x3566 typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 356a 356a fiu_fill_mode_src 0 ; Flow C cc=False 0x356e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 356e 0x356e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 356b 356b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 356c 356c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 356d 356d ioc_load_wdr 0 ; Flow J 0x3561 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3561 0x3561 val_b_adr 0e GP0e 356e ; -------------------------------------------------------------------------------------- 356e ; Comes from: 356e ; 356a C False from color 0x0000 356e ; -------------------------------------------------------------------------------------- 356e 356e fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 356f 356f fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3570 3570 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 3571 ; -------------------------------------------------------------------------------------- 3571 ; Comes from: 3571 ; 355f C False from color 0x0000 3571 ; -------------------------------------------------------------------------------------- 3571 3571 fiu_mem_start 2 start-rd; Flow C 0x3573 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 3573 0x3573 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 3572 3572 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3573 ; -------------------------------------------------------------------------------------- 3573 ; Comes from: 3573 ; 1b23 C from color MACRO_Execute_Access,Deallocate 3573 ; 352f C from color 0x0000 3573 ; 3571 C from color 0x3571 3573 ; -------------------------------------------------------------------------------------- 3573 3573 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3574 3574 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 3575 3575 ioc_tvbs 1 typ+fiu val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3576 3576 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32aa fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32aa 0x32aa seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3577 3577 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS 3578 3578 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3588 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3588 0x3588 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3579 3579 seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 357a 357a seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 357b 357b ioc_fiubs 2 typ ; Flow J cc=True 0x3582 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3582 0x3582 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 357c 357c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 08 GP08 357d 357d ioc_load_wdr 0 ; Flow J cc=False 0x3585 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3585 0x3585 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 06 GP06 357e 357e fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x3585 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 3585 0x3585 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 357f 357f fiu_fill_mode_src 0 ; Flow J cc=False 0x358e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 358e 0x358e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 3580 3580 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3581 3581 ioc_load_wdr 0 ; Flow J 0x3592 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3592 0x3592 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 3582 3582 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3583 3583 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x357c seq_br_type 0 Branch False seq_branch_adr 357c 0x357c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3584 3584 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e 3585 3585 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3586 3586 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3587 3587 fiu_load_var 1 hold_var; Flow J 0x3575 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3575 0x3575 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3588 ; -------------------------------------------------------------------------------------- 3588 ; Comes from: 3588 ; 3578 C True from color 0x0000 3588 ; -------------------------------------------------------------------------------------- 3588 3588 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x351e seq_br_type 1 Branch True seq_branch_adr 351e 0x351e seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3589 3589 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 358a 358a typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 7 358b 358b typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 358c 358c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 358d 358d ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 358e 358e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 358f 358f fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 3590 3590 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 3591 3591 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 3592 3592 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3593 3593 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3594 ; -------------------------------------------------------------------------------------- 3594 ; Comes from: 3594 ; 10c6 C from color 0x10a8 3594 ; 10cb C from color 0x10bf 3594 ; 10e0 C from color 0x10d4 3594 ; 10f4 C from color 0x10d5 3594 ; 1122 C from color 0x110d 3594 ; 1132 C from color 0x110d 3594 ; 1140 C from color 0x110d 3594 ; 114a C from color 0x110d 3594 ; 1159 C from color 0x1115 3594 ; 1162 C from color 0x1162 3594 ; 117d C from color 0x111b 3594 ; 1194 C from color 0x111b 3594 ; 11c1 C from color 0x111b 3594 ; 11cc C from color 0x111b 3594 ; 120a C from color 0x10bf 3594 ; 121e C from color 0x10d4 3594 ; 1231 C from color 0x11ff 3594 ; 123a C from color 0x11ff 3594 ; 1287 C from color 0x10d4 3594 ; 12ae C from color 0x125d 3594 ; -------------------------------------------------------------------------------------- 3594 3594 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x3595 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3597 0x3597 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 07 GP07 3595 3595 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3513 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3513 0x3513 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 3596 3596 seq_br_type 3 Unconditional Branch; Flow J 0x351f seq_branch_adr 351f 0x351f seq_random 06 Pop_stack+? val_c_adr 39 GP06 3597 3597 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 3598 3598 ioc_fiubs 2 typ ; Flow R cc=True ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3599 0x3599 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3599 3599 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 359a 359a fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 359b 359b ioc_fiubs 1 val ; Flow J 0x359c seq_br_type 2 Push (branch address) seq_branch_adr 35a0 0x35a0 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 359c 359c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x359f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 359f 0x359f seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 37 VR13:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 359d 359d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3513 fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3513 0x3513 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 359e 359e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 359f 359f seq_br_type 3 Unconditional Branch; Flow J 0x32fc seq_branch_adr 32fc 0x32fc seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 35a0 35a0 fiu_load_var 1 hold_var; Flow C 0x210 fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35a1 35a1 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35a2 35a2 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 35a3 35a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME 35a4 35a4 fiu_fill_mode_src 0 ; Flow J cc=False 0x35a6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35a6 0x35a6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 35a5 35a5 fiu_fill_mode_src 0 ; Flow J 0x35a9 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35a9 0x35a9 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35a6 35a6 fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35a7 35a7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 35a8 35a8 fiu_load_var 1 hold_var; Flow J 0x35a9 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 35a9 0x35a9 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 35a9 35a9 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 35aa 35aa fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 3a VR05:1a val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 35ab 35ab fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35ac 35ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32ac seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 35ad 35ad fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 35ae 0x35ae seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR11:07 val_frame 11 35ae 35ae seq_br_type 7 Unconditional Call; Flow C 0x32ac seq_branch_adr 32ac 0x32ac 35af 35af fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_b_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 35b0 35b0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 35b1 35b1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 35b2 35b2 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x35ba fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35ba 0x35ba seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 35b3 35b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x35b7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 35b7 0x35b7 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 35b4 35b4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3e GP01 val_c_source 0 FIU_BUS 35b5 35b5 ioc_tvbs 2 fiu+val seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35b6 35b6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x35b9 fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 35b9 0x35b9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 35b7 35b7 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 35b8 35b8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 35b9 0x35b9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 4 35b9 35b9 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af typ_csa_cntl 3 POP_CSA 35ba 35ba fiu_load_var 1 hold_var; Flow J 0x35b8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 35b8 0x35b8 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 35bb 35bb ioc_fiubs 2 typ ; Flow J cc=True 0x35c4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35c4 0x35c4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35bc 35bc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 35bd 35bd seq_b_timing 1 Latch Condition; Flow J cc=True 0x35c3 seq_br_type 1 Branch True seq_branch_adr 35c3 0x35c3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 35be 35be fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32af ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32af 0x32af typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35bf 35bf val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35c0 35c0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32af fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 35c1 35c1 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32af seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32af 0x32af seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 35c2 35c2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 35c3 35c3 fiu_mem_start 2 start-rd; Flow J 0x35bf ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 35bf 0x35bf typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35c4 35c4 seq_br_type 3 Unconditional Branch; Flow J 0x35c2 seq_branch_adr 35c2 0x35c2 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35c5 35c5 seq_br_type 4 Call False; Flow C cc=False 0x32af seq_branch_adr 32af 0x32af seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35c6 35c6 fiu_mem_start 2 start-rd; Flow C cc=True 0x32af ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32af 0x32af seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35c7 35c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32af fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 35c8 35c8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 35c9 35c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35cb fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35cb 0x35cb seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35ca 35ca ioc_load_wdr 0 ; Flow J cc=False 0x35cc ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 35cc 0x35cc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 35cb 35cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 35cc 35cc fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc 35cd 35cd seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 35ce 35ce seq_br_type 4 Call False; Flow C cc=False 0x32af seq_branch_adr 32af 0x32af seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35cf 35cf fiu_mem_start 2 start-rd; Flow C cc=True 0x32af ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32af 0x32af seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 35d0 35d0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32af fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32af 0x32af seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 35d1 35d1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 35d2 35d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35ca fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 35ca 0x35ca seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35d3 35d3 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 35d4 35d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x326c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 35d5 35d5 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 35d6 35d6 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35d7 35d7 ioc_load_wdr 0 typ_csa_cntl 3 POP_CSA 35d8 35d8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 35d9 35d9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x326c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 326c 0x326c seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 35da 35da fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 35db 35db fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 35dc 0x35dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 35dc 35dc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 35dd 35dd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x35e6 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 35e6 0x35e6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 35de 35de fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a5 ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 35df 35df fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x326f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 35e0 35e0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 35e1 35e1 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35e2 35e2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 35e3 35e3 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 35e4 35e4 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1d46 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 35e5 35e5 seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 35e6 35e6 ioc_fiubs 0 fiu ; Flow J cc=True 0x3602 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3602 0x3602 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 35e7 35e7 fiu_load_tar 1 hold_tar; Flow J cc=False 0x35ea fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35ea 0x35ea seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 35e8 35e8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3603 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3603 0x3603 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 35e9 35e9 seq_br_type 7 Unconditional Call; Flow C 0x3277 seq_branch_adr 3277 0x3277 seq_en_micro 0 seq_random 02 ? 35ea 35ea fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 35eb 35eb fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35ec 35ec fiu_mem_start a start_continue_if_false; Flow J cc=False 0x35ef ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35ef 0x35ef seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 35ed 35ed fiu_fill_mode_src 0 ; Flow C cc=False 0x35fe fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 35fe 0x35fe typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 35ee 35ee seq_br_type 3 Unconditional Branch; Flow J 0x35f2 seq_branch_adr 35f2 0x35f2 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 35ef 35ef fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35f0 35f0 fiu_fill_mode_src 0 ; Flow C cc=False 0x35fe fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 35fe 0x35fe typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 35f1 35f1 seq_br_type 3 Unconditional Branch; Flow J 0x35f2 seq_branch_adr 35f2 0x35f2 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 35f2 35f2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x35f5 seq_br_type 1 Branch True seq_branch_adr 35f5 0x35f5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 35f3 35f3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 35f4 35f4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 35f5 35f5 seq_br_type 1 Branch True; Flow J cc=True 0x3603 seq_branch_adr 3603 0x3603 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B 35f6 35f6 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 35f7 35f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35fc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 35fc 0x35fc typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35f8 35f8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x35fa seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35fa 0x35fa seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 35f9 35f9 fiu_fill_mode_src 0 ; Flow J 0x35f6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35f6 0x35f6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 35fa 35fa fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35fb 35fb fiu_fill_mode_src 0 ; Flow J 0x35f6 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35f6 0x35f6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 35fc 35fc seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 35fd 35fd seq_br_type 3 Unconditional Branch; Flow J 0x3603 seq_branch_adr 3603 0x3603 seq_en_micro 0 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 35fe ; -------------------------------------------------------------------------------------- 35fe ; Comes from: 35fe ; 35ed C False from color 0x0000 35fe ; 35f0 C False from color 0x0000 35fe ; -------------------------------------------------------------------------------------- 35fe 35fe fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3600 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3600 0x3600 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 35ff 35ff fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3600 3600 fiu_load_var 1 hold_var; Flow C cc=False 0x3075 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3075 0x3075 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3601 3601 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3602 3602 fiu_mem_start 2 start-rd; Flow C 0x2452 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2452 0x2452 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3603 3603 fiu_mem_start 2 start-rd; Flow C cc=True 0x326f ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 326f 0x326f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 3604 3604 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3605 3605 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3608 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3608 0x3608 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 3606 3606 fiu_mem_start 2 start-rd; Flow C 0x323d ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 323d 0x323d typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3607 3607 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 3608 3608 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3609 3609 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 39 GP06 val_c_source 0 FIU_BUS 360a 360a val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 360b 360b ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 360c 360c seq_br_type 5 Call True; Flow C cc=True 0x1eec seq_branch_adr 1eec 0x1eec seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 360d 360d fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 360e 0x360e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 360e 360e seq_br_type 7 Unconditional Call; Flow C 0x32af seq_branch_adr 32af 0x32af 360f 360f fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3610 3610 fiu_len_fill_lit 75 zero-fill 0x35 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3611 3611 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3614 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3614 0x3614 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_frame 19 val_a_adr 38 VR12:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3612 3612 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 3613 3613 fiu_mem_start 3 start-wr seq_en_micro 0 3614 3614 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_c_adr 1e TR19:01 typ_frame 19 val_b_adr 0d GP0d val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 3615 3615 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3617 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3617 0x3617 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3616 3616 fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x211 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 39 TR12:19 typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 20 VR19:00 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 3617 3617 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2b VR11:0b val_frame 11 3618 3618 ioc_load_wdr 0 ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_frame 2 3619 3619 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 23 TR0d:03 typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 1c TR0d:03 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 29 VR0d:09 val_alu_func 0 PASS_A val_c_adr 15 VR0d:0a val_c_mux_sel 2 ALU val_frame d 361a 361a fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 7f fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 21 TR11:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 11 val_b_adr 30 VR02:10 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame 2 361b 361b fiu_tivi_src c mar_0xc; Flow C cc=True 0xba9 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0ba9 0x0ba9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 16 VR0d:09 val_c_source 0 FIU_BUS val_frame d 361c 361c seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 361d 361d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 22 TR11:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 361e 361e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 0e GP0e val_a_adr 2f VR02:0f val_b_adr 39 VR02:19 val_frame 2 361f 361f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_frame d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 3620 3620 ioc_fiubs 0 fiu ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 0e GP0e val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3621 3621 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3711 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3711 0x3711 seq_en_micro 0 seq_random 0a ? typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3622 ; -------------------------------------------------------------------------------------- 3622 ; Comes from: 3622 ; 0fba C from color 0x0fb9 3622 ; -------------------------------------------------------------------------------------- 3622 3622 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x360f fiu_load_mdr 1 hold_mdr fiu_offs_lit 02 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 360f 0x360f seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2a VR05:0a val_frame 5 3623 3623 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_frame 3 3624 3624 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 3625 3625 ioc_fiubs 0 fiu ; Flow J 0x3611 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3611 0x3611 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3626 3626 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x360f fiu_load_mdr 1 hold_mdr fiu_offs_lit 03 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 360f 0x360f seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2b VR05:0b val_frame 5 3627 3627 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x360f fiu_load_mdr 1 hold_mdr fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 360f 0x360f seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR06:01 val_frame 6 3628 ; -------------------------------------------------------------------------------------- 3628 ; Comes from: 3628 ; 344d C from color 0x02c9 3628 ; -------------------------------------------------------------------------------------- 3628 3628 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x360f fiu_load_mdr 1 hold_mdr fiu_offs_lit 05 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 360f 0x360f seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 3d VR02:1d val_frame 2 3629 3629 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x360f fiu_load_mdr 1 hold_mdr fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 360f 0x360f seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 23 VR07:03 val_frame 7 362a 362a ioc_tvbs 1 typ+fiu; Flow J cc=True 0x362b ; Flow J cc=#0x0 0x362b seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 362b 0x362b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 28 VR05:08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 362b 362b seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 362c 362c fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 362d 362d fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 362e 362e fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 362f 362f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3630 3630 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3631 3631 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3638 fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3638 0x3638 seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3632 3632 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363d fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363d 0x363d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3633 3633 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3634 3634 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x363b fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 363b 0x363b seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3635 3635 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3642 fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3642 0x3642 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3636 3636 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3644 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3644 0x3644 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3637 ; -------------------------------------------------------------------------------------- 3637 ; Comes from: 3637 ; 3638 C from color 0x362c 3637 ; 363f C from color 0x0fd0 3637 ; -------------------------------------------------------------------------------------- 3637 3637 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3638 3638 fiu_mem_start 2 start-rd; Flow C 0x3637 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3637 0x3637 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3639 3639 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 363a 363a ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 2 typ_frame 1f val_b_adr 0c GP0c 363b 363b fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 7d fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 363c 363c ioc_load_wdr 0 ; Flow J 0x3b59 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b59 0x3b59 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 363d 363d ioc_adrbs 1 val ; Flow C 0xfd0 seq_br_type 7 Unconditional Call seq_branch_adr 0fd0 0x0fd0 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 363e 363e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 363f 0x363f seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 363f 363f fiu_mem_start 2 start-rd; Flow C 0x3637 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3637 0x3637 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3640 3640 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3641 3641 ioc_adrbs 2 typ ; Flow R cc=True ; Flow J cc=False 0x104f ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 104f 0x104f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3642 3642 ioc_adrbs 1 val ; Flow C 0xfd0 seq_br_type 7 Unconditional Call seq_branch_adr 0fd0 0x0fd0 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3643 3643 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3644 3644 seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3645 3645 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3646 3646 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3647 3647 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 32 VR03:12 val_frame 3 3648 3648 ioc_load_wdr 0 ; Flow J 0x3b4a ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 3649 ; -------------------------------------------------------------------------------------- 3649 ; Comes from: 3649 ; 0141 C from color 0x0141 3649 ; 08f6 C from color 0x0127 3649 ; -------------------------------------------------------------------------------------- 3649 3649 fiu_load_var 1 hold_var; Flow C 0x364b fiu_vmux_sel 1 fill value ioc_random f disable delay timer seq_br_type 7 Unconditional Call seq_branch_adr 364b 0x364b seq_en_micro 0 364a 364a fiu_load_var 1 hold_var; Flow J 0x364e fiu_vmux_sel 1 fill value ioc_random d disable slice timer seq_br_type 3 Unconditional Branch seq_branch_adr 364e 0x364e seq_en_micro 0 364b ; -------------------------------------------------------------------------------------- 364b ; Comes from: 364b ; 3649 C from color 0x337f 364b ; -------------------------------------------------------------------------------------- 364b 364b fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 364c 364c ioc_random 7 load delay timer ioc_tvbs 2 fiu+val seq_en_micro 0 364d 364d ioc_random b clear delay event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 364e 364e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 364f ; -------------------------------------------------------------------------------------- 364f ; Comes from: 364f ; 0763 C from color 0x0000 364f ; 07bd C from color 0x07b9 364f ; 0f76 C from color 0x0f62 364f ; -------------------------------------------------------------------------------------- 364f 364f ioc_random 6 load slice timer ioc_tvbs 2 fiu+val seq_en_micro 0 3650 3650 ioc_random a clear slice event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 3651 ; -------------------------------------------------------------------------------------- 3651 ; Comes from: 3651 ; 0567 C from color 0x0567 3651 ; 05a0 C from color 0x0599 3651 ; 0812 C from color 0x0000 3651 ; 0ee6 C from color 0x0ee6 3651 ; -------------------------------------------------------------------------------------- 3651 3651 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 3652 3652 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3653 3653 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 3654 3654 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 39 VR03:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3655 3655 fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 39 VR03:19 val_frame 3 3656 3656 ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3657 3657 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 3658 3658 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 3659 3659 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 365a 365a seq_en_micro 0 365b 365b fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 365c 365c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 365d 365d fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 val_b_adr 3a VR04:1a val_frame 4 365e 365e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x3665 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3665 0x3665 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 05 VR04:1a val_c_mux_sel 2 ALU val_frame 4 365f 365f fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3660 3660 seq_en_micro 0 3661 3661 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 05 TR04:1a typ_c_mux_sel 0 ALU typ_frame 4 3662 3662 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3663 3663 seq_br_type 0 Branch False; Flow J cc=False 0x3665 seq_branch_adr 3665 0x3665 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3a TR04:1a typ_b_adr 2d TR04:0d typ_frame 4 3664 3664 fiu_mem_start 2 start-rd; Flow J 0x3660 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3660 0x3660 seq_en_micro 0 typ_a_adr 2d TR04:0d typ_alu_func 0 PASS_A typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3665 3665 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3666 3666 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 3667 3667 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3668 3668 fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 3669 3669 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 4 366a 366a fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 366b 366b fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3674 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3674 0x3674 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 366c 366c fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 366d 366d seq_en_micro 0 366e 366e fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 366f 366f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3674 seq_br_type 1 Branch True seq_branch_adr 3674 0x3674 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3670 3670 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3671 3671 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 04 GP04 3672 3672 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 3673 3673 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3674 3674 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x20a ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1e TR17:01 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3675 3675 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 3676 3676 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3677 3677 fiu_len_fill_lit 44 zero-fill 0x4 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3678 3678 ioc_load_wdr 0 ; Flow J cc=True 0x3680 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3680 0x3680 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 3679 3679 seq_br_type 4 Call False; Flow C cc=False 0x20a seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 367a 367a ioc_tvbs 2 fiu+val; Flow J cc=True 0x367e seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 367e 0x367e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 367b 367b seq_b_timing 1 Latch Condition; Flow J cc=True 0x3682 seq_br_type 1 Branch True seq_branch_adr 3682 0x3682 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 367c 367c seq_b_timing 1 Latch Condition; Flow J cc=True 0x368a seq_br_type 1 Branch True seq_branch_adr 368a 0x368a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 367d 367d seq_b_timing 1 Latch Condition; Flow J cc=True 0x368a seq_br_type 1 Branch True seq_branch_adr 368a 0x368a seq_en_micro 0 367e 367e seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 367f 367f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3680 3680 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b52 fiu_load_mdr 1 hold_mdr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3b52 0x3b52 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 3681 3681 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 3682 3682 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3686 seq_br_type 1 Branch True seq_branch_adr 3686 0x3686 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 3683 3683 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3684 3684 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3685 3685 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20a ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3686 3686 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3687 3687 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3688 3688 seq_br_type 1 Branch True; Flow J cc=True 0x367e seq_branch_adr 367e 0x367e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3689 3689 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 368a 368a fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 368b 368b seq_en_micro 0 368c 368c fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 368d 368d fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x58b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 058b 0x058b seq_en_micro 0 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 368e 368e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 368f ; -------------------------------------------------------------------------------------- 368f ; Comes from: 368f ; 0e0d C from color 0x0000 368f ; 106f C from color 0x0ef8 368f ; 3b6a C from color 0x0ba9 368f ; -------------------------------------------------------------------------------------- 368f 368f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 3690 3690 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 3691 3691 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3692 3692 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 3693 3693 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 3694 3694 fiu_mem_start 4 continue ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR04:03 val_frame 4 3695 3695 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3698 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3698 0x3698 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 3696 3696 seq_br_type 7 Unconditional Call; Flow C 0x6ec seq_branch_adr 06ec 0x06ec seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 3697 3697 seq_br_type 3 Unconditional Branch; Flow J 0x36ae seq_branch_adr 36ae 0x36ae seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3698 3698 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x36a2 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36a2 0x36a2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3c TR09:1c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 3699 3699 ioc_adrbs 1 val ; Flow C cc=#0x0 0x369e seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 369e 0x369e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_frame 4 369a 369a fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 369b 369b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS 369c 369c fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 369d 369d ioc_load_wdr 0 ; Flow J 0x36ae ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36ae 0x36ae seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 369e ; -------------------------------------------------------------------------------------- 369e ; Comes from: 369e ; 3699 C #0x0 from color 0x05a7 369e ; -------------------------------------------------------------------------------------- 369e 369e seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 369f 369f seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36a0 36a0 seq_br_type 3 Unconditional Branch; Flow J 0x3b85 seq_branch_adr 3b85 0x3b85 seq_en_micro 0 36a1 36a1 seq_br_type 3 Unconditional Branch; Flow J 0x3b87 seq_branch_adr 3b87 0x3b87 seq_en_micro 0 36a2 36a2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3696 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3696 0x3696 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36a3 36a3 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36a4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 36a7 0x36a7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 36a4 36a4 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 36a5 36a5 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 36a6 36a6 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36a7 36a7 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 36a8 36a8 seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 36a9 36a9 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36aa 36aa fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36ab 36ab fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 36 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 36ac 36ac fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_en_micro 0 36ad 36ad fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36ae fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36ae 0x36ae seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_source 0 FIU_BUS typ_frame 4 36ae 36ae fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3b TR05:1b typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_c_adr 13 VR04:0c val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 36af 36af seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 val_a_adr 26 VR04:06 val_alu_func 6 A_MINUS_B val_b_adr 2c VR04:0c val_frame 4 36b0 36b0 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36b1 36b1 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36b2 36b2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 12 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 36b3 36b3 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 36b4 36b4 ioc_fiubs 1 val ; Flow J cc=False 0x36bc ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 36bc 0x36bc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 38 VR05:18 val_frame 5 36b5 36b5 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2c TR04:0c typ_alu_func 0 PASS_A typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 3c VR12:1c val_frame 12 36b6 36b6 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36b7 36b7 ioc_load_wdr 0 ; Flow J cc=True 0x36be ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 36be 0x36be seq_en_micro 0 36b8 36b8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 26 VR04:06 val_frame 4 36b9 36b9 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36ba 36ba seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36bb 0x36bb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 26 VR04:06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36bb 36bb seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36bc 36bc ioc_tvbs 2 fiu+val; Flow J cc=False 0x36b6 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 36b6 0x36b6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36bd 36bd fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36b6 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36b6 0x36b6 seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 36be 36be fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 22 TR04:02 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 36bf 36bf seq_en_micro 0 36c0 36c0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_a_adr 31 VR04:11 val_alu_func 0 PASS_A val_c_adr 13 VR04:0c val_c_mux_sel 2 ALU val_frame 4 36c1 36c1 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR04:03 val_frame 4 36c2 36c2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR04:03 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36c3 36c3 seq_en_micro 0 val_a_adr 2c VR04:0c val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36c4 36c4 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 36c5 36c5 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36c6 36c6 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 2c VR04:0c val_frame 4 36c7 36c7 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36c8 36c8 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36c9 0x36c9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 36c9 36c9 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36ca ; -------------------------------------------------------------------------------------- 36ca ; 0x0010 Halt InMicrocode 36ca ; -------------------------------------------------------------------------------------- 36ca MACRO_Halt_InMicrocode: 36ca 36ca dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36ca ioc_random 14 clear cpu running seq_en_micro 0 seq_random 01 Halt+? 36cb 36cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36cc ; -------------------------------------------------------------------------------------- 36cc ; 0x0011 QQUnknown InMicrocode 36cc ; -------------------------------------------------------------------------------------- 36cc MACRO_36cc_QQUnknown_InMicrocode: 36cc 36cc dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36cc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36cd 36cd <halt> ; Flow R 36ce ; -------------------------------------------------------------------------------------- 36ce ; 0x0012 QQUnknown InMicrocode 36ce ; -------------------------------------------------------------------------------------- 36ce MACRO_36ce_QQUnknown_InMicrocode: 36ce 36ce dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36ce fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36cf 36cf <halt> ; Flow R 36d0 ; -------------------------------------------------------------------------------------- 36d0 ; 0x0013 QQUnknown InMicrocode 36d0 ; -------------------------------------------------------------------------------------- 36d0 MACRO_36d0_QQUnknown_InMicrocode: 36d0 36d0 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d1 36d1 <halt> ; Flow R 36d2 ; -------------------------------------------------------------------------------------- 36d2 ; 0x0014 QQUnknown InMicrocode 36d2 ; -------------------------------------------------------------------------------------- 36d2 MACRO_36d2_QQUnknown_InMicrocode: 36d2 36d2 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d3 36d3 <halt> ; Flow R 36d4 ; -------------------------------------------------------------------------------------- 36d4 ; 0x0015 QQUnknown InMicrocode 36d4 ; -------------------------------------------------------------------------------------- 36d4 MACRO_36d4_QQUnknown_InMicrocode: 36d4 36d4 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d5 36d5 <halt> ; Flow R 36d6 ; -------------------------------------------------------------------------------------- 36d6 ; 0x0016 QQUnknown InMicrocode 36d6 ; -------------------------------------------------------------------------------------- 36d6 MACRO_36d6_QQUnknown_InMicrocode: 36d6 36d6 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d7 36d7 <halt> ; Flow R 36d8 ; -------------------------------------------------------------------------------------- 36d8 ; 0x0017 QQUnknown InMicrocode 36d8 ; -------------------------------------------------------------------------------------- 36d8 MACRO_36d8_QQUnknown_InMicrocode: 36d8 36d8 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36d8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36d9 36d9 <halt> ; Flow R 36da ; -------------------------------------------------------------------------------------- 36da ; 0x0018 QQUnknown InMicrocode 36da ; -------------------------------------------------------------------------------------- 36da MACRO_36da_QQUnknown_InMicrocode: 36da 36da dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36da fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36db 36db <halt> ; Flow R 36dc ; -------------------------------------------------------------------------------------- 36dc ; 0x0019 QQUnknown InMicrocode 36dc ; -------------------------------------------------------------------------------------- 36dc MACRO_36dc_QQUnknown_InMicrocode: 36dc 36dc dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36dc fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36dd 36dd <halt> ; Flow R 36de ; -------------------------------------------------------------------------------------- 36de ; 0x001a QQUnknown InMicrocode 36de ; -------------------------------------------------------------------------------------- 36de MACRO_36de_QQUnknown_InMicrocode: 36de 36de dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36de fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36df 36df <halt> ; Flow R 36e0 ; -------------------------------------------------------------------------------------- 36e0 ; 0x001b QQUnknown InMicrocode 36e0 ; -------------------------------------------------------------------------------------- 36e0 MACRO_36e0_QQUnknown_InMicrocode: 36e0 36e0 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e1 36e1 <halt> ; Flow R 36e2 ; -------------------------------------------------------------------------------------- 36e2 ; 0x001c QQUnknown InMicrocode 36e2 ; -------------------------------------------------------------------------------------- 36e2 MACRO_36e2_QQUnknown_InMicrocode: 36e2 36e2 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e3 36e3 <halt> ; Flow R 36e4 ; -------------------------------------------------------------------------------------- 36e4 ; 0x001d QQUnknown InMicrocode 36e4 ; -------------------------------------------------------------------------------------- 36e4 MACRO_36e4_QQUnknown_InMicrocode: 36e4 36e4 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e5 36e5 <halt> ; Flow R 36e6 ; -------------------------------------------------------------------------------------- 36e6 ; 0x001e QQUnknown InMicrocode 36e6 ; -------------------------------------------------------------------------------------- 36e6 MACRO_36e6_QQUnknown_InMicrocode: 36e6 36e6 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e7 36e7 <halt> ; Flow R 36e8 ; -------------------------------------------------------------------------------------- 36e8 ; 0x001f QQUnknown InMicrocode 36e8 ; -------------------------------------------------------------------------------------- 36e8 MACRO_36e8_QQUnknown_InMicrocode: 36e8 36e8 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36e8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36e9 36e9 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36eb fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 27 VR05:07 val_frame 5 36ea 36ea fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36eb fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36eb 0x36eb typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 36eb 36eb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 2f VR02:0f val_frame 2 36ec 36ec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 36ed 36ed fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x36ef fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36ef 0x36ef seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_c_adr 3f GP00 val_frame 7 val_rand 9 PASS_A_HIGH 36ee 36ee fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x36ef ; Flow J cc=#0x0 0x36f3 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 36f3 0x36f3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36ef 36ef fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x36f2 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36f2 0x36f2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f0 36f0 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x42f seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 36f1 36f1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36f2 36f2 seq_br_type 3 Unconditional Branch; Flow J 0x32a4 seq_branch_adr 32a4 0x32a4 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 36f3 36f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3cb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 03cb 0x03cb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f4 36f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36fb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36fb 0x36fb seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f5 36f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36ff fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36ff 0x36ff seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f6 36f6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36fb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36fb 0x36fb seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f7 36f7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36fd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 36fd 0x36fd seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 36f8 36f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36f9 36f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36fa 36fa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 36fb 36fb ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 36fc 36fc seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 36fd 36fd ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 36fe 36fe seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 36ff 36ff ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 3700 3700 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 2c TR02:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 3701 3701 ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 3702 3702 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3703 3703 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 3704 3704 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 val_b_adr 16 CSA/VAL_BUS 3705 3705 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x370f fiu_offs_lit 65 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 370f 0x370f seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 3706 3706 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3707 3707 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3709 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3709 0x3709 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3c TR09:1c typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 3708 3708 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x3b71 fiu_offs_lit 65 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 3709 3709 ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 09 GP09 val_rand a PASS_B_HIGH 370a 370a fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3706 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3706 0x3706 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 370b 370b seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 370c 370c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x370f seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 370f 0x370f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 370d 370d fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 370e 370e ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 370f 370f typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3710 3710 seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 typ_a_adr 35 TR13:15 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 3711 3711 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 3712 3712 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x372f seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 372f 0x372f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3713 3713 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3714 3714 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3716 fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3716 0x3716 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3715 3715 seq_b_timing 0 Early Condition; Flow J cc=True 0x3716 ; Flow J cc=#0x0 0x3721 seq_br_type b Case False seq_branch_adr 3721 0x3721 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b 3716 3716 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3717 3717 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x470 seq_br_type 0 Branch False seq_branch_adr 0470 0x0470 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 32 VR03:12 val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 3 3718 3718 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR09:0f val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 9 val_rand a PASS_B_HIGH 3719 3719 ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 2b VR09:0b val_frame 9 371a 371a fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 2 val_rand a PASS_B_HIGH 371b 371b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 371c 371c fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 371d 371d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x211 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0211 0x0211 371e 371e fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 25 TR02:05 typ_b_adr 20 TR02:00 typ_frame 2 371f 371f fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 23 VR02:03 val_frame 2 3720 3720 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3721 ; Flow J cc=#0x0 0x0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 1a TR02:05 typ_c_source 0 FIU_BUS typ_frame 2 3721 3721 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3722 3722 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3729 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3729 0x3729 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3723 3723 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372b 0x372b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3724 3724 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3725 3725 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3726 3726 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3727 3727 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3728 3728 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3729 3729 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 372a 372a seq_br_type 3 Unconditional Branch; Flow J 0x412 seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 372b 372b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 372c 372c ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 372d 372d seq_b_timing 1 Latch Condition; Flow J cc=True 0x412 seq_br_type 1 Branch True seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 372e 372e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372f 372f seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x3717 seq_branch_adr 3717 0x3717 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 3730 3730 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3731 3731 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 3732 3732 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x3751 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3751 0x3751 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3733 3733 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x379b fiu_load_var 1 hold_var fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 379b 0x379b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 28 VR09:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3734 3734 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=#0x0 0x3761 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3761 0x3761 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3735 3735 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_b_adr 02 GP02 3736 3736 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x376d ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 376d 0x376d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3737 3737 ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 3738 3738 fiu_load_tar 1 hold_tar; Flow J cc=False 0x373b fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 373b 0x373b seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 3739 3739 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 373a 373a fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 373b 373b ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 1 373c 373c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 373d 373d ioc_fiubs 0 fiu ; Flow J cc=False 0x3738 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3738 0x3738 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3b GP04 val_c_source 0 FIU_BUS 373e 373e fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 373f 373f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x3769 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3769 0x3769 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 3740 3740 fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3741 3741 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3742 3742 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_source 0 FIU_BUS val_frame 2 3743 3743 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3757 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3757 0x3757 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3744 3744 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3745 3745 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3754 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3754 0x3754 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 3746 3746 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3747 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 375a 0x375a typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3747 3747 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34aa ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 34aa 0x34aa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 3748 3748 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 val_rand a PASS_B_HIGH 3749 3749 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 374a 374a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x379e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 379e 0x379e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 374b 374b seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 374c 374c ioc_adrbs 3 seq ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 374d 374d fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 374e 374e fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 374f 0x374f seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 374f 374f seq_br_type 7 Unconditional Call; Flow C 0x33ba seq_branch_adr 33ba 0x33ba 3750 3750 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3751 3751 fiu_tivi_src c mar_0xc; Flow J cc=False 0x3753 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3753 0x3753 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3752 3752 seq_br_type 3 Unconditional Branch; Flow J 0x378c seq_branch_adr 378c 0x378c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3753 3753 fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3754 3754 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3755 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 375a 0x375a typ_a_adr 06 GP06 3755 3755 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3756 3756 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3747 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3747 0x3747 typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3757 3757 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3758 3758 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3759 3759 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3745 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3745 0x3745 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 375a 375a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 375b 375b fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x379e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 379e 0x379e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 375c 375c ioc_load_wdr 0 ; Flow C 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 375d 375d fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 375e 375e seq_random 03 ? 375f 375f ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 3760 3760 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3761 ; -------------------------------------------------------------------------------------- 3761 ; Comes from: 3761 ; 3734 C #0x0 from color 0x0000 3761 ; -------------------------------------------------------------------------------------- 3761 3761 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3762 3762 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3763 3763 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3764 3764 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3765 3765 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3766 3766 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3767 3767 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x377f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 377f 0x377f seq_random 06 Pop_stack+? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 32 VR03:12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 3 3768 3768 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3769 ; -------------------------------------------------------------------------------------- 3769 ; Comes from: 3769 ; 373f C #0x0 from color 0x3738 3769 ; -------------------------------------------------------------------------------------- 3769 3769 seq_br_type a Unconditional Return; Flow R seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 05 ? typ_b_adr 06 GP06 376a 376a ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 376b 376b ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 376c 376c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 376d 376d ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 376e 376e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 376f 376f ioc_fiubs 0 fiu ; Flow J 0x373e seq_br_type 3 Unconditional Branch seq_branch_adr 373e 0x373e val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3770 3770 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3b TR05:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 3771 3771 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_frame d 3772 3772 ioc_tvbs 2 fiu+val; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3773 3773 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3774 3774 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3775 3775 ioc_load_wdr 0 ; Flow J 0x3776 seq_br_type 2 Push (branch address) seq_branch_adr 3298 0x3298 typ_b_adr 02 GP02 3776 3776 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3777 3777 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 06 Pop_stack+? typ_b_adr 2e TR02:0e typ_frame 2 3778 3778 ioc_adrbs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 3779 3779 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3740 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3740 0x3740 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 02 GP02 377a 377a seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 377b 377b ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 377c 377c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 377d 377d ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 377e 377e fiu_vmux_sel 1 fill value; Flow J 0x373f ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 373f 0x373f typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 377f 377f ioc_tvbs 5 seq+seq; Flow J cc=True 0x377a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 377a 0x377a seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3780 3780 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A 3781 3781 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR09:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 3782 3782 fiu_mem_start 3 start-wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 3783 3783 fiu_mem_start 2 start-rd; Flow C cc=False 0x211 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 3784 3784 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3785 3785 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x378a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 378a 0x378a seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 32 VR07:12 val_frame 7 3786 3786 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3787 3787 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3788 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 378c 0x378c typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3788 3788 seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 3789 3789 ioc_adrbs 1 val ; Flow J 0x3b71 seq_br_type 3 Unconditional Branch seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 378a 378a ioc_adrbs 1 val ; Flow C 0x3467 seq_br_type 7 Unconditional Call seq_branch_adr 3467 0x3467 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 378b 378b ioc_adrbs 1 val ; Flow C 0x3b71 seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 378c 378c fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 06 GP06 typ_b_adr 06 GP06 378d 378d ioc_adrbs 1 val typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 378e 378e ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 378f 378f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 3790 3790 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3791 3791 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3792 3792 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3793 3793 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3794 3794 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 3795 3795 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3796 3796 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 3797 3797 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 3798 3798 fiu_len_fill_lit 6b zero-fill 0x2b; Flow C 0x32fc fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_random 15 ? typ_a_adr 06 GP06 typ_mar_cntl 9 LOAD_MAR_CODE 3799 3799 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 379a 379a fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 379b 379b ioc_adrbs 1 val ; Flow C 0x3b71 seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 379c 379c fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR09:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 379d 379d ioc_load_wdr 0 ; Flow J 0x378c seq_br_type 3 Unconditional Branch seq_branch_adr 378c 0x378c 379e 379e fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 379f 379f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37a7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37a7 0x37a7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 37a0 37a0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37a1 37a1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37a2 37a2 fiu_load_tar 1 hold_tar; Flow J cc=False 0x37a5 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 37a5 0x37a5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37a3 37a3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val 37a4 37a4 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x375c fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 375c 0x375c typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 37a5 37a5 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37a6 37a6 ioc_load_wdr 0 ; Flow J 0x375d ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 375d 0x375d typ_b_adr 06 GP06 37a7 37a7 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37a8 37a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37a9 37a9 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37aa 37aa fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37ab 37ab ioc_load_wdr 0 ; Flow J 0x375d ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 375d 0x375d typ_b_adr 06 GP06 37ac ; -------------------------------------------------------------------------------------- 37ac ; Comes from: 37ac ; 37d8 C from color MACRO_Execute_Family,Count 37ac ; -------------------------------------------------------------------------------------- 37ac 37ac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37ad 37ad fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x3274 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3274 0x3274 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37ae 37ae fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 37af 37af ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x3274 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3274 0x3274 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 37b0 ; -------------------------------------------------------------------------------------- 37b0 ; 0x0137 Execute Entry,Rendezvous 37b0 ; -------------------------------------------------------------------------------------- 37b0 MACRO_Execute_Entry,Rendezvous: 37b0 37b0 dispatch_brk_class 5 ; Flow J cc=True 0x38d8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 37b0 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38d8 0x38d8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A 37b1 37b1 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37b2 37b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37b3 37b3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37b4 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37b0 MACRO_Execute_Entry,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand a PASS_B_HIGH val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37b4 37b4 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x37bc fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 37bc 0x37bc typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37b5 37b5 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x38d8 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38d8 0x38d8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 37b6 37b6 fiu_mem_start 3 start-wr; Flow J 0x37b7 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37b7 0x37b7 seq_random 02 ? typ_alu_func 1b A_OR_B typ_b_adr 2d TR02:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37b7 37b7 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x37b8 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 37b8 37b8 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x337d fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_frame 2 37b9 37b9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37ba 37ba seq_br_type 7 Unconditional Call; Flow C 0x38e0 seq_branch_adr 38e0 0x38e0 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 37bb 37bb seq_br_type 3 Unconditional Branch; Flow J 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 37bc 37bc fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x38d8 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38d8 0x38d8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 37bd 37bd ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37bf seq_br_type 1 Branch True seq_branch_adr 37bf 0x37bf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37be 37be seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37bf 37bf fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 37c0 37c0 ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A 37c1 37c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37c2 37c2 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x37c4 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 37c4 0x37c4 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 37c3 37c3 ioc_load_wdr 0 ; Flow J 0x3892 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37c4 37c4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37c5 37c5 fiu_tivi_src 2 tar_fiu; Flow J 0x3892 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 typ_a_adr 14 ZEROS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37c6 ; -------------------------------------------------------------------------------------- 37c6 ; 0x0133 Execute Family,Rendezvous 37c6 ; -------------------------------------------------------------------------------------- 37c6 MACRO_Execute_Family,Rendezvous: 37c6 37c6 dispatch_brk_class 5 ; Flow J cc=True 0x38da dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 37c6 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38da 0x38da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP 37c7 37c7 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37c8 37c8 seq_br_type 7 Unconditional Call; Flow C 0x37ac seq_branch_adr 37ac 0x37ac typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37c9 37c9 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37ca fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37c6 MACRO_Execute_Family,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37ca 37ca fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x37cd fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 37cd 0x37cd seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 37cb 37cb fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x38da fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38da 0x38da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 37cc 37cc fiu_mem_start 3 start-wr; Flow J 0x37b7 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37b7 0x37b7 typ_alu_func 1b A_OR_B typ_b_adr 29 TR09:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37cd 37cd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x38da fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38da 0x38da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 37ce 37ce ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37bf seq_br_type 1 Branch True seq_branch_adr 37bf 0x37bf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37cf 37cf seq_br_type 3 Unconditional Branch; Flow J 0x37be seq_branch_adr 37be 0x37be seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 37d0 ; -------------------------------------------------------------------------------------- 37d0 ; 0x0136 Execute Entry,Count 37d0 ; -------------------------------------------------------------------------------------- 37d0 MACRO_Execute_Entry,Count: 37d0 37d0 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 37d0 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 37d1 37d1 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 37d2 37d2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 37d3 37d3 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH 37d4 37d4 fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 37d5 37d5 <halt> ; Flow R 37d6 ; -------------------------------------------------------------------------------------- 37d6 ; 0x0132 Execute Family,Count 37d6 ; -------------------------------------------------------------------------------------- 37d6 MACRO_Execute_Family,Count: 37d6 37d6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 37d6 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 37d7 37d7 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 37d8 37d8 seq_br_type 7 Unconditional Call; Flow C 0x37ac seq_branch_adr 37ac 0x37ac typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37d9 37d9 fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 1c ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 37da ; -------------------------------------------------------------------------------------- 37da ; 0x013f Execute Select,Rendezvous 37da ; -------------------------------------------------------------------------------------- 37da MACRO_Execute_Select,Rendezvous: 37da 37da dispatch_brk_class 5 ; Flow J cc=True 0x38dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 37da fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38dc 0x38dc seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 37db 37db fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 37dc 37dc fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37dd 37dd ioc_fiubs 1 val ; Flow J cc=True 0x37ed ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 37ed 0x37ed seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_b_adr 16 CSA/VAL_BUS 37de 37de fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 37df 37df fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x37e0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 37e0 0x37e0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 20 VR02:00 val_frame 2 37e0 37e0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x37e4 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 37e4 0x37e4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 6 typ_rand 1 INC_LOOP_COUNTER 37e1 37e1 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 37e2 37e2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 37e3 37e3 ioc_fiubs 0 fiu seq_en_micro 0 37e4 37e4 seq_b_timing 0 Early Condition; Flow J cc=True 0x37e5 ; Flow J cc=#0x0 0x37e5 seq_br_type b Case False seq_branch_adr 37e5 0x37e5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 37e5 37e5 fiu_load_var 1 hold_var; Flow J 0x37e9 fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 37e9 0x37e9 val_b_adr 22 VR07:02 val_frame 7 37e6 37e6 seq_br_type 3 Unconditional Branch; Flow J 0x3823 seq_branch_adr 3823 0x3823 seq_en_micro 0 37e7 37e7 fiu_load_var 1 hold_var; Flow J 0x37e9 fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 37e9 0x37e9 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 31 VR06:11 val_frame 6 37e8 37e8 seq_br_type 3 Unconditional Branch; Flow J 0x3823 seq_branch_adr 3823 0x3823 seq_en_micro 0 37e9 37e9 fiu_mem_start 2 start-rd; Flow J cc=True 0x37eb ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37eb 0x37eb seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37ea 37ea seq_br_type 3 Unconditional Branch; Flow J 0x37e0 seq_branch_adr 37e0 0x37e0 37eb 37eb seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 37ec 37ec seq_br_type 7 Unconditional Call; Flow C 0x3823 seq_branch_adr 3823 0x3823 seq_en_micro 0 37ed 37ed ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x37fb seq_br_type 0 Branch False seq_branch_adr 37fb 0x37fb seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 37ee 37ee seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 37ef 37ef fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 37f0 37f0 fiu_mem_start 2 start-rd; Flow J 0x37f1 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 37f1 0x37f1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 37f1 37f1 seq_br_type 3 Unconditional Branch; Flow J 0x37f2 seq_branch_adr 37f2 0x37f2 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 37f2 37f2 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x37f6 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 37f6 0x37f6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37f3 37f3 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 37f4 37f4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 37f5 37f5 ioc_fiubs 0 fiu seq_en_micro 0 37f6 37f6 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x37fd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 37fd 0x37fd seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 37f7 37f7 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x3823 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3823 0x3823 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 20 TR02:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37f8 37f8 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x37f2 seq_br_type 1 Branch True seq_branch_adr 37f2 0x37f2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 37f9 37f9 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 37fa 37fa seq_br_type 3 Unconditional Branch; Flow J 0x37f2 seq_branch_adr 37f2 0x37f2 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 37fb 37fb ioc_adrbs 2 typ ; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 37fc 37fc fiu_mem_start 2 start-rd; Flow J 0x37f1 seq_br_type 3 Unconditional Branch seq_branch_adr 37f1 0x37f1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 37fd ; -------------------------------------------------------------------------------------- 37fd ; Comes from: 37fd ; 37f6 C #0x0 from color 0x37dc 37fd ; -------------------------------------------------------------------------------------- 37fd 37fd fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 37fe 37fe fiu_load_tar 1 hold_tar; Flow J 0x3802 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3802 0x3802 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 37ff 37ff fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x3801 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 3801 0x3801 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3800 3800 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3810 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 3810 0x3810 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3801 3801 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3802 3802 ioc_load_wdr 0 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP val_b_adr 10 TOP 3803 3803 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 3804 3804 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3805 0x3805 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3805 3805 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 3806 3806 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3807 3807 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 3808 3808 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3809 3809 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 0 fiu typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 380a 380a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 380b 380b seq_b_timing 1 Latch Condition; Flow J cc=True 0x380e seq_br_type 1 Branch True seq_branch_adr 380e 0x380e typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 380c 380c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 380d 380d ioc_load_wdr 0 ; Flow J 0x3892 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 380e 380e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 380f 380f ioc_load_wdr 0 ; Flow J 0x3892 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3810 3810 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 3811 3811 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x381f ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 381f 0x381f seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 3812 3812 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 3813 3813 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3814 0x3814 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3814 3814 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 3815 3815 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3816 3816 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 3817 3817 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3818 3818 ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 3819 3819 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 381a 381a seq_b_timing 1 Latch Condition; Flow J cc=True 0x381d seq_br_type 1 Branch True seq_branch_adr 381d 0x381d typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 381b 381b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 381c 381c ioc_load_wdr 0 ; Flow J 0x3892 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 381d 381d fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 381e 381e ioc_load_wdr 0 ; Flow J 0x3892 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3892 0x3892 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 381f 381f fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3820 3820 ioc_tvbs 2 fiu+val; Flow C 0x38e0 seq_br_type 7 Unconditional Call seq_branch_adr 38e0 0x38e0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3821 3821 seq_br_type 5 Call True; Flow C cc=True 0x3274 seq_branch_adr 3274 0x3274 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 09 GP09 typ_c_lit 0 typ_frame 1e 3822 3822 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3823 ; -------------------------------------------------------------------------------------- 3823 ; Comes from: 3823 ; 37ec C from color 0x37dc 3823 ; 37f7 C True from color 0x37dc 3823 ; -------------------------------------------------------------------------------------- 3823 3823 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 2e TR07:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 3824 3824 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 1 3825 3825 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x3826 ; Flow J cc=#0x0 0x382d fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 382d 0x382d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3826 3826 fiu_load_var 1 hold_var; Flow J cc=True 0x3827 ; Flow J cc=#0x0 0x3843 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3843 0x3843 seq_en_micro 0 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 3827 3827 fiu_mem_start 3 start-wr; Flow J 0x3828 ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3828 3828 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x337d fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3829 3829 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x38e0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 38e0 0x38e0 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 382a 382a seq_b_timing 1 Latch Condition; Flow J cc=True 0x3371 seq_br_type 1 Branch True seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 382b 382b seq_br_type 5 Call True; Flow C cc=True 0x3279 seq_branch_adr 3279 0x3279 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 382c 382c seq_br_type 7 Unconditional Call; Flow C 0x32b0 seq_branch_adr 32b0 0x32b0 382d 382d seq_br_type 3 Unconditional Branch; Flow J 0x3830 seq_branch_adr 3830 0x3830 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 382e 382e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3832 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3832 0x3832 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 382f 382f seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3830 3830 fiu_load_var 1 hold_var; Flow J cc=True 0x3827 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3827 0x3827 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 3831 3831 seq_br_type 7 Unconditional Call; Flow C 0x3827 seq_branch_adr 3827 0x3827 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3832 3832 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA 3833 3833 fiu_load_tar 1 hold_tar; Flow J cc=True 0x383f fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 383f 0x383f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR07:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3834 3834 seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d 3835 3835 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 3836 3836 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x3837 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 383b 0x383b typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 20 VR11:00 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 3837 3837 ioc_tvbs 2 fiu+val; Flow C 0x38e0 seq_br_type 7 Unconditional Call seq_branch_adr 38e0 0x38e0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 3838 3838 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3371 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3839 3839 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 383a 383a seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 383b 383b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x383d fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 383d 0x383d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 383c 383c seq_br_type 3 Unconditional Branch; Flow J 0x3841 seq_branch_adr 3841 0x3841 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 383d 383d seq_br_type 2 Push (branch address); Flow J 0x383e seq_branch_adr 383b 0x383b 383e 383e seq_br_type 3 Unconditional Branch; Flow J 0x38de seq_branch_adr 38de 0x38de typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 383f 383f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3840 3840 seq_br_type 7 Unconditional Call; Flow C 0x38e0 seq_branch_adr 38e0 0x38e0 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3841 3841 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3842 3842 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3843 3843 seq_br_type 3 Unconditional Branch; Flow J 0x3830 seq_branch_adr 3830 0x3830 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3844 3844 fiu_load_tar 1 hold_tar; Flow J 0x3845 fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3845 0x3845 seq_int_reads 5 RESOLVE RAM typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3845 3845 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3847 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3847 0x3847 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3846 3846 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x3857 seq_br_type 1 Branch True seq_branch_adr 3857 0x3857 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 3847 3847 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3848 3848 fiu_mem_start 2 start-rd; Flow J cc=False 0x3855 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 3855 0x3855 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR02:03 val_alu_func 1 A_PLUS_B val_b_adr 37 VR02:17 val_frame 2 3849 3849 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3853 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3853 0x3853 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 384a 384a fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 384b 384b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 384c 384c fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x384d fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 3848 0x3848 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 384d 384d ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 384e 0x384e val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 384e 384e ioc_fiubs 2 typ ; Flow R cc=True ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 384f 0x384f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 384f 384f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3850 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 23 VR02:03 val_frame 2 3850 3850 ioc_fiubs 0 fiu ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_alu_func 1b A_OR_B typ_b_adr 20 TR11:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3851 3851 seq_br_type 7 Unconditional Call; Flow C 0x38e0 seq_branch_adr 38e0 0x38e0 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 3852 3852 seq_br_type 3 Unconditional Branch; Flow J 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3853 3853 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? 3854 3854 seq_br_type 3 Unconditional Branch; Flow J 0x3848 seq_branch_adr 3848 0x3848 3855 3855 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_b_adr 22 TR06:02 typ_frame 6 typ_mar_cntl 4 RESTORE_MAR 3856 3856 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3857 3857 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3858 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3859 0x3859 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3858 3858 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x39b2 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 39b2 0x39b2 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3859 3859 typ_a_adr 21 TR07:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 385a 385a seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 385b 385b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x386a seq_br_type 1 Branch True seq_branch_adr 386a 0x386a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 385c 385c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 385d 385d ioc_tvbs 1 typ+fiu; Flow J cc=False 0x388e seq_br_type 0 Branch False seq_branch_adr 388e 0x388e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 385e 385e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 385f 385f fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 3860 3860 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3861 3861 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3865 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3865 0x3865 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3862 3862 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 3863 3863 ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 3864 3864 seq_br_type 3 Unconditional Branch; Flow J 0x385b seq_branch_adr 385b 0x385b typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3865 3865 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 3866 3866 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 3867 3867 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 3868 3868 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3869 3869 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3864 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3864 0x3864 seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 386a 386a fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 386b 386b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3870 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3870 0x3870 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 386c 386c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 386d 386d fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x386e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 386a 0x386a typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 386e 386e fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x386f fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 386f 386f ioc_tvbs 1 typ+fiu; Flow J 0x3371 seq_br_type 3 Unconditional Branch seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3870 3870 fiu_mem_start 2 start-rd; Flow C 0x3345 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3871 3871 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x3877 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3877 0x3877 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3872 3872 ioc_fiubs 2 typ ; Flow J 0x3873 seq_br_type 3 Unconditional Branch seq_branch_adr 3873 0x3873 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3873 3873 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x388c fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 388c 0x388c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 3874 3874 fiu_load_oreg 1 hold_oreg; Flow C 0x335a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 335a 0x335a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 3875 3875 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x3877 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3877 0x3877 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3876 3876 ioc_fiubs 2 typ ; Flow J 0x3873 seq_br_type 3 Unconditional Branch seq_branch_adr 3873 0x3873 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3877 3877 seq_br_type 3 Unconditional Branch; Flow J 0x387b seq_branch_adr 387b 0x387b 3878 3878 seq_br_type 3 Unconditional Branch; Flow J 0x387b seq_branch_adr 387b 0x387b 3879 3879 fiu_mem_start 2 start-rd; Flow J 0x3455 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3455 0x3455 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 387a 387a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x387e fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 387e 0x387e seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 387b 387b seq_br_type 2 Push (branch address); Flow J 0x387c seq_branch_adr 3873 0x3873 387c 387c fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 387d 387d ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 387e 387e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 387f 387f ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3880 3880 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3881 3881 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 3882 3882 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x388b seq_br_type 1 Branch True seq_branch_adr 388b 0x388b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 3883 3883 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 3884 3884 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3886 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3886 0x3886 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3885 3885 fiu_fill_mode_src 0 ; Flow J 0x3888 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3888 0x3888 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3886 3886 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 3887 3887 fiu_fill_mode_src 0 ; Flow J 0x3888 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3888 0x3888 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3888 3888 ioc_fiubs 2 typ ; Flow J 0x3889 seq_br_type 2 Push (branch address) seq_branch_adr 3882 0x3882 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3889 3889 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 388a 388a ioc_fiubs 0 fiu ; Flow J 0x39dc seq_br_type 3 Unconditional Branch seq_branch_adr 39dc 0x39dc val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 388b 388b seq_br_type 3 Unconditional Branch; Flow J 0x3873 seq_branch_adr 3873 0x3873 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 388c 388c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a82 seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 388d 388d seq_br_type 3 Unconditional Branch; Flow J 0x385c seq_branch_adr 385c 0x385c typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 388e 388e fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 388f 388f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3890 3890 ioc_load_wdr 0 ; Flow J 0x3891 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3891 3891 fiu_mem_start 2 start-rd; Flow J 0x3464 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3464 0x3464 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3892 3892 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3893 3893 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 3894 3894 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3895 3895 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3897 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3897 0x3897 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_b_adr 20 VR02:00 val_frame 2 3896 3896 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3896 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3896 0x3896 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 14 BOT - 1 3897 3897 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x389f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 389f 0x389f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2f VR02:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3898 3898 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3899 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3899 0x3899 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 3899 3899 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 0 LOAD_CONTROL_TOP 389a 389a fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 389b 389b seq_b_timing 0 Early Condition; Flow J cc=True 0x38a0 seq_br_type 1 Branch True seq_branch_adr 38a0 0x38a0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 389c 389c fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3899 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3899 0x3899 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 389d 389d seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 389e 389e fiu_mem_start 2 start-rd; Flow J 0x3899 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3899 0x3899 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 389f 389f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 38a0 38a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 38a1 38a1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 38a2 38a2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 38a3 38a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 38a4 38a4 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x38a5 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 38ac 0x38ac seq_int_reads 0 TYP VAL BUS seq_random 31 ? typ_b_adr 03 GP03 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38a5 38a5 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 39 ? typ_a_adr 22 TR02:02 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 38a6 38a6 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x38a9 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 38a9 0x38a9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_frame 2 38a7 38a7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38a8 38a8 fiu_mem_start 2 start-rd; Flow J 0x2abd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2abd 0x2abd typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38a9 38a9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38aa 38aa ioc_tvbs 1 typ+fiu val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38ab 38ab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2abd fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2abd 0x2abd typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 38ac 38ac ioc_adrbs 1 val ; Flow C cc=True 0x38b3 ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 38b3 0x38b3 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 38ad 38ad seq_br_type 3 Unconditional Branch; Flow J 0x38b1 seq_branch_adr 38b1 0x38b1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 38ae 38ae typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38af 38af ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32ac seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 38b0 38b0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 38b1 38b1 seq_br_type 7 Unconditional Call; Flow C 0x38e0 seq_branch_adr 38e0 0x38e0 seq_en_micro 0 38b2 38b2 fiu_mem_start 2 start-rd; Flow J 0x38ae ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 38ae 0x38ae seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 38b3 ; -------------------------------------------------------------------------------------- 38b3 ; Comes from: 38b3 ; 38ac C True from color 0x38ac 38b3 ; -------------------------------------------------------------------------------------- 38b3 38b3 fiu_mem_start 2 start-rd; Flow C 0x32fc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 38b4 38b4 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 38b5 38b5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38b9 ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38b9 0x38b9 seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38b6 38b6 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 24 TR05:04 typ_frame 5 38b7 38b7 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 38b8 38b8 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 38b9 38b9 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38ba 38ba <default> 38bb 38bb fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x38c4 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38c4 0x38c4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38bc 38bc seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 38bd 38bd fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38c3 ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38c3 0x38c3 seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38be 38be <default> 38bf 38bf fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 36 TR13:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38c0 38c0 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 38c1 38c1 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 38c2 0x38c2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 38c2 38c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 38c3 38c3 fiu_mem_start 2 start-rd; Flow J 0x38ba ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ba 0x38ba typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38c4 38c4 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38c5 38c5 seq_b_timing 0 Early Condition; Flow J cc=True 0x38c6 ; Flow J cc=#0x0 0x38c6 seq_br_type b Case False seq_branch_adr 38c6 0x38c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 38c6 38c6 seq_br_type 3 Unconditional Branch; Flow J 0x38cb seq_branch_adr 38cb 0x38cb 38c7 38c7 seq_br_type 3 Unconditional Branch; Flow J 0x38d0 seq_branch_adr 38d0 0x38d0 38c8 38c8 seq_br_type 3 Unconditional Branch; Flow J 0x38d4 seq_branch_adr 38d4 0x38d4 38c9 38c9 seq_br_type 3 Unconditional Branch; Flow J 0x38ca seq_branch_adr 38ca 0x38ca 38ca 38ca ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38cb 38cb ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 38cc 38cc fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 37 TR13:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38cd 38cd ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 38ce 38ce fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38cf 38cf ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 38d0 38d0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 01 GP01 val_b_adr 39 VR02:19 val_frame 2 38d1 38d1 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 38d2 38d2 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38d3 38d3 fiu_mem_start 2 start-rd; Flow J 0x38ba ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ba 0x38ba typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38d4 38d4 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 11 val_rand a PASS_B_HIGH 38d5 38d5 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 38d6 38d6 fiu_mem_start 3 start-wr; Flow C 0x3b59 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b59 0x3b59 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38d7 38d7 fiu_mem_start 2 start-rd; Flow J 0x38ba ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ba 0x38ba typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38d8 38d8 seq_br_type 7 Unconditional Call; Flow C 0x38de seq_branch_adr 38de 0x38de typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38d9 38d9 seq_br_type 3 Unconditional Branch; Flow J 0x37b0 seq_branch_adr 37b0 MACRO_Execute_Entry,Rendezvous 38da 38da seq_br_type 7 Unconditional Call; Flow C 0x38de seq_branch_adr 38de 0x38de typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38db 38db seq_br_type 3 Unconditional Branch; Flow J 0x37c6 seq_branch_adr 37c6 MACRO_Execute_Family,Rendezvous 38dc 38dc seq_br_type 7 Unconditional Call; Flow C 0x38de seq_branch_adr 38de 0x38de typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38dd 38dd seq_br_type 3 Unconditional Branch; Flow J 0x37da seq_branch_adr 37da MACRO_Execute_Select,Rendezvous 38de ; -------------------------------------------------------------------------------------- 38de ; Comes from: 38de ; 38dc C from color MACRO_Execute_Select,Rendezvous 38de ; -------------------------------------------------------------------------------------- 38de 38de fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 38df 38df fiu_mem_start 3 start-wr; Flow J 0x3b4a fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 38e0 ; -------------------------------------------------------------------------------------- 38e0 ; Comes from: 38e0 ; 37ba C from color 0x0000 38e0 ; 3820 C from color 0x37ff 38e0 ; 3829 C from color 0x0000 38e0 ; 3837 C from color 0x0000 38e0 ; 3840 C from color 0x0000 38e0 ; 3851 C from color 0x0000 38e0 ; 38b1 C from color 0x38ac 38e0 ; -------------------------------------------------------------------------------------- 38e0 38e0 ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38e1 38e1 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 38e2 38e2 seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d 38e3 38e3 ioc_adrbs 1 val ; Flow C 0x33e0 seq_br_type 7 Unconditional Call seq_branch_adr 33e0 0x33e0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 09 GP09 38e4 38e4 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 38e5 38e5 ioc_tvbs 2 fiu+val; Flow C 0x3371 seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38e6 38e6 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 38e7 38e7 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 3c TR12:1c typ_b_adr 07 GP07 typ_frame 12 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 38e8 38e8 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 38e9 38e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x38ed fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 38ed 0x38ed typ_a_adr 30 TR1b:10 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 38ea 38ea fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 31 TR1b:11 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 38eb 38eb fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 33 TR1b:13 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 38ec 38ec fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x38f0 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 38f0 0x38f0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 38ed 38ed fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 32 TR1b:12 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 38ee 38ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 34 TR1b:14 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 38ef 38ef fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x38f0 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 38f0 0x38f0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 38f0 38f0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 35 TR1b:15 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 35 VR1b:15 val_frame 1b 38f1 38f1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 08 GP08 typ_b_adr 36 TR1b:16 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 36 VR1b:16 val_frame 1b 38f2 38f2 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 38 TR1b:18 typ_b_adr 37 TR1b:17 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 37 VR1b:17 val_frame 1b 38f3 38f3 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 31 VR07:11 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 38f4 38f4 ioc_load_wdr 0 ; Flow C cc=True 0x390a seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 390a 0x390a typ_b_adr 39 TR1b:19 typ_frame 1b val_b_adr 39 VR1b:19 val_frame 1b 38f5 38f5 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 38f6 38f6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 3d TR1b:1d typ_b_adr 04 GP04 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 38f7 38f7 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3d VR1b:1d val_frame 1b 38f8 38f8 ioc_load_wdr 0 ; Flow C cc=True 0x390c seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 390c 0x390c typ_b_adr 3e TR1b:1e typ_frame 1b val_b_adr 3e VR1b:1e val_frame 1b 38f9 38f9 ioc_adrbs 1 val ; Flow C 0x3ae3 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3ae3 0x3ae3 typ_alu_func 1a PASS_B typ_b_adr 33 TR05:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 0 PASS_A 38fa 38fa fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3903 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3903 0x3903 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 08 GP08 38fb 38fb fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 38fc 38fc ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 38fd 38fd ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 0 LOAD_CONTROL_TOP val_rand 2 DEC_LOOP_COUNTER 38fe 38fe fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 38ff 38ff fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 22 VR06:02 val_frame 6 3900 3900 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32a5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL 3901 3901 ioc_load_wdr 0 ; Flow C cc=True 0x3909 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3909 0x3909 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3902 3902 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x38ff ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 38ff 0x38ff seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 3903 3903 fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3904 0x3904 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 21 VR06:01 val_frame 6 3904 3904 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 3905 3905 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 38 VR09:18 val_frame 9 3906 3906 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 37 VR09:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 9 3907 3907 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 3908 3908 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3909 3909 seq_br_type 3 Unconditional Branch; Flow J 0x2a82 seq_branch_adr 2a82 0x2a82 390a ; -------------------------------------------------------------------------------------- 390a ; Comes from: 390a ; 38f4 C True from color 0x0000 390a ; -------------------------------------------------------------------------------------- 390a 390a val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 2d VR1b:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1b 390b 390b seq_br_type a Unconditional Return; Flow R val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 29 VR05:09 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 390c ; -------------------------------------------------------------------------------------- 390c ; Comes from: 390c ; 38f8 C True from color 0x0000 390c ; -------------------------------------------------------------------------------------- 390c 390c fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 33 TR05:13 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 39 VR05:19 val_frame 5 val_rand 9 PASS_A_HIGH 390d 390d fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 06 GP06 val_b_adr 06 GP06 390e 390e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 390f 390f ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3910 3910 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3911 3911 ioc_load_wdr 0 ; Flow R cc=False ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3912 0x3912 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3912 3912 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3913 3913 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3914 3914 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3915 ; -------------------------------------------------------------------------------------- 3915 ; Comes from: 3915 ; 0218 C from color MACRO_Action_Accept_Activation 3915 ; 2eb3 C from color 0x2ead 3915 ; 2eb4 C from color 0x2ead 3915 ; -------------------------------------------------------------------------------------- 3915 3915 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x3916 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 391e 0x391e typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3a VR02:1a val_frame 2 3916 3916 ioc_tvbs 2 fiu+val; Flow C 0x3371 seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 seq_random 02 ? typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3917 3917 fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3918 3918 seq_b_timing 1 Latch Condition; Flow J cc=True 0x391b seq_br_type 1 Branch True seq_branch_adr 391b 0x391b typ_a_adr 30 TR08:10 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 3919 3919 seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 391a 391a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 391b 391b fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 391c 391c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3ae4 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3ae4 0x3ae4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 391d 391d seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 391e 391e fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 08 GP08 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 391f 391f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3920 3920 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame f typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3921 3921 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x392f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 392f 0x392f seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3922 3922 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3926 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3926 0x3926 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3923 3923 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 3924 3924 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN 3925 3925 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN 3926 3926 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3927 0x3927 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1c typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3927 3927 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 3928 3928 fiu_fill_mode_src 0 ; Flow J cc=False 0x392a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 392a 0x392a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 3929 3929 fiu_fill_mode_src 0 ; Flow J 0x392d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 392d 0x392d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 392a 392a fiu_fill_mode_src 0 ; Flow C cc=False 0x3079 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3079 0x3079 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 392b 392b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 392c 392c fiu_load_var 1 hold_var; Flow J 0x392d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 392d 0x392d typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 392d 392d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 392e 392e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 392f 392f seq_br_type 7 Unconditional Call; Flow C 0x3934 seq_branch_adr 3934 0x3934 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3930 3930 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3931 3931 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3932 3932 fiu_mem_start 3 start-wr; Flow J 0x3933 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3268 0x3268 typ_a_adr 30 TR08:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3933 3933 ioc_load_wdr 0 ; Flow J 0x6bd seq_br_type 3 Unconditional Branch seq_branch_adr 06bd 0x06bd typ_b_adr 02 GP02 val_b_adr 02 GP02 3934 ; -------------------------------------------------------------------------------------- 3934 ; Comes from: 3934 ; 392f C from color 0x062d 3934 ; -------------------------------------------------------------------------------------- 3934 3934 fiu_mem_start 2 start-rd; Flow C 0x3369 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3369 0x3369 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3935 3935 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 3936 3936 ioc_load_wdr 0 ; Flow J cc=True 0x3ae7 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ae7 0x3ae7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_frame 5 3937 3937 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3938 3938 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR 3939 3939 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3b GP04 val_c_source 0 FIU_BUS 393a 393a fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 393b 393b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 393c 393c seq_br_type a Unconditional Return; Flow R 393d ; -------------------------------------------------------------------------------------- 393d ; Comes from: 393d ; 0931 C from color 0x0000 393d ; -------------------------------------------------------------------------------------- 393d 393d fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 393e 393e ioc_tvbs 2 fiu+val; Flow C 0x3371 seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 393f 393f fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3940 3940 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3943 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3943 0x3943 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3941 3941 <default> 3942 3942 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3944 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3944 0x3944 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3943 3943 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3944 3944 seq_br_type 7 Unconditional Call; Flow C 0x3ae3 seq_branch_adr 3ae3 0x3ae3 3945 3945 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 3946 3946 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a2 fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 08 GP08 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3947 3947 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 39 TR1b:19 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3948 3948 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 01 GP01 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 01 GP01 3949 3949 seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 394a 394a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 394b 394b fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3e VR03:1e val_frame 3 394c 394c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34be fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be seq_random 02 ? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 394d 394d fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3956 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3956 0x3956 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 394e 394e fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_b_adr 08 GP08 typ_frame 1b 394f 394f fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x3956 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3956 0x3956 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3950 3950 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 3951 3951 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 3952 3952 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3953 3953 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3954 3954 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER 3955 3955 ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 3956 3956 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3957 3957 fiu_mem_start 3 start-wr; Flow C cc=False 0x20d ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3958 3958 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1 val_b_adr 0f GP0f 3959 ; -------------------------------------------------------------------------------------- 3959 ; Comes from: 3959 ; 022f C True from color MACRO_Action_Signal_Activated 3959 ; 2eb9 C from color 0x0000 3959 ; 2eba C from color 0x0000 3959 ; -------------------------------------------------------------------------------------- 3959 3959 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x396e ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 396e 0x396e seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 09 GP09 395a 395a seq_br_type 0 Branch False; Flow J cc=False 0x3967 seq_branch_adr 3967 0x3967 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 395b 395b fiu_load_tar 1 hold_tar; Flow J cc=False 0x3ae7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3ae7 0x3ae7 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 395c 395c ioc_load_wdr 0 ; Flow C cc=True 0x398b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 398b 0x398b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 04 GP04 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 395d 395d fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 395e 395e fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3969 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3969 0x3969 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 395f 395f seq_br_type 2 Push (branch address); Flow J 0x3960 seq_branch_adr 3961 0x3961 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3960 3960 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True ; Flow J cc=False 0x3962 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 3962 0x3962 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3961 3961 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x62f ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 062f 0x062f seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3962 3962 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3963 ; Flow J cc=#0x0 0x396f fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 396f 0x396f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_c_adr 3f GP00 val_frame 5 3963 3963 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 3964 0x3964 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3964 3964 ioc_load_wdr 0 ; Flow C cc=False 0x32a2 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 5 3965 3965 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3966 3966 seq_br_type 3 Unconditional Branch; Flow J 0x395d seq_branch_adr 395d 0x395d 3967 3967 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3968 3968 seq_br_type 1 Branch True; Flow J cc=True 0x3959 seq_branch_adr 3959 0x3959 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3969 3969 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 396a 396a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x396d seq_br_type 1 Branch True seq_branch_adr 396d 0x396d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 04 GP04 typ_b_adr 08 GP08 396b 396b fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 396c 396c ioc_load_wdr 0 typ_b_adr 03 GP03 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 396d 396d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 396e 396e fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 396f 396f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3970 3970 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3971 3971 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3972 3972 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3975 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3975 0x3975 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3973 3973 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x397f ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 397f 0x397f seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3974 3974 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x3982 ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 3982 0x3982 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3975 3975 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x397a ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 397a 0x397a typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3976 3976 ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3977 3977 ioc_tvbs 2 fiu+val typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 3978 3978 seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 3979 3979 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 397a 397a seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 397b 397b ioc_adrbs 3 seq ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 397c 397c fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 397d 397d seq_b_timing 1 Latch Condition; Flow C cc=True 0x33ba seq_br_type 5 Call True seq_branch_adr 33ba 0x33ba 397e 397e seq_br_type 7 Unconditional Call; Flow C 0x3268 seq_branch_adr 3268 0x3268 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 397f 397f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3985 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3985 0x3985 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 3980 3980 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_b_adr 01 GP01 3981 3981 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3982 3982 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3985 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3985 0x3985 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 3983 3983 ioc_load_wdr 0 ; Flow J cc=True 0x3988 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3988 0x3988 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 9 PASS_A_HIGH 3984 3984 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3985 ; -------------------------------------------------------------------------------------- 3985 ; Comes from: 3985 ; 397f C True from color 0x3972 3985 ; 3982 C True from color 0x3974 3985 ; -------------------------------------------------------------------------------------- 3985 3985 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 3986 3986 fiu_mem_start 7 start_wr_if_true; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3987 0x3987 3987 3987 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR02:11 val_frame 2 3988 3988 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3989 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3989 3989 ioc_load_wdr 0 ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 398a 398a ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 398b ; -------------------------------------------------------------------------------------- 398b ; Comes from: 398b ; 395c C True from color 0x03fa 398b ; -------------------------------------------------------------------------------------- 398b 398b seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 398c 0x398c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 398c 398c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 398d 398d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 398e 398e fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 398f 398f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x399a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 399a 0x399a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 3990 3990 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3991 0x3991 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3991 3991 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3992 3992 ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 3993 3993 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 2b TR06:0b typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3994 3994 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 3995 3995 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x399c fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 399c 0x399c typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 3996 3996 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3997 3997 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3998 3998 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3999 3999 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3995 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3995 0x3995 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 399a 399a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x399c fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 399c 0x399c typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 399b 399b seq_br_type 3 Unconditional Branch; Flow J 0x398c seq_branch_adr 398c 0x398c 399c ; -------------------------------------------------------------------------------------- 399c ; Comes from: 399c ; 3995 C from color 0x398b 399c ; 399a C from color 0x398b 399c ; -------------------------------------------------------------------------------------- 399c 399c ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 399d 399d fiu_mem_start 3 start-wr; Flow J 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 399e 399e fiu_mem_start 2 start-rd; Flow J cc=False 0x39a2 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39a2 0x39a2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 399f 399f <default> 39a0 39a0 fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c1 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c1 0x39c1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39a1 39a1 seq_br_type 3 Unconditional Branch; Flow J 0x39bd seq_branch_adr 39bd 0x39bd seq_en_micro 0 39a2 39a2 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39a3 39a3 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 39a4 39a4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3371 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39a5 39a5 fiu_mem_start 2 start-rd; Flow J cc=False 0x39ac ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39ac 0x39ac seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 39a6 39a6 seq_br_type 2 Push (branch address); Flow J 0x39a7 seq_branch_adr 39ae 0x39ae 39a7 39a7 fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c1 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c1 0x39c1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39a8 39a8 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39a9 39a9 seq_br_type 1 Branch True; Flow J cc=True 0x39bf seq_branch_adr 39bf 0x39bf seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39aa 39aa fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_frame 2 39ab 39ab ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39ac 39ac fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 39ad 39ad ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39ae 39ae fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x68d fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 39af 39af fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39b0 39b0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x68d seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 39b1 39b1 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39b2 39b2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR11:01 val_frame 11 39b3 39b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3371 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39b4 39b4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39b5 39b5 seq_br_type 2 Push (branch address); Flow J 0x39b6 seq_branch_adr 39b8 0x39b8 39b6 39b6 fiu_load_tar 1 hold_tar; Flow J cc=True 0x39c1 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39c1 0x39c1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39b7 39b7 seq_br_type 3 Unconditional Branch; Flow J 0x39bd seq_branch_adr 39bd 0x39bd seq_en_micro 0 39b8 39b8 seq_br_type 1 Branch True; Flow J cc=True 0x39ba seq_branch_adr 39ba 0x39ba seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_frame 2 39b9 39b9 ioc_adrbs 2 typ ; Flow C 0x3b71 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39ba 39ba fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39bb 39bb fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 39bc 39bc ioc_load_wdr 0 ; Flow C 0x68d seq_br_type 7 Unconditional Call seq_branch_adr 068d 0x068d typ_b_adr 05 GP05 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 39bd 39bd fiu_tivi_src c mar_0xc; Flow C 0x349b ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 39be 39be seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39bf 39bf fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39c0 39c0 fiu_load_tar 1 hold_tar; Flow J 0x39c1 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39c1 0x39c1 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39c1 39c1 ioc_load_wdr 0 ; Flow J cc=True 0x39c3 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39c3 0x39c3 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 5 39c2 39c2 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3ae6 seq_br_type 9 Return False seq_branch_adr 3ae6 0x3ae6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? val_a_adr 3e VR05:1e val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_frame 5 39c3 39c3 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 2e TR02:0e typ_b_adr 08 GP08 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39c4 39c4 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 39c5 39c5 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 39c6 39c6 fiu_load_var 1 hold_var; Flow J cc=True 0x39d7 fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39d7 0x39d7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 39c7 39c7 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 39c8 0x39c8 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_frame 5 39c8 39c8 fiu_mem_start 2 start-rd; Flow C 0x34ac ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34ac 0x34ac typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39c9 39c9 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39ca 39ca fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 39cb 39cb fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 31 GP0e val_c_source 0 FIU_BUS 39cc 39cc fiu_load_var 1 hold_var; Flow J cc=False 0x39ce fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 39ce 0x39ce seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 39cd 39cd seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x39d7 seq_br_type 8 Return True seq_branch_adr 39d7 0x39d7 seq_en_micro 0 39ce 39ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x39d2 seq_br_type 1 Branch True seq_branch_adr 39d2 0x39d2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 39cf 39cf ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 39d0 0x39d0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 39d0 39d0 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39d1 39d1 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 39d2 39d2 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 39d3 0x39d3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 39d3 39d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x39d6 seq_br_type 1 Branch True seq_branch_adr 39d6 0x39d6 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 39d4 39d4 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39d5 39d5 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 39d6 39d6 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39d7 39d7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 09 GP09 val_b_adr 0e GP0e 39d8 39d8 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 39d9 39d9 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39da 39da fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39db 39db fiu_load_tar 1 hold_tar; Flow J 0x39c1 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39c1 0x39c1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 39dc 39dc seq_br_type 7 Unconditional Call; Flow C 0x337d seq_branch_adr 337d 0x337d 39dd 39dd fiu_mem_start 2 start-rd; Flow J 0x39de ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 39dd 0x39dd seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39de 39de fiu_mem_start 4 continue seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 39df 39df fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3a19 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a19 0x3a19 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 39e0 39e0 fiu_load_var 1 hold_var; Flow J cc=True 0x3a0f fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3a0f 0x3a0f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39e1 39e1 seq_br_type 0 Branch False; Flow J cc=False 0x39ea seq_branch_adr 39ea 0x39ea seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39e2 39e2 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x39ef fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 39ef 0x39ef seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 34 TR08:14 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39e3 39e3 seq_br_type 1 Branch True; Flow J cc=True 0x3a1b seq_branch_adr 3a1b 0x3a1b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39e4 39e4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a1b seq_br_type 1 Branch True seq_branch_adr 3a1b 0x3a1b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 39e5 39e5 seq_br_type 1 Branch True; Flow J cc=True 0x3a03 seq_branch_adr 3a03 0x3a03 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 2 39e6 39e6 seq_br_type 1 Branch True; Flow J cc=True 0x39f3 seq_branch_adr 39f3 0x39f3 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 39e7 39e7 fiu_mem_start 2 start-rd; Flow J cc=True 0x39ee ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 39ee 0x39ee seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 39e8 39e8 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x39e9 fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3a1b 0x3a1b typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 39e9 39e9 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 39ea 39ea fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 39eb 39eb ioc_fiubs 1 val ; Flow C 0x34f9 seq_br_type 7 Unconditional Call seq_branch_adr 34f9 0x34f9 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2a VR05:0a val_frame 5 39ec 39ec ioc_tvbs 8 typ+mem; Flow J cc=True 0x39e2 seq_br_type 1 Branch True seq_branch_adr 39e2 0x39e2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 2d VR05:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 39ed 39ed fiu_mem_start 2 start-rd; Flow J 0x34ac ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34ac 0x34ac typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39ee 39ee seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 05 ? 39ef 39ef fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 38 TR07:18 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39f0 39f0 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR13:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 39f1 39f1 fiu_mem_start 3 start-wr; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR07:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 39f2 39f2 ioc_load_wdr 0 ; Flow J 0x3a0b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a0b 0x3a0b typ_b_adr 03 GP03 39f3 39f3 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 39f4 39f4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x39e7 seq_br_type 1 Branch True seq_branch_adr 39e7 0x39e7 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 39f5 39f5 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39f6 39f6 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 39f7 39f7 fiu_mem_start 3 start-wr; Flow J 0x39f8 seq_br_type 2 Push (branch address) seq_branch_adr 39fe 0x39fe seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 39f8 39f8 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 39f9 39f9 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 39fa 39fa fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 39fb 39fb ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 39fc 39fc seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 39fd 39fd seq_br_type 3 Unconditional Branch; Flow J 0x3a1b seq_branch_adr 3a1b 0x3a1b 39fe 39fe fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 39ff 39ff fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a00 3a00 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a01 3a01 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3a02 3a02 ioc_load_wdr 0 ; Flow J 0x3a3a ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a3a 0x3a3a val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3a03 3a03 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32fc fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 2d TR08:0d typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a04 3a04 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 32 TR13:12 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3b VR13:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 3a05 3a05 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a0d seq_br_type 1 Branch True seq_branch_adr 3a0d 0x3a0d seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_a_adr 21 TR07:01 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR09:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 3a06 3a06 fiu_mem_start 3 start-wr; Flow J 0x3a07 seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a07 3a07 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a08 3a08 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 3a09 3a09 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a0a 3a0a ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 3a0b 3a0b seq_b_timing 1 Latch Condition; Flow C cc=False 0x6b4 seq_br_type 4 Call False seq_branch_adr 06b4 0x06b4 seq_en_micro 0 3a0c 3a0c seq_br_type 3 Unconditional Branch; Flow J 0x3a0f seq_branch_adr 3a0f 0x3a0f 3a0d 3a0d fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a0e 3a0e ioc_load_wdr 0 ; Flow J 0x3a0b seq_br_type 3 Unconditional Branch seq_branch_adr 3a0b 0x3a0b seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a0f 3a0f fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a10 3a10 seq_br_type 7 Unconditional Call; Flow C 0x34f9 seq_branch_adr 34f9 0x34f9 seq_en_micro 0 3a11 3a11 ioc_tvbs 8 typ+mem; Flow J cc=True 0x3a15 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a15 0x3a15 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a12 3a12 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a13 3a13 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a14 3a14 fiu_mem_start 3 start-wr; Flow J 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a15 3a15 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a16 3a16 seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 3a17 3a17 ioc_adrbs 3 seq ; Flow C 0x6bd seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3a18 3a18 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3a19 3a19 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a1a 3a1a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3a1b 0x3a1b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a1b 3a1b seq_en_micro 0 seq_random 06 Pop_stack+? 3a1c 3a1c seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2a82 seq_br_type 9 Return False seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT 3a1d ; -------------------------------------------------------------------------------------- 3a1d ; Comes from: 3a1d ; 0288 C from color 0x0000 3a1d ; 03fb C from color 0x0000 3a1d ; -------------------------------------------------------------------------------------- 3a1d 3a1d fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a1e 3a1e fiu_load_tar 1 hold_tar; Flow C cc=False 0x3a35 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3a35 0x3a35 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a1f 3a1f ioc_load_wdr 0 ; Flow J cc=True 0x3ae7 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ae7 0x3ae7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 5 3a20 3a20 fiu_mem_start 2 start-rd; Flow C 0x34aa ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 3a21 3a21 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a22 3a22 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a23 3a23 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a24 3a24 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a26 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a26 0x3a26 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 3a25 3a25 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a31 seq_br_type 8 Return True seq_branch_adr 3a31 0x3a31 seq_en_micro 0 3a26 3a26 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a27 0x3a27 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a27 3a27 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a28 3a28 ioc_load_wdr 0 ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a29 3a29 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a2a 3a2a ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a2b 3a2b fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a2c 3a2c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a2d 3a2d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a2e 3a2e fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3a2f 3a2f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3a30 0x3a30 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 3a30 3a30 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a29 seq_br_type 8 Return True seq_branch_adr 3a29 0x3a29 3a31 3a31 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a32 3a32 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a33 3a33 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a34 3a34 seq_br_type 3 Unconditional Branch; Flow J 0x3a20 seq_branch_adr 3a20 0x3a20 3a35 ; -------------------------------------------------------------------------------------- 3a35 ; Comes from: 3a35 ; 3a1e C False from color 0x03fa 3a35 ; -------------------------------------------------------------------------------------- 3a35 3a35 ioc_adrbs 2 typ ; Flow C 0x349b seq_br_type 7 Unconditional Call seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a36 3a36 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a37 3a37 fiu_mem_start 2 start-rd; Flow C 0x32fc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a38 3a38 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a39 3a39 ioc_fiubs 1 val ; Flow J 0x3a3b seq_br_type 3 Unconditional Branch seq_branch_adr 3a3b 0x3a3b typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3a 3a3a ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3b 3a3b ioc_adrbs 1 val ; Flow J 0x3a3c seq_br_type 2 Push (branch address) seq_branch_adr 3a39 0x3a39 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a3c 3a3c ioc_fiubs 1 val ; Flow J 0x3a41 seq_br_type 3 Unconditional Branch seq_branch_adr 3a41 0x3a41 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 29 VR05:09 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3a3d 3a3d ioc_fiubs 1 val ; Flow J 0x3a3f seq_br_type 3 Unconditional Branch seq_branch_adr 3a3f 0x3a3f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3e 3a3e ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a3f 3a3f ioc_adrbs 1 val ; Flow J 0x3a40 seq_br_type 2 Push (branch address) seq_branch_adr 3a3e 0x3a3e typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a40 3a40 ioc_fiubs 1 val ; Flow J 0x3a41 seq_br_type 3 Unconditional Branch seq_branch_adr 3a41 0x3a41 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 23 VR07:03 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3a41 3a41 fiu_mem_start 5 start_rd_if_true; Flow C cc=True 0x34be ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 34be 0x34be seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS 3a42 3a42 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3aa9 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3aa9 0x3aa9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a43 3a43 fiu_mem_start 4 continue; Flow C cc=False 0x3a6a ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3a6a 0x3a6a seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 3a44 3a44 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a45 3a45 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3aa9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aa9 0x3aa9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2a VR05:0a val_frame 5 3a46 3a46 ioc_fiubs 0 fiu ; Flow J cc=True 0x3aab seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aab 0x3aab seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_c_adr 3e GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a47 3a47 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3ac0 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3ac0 0x3ac0 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 01 GP01 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 3a48 3a48 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x3aa8 fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aa8 0x3aa8 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 3a49 3a49 fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad5 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad5 0x3ad5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_rand 9 PASS_A_HIGH 3a4a 3a4a fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad5 0x3ad5 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3a4b 3a4b fiu_mem_start 2 start-rd; Flow J cc=False 0x3a58 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a58 0x3a58 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR05:04 val_frame 5 3a4c 3a4c fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x32fc fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc seq_en_micro 0 typ_a_adr 03 GP03 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a4d 3a4d fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3a4e 3a4e fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3a95 fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3a95 0x3a95 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a4f 3a4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3aa7 seq_br_type 5 Call True seq_branch_adr 3aa7 0x3aa7 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 3a50 3a50 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a53 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a53 0x3a53 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a51 3a51 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 3a52 3a52 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a53 3a53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3a94 seq_br_type 5 Call True seq_branch_adr 3a94 0x3a94 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3a54 3a54 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x3371 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3371 0x3371 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a55 3a55 fiu_load_var 1 hold_var; Flow J cc=False 0x3a6d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3a6d 0x3a6d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 3a56 3a56 fiu_mem_start 2 start-rd; Flow C 0x3392 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a57 3a57 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x3a6d fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3a6d 0x3a6d typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a58 3a58 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3a4c seq_br_type 0 Branch False seq_branch_adr 3a4c 0x3a4c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR05:07 val_frame 5 3a59 3a59 fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a5a 3a5a ioc_fiubs 1 val ; Flow C 0x3ad5 seq_br_type 7 Unconditional Call seq_branch_adr 3ad5 0x3ad5 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 3a5b 3a5b fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3aba fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aba 0x3aba seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a5c 3a5c ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a5d 3a5d fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x3a64 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a64 0x3a64 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a5e 3a5e ioc_fiubs 2 typ ; Flow J cc=True 0x3a4c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a4c 0x3a4c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 05 GP05 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a5f 3a5f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3ad5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad5 0x3ad5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a60 3a60 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a4c seq_br_type 0 Branch False seq_branch_adr 3a4c 0x3a4c seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3a61 3a61 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3a4c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a4c 0x3a4c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 3a62 3a62 fiu_mem_start 2 start-rd; Flow C cc=True 0x3ad5 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3ad5 0x3ad5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 3a63 3a63 seq_br_type 3 Unconditional Branch; Flow J 0x3a4c seq_branch_adr 3a4c 0x3a4c seq_en_micro 0 3a64 3a64 ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a65 3a65 seq_br_type 1 Branch True; Flow J cc=True 0x3a4c seq_branch_adr 3a4c 0x3a4c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 3a66 3a66 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_en_micro 0 3a67 3a67 ioc_fiubs 1 val ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a68 0x3a68 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a68 3a68 ioc_adrbs 1 val ; Flow J 0x3a69 seq_br_type 2 Push (branch address) seq_branch_adr 3a42 0x3a42 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a69 3a69 fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34be ioc_tvbs 5 seq+seq seq_br_type 9 Return False seq_branch_adr 34be 0x34be seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS 3a6a ; -------------------------------------------------------------------------------------- 3a6a ; Comes from: 3a6a ; 3a43 C False from color 0x0000 3a6a ; -------------------------------------------------------------------------------------- 3a6a 3a6a seq_br_type 7 Unconditional Call; Flow C 0x3371 seq_branch_adr 3371 0x3371 seq_en_micro 0 3a6b 3a6b fiu_mem_start 5 start_rd_if_true ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a6c 3a6c fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 3a6d 3a6d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 3a6e 3a6e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a6f 3a6f fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 3a70 3a70 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 3a71 3a71 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3a73 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3a73 0x3a73 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a72 3a72 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a73 3a73 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x3a74 ; Flow J cc=#0x0 0x3a74 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3a74 0x3a74 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS 3a74 3a74 ioc_adrbs 1 val ; Flow J 0x3ac7 seq_br_type 3 Unconditional Branch seq_branch_adr 3ac7 0x3ac7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a75 3a75 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a76 3a76 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a77 3a77 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a78 3a78 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a79 3a79 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a7a 3a7a seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a7b 3a7b fiu_mem_start 2 start-rd; Flow J 0x3acb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3acb 0x3acb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3a7c 3a7c seq_br_type 3 Unconditional Branch; Flow J 0x3ace seq_branch_adr 3ace 0x3ace 3a7d 3a7d seq_br_type 3 Unconditional Branch; Flow J 0x3acd seq_branch_adr 3acd 0x3acd 3a7e 3a7e seq_br_type 3 Unconditional Branch; Flow J 0x3ace seq_branch_adr 3ace 0x3ace 3a7f 3a7f ioc_adrbs 1 val ; Flow J 0x3ac9 seq_br_type 3 Unconditional Branch seq_branch_adr 3ac9 0x3ac9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a80 3a80 ioc_tvbs 2 fiu+val; Flow J 0x3ad2 seq_br_type 3 Unconditional Branch seq_branch_adr 3ad2 0x3ad2 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a81 3a81 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a82 3a82 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a83 3a83 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a84 3a84 ioc_adrbs 1 val ; Flow J 0x3ac9 seq_br_type 3 Unconditional Branch seq_branch_adr 3ac9 0x3ac9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a85 3a85 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a86 3a86 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a87 3a87 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a88 3a88 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a89 3a89 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8a 3a8a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8b 3a8b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a8c 3a8c seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a8d 3a8d seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a8e 3a8e ioc_adrbs 1 val ; Flow J 0x3ac9 seq_br_type 3 Unconditional Branch seq_branch_adr 3ac9 0x3ac9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3a8f 3a8f seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3a90 3a90 fiu_mem_start 2 start-rd; Flow J 0x3acb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3acb 0x3acb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3a91 3a91 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a92 3a92 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a93 3a93 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3a94 3a94 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3aa9 seq_br_type 9 Return False seq_branch_adr 3aa9 0x3aa9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR13:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 13 3a95 3a95 val_c_adr 3e GP01 3a96 3a96 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ab4 0x3ab4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3a97 3a97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3a94 seq_br_type 5 Call True seq_branch_adr 3a94 0x3a94 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3a98 3a98 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a99 3a99 ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3a9a 3a9a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a9f seq_br_type 1 Branch True seq_branch_adr 3a9f 0x3a9f seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 3a9b 3a9b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a9f seq_br_type 1 Branch True seq_branch_adr 3a9f 0x3a9f seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 3a9c 3a9c seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3a9d 3a9d ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3a9e 3a9e ioc_fiubs 2 typ ; Flow J 0x3a41 seq_br_type 3 Unconditional Branch seq_branch_adr 3a41 0x3a41 typ_a_adr 06 GP06 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3a9f 3a9f seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3aa0 3aa0 ioc_adrbs 2 typ ; Flow J cc=True 0x3a9e ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a9e 0x3a9e seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 26 VR05:06 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 5 3aa1 3aa1 seq_br_type 7 Unconditional Call; Flow C 0x34be seq_branch_adr 34be 0x34be 3aa2 3aa2 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3aa9 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3aa9 0x3aa9 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3aa3 3aa3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 3aa4 3aa4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 3aa5 3aa5 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 31 TR02:11 typ_frame 2 3aa6 3aa6 ioc_load_wdr 0 ; Flow J 0x3a9e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a9e 0x3a9e 3aa7 3aa7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x3aa9 seq_br_type 8 Return True seq_branch_adr 3aa9 0x3aa9 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 3aa8 3aa8 fiu_mem_start 3 start-wr; Flow C 0x32fc ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 32fc 0x32fc typ_b_adr 05 GP05 3aa9 3aa9 seq_br_type 1 Branch True; Flow J cc=True 0x3ae2 seq_branch_adr 3ae2 0x3ae2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 08 GP08 3aaa 3aaa seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 3aab 3aab seq_br_type 1 Branch True; Flow J cc=True 0x3ab4 seq_branch_adr 3ab4 0x3ab4 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR13:14 typ_frame 13 3aac 3aac fiu_mem_start 2 start-rd; Flow C 0x32fd ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32fd 0x32fd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3aad 3aad fiu_tivi_src 1 tar_val; Flow C 0x210 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3aae 3aae ioc_tvbs 5 seq+seq; Flow J cc=True 0x3ab4 seq_br_type 1 Branch True seq_branch_adr 3ab4 0x3ab4 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3aaf 3aaf fiu_mem_start 2 start-rd; Flow J 0x3ab0 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3a39 0x3a39 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR13:1c val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 13 val_rand a PASS_B_HIGH 3ab0 3ab0 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3ab1 3ab1 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3ab2 3ab2 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 3ab3 3ab3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a47 seq_br_type 1 Branch True seq_branch_adr 3a47 0x3a47 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 39 TR13:19 typ_frame 13 3ab4 3ab4 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 01 GP01 3ab5 3ab5 fiu_mem_start 2 start-rd; Flow J cc=True 0x3ab6 ; Flow J cc=#0x0 0x3ab6 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3ab6 0x3ab6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3ab6 3ab6 seq_br_type 3 Unconditional Branch; Flow J 0x3ac0 seq_branch_adr 3ac0 0x3ac0 3ab7 3ab7 seq_br_type 3 Unconditional Branch; Flow J 0x3ac0 seq_branch_adr 3ac0 0x3ac0 3ab8 3ab8 seq_br_type 3 Unconditional Branch; Flow J 0x3ac3 seq_branch_adr 3ac3 0x3ac3 3ab9 3ab9 seq_br_type 3 Unconditional Branch; Flow J 0x3ac5 seq_branch_adr 3ac5 0x3ac5 3aba 3aba fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3abd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3abd 0x3abd seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3abb 3abb fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3a5c ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a5c 0x3a5c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3abc 3abc seq_br_type 3 Unconditional Branch; Flow J 0x3abf seq_branch_adr 3abf 0x3abf seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3abd 3abd fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3abe 3abe ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3abf 3abf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3ac1 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ac1 0x3ac1 seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 39 VR02:19 val_frame 2 3ac0 3ac0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3ac1 3ac1 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 3ac2 3ac2 fiu_mem_start 3 start-wr; Flow J 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3ac3 3ac3 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3ac4 3ac4 fiu_mem_start 3 start-wr; Flow J 0x3b59 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b59 0x3b59 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3ac5 3ac5 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3ac6 3ac6 fiu_mem_start 3 start-wr; Flow J 0x3b4a ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b4a 0x3b4a seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3ac7 3ac7 seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3ac8 3ac8 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3ac9 3ac9 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3aca 3aca seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 3acb 3acb seq_br_type 2 Push (branch address); Flow J 0x3acc seq_branch_adr 3ad2 0x3ad2 3acc 3acc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a1d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a1d 0x3a1d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3acd 3acd ioc_adrbs 3 seq ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3ace 3ace seq_br_type 7 Unconditional Call; Flow C 0x662 seq_branch_adr 0662 0x0662 3acf 3acf seq_b_timing 1 Latch Condition; Flow J cc=True 0x3ad1 seq_br_type 1 Branch True seq_branch_adr 3ad1 0x3ad1 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3ad0 3ad0 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3ad1 3ad1 seq_br_type 3 Unconditional Branch; Flow J 0x3ad2 seq_branch_adr 3ad2 0x3ad2 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3ad2 3ad2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3ad3 3ad3 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3ad4 3ad4 ioc_load_wdr 0 ; Flow J 0x62f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 062f 0x062f typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3ad5 ; -------------------------------------------------------------------------------------- 3ad5 ; Comes from: 3ad5 ; 3a49 C True from color 0x0000 3ad5 ; 3a4a C True from color 0x0000 3ad5 ; 3a5a C from color 0x0000 3ad5 ; 3a5f C True from color 0x0000 3ad5 ; 3a62 C True from color 0x0000 3ad5 ; -------------------------------------------------------------------------------------- 3ad5 3ad5 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3ad6 0x3ad6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3ad6 3ad6 seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3ad7 3ad7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 06 Pop_stack+? 3ad8 3ad8 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3ad9 3ad9 fiu_mem_start 2 start-rd; Flow C 0x34be ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34be 0x34be typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3ada 3ada fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3adb 0x3adb seq_int_reads 6 CONTROL TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3adb 3adb ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3adc 0x3adc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3adc 3adc fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 32 TR09:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3add 3add ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3ae0 seq_br_type 1 Branch True seq_branch_adr 3ae0 0x3ae0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR07:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3ade 3ade ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3ae0 seq_br_type 1 Branch True seq_branch_adr 3ae0 0x3ae0 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3adf 3adf seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3ae0 3ae0 fiu_mem_start 3 start-wr 3ae1 3ae1 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3ae2 3ae2 seq_br_type 7 Unconditional Call; Flow C 0x69b seq_branch_adr 069b 0x069b seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3ae3 ; -------------------------------------------------------------------------------------- 3ae3 ; Comes from: 3ae3 ; 3944 C from color 0x0913 3ae3 ; -------------------------------------------------------------------------------------- 3ae3 3ae3 fiu_mem_start 2 start-rd; Flow C 0x34aa fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34aa 0x34aa typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 3ae4 3ae4 fiu_mem_start 2 start-rd; Flow C 0x3392 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3392 0x3392 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3ae5 3ae5 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x33ba seq_br_type 9 Return False seq_branch_adr 33ba 0x33ba 3ae6 3ae6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3ae7 3ae7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3ae8 ; -------------------------------------------------------------------------------------- 3ae8 ; 0x00ad Action InMicrocode,Package,Field_Execute_Dynamic 3ae8 ; -------------------------------------------------------------------------------------- 3ae8 MACRO_Action_InMicrocode,Package,Field_Execute_Dynamic: 3ae8 3ae8 dispatch_brk_class 0 ; Flow J 0x3ae9 dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3ae8 seq_br_type 2 Push (branch address) seq_branch_adr 3aee 0x3aee typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3ae9 3ae9 ioc_fiubs 1 val ; Flow J 0x3aeb seq_br_type 3 Unconditional Branch seq_branch_adr 3aeb 0x3aeb typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3aea ; -------------------------------------------------------------------------------------- 3aea ; 0x1700-0x17ff Execute Task,Entry_Call,fieldnum 3aea ; -------------------------------------------------------------------------------------- 3aea MACRO_Execute_Task,Entry_Call,fieldnum: 3aea 3aea dispatch_brk_class 5 ; Flow J 0x3aeb dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_uadr 3aea ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3aef 0x3aef typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3aeb 3aeb ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3aec 3aec fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3aed 3aed fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3aee 3aee fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3af0 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3af0 0x3af0 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3aef 3aef fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3af0 3af0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3af1 3af1 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3af2 3af2 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3af3 3af3 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3af4 3af4 fiu_mem_start 2 start-rd; Flow J 0x36ea ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36ea 0x36ea typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3af5 3af5 <halt> ; Flow R 3af6 ; -------------------------------------------------------------------------------------- 3af6 ; 0x00aa QQUnknown InMicrocode 3af6 ; -------------------------------------------------------------------------------------- 3af6 MACRO_3af6_QQUnknown_InMicrocode: 3af6 3af6 dispatch_brk_class 0 ; Flow J 0x3af7 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3af6 seq_br_type 2 Push (branch address) seq_branch_adr 3afc 0x3afc typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3af7 3af7 ioc_fiubs 1 val ; Flow J 0x3af9 seq_br_type 3 Unconditional Branch seq_branch_adr 3af9 0x3af9 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3af8 ; -------------------------------------------------------------------------------------- 3af8 ; 0x1400-0x14ff Execute Task,Family_Call,fieldnum 3af8 ; -------------------------------------------------------------------------------------- 3af8 MACRO_Execute_Task,Family_Call,fieldnum: 3af8 3af8 dispatch_brk_class 5 ; Flow J 0x3af9 dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3af8 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3afd 0x3afd typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3af9 3af9 ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3afa 3afa fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3afb 3afb fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3afc 3afc fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3afe fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3afe 0x3afe typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3afd 3afd fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3afe 3afe fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3aff 3aff fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b00 3b00 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b01 3b01 ioc_tvbs 3 fiu+fiu typ_a_adr 22 TR01:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b02 3b02 fiu_mem_start 2 start-rd; Flow J 0x36ea ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36ea 0x36ea typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b03 3b03 <halt> ; Flow R 3b04 ; -------------------------------------------------------------------------------------- 3b04 ; 0x00ab QQUnknown InMicrocode 3b04 ; -------------------------------------------------------------------------------------- 3b04 MACRO_3b04_QQUnknown_InMicrocode: 3b04 3b04 dispatch_brk_class 0 ; Flow J 0x3b05 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b04 seq_br_type 2 Push (branch address) seq_branch_adr 3b0a 0x3b0a typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b05 3b05 ioc_fiubs 1 val ; Flow J 0x3b07 seq_br_type 3 Unconditional Branch seq_branch_adr 3b07 0x3b07 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b06 ; -------------------------------------------------------------------------------------- 3b06 ; 0x1500-0x15ff Execute Task,Timed_Call,fieldnum 3b06 ; -------------------------------------------------------------------------------------- 3b06 MACRO_Execute_Task,Timed_Call,fieldnum: 3b06 3b06 dispatch_brk_class 5 ; Flow J 0x3b07 dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3b06 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b0b 0x3b0b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b07 3b07 ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b08 3b08 fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b09 3b09 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b0a 3b0a fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b0c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b0c 0x3b0c typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b0b 3b0b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b0c 3b0c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b0d 3b0d fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b0e 3b0e ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b0f 3b0f ioc_tvbs 3 fiu+fiu typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b10 3b10 fiu_mem_start 2 start-rd; Flow J 0x36e9 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36e9 0x36e9 typ_a_adr 04 GP04 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b11 3b11 <halt> ; Flow R 3b12 ; -------------------------------------------------------------------------------------- 3b12 ; 0x00a8 QQUnknown InMicrocode 3b12 ; -------------------------------------------------------------------------------------- 3b12 MACRO_3b12_QQUnknown_InMicrocode: 3b12 3b12 dispatch_brk_class 0 ; Flow J 0x3b13 dispatch_csa_valid 5 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b12 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b19 0x3b19 typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 3b13 3b13 ioc_fiubs 1 val ; Flow J 0x3b15 seq_br_type 3 Unconditional Branch seq_branch_adr 3b15 0x3b15 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b14 ; -------------------------------------------------------------------------------------- 3b14 ; 0x1200-0x12ff Execute Task,Family_Timed,fieldnum 3b14 ; -------------------------------------------------------------------------------------- 3b14 MACRO_Execute_Task,Family_Timed,fieldnum: 3b14 3b14 dispatch_brk_class 5 ; Flow J 0x3b15 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_uadr 3b14 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b1b 0x3b1b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b15 3b15 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b16 3b16 ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_b_adr 1d TOP - 3 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3b17 3b17 fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b18 3b18 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3b19 3b19 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b1a 3b1a fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3b1d fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3b1d 0x3b1d typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b1b 3b1b fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b1c 3b1c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b1d 3b1d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3b1e 3b1e fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b1f 3b1f ioc_tvbs 3 fiu+fiu typ_a_adr 29 TR07:09 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b20 3b20 fiu_mem_start 2 start-rd; Flow J 0x36e9 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36e9 0x36e9 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b21 3b21 <halt> ; Flow R 3b22 ; -------------------------------------------------------------------------------------- 3b22 ; 0x00ac QQUnknown InMicrocode 3b22 ; -------------------------------------------------------------------------------------- 3b22 MACRO_3b22_QQUnknown_InMicrocode: 3b22 3b22 dispatch_brk_class 0 ; Flow J 0x3b23 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3b22 seq_br_type 2 Push (branch address) seq_branch_adr 3b28 0x3b28 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b23 3b23 ioc_fiubs 1 val ; Flow J 0x3b25 seq_br_type 3 Unconditional Branch seq_branch_adr 3b25 0x3b25 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b24 ; -------------------------------------------------------------------------------------- 3b24 ; 0x1600-0x16ff Execute Task,Conditional_Call,fieldnum 3b24 ; -------------------------------------------------------------------------------------- 3b24 MACRO_Execute_Task,Conditional_Call,fieldnum: 3b24 3b24 dispatch_brk_class 5 ; Flow J 0x3b25 dispatch_csa_valid 2 dispatch_uadr 3b24 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b29 0x3b29 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b25 3b25 ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3b26 3b26 fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b27 3b27 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b28 3b28 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b2a fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b2a 0x3b2a typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b29 3b29 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b2a 3b2a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b2b 3b2b fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b2c 3b2c ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b2d 3b2d ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR01:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b2e 3b2e fiu_mem_start 2 start-rd; Flow J 0x36e9 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 36e9 0x36e9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b2f 3b2f <halt> ; Flow R 3b30 ; -------------------------------------------------------------------------------------- 3b30 ; 0x00a9 QQUnknown InMicrocode 3b30 ; -------------------------------------------------------------------------------------- 3b30 MACRO_3b30_QQUnknown_InMicrocode: 3b30 3b30 dispatch_brk_class 0 ; Flow J 0x3b31 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3b30 seq_br_type 2 Push (branch address) seq_branch_adr 3b36 0x3b36 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b31 3b31 ioc_fiubs 1 val ; Flow J 0x3b33 seq_br_type 3 Unconditional Branch seq_branch_adr 3b33 0x3b33 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b32 ; -------------------------------------------------------------------------------------- 3b32 ; 0x1300-0x13ff Execute Task,Family_Cond,fieldnum 3b32 ; -------------------------------------------------------------------------------------- 3b32 MACRO_Execute_Task,Family_Cond,fieldnum: 3b32 3b32 dispatch_brk_class 5 ; Flow J 0x3b33 dispatch_csa_valid 3 dispatch_uadr 3b32 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b37 0x3b37 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b33 3b33 ioc_fiubs 1 val ; Flow C 0x337d seq_br_type 7 Unconditional Call seq_branch_adr 337d 0x337d typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b34 3b34 fiu_mem_start 2 start-rd; Flow C 0x3b3d ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b35 3b35 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32aa fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32aa 0x32aa seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b36 3b36 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b38 0x3b38 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b37 3b37 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b38 3b38 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b39 3b39 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b3a 3b3a ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b3b 3b3b ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR07:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b3c 3b3c fiu_mem_start 2 start-rd; Flow J 0x36e9 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36e9 0x36e9 typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b3d ; -------------------------------------------------------------------------------------- 3b3d ; Comes from: 3b3d ; 3b17 C from color MACRO_3b12_QQUnknown_InMicrocode 3b3d ; -------------------------------------------------------------------------------------- 3b3d 3b3d ioc_tvbs 5 seq+seq; Flow J cc=False 0x3b42 seq_br_type 0 Branch False seq_branch_adr 3b42 0x3b42 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3b3e 3b3e fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b44 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3b44 0x3b44 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b3f 3b3f seq_br_type 7 Unconditional Call; Flow C 0x349b seq_branch_adr 349b 0x349b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b40 3b40 seq_br_type 1 Branch True; Flow J cc=True 0x3b48 seq_branch_adr 3b48 0x3b48 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b41 3b41 seq_br_type 3 Unconditional Branch; Flow J 0x32a3 seq_branch_adr 32a3 0x32a3 3b42 3b42 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b43 3b43 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x3b45 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b45 0x3b45 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 13 ONES val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3b44 3b44 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b45 0x3b45 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR01:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 3b45 3b45 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a3 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3b46 3b46 ioc_load_wdr 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 3b47 3b47 fiu_mem_start 3 start-wr; Flow C 0x3b4a ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3b4a 0x3b4a typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3b48 3b48 fiu_mem_start 2 start-rd; Flow J 0x3b3d ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3b3d 0x3b3d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b49 ; -------------------------------------------------------------------------------------- 3b49 ; Comes from: 3b49 ; 3b8f C from color 0x3b8b 3b49 ; -------------------------------------------------------------------------------------- 3b49 3b49 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3b4a ; -------------------------------------------------------------------------------------- 3b4a ; Comes from: 3b4a ; 0625 C from color 0x05fb 3b4a ; 38d2 C from color 0x38b3 3b4a ; 3965 C from color 0x03fa 3b4a ; 3a2b C from color 0x3a28 3b4a ; 3a33 C from color 0x03fa 3b4a ; -------------------------------------------------------------------------------------- 3b4a 3b4a fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b4b 3b4b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b4c 3b4c fiu_tivi_src c mar_0xc; Flow J 0x3b4d ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068f 0x068f seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b4d 3b4d ioc_fiubs 2 typ ; Flow J 0x7b6 seq_br_type 3 Unconditional Branch seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b4e ; -------------------------------------------------------------------------------------- 3b4e ; Comes from: 3b4e ; 05ab C from color 0x05a7 3b4e ; 06d3 C from color 0x06d2 3b4e ; -------------------------------------------------------------------------------------- 3b4e 3b4e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b4f 3b4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b50 3b50 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b51 3b51 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b52 3b52 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert seq_en_micro 0 3b53 3b53 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b54 3b54 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b55 3b55 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 30 TR03:10 typ_frame 3 3b56 3b56 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3b57 3b57 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b58 3b58 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 3b59 ; -------------------------------------------------------------------------------------- 3b59 ; Comes from: 3b59 ; 38d6 C from color 0x38b3 3b59 ; -------------------------------------------------------------------------------------- 3b59 3b59 fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_frame 2 3b5a ; -------------------------------------------------------------------------------------- 3b5a ; Comes from: 3b5a ; 3b6c C from color 0x0ba9 3b5a ; -------------------------------------------------------------------------------------- 3b5a 3b5a fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3b5b 3b5b ioc_tvbs 1 typ+fiu; Flow C 0x34f2 seq_br_type 7 Unconditional Call seq_branch_adr 34f2 0x34f2 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 4 3b5c 3b5c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3b5f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3b5f 0x3b5f seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A 3b5d 3b5d fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b61 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 3b61 0x3b61 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 3d VR02:1d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3b5e 3b5e ioc_tvbs 5 seq+seq; Flow J cc=True 0x3b5f ; Flow J cc=#0x0 0x3b60 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b60 0x3b60 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b5f 3b5f seq_br_type 3 Unconditional Branch; Flow J 0x3b61 seq_branch_adr 3b61 0x3b61 seq_en_micro 0 3b60 3b60 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 3b61 3b61 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b62 3b62 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b63 3b63 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f typ_frame 3 3b64 3b64 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3b65 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 33 VR04:13 val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b65 3b65 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x3b66 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3b66 3b66 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3b67 ; Flow J cc=#0x0 0x3b68 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b68 0x3b68 seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3b67 3b67 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0xba9 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0ba9 0x0ba9 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 3 LEFT_I_A typ_frame d val_b_adr 0c GP0c 3b68 3b68 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b68 seq_br_type 1 Branch True seq_branch_adr 3b68 0x3b68 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 3b69 3b69 seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 3b6a 3b6a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x368f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 368f 0x368f seq_en_micro 0 seq_int_reads 6 CONTROL TOP val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b6b 3b6b seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3b6c 3b6c fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x3b5a fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b5a 0x3b5a seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3b6d 3b6d fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 3b6e 3b6e fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x3b70 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3b70 0x3b70 seq_en_micro 0 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3b6f 3b6f fiu_mem_start 3 start-wr; Flow J cc=False 0x3b6c fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3b6c 0x3b6c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 3b70 3b70 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3b71 ; -------------------------------------------------------------------------------------- 3b71 ; Comes from: 3b71 ; 0410 C from color 0x0410 3b71 ; 0627 C from color 0x0627 3b71 ; 0687 C from color 0x0687 3b71 ; 07eb C from color 0x07e8 3b71 ; 38ca C from color 0x38b3 3b71 ; 38e0 C from color 0x38e0 3b71 ; -------------------------------------------------------------------------------------- 3b71 3b71 fiu_tivi_src c mar_0xc; Flow R cc=False fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 9 Return False seq_branch_adr 3b72 0x3b72 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3b72 3b72 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 3b73 3b73 fiu_mem_start 5 start_rd_if_true; Flow C 0x3b7c fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3b7c 0x3b7c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 30 TR03:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3b74 3b74 seq_br_type 3 Unconditional Branch; Flow J 0x3b73 seq_branch_adr 3b73 0x3b73 seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b75 3b75 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd29 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d29 0x0d29 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 3b76 3b76 fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0x3b77 fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3b70 0x3b70 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3b77 3b77 fiu_mem_start 5 start_rd_if_true; Flow C 0x3b7c fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3b7c 0x3b7c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 31 TR03:11 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_alu_func 13 ONES val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3b78 3b78 seq_br_type 3 Unconditional Branch; Flow J 0x3b77 seq_branch_adr 3b77 0x3b77 seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b79 3b79 ioc_load_wdr 0 ; Flow C cc=True 0x2a82 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a82 0x2a82 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 3b7a 3b7a fiu_mem_start 5 start_rd_if_true; Flow J 0x3b7c ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b7c 0x3b7c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3b7b 3b7b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 3b7c ; -------------------------------------------------------------------------------------- 3b7c ; Comes from: 3b7c ; 3b73 C from color 0x0000 3b7c ; 3b77 C from color 0x3b75 3b7c ; -------------------------------------------------------------------------------------- 3b7c 3b7c seq_b_timing 1 Latch Condition; Flow J cc=False 0x3b84 seq_br_type 0 Branch False seq_branch_adr 3b84 0x3b84 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_latch 1 val_a_adr 33 VR04:13 val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 3b7d 3b7d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3b7e 3b7e fiu_mem_start 4 continue; Flow J cc=True 0x3b79 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3b79 0x3b79 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3b7f 3b7f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b7b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3b7b 0x3b7b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU 3b80 3b80 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b81 3b81 fiu_load_oreg 1 hold_oreg ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 32 GP0d val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3b82 3b82 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 3b83 3b83 fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x3b79 ioc_adrbs 2 typ seq_br_type 9 Return False seq_branch_adr 3b79 0x3b79 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 0d GP0d typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0c GP0c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b84 3b84 fiu_load_tar 1 hold_tar; Flow J 0x3b49 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 3 Unconditional Branch seq_branch_adr 3b49 0x3b49 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3b85 3b85 fiu_mem_start 11 start_tag_query; Flow C 0x3b89 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b89 0x3b89 seq_en_micro 0 typ_a_adr 31 TR03:11 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 33 VR04:13 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b86 3b86 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b87 3b87 fiu_mem_start 11 start_tag_query; Flow C 0x3b89 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b89 0x3b89 seq_en_micro 0 typ_a_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b88 3b88 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b89 ; -------------------------------------------------------------------------------------- 3b89 ; Comes from: 3b89 ; 3b85 C from color 0x369e 3b89 ; 3b87 C from color 0x36a1 3b89 ; -------------------------------------------------------------------------------------- 3b89 3b89 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3b8a 3b8a fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b8b 3b8b ioc_fiubs 1 val ; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3b8c 0x3b8c seq_en_micro 0 val_a_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b8c 3b8c fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3b8d 3b8d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3b90 seq_br_type 0 Branch False seq_branch_adr 3b90 0x3b90 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b8e 3b8e seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 seq_en_micro 0 3b8f 3b8f fiu_mem_start 11 start_tag_query; Flow C 0x3b49 seq_br_type 7 Unconditional Call seq_branch_adr 3b49 0x3b49 seq_en_micro 0 3b90 3b90 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 4 val_rand a PASS_B_HIGH 3b91 3b91 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b8c seq_br_type 1 Branch True seq_branch_adr 3b8c 0x3b8c seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3b92 3b92 fiu_mem_start e start_physical_wr ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d val_alu_func 0 PASS_A 3b93 3b93 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3b94 3b94 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x3b96 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 3b96 0x3b96 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 6a ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 2a VR05:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 3b95 3b95 seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 3b96 3b96 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x32c3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32c3 0x32c3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR05:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR09:00 val_frame 9 3b97 3b97 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x3b98 ; Flow J cc=#0x0 0x3ba5 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 3ba5 0x3ba5 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 31 TR02:11 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 3b98 3b98 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x3b9e fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3b9e 0x3b9e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 3b99 3b99 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3b9a 3b9a typ_a_adr 01 GP01 typ_alu_func 10 NOT_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 3b9b 3b9b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x3b9d ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3b9d 0x3b9d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3b9c 3b9c seq_br_type 3 Unconditional Branch; Flow J 0x3b9b seq_branch_adr 3b9b 0x3b9b seq_en_micro 0 typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 2b BOT - 1 3b9d 3b9d fiu_mem_start 2 start-rd; Flow J 0x3ba2 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba2 0x3ba2 seq_en_micro 0 seq_random 15 ? typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 2b BOT - 1 3b9e 3b9e fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3b9f 3b9f fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 3ba0 3ba0 ioc_load_wdr 0 ; Flow J cc=False 0x3b9f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3b9f 0x3b9f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 14 BOT - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 3ba1 3ba1 fiu_mem_start 2 start-rd; Flow J 0x3ba2 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba2 0x3ba2 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3ba2 3ba2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3ba3 ; Flow J cc=#0x0 0x3ba5 seq_br_type b Case False seq_branch_adr 3ba5 0x3ba5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3ba3 3ba3 seq_br_type 7 Unconditional Call; Flow C 0x2a82 seq_branch_adr 2a82 0x2a82 3ba4 3ba4 fiu_mem_start 2 start-rd; Flow J 0x3ba2 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3ba2 0x3ba2 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3ba5 3ba5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdca seq_br_type 3 Unconditional Branch seq_branch_adr 0dca 0x0dca seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3ba6 3ba6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdd5 seq_br_type 3 Unconditional Branch seq_branch_adr 0dd5 0x0dd5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3ba7 3ba7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdd8 seq_br_type 3 Unconditional Branch seq_branch_adr 0dd8 0x0dd8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3ba8 3ba8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd3a seq_br_type 3 Unconditional Branch seq_branch_adr 0d3a 0x0d3a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3ba9 3ba9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe4a seq_br_type 3 Unconditional Branch seq_branch_adr 0e4a 0x0e4a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3baa 3baa ioc_tvbs c mem+mem+csa+dummy; Flow J 0xde6 seq_br_type 3 Unconditional Branch seq_branch_adr 0de6 0x0de6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bab 3bab ioc_tvbs c mem+mem+csa+dummy; Flow J 0xedb seq_br_type 3 Unconditional Branch seq_branch_adr 0edb 0x0edb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bac 3bac ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd5e seq_br_type 3 Unconditional Branch seq_branch_adr 0d5e 0x0d5e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bad 3bad ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdea seq_br_type 3 Unconditional Branch seq_branch_adr 0dea 0x0dea seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bae 3bae ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdf5 seq_br_type 3 Unconditional Branch seq_branch_adr 0df5 0x0df5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3baf 3baf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdf8 seq_br_type 3 Unconditional Branch seq_branch_adr 0df8 0x0df8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb0 3bb0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdfa seq_br_type 3 Unconditional Branch seq_branch_adr 0dfa 0x0dfa seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb1 3bb1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe11 seq_br_type 3 Unconditional Branch seq_branch_adr 0e11 0x0e11 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb2 3bb2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe1f seq_br_type 3 Unconditional Branch seq_branch_adr 0e1f 0x0e1f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb3 3bb3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe51 seq_br_type 3 Unconditional Branch seq_branch_adr 0e51 0x0e51 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb4 3bb4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe2d seq_br_type 3 Unconditional Branch seq_branch_adr 0e2d 0x0e2d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb5 3bb5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe32 seq_br_type 3 Unconditional Branch seq_branch_adr 0e32 0x0e32 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb6 3bb6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe37 seq_br_type 3 Unconditional Branch seq_branch_adr 0e37 0x0e37 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb7 3bb7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe59 seq_br_type 3 Unconditional Branch seq_branch_adr 0e59 0x0e59 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb8 3bb8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe39 seq_br_type 3 Unconditional Branch seq_branch_adr 0e39 0x0e39 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bb9 3bb9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe3d seq_br_type 3 Unconditional Branch seq_branch_adr 0e3d 0x0e3d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bba 3bba ioc_tvbs c mem+mem+csa+dummy; Flow J 0x883 seq_br_type 3 Unconditional Branch seq_branch_adr 0883 0x0883 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbb 3bbb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xec6 seq_br_type 3 Unconditional Branch seq_branch_adr 0ec6 0x0ec6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbc 3bbc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee6 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee6 0x0ee6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbd 3bbd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee9 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee9 0x0ee9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbe 3bbe ioc_tvbs c mem+mem+csa+dummy; Flow J 0xecb seq_br_type 3 Unconditional Branch seq_branch_adr 0ecb 0x0ecb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bbf 3bbf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xecc seq_br_type 3 Unconditional Branch seq_branch_adr 0ecc 0x0ecc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc0 3bc0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xecf seq_br_type 3 Unconditional Branch seq_branch_adr 0ecf 0x0ecf seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc1 3bc1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe9d seq_br_type 3 Unconditional Branch seq_branch_adr 0e9d 0x0e9d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc2 3bc2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x799 seq_br_type 3 Unconditional Branch seq_branch_adr 0799 0x0799 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc3 3bc3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3657 seq_br_type 3 Unconditional Branch seq_branch_adr 3657 0x3657 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc4 3bc4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed6 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed6 0x0ed6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc5 3bc5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf4 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf4 0x2cf4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc6 3bc6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d17 seq_br_type 3 Unconditional Branch seq_branch_adr 2d17 0x2d17 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc7 3bc7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cfb seq_br_type 3 Unconditional Branch seq_branch_adr 2cfb 0x2cfb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc8 3bc8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x345 seq_br_type 3 Unconditional Branch seq_branch_adr 0345 0x0345 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bc9 3bc9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xde0 seq_br_type 3 Unconditional Branch seq_branch_adr 0de0 0x0de0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bca 3bca ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee1 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee1 0x0ee1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcb 3bcb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd64 seq_br_type 3 Unconditional Branch seq_branch_adr 0d64 0x0d64 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcc 3bcc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdc2 seq_br_type 3 Unconditional Branch seq_branch_adr 0dc2 0x0dc2 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcd 3bcd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd74 seq_br_type 3 Unconditional Branch seq_branch_adr 0d74 0x0d74 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bce 3bce ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe85 seq_br_type 3 Unconditional Branch seq_branch_adr 0e85 0x0e85 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bcf 3bcf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe96 seq_br_type 3 Unconditional Branch seq_branch_adr 0e96 0x0e96 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd0 3bd0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe53 seq_br_type 3 Unconditional Branch seq_branch_adr 0e53 0x0e53 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd1 3bd1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeda seq_br_type 3 Unconditional Branch seq_branch_adr 0eda 0x0eda seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd2 3bd2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x334 seq_br_type 3 Unconditional Branch seq_branch_adr 0334 0x0334 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd3 3bd3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe3f seq_br_type 3 Unconditional Branch seq_branch_adr 0e3f 0x0e3f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd4 3bd4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdda seq_br_type 3 Unconditional Branch seq_branch_adr 0dda 0x0dda seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd5 3bd5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x87b seq_br_type 3 Unconditional Branch seq_branch_adr 087b 0x087b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd6 3bd6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x903 seq_br_type 3 Unconditional Branch seq_branch_adr 0903 0x0903 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd7 3bd7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x905 seq_br_type 3 Unconditional Branch seq_branch_adr 0905 0x0905 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd8 3bd8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb36 seq_br_type 3 Unconditional Branch seq_branch_adr 0b36 0x0b36 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bd9 3bd9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x913 seq_br_type 3 Unconditional Branch seq_branch_adr 0913 0x0913 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bda 3bda ioc_tvbs c mem+mem+csa+dummy; Flow J 0x917 seq_br_type 3 Unconditional Branch seq_branch_adr 0917 0x0917 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdb 3bdb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed8 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed8 0x0ed8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdc 3bdc ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3666 seq_br_type 3 Unconditional Branch seq_branch_adr 3666 0x3666 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdd 3bdd ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf7 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf7 0x2cf7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bde 3bde ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe50 seq_br_type 3 Unconditional Branch seq_branch_adr 0e50 0x0e50 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdf 3bdf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe70 seq_br_type 3 Unconditional Branch seq_branch_adr 0e70 0x0e70 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be0 3be0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe7f seq_br_type 3 Unconditional Branch seq_branch_adr 0e7f 0x0e7f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be1 3be1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x919 seq_br_type 3 Unconditional Branch seq_branch_adr 0919 0x0919 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be2 3be2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x977 seq_br_type 3 Unconditional Branch seq_branch_adr 0977 0x0977 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be3 3be3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf8 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf8 0x2cf8 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be4 3be4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe78 seq_br_type 3 Unconditional Branch seq_branch_adr 0e78 0x0e78 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be5 3be5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dbd seq_br_type 3 Unconditional Branch seq_branch_adr 2dbd 0x2dbd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be6 3be6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d06 seq_br_type 3 Unconditional Branch seq_branch_adr 2d06 0x2d06 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be7 3be7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d0e seq_br_type 3 Unconditional Branch seq_branch_adr 2d0e 0x2d0e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be8 3be8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d11 seq_br_type 3 Unconditional Branch seq_branch_adr 2d11 0x2d11 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be9 3be9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35d4 seq_br_type 3 Unconditional Branch seq_branch_adr 35d4 0x35d4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bea 3bea ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35d9 seq_br_type 3 Unconditional Branch seq_branch_adr 35d9 0x35d9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3beb 3beb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb6e seq_br_type 3 Unconditional Branch seq_branch_adr 0b6e 0x0b6e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bec 3bec ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35ce seq_br_type 3 Unconditional Branch seq_branch_adr 35ce 0x35ce seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bed 3bed ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d01 seq_br_type 3 Unconditional Branch seq_branch_adr 2d01 0x2d01 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bee 3bee ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d03 seq_br_type 3 Unconditional Branch seq_branch_adr 2d03 0x2d03 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bef 3bef ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3b6d seq_br_type 3 Unconditional Branch seq_branch_adr 3b6d 0x3b6d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf0 3bf0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3b75 seq_br_type 3 Unconditional Branch seq_branch_adr 3b75 0x3b75 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf1 3bf1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x95c seq_br_type 3 Unconditional Branch seq_branch_adr 095c 0x095c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf2 3bf2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb2f seq_br_type 3 Unconditional Branch seq_branch_adr 0b2f 0x0b2f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf3 3bf3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cf9 seq_br_type 3 Unconditional Branch seq_branch_adr 2cf9 0x2cf9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf4 3bf4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35aa seq_br_type 3 Unconditional Branch seq_branch_adr 35aa 0x35aa seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf5 3bf5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35b2 seq_br_type 3 Unconditional Branch seq_branch_adr 35b2 0x35b2 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf6 3bf6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35bb seq_br_type 3 Unconditional Branch seq_branch_adr 35bb 0x35bb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf7 3bf7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35af seq_br_type 3 Unconditional Branch seq_branch_adr 35af 0x35af seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf8 3bf8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cfe seq_br_type 3 Unconditional Branch seq_branch_adr 2cfe 0x2cfe seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf9 3bf9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd4e seq_br_type 3 Unconditional Branch seq_branch_adr 0d4e 0x0d4e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfa 3bfa ioc_tvbs c mem+mem+csa+dummy; Flow J 0xece seq_br_type 3 Unconditional Branch seq_branch_adr 0ece 0x0ece seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfb 3bfb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2bdf seq_br_type 3 Unconditional Branch seq_branch_adr 2bdf 0x2bdf seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfc 3bfc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe82 seq_br_type 3 Unconditional Branch seq_branch_adr 0e82 0x0e82 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfd 3bfd ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35dd seq_br_type 3 Unconditional Branch seq_branch_adr 35dd 0x35dd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfe 3bfe ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35c5 seq_br_type 3 Unconditional Branch seq_branch_adr 35c5 0x35c5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bff 3bff ioc_tvbs c mem+mem+csa+dummy; Flow J 0x767 seq_br_type 3 Unconditional Branch seq_branch_adr 0767 0x0767 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c00 3c00 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x776 seq_br_type 3 Unconditional Branch seq_branch_adr 0776 0x0776 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c01 3c01 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x774 seq_br_type 3 Unconditional Branch seq_branch_adr 0774 0x0774 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c02 3c02 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x784 seq_br_type 3 Unconditional Branch seq_branch_adr 0784 0x0784 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c03 3c03 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x775 seq_br_type 3 Unconditional Branch seq_branch_adr 0775 0x0775 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c04 3c04 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb93 seq_br_type 3 Unconditional Branch seq_branch_adr 0b93 0x0b93 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c05 3c05 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed4 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed4 0x0ed4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c06 3c06 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x34f seq_br_type 3 Unconditional Branch seq_branch_adr 034f 0x034f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c07 3c07 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36a seq_br_type 3 Unconditional Branch seq_branch_adr 036a 0x036a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c08 3c08 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36c seq_br_type 3 Unconditional Branch seq_branch_adr 036c 0x036c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c09 3c09 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x377 seq_br_type 3 Unconditional Branch seq_branch_adr 0377 0x0377 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0a 3c0a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d1f seq_br_type 3 Unconditional Branch seq_branch_adr 2d1f 0x2d1f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0b 3c0b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x349 seq_br_type 3 Unconditional Branch seq_branch_adr 0349 0x0349 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0c 3c0c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x794 seq_br_type 3 Unconditional Branch seq_branch_adr 0794 0x0794 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0d 3c0d ioc_tvbs c mem+mem+csa+dummy; Flow J 0xee3 seq_br_type 3 Unconditional Branch seq_branch_adr 0ee3 0x0ee3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0e 3c0e ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe9b seq_br_type 3 Unconditional Branch seq_branch_adr 0e9b 0x0e9b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0f 3c0f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2cdc seq_br_type 3 Unconditional Branch seq_branch_adr 2cdc 0x2cdc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c10 3c10 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xed5 seq_br_type 3 Unconditional Branch seq_branch_adr 0ed5 0x0ed5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c11 3c11 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeea seq_br_type 3 Unconditional Branch seq_branch_adr 0eea 0x0eea seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c12 3c12 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeec seq_br_type 3 Unconditional Branch seq_branch_adr 0eec 0x0eec seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c13 3c13 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd9f seq_br_type 3 Unconditional Branch seq_branch_adr 0d9f 0x0d9f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c14 3c14 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dd2 seq_br_type 3 Unconditional Branch seq_branch_adr 2dd2 0x2dd2 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c15 3c15 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdb3 seq_br_type 3 Unconditional Branch seq_branch_adr 0db3 0x0db3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c16 3c16 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c17 3c17 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c18 3c18 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c19 3c19 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1a 3c1a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1b 3c1b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1c 3c1c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1d 3c1d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1e 3c1e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1f 3c1f ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe57 seq_br_type 3 Unconditional Branch seq_branch_adr 0e57 0x0e57 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c20 3c20 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x32c3 seq_br_type 3 Unconditional Branch seq_branch_adr 32c3 0x32c3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c21 3c21 <default>
PyReveng3/R1000.Disassembly disass_ucode.py /tmp/_aa_r1k_dfs/r1k_dfs/d8/d8a4b6cdb.tmp.0.18470 /tmp/_aa_r1k_dfs/r1k_dfs/d8/d8a4b6cdb.tmp.1.18471
FN /tmp/_aa_r1k_dfs/r1k_dfs/d8/d8a4b6cdb.tmp.0.18470
CX <__main__.R1kUcode object at 0x13eaf7024690> CX.M <word_mem 0x100-0x3c22, @14 bits, 0 attr>
Case table at 0x0000 lacks width <leaf 0x735-0x736 R1KUCODE>
? None <leaf 0x0-0x1 R1KUCODE>
Case table at 0x0bb0 lacks width <leaf 0xbac-0xbad R1KUCODE>
Case table at 0x0bfd lacks width <leaf 0xbfc-0xbfd R1KUCODE>
Case table at 0x0bcb lacks width <leaf 0xbca-0xbcb R1KUCODE>
Case table at 0x081f lacks width <leaf 0x81d-0x81e R1KUCODE>
Case table at 0x0830 lacks width <leaf 0x82f-0x830 R1KUCODE>
Case table at 0x3721 lacks width <leaf 0x3715-0x3716 R1KUCODE>
Case table at 0x04af lacks width <leaf 0x4ae-0x4af R1KUCODE>
Case table at 0x22cb lacks width <leaf 0x22c8-0x22c9 R1KUCODE>
Case table at 0x2d65 lacks width <leaf 0x149-0x14a R1KUCODE>
Case table at 0x34a0 lacks width <leaf 0x349f-0x34a0 R1KUCODE>
Case table at 0x2d55 lacks width <leaf 0x2d54-0x2d55 R1KUCODE>
Case table at 0x0f0f lacks width <leaf 0xef1-0xef2 R1KUCODE>
Case table at 0x0ef5 lacks width <leaf 0xef2-0xef3 R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x69e-0x69f R1KUCODE>
Case table at 0x396f lacks width <leaf 0x3962-0x3963 R1KUCODE>
Case table at 0x3350 lacks width <leaf 0x334a-0x334b R1KUCODE>
Case table at 0x334c lacks width <leaf 0x334b-0x334c R1KUCODE>
Case table at 0x0260 lacks width <leaf 0x24f-0x250 R1KUCODE>
Case table at 0x335d lacks width <leaf 0x335c-0x335d R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c1-0x2c2 R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c5-0x2c6 R1KUCODE>
Case table at 0x3ab6 lacks width <leaf 0x3ab5-0x3ab6 R1KUCODE>
Case table at 0x0396 lacks width <leaf 0x38e-0x38f R1KUCODE>
Case table at 0x03c0 lacks width <leaf 0x3b9-0x3ba R1KUCODE>
Case table at 0x03f8 lacks width <leaf 0x3f6-0x3f7 R1KUCODE>
Case table at 0x04b8 lacks width <leaf 0x4b3-0x4b4 R1KUCODE>
Case table at 0x3507 lacks width <leaf 0x3501-0x3502 R1KUCODE>
Case table at 0x3507 lacks width <leaf 0x3503-0x3504 R1KUCODE>
Case table at 0x3507 lacks width <leaf 0x3512-0x3513 R1KUCODE>
Case table at 0x0516 lacks width <leaf 0x514-0x515 R1KUCODE>
Case table at 0x04f5 lacks width <leaf 0x4f0-0x4f1 R1KUCODE>
Case table at 0x0552 lacks width <leaf 0x551-0x552 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x635-0x636 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x63b-0x63c R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x697-0x698 R1KUCODE>
Case table at 0x0802 lacks width <leaf 0x801-0x802 R1KUCODE>
Case table at 0x3319 lacks width <leaf 0x3311-0x3312 R1KUCODE>
Case table at 0x3319 lacks width <leaf 0x3312-0x3313 R1KUCODE>
Case table at 0x3319 lacks width <leaf 0x3315-0x3316 R1KUCODE>
Case table at 0x3319 lacks width <leaf 0x3318-0x3319 R1KUCODE>
Case table at 0x3328 lacks width <leaf 0x3327-0x3328 R1KUCODE>
Case table at 0x3328 lacks width <leaf 0x3325-0x3326 R1KUCODE>
Case table at 0x3328 lacks width <leaf 0x3322-0x3323 R1KUCODE>
Case table at 0x3328 lacks width <leaf 0x3323-0x3324 R1KUCODE>
Case table at 0x0981 lacks width <leaf 0x980-0x981 R1KUCODE>
Case table at 0x0991 lacks width <leaf 0x990-0x991 R1KUCODE>
Case table at 0x09a3 lacks width <leaf 0x9a2-0x9a3 R1KUCODE>
Case table at 0x09b3 lacks width <leaf 0x9b2-0x9b3 R1KUCODE>
Case table at 0x0a27 lacks width <leaf 0xa26-0xa27 R1KUCODE>
Case table at 0x0a39 lacks width <leaf 0xa38-0xa39 R1KUCODE>
Case table at 0x0a50 lacks width <leaf 0xa4d-0xa4e R1KUCODE>
Case table at 0x0a61 lacks width <leaf 0xa4e-0xa4f R1KUCODE>
Case table at 0x0a71 lacks width <leaf 0xa70-0xa71 R1KUCODE>
Case table at 0x0a61 lacks width <leaf 0xa60-0xa61 R1KUCODE>
Case table at 0x0a85 lacks width <leaf 0xa84-0xa85 R1KUCODE>
Case table at 0x0a99 lacks width <leaf 0xa98-0xa99 R1KUCODE>
Case table at 0x1d47 lacks width <leaf 0x1d46-0x1d47 R1KUCODE>
Case table at 0x0ab9 lacks width <leaf 0xab7-0xab8 R1KUCODE>
Case table at 0x0c67 lacks width <leaf 0xc66-0xc67 R1KUCODE>
Case table at 0x0ccb lacks width <leaf 0xcca-0xccb R1KUCODE>
Case table at 0x0dd0 lacks width <leaf 0xdcf-0xdd0 R1KUCODE>
Case table at 0x0e0a lacks width <leaf 0xe08-0xe09 R1KUCODE>
Case table at 0x0e0c lacks width <leaf 0xe0a-0xe0b R1KUCODE>
Case table at 0x369e lacks width <leaf 0x3699-0x369a R1KUCODE>
Case table at 0x0e16 lacks width <leaf 0xe15-0xe16 R1KUCODE>
Case table at 0x1001 lacks width <leaf 0xfe8-0xfe9 R1KUCODE>
Case table at 0x1054 lacks width <leaf 0x1052-0x1053 R1KUCODE>
Case table at 0x0e5d lacks width <leaf 0xe5b-0xe5c R1KUCODE>
Case table at 0x0eb1 lacks width <leaf 0xeb0-0xeb1 R1KUCODE>
Case table at 0x0efc lacks width <leaf 0xefb-0xefc R1KUCODE>
Case table at 0x0fcb lacks width <leaf 0xfca-0xfcb R1KUCODE>
Case table at 0x0fc3 lacks width <leaf 0xfc1-0xfc2 R1KUCODE>
Case table at 0x362b lacks width <leaf 0x362a-0x362b R1KUCODE>
Case table at 0x102e lacks width <leaf 0x102c-0x102d R1KUCODE>
Case table at 0x1025 lacks width <leaf 0x102e-0x102f R1KUCODE>
Case table at 0x1025 lacks width <leaf 0x1024-0x1025 R1KUCODE>
Case table at 0x101c lacks width <leaf 0x101b-0x101c R1KUCODE>
Case table at 0x1025 lacks width <leaf 0x101c-0x101d R1KUCODE>
Case table at 0x10b6 lacks width <leaf 0x10a7-0x10a8 R1KUCODE>
Case table at 0x10b6 lacks width <leaf 0x10ab-0x10ac R1KUCODE>
Case table at 0x10d3 lacks width <leaf 0x10d1-0x10d2 R1KUCODE>
Case table at 0x10b6 lacks width <leaf 0x10af-0x10b0 R1KUCODE>
Case table at 0x10b6 lacks width <leaf 0x10b3-0x10b4 R1KUCODE>
Case table at 0x110d lacks width <leaf 0x10ff-0x1100 R1KUCODE>
Case table at 0x110d lacks width <leaf 0x1103-0x1104 R1KUCODE>
Case table at 0x110d lacks width <leaf 0x1107-0x1108 R1KUCODE>
Case table at 0x110d lacks width <leaf 0x110b-0x110c R1KUCODE>
Case table at 0x1169 lacks width <leaf 0x1161-0x1162 R1KUCODE>
Case table at 0x1198 lacks width <leaf 0x1171-0x1172 R1KUCODE>
Case table at 0x11f1 lacks width <leaf 0x11e3-0x11e4 R1KUCODE>
Case table at 0x11f1 lacks width <leaf 0x11e7-0x11e8 R1KUCODE>
Case table at 0x11f1 lacks width <leaf 0x11eb-0x11ec R1KUCODE>
Case table at 0x11f1 lacks width <leaf 0x11ef-0x11f0 R1KUCODE>
Case table at 0x124f lacks width <leaf 0x1241-0x1242 R1KUCODE>
Case table at 0x124f lacks width <leaf 0x1245-0x1246 R1KUCODE>
Case table at 0x124f lacks width <leaf 0x1249-0x124a R1KUCODE>
Case table at 0x124f lacks width <leaf 0x124d-0x124e R1KUCODE>
Case table at 0x1684 lacks width <leaf 0x1683-0x1684 R1KUCODE>
Case table at 0x168a lacks width <leaf 0x1689-0x168a R1KUCODE>
Case table at 0x1690 lacks width <leaf 0x168f-0x1690 R1KUCODE>
Case table at 0x191b lacks width <leaf 0x190f-0x1910 R1KUCODE>
Case table at 0x1d26 lacks width <leaf 0x1d0a-0x1d0b R1KUCODE>
Case table at 0x1ca3 lacks width <leaf 0x1ca2-0x1ca3 R1KUCODE>
Case table at 0x26bd lacks width <leaf 0x26ba-0x26bb R1KUCODE>
Case table at 0x26d7 lacks width <leaf 0x26d3-0x26d4 R1KUCODE>
Case table at 0x1ebf lacks width <leaf 0x1ebe-0x1ebf R1KUCODE>
Case table at 0x1f64 lacks width <leaf 0x1f5e-0x1f5f R1KUCODE>
Case table at 0x20a6 lacks width <leaf 0x200f-0x2010 R1KUCODE>
Case table at 0x206d lacks width <leaf 0x206b-0x206c R1KUCODE>
Case table at 0x20a6 lacks width <leaf 0x20cb-0x20cc R1KUCODE>
Case table at 0x206d lacks width <leaf 0x209c-0x209d R1KUCODE>
Case table at 0x206d lacks width <leaf 0x209f-0x20a0 R1KUCODE>
Case table at 0x20a6 lacks width <leaf 0x2114-0x2115 R1KUCODE>
Case table at 0x20a6 lacks width <leaf 0x2119-0x211a R1KUCODE>
Case table at 0x206d lacks width <leaf 0x20a4-0x20a5 R1KUCODE>
Case table at 0x20a6 lacks width <leaf 0x211e-0x211f R1KUCODE>
Case table at 0x21c7 lacks width <leaf 0x21c2-0x21c3 R1KUCODE>
Case table at 0x21f1 lacks width <leaf 0x21eb-0x21ec R1KUCODE>
Case table at 0x220e lacks width <leaf 0x220d-0x220e R1KUCODE>
Case table at 0x230e lacks width <leaf 0x230d-0x230e R1KUCODE>
Case table at 0x2553 lacks width <leaf 0x260e-0x260f R1KUCODE>
Case table at 0x2553 lacks width <leaf 0x2550-0x2551 R1KUCODE>
Case table at 0x26e2 lacks width <leaf 0x26df-0x26e0 R1KUCODE>
Case table at 0x2553 lacks width <leaf 0x25a5-0x25a6 R1KUCODE>
Case table at 0x25b1 lacks width <leaf 0x25ab-0x25ac R1KUCODE>
Case table at 0x2676 lacks width <leaf 0x2665-0x2666 R1KUCODE>
Case table at 0x2676 lacks width <leaf 0x26b2-0x26b3 R1KUCODE>
Case table at 0x26d7 lacks width <leaf 0x26f5-0x26f6 R1KUCODE>
Case table at 0x27b2 lacks width <leaf 0x27b1-0x27b2 R1KUCODE>
Case table at 0x27b2 lacks width <leaf 0x27b8-0x27b9 R1KUCODE>
Case table at 0x27dd lacks width <leaf 0x27dc-0x27dd R1KUCODE>
Case table at 0x27e1 lacks width <leaf 0x27e0-0x27e1 R1KUCODE>
Case table at 0x2b03 lacks width <leaf 0x2af8-0x2af9 R1KUCODE>
Case table at 0x2b18 lacks width <leaf 0x2b15-0x2b16 R1KUCODE>
Case table at 0x2b6e lacks width <leaf 0x2b6c-0x2b6d R1KUCODE>
Case table at 0x3ba5 lacks width <leaf 0x3b97-0x3b98 R1KUCODE>
Case table at 0x3ba5 lacks width <leaf 0x3ba2-0x3ba3 R1KUCODE>
Case table at 0x2c4d lacks width <leaf 0x2c4b-0x2c4c R1KUCODE>
Case table at 0x2c5e lacks width <leaf 0x2c5c-0x2c5d R1KUCODE>
Case table at 0x2f70 lacks width <leaf 0x2f6a-0x2f6b R1KUCODE>
Case table at 0x2e19 lacks width <leaf 0x2e14-0x2e15 R1KUCODE>
Case table at 0x2e3e lacks width <leaf 0x2e3d-0x2e3e R1KUCODE>
Case table at 0x2e59 lacks width <leaf 0x2e57-0x2e58 R1KUCODE>
Case table at 0x2ead lacks width <leaf 0x2eac-0x2ead R1KUCODE>
Case table at 0x2ee9 lacks width <leaf 0x2ee7-0x2ee8 R1KUCODE>
Case table at 0x2f70 lacks width <leaf 0x2f6e-0x2f6f R1KUCODE>
Case table at 0x3761 lacks width <leaf 0x3734-0x3735 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305a-0x305b R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305b-0x305c R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305c-0x305d R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305d-0x305e R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305e-0x305f R1KUCODE>
Case table at 0x305b lacks width <leaf 0x305f-0x3060 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3060-0x3061 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3061-0x3062 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3062-0x3063 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3063-0x3064 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3064-0x3065 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3065-0x3066 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3066-0x3067 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3067-0x3068 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3068-0x3069 R1KUCODE>
Case table at 0x305b lacks width <leaf 0x3069-0x306a R1KUCODE>
Case table at 0x305b lacks width <leaf 0x306a-0x306b R1KUCODE>
Case table at 0x3188 lacks width <leaf 0x3181-0x3182 R1KUCODE>
Case table at 0x36f3 lacks width <leaf 0x36ee-0x36ef R1KUCODE>
Case table at 0x0000 lacks width <leaf 0x3720-0x3721 R1KUCODE>
Case table at 0x3769 lacks width <leaf 0x373f-0x3740 R1KUCODE>
Case table at 0x37e5 lacks width <leaf 0x37e4-0x37e5 R1KUCODE>
Case table at 0x37fd lacks width <leaf 0x37f6-0x37f7 R1KUCODE>
Case table at 0x382d lacks width <leaf 0x3825-0x3826 R1KUCODE>
Case table at 0x3843 lacks width <leaf 0x3826-0x3827 R1KUCODE>
Case table at 0x3877 lacks width <leaf 0x3871-0x3872 R1KUCODE>
Case table at 0x3877 lacks width <leaf 0x3875-0x3876 R1KUCODE>
Case table at 0x38c6 lacks width <leaf 0x38c5-0x38c6 R1KUCODE>
Case table at 0x3a74 lacks width <leaf 0x3a73-0x3a74 R1KUCODE>
Case table at 0x3b60 lacks width <leaf 0x3b5e-0x3b5f R1KUCODE>
Case table at 0x3b68 lacks width <leaf 0x3b66-0x3b67 R1KUCODE>
? None <leaf 0x3c40-0x3c41 R1KUCODE>
fiu_len_fill_reg_ctl 1 {3}
fiu_load_mdr 1 {0}
fiu_load_oreg 1 {0}
fiu_mem_start 1 {2}
fiu_oreg_src 1 {1}
ioc_adrbs 1 {3}
seq_lex_adr 1 {0}
typ_mar_cntl 1 {14}
typ_priv_check 1 {7}
Stranger in color <Color 15 0x117-0x73c #2> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 24 0x127-0x2abc #136> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 44 0x148-0x3c0f #100> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 61 0x160-0x2a62 #13> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 175 0x200-0x3bdc #47> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 176 0x201-0x20b #2> <Stretch 202 259> <Color 177 0x202-0x20c #2>
Stranger in color <Color 177 0x202-0x20c #2> <Stretch 203 260> <Color 178 0x203-0xed3 #25>
Stranger in color <Color 178 0x203-0xed3 #25> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 179 0x204-0x20e #2> <Stretch 205 262> <Color 180 0x205-0x20f #2>
Stranger in color <Color 180 0x205-0x20f #2> <Stretch 206 263> <Color 181 0x206-0x210 #2>
Stranger in color <Color 181 0x206-0x210 #2> <Stretch 207 264> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 182 0x208-0x212 #2> <Stretch 209 266> <Color 183 0x209-0x213 #2>
Stranger in color <Color 183 0x209-0x213 #2> <Stretch 20a 267> <Color 175 0x200-0x3bdc #47>
Stranger in color <Color 184 0x214-0x3359 #50> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 193 0x2c9-0x3879 #12> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 194 0x2ca-0x2d5 #6> <Stretch 2cb 460> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 210 0x377-0x3c09 #10> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 214 0x397-0x3a1 #8> <Stretch 398 665> <Color 215 0x398-0x3c3 #16>
Stranger in color <Color 215 0x398-0x3c3 #16> <Stretch 39b 668> <Color 214 0x397-0x3a1 #8>
Stranger in color <Color 219 0x3c1-0x3ca #8> <Stretch 3c2 707> <Color 215 0x398-0x3c3 #16>
Stranger in color <Color 222 0x3f0-0x407 #17> <Stretch 3f7 760> <Color 223 0x3f7-0x3f7 #1>
Stranger in color <Color 225 0x3fa-0x3ae7 #51> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 244 0x4fa-0x50a #13> <Stretch 4fd 1022> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 261 0x573-0x598 #18> <Stretch 576 1143> <Color 262 0x576-0x577 #2>
Stranger in color <Color 270 0x5a7-0x36ca #93> <Stretch 5e0 1249> <Color 277 0x5db-0x364d #17>
Stranger in color <Color 277 0x5db-0x364d #17> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 283 0x5fb-0x626 #15> <Stretch 606 1287> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 287 0x62d-0x3933 #25> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 293 0x66a-0x68c #28> <Stretch 683 1412> <Color 294 0x683-0x683 #1>
Stranger in color <Color 302 0x6b6-0x398a #58> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 305 0x6ce-0x6e5 #10> <Stretch 6d2 1491> <Color 306 0x6d2-0x6fb #29>
Stranger in color <Color 306 0x6d2-0x6fb #29> <Stretch 6db 1500> <Color 307 0x6db-0x6db #1>
Stranger in color <Color 315 0x767-0x3c02 #45> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 317 0x794-0x3c0c #6> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 318 0x799-0x3bc2 #8> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 323 0x7b5-0x3b4d #6> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 324 0x7b9-0x7e7 #18> <Stretch 7c0 1729> <Color 325 0x7c0-0x7c0 #1>
Stranger in color <Color 334 0x820-0x870 #47> <Stretch 821 1826> <Color 335 0x821-0x87a #11>
Stranger in color <Color 335 0x821-0x87a #11> <Stretch 822 1827> <Color 334 0x820-0x870 #47>
Stranger in color <Color 338 0x903-0x3bd6 #3> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 339 0x905-0x3bd7 #15> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 340 0x913-0x3bd9 #19> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 341 0x917-0x3bda #3> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 346 0x950-0x3bf1 #30> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 349 0x97e-0x3162 #6> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 351 0x98a-0x12d3 #16> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 354 0x98e-0x3161 #7> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 355 0x993-0x30cb #3> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 359 0x9a0-0x2f9a #6> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 361 0x9a6-0x22c0 #64> <Stretch 1f47 7752> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 362 0x9a9-0x183a #37> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 363 0x9aa-0x1465 #50> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 364 0x9ab-0x17f1 #6> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 365 0x9ac-0x174a #11> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 368 0x9b0-0x2f9e #6> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 374 0x9ca-0x9f4 #39> <Stretch 9df 2272> <Color 375 0x9df-0x9e2 #4>
Stranger in color <Color 384 0xa24-0x306b #80> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 385 0xa29-0x28fb #44> <Stretch 1f47 7752> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 386 0xa2d-0x1ab3 #78> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 387 0xa2f-0x180e #21> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 388 0xa30-0x17a8 #15> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 389 0xa31-0x1b11 #20> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 390 0xa33-0xc4d #17> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 394 0xa4e-0x2feb #36> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 398 0xa55-0xa5a #2> <Stretch a56 2391> <Color 399 0xa56-0xa5b #2>
Stranger in color <Color 399 0xa56-0xa5b #2> <Stretch a57 2392> <Color 394 0xa4e-0x2feb #36>
Stranger in color <Color 403 0xa73-0x28f7 #15> <Stretch 1f47 7752> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 404 0xa74-0xa80 #6> <Stretch a76 2423> <Color 405 0xa76-0x1bb0 #14>
Stranger in color <Color 405 0xa76-0x1bb0 #14> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 406 0xa78-0x14b0 #4> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 407 0xa7a-0x17b1 #5> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 408 0xa7b-0x1afe #12> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 409 0xa7c-0xc3e #13> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 411 0xa88-0xa94 #6> <Stretch a8a 2443> <Color 412 0xa8a-0x1bbe #14>
Stranger in color <Color 412 0xa8a-0x1bbe #14> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 413 0xa8c-0x14b4 #4> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 414 0xa8e-0x17b5 #5> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 415 0xa8f-0x1b04 #6> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 416 0xa90-0xc44 #7> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 418 0xa9c-0xaa7 #5> <Stretch a9e 2463> <Color 419 0xa9e-0x1bd2 #20>
Stranger in color <Color 419 0xa9e-0x1bd2 #20> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 420 0xa9f-0x1ac3 #17> <Stretch 1a4c 6477> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 421 0xaa0-0x14ee #46> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 422 0xaa2-0x17c0 #6> <Stretch b1b 2588> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 428 0xac1-0xacb #2> <Stretch ac2 2499> <Color 429 0xac2-0xadc #18>
Stranger in color <Color 429 0xac2-0xadc #18> <Stretch ac3 2500> <Color 430 0xac3-0xac3 #1>
Stranger in color <Color 439 0xb6e-0x3beb #5> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 446 0xb93-0x3c04 #23> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 447 0xba9-0x3bef #106> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
Stranger in color <Color 448 0xc05-0xc16 #12> <Stretch c06 2823> <Color 449 0xc06-0xc06 #1>
Stranger in color <Color 490 0xd34-0x3bd3 #106> <Stretch 297e 10367> <Color 0 0x0-0x3c20 #5344>
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