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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 1870 (0x74e)
Types: EM, TextFile
Names: »VRFA16.EM«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─⟦this⟧ »VRFA16.EM«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─⟦this⟧ »VRFA16.EM«
[eq %1%,]
[set vrf_addr [read A_ADDRESS =,,]]
[else]
[set vrf_addr %1%]
[end]
[#lt [var vrf_addr] 10]
[set vrf_addr 0[var vrf_addr]]
[end]
[write]
[write,,RF A ADDR,,,,VAL DATA]
[write,,---------,,,,--------]
[write,,,,,,[var vrf_addr]0,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]0 0]]
[write,,,,,,[var vrf_addr]1,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]1 0]]
[write,,,,,,[var vrf_addr]2,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]2 0]]
[write,,,,,,[var vrf_addr]3,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]3 0]]
[write,,,,,,[var vrf_addr]4,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]4 0]]
[write,,,,,,[var vrf_addr]5,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]5 0]]
[write,,,,,,[var vrf_addr]6,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]6 0]]
[write,,,,,,[var vrf_addr]7,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]7 0]]
[write,,,,,,[var vrf_addr]8,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]8 0]]
[write,,,,,,[var vrf_addr]9,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]9 0]]
[write,,,,,,[var vrf_addr]A,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]A 0]]
[write,,,,,,[var vrf_addr]B,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]B 0]]
[write,,,,,,[var vrf_addr]C,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]C 0]]
[write,,,,,,[var vrf_addr]D,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]D 0]]
[write,,,,,,[var vrf_addr]E,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]E 0]]
[write,,,,,,[var vrf_addr]F,,,,,,[xeq val prep_read_reg;
xeq val read_a_reg [var vrf_addr]F 0]]
[kill vrf_addr]