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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 449536 (0x6dc00)
Types: M200_UCODE
Names: »DIAG.M200_UCODE«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─⟦this⟧ »DIAG.M200_UCODE«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─⟦this⟧ »DIAG.M200_UCODE«
└─⟦b4205821b⟧ Bits:30000743 8mm tape, Rational 1000, DFS, D_12_7_3 SEQ288
└─⟦this⟧ »DIAG.M200_UCODE«
└─⟦b434774df⟧ Bits:30000528 8mm tape, Rational 1000, DFS, D_12_6_5
└─⟦this⟧ »DIAG.M200_UCODE«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─⟦this⟧ »DIAG.M200_UCODE«
0100 ; --------------------------------------------------------------------------------------
0100 ; Initial Register File (adr, typ, val, frame:offset) where non-zero
0100 ; 000 TR00:00 0000000000000000 VR00:00 0000000000000000
0100 ; 001 TR00:01 0000000000000000 VR00:01 0000000000000000
0100 ; 002 TR00:02 0000000000000000 VR00:02 0000000000000000
0100 ; 003 TR00:03 0000000000000000 VR00:03 0000000000000000
0100 ; 004 TR00:04 0000000000000000 VR00:04 0000000000000000
0100 ; 005 TR00:05 0000000000000000 VR00:05 0000000000000000
0100 ; 006 TR00:06 0000000000000000 VR00:06 0000000000000000
0100 ; 007 TR00:07 0000000000000000 VR00:07 0000000000000000
0100 ; 008 TR00:08 0000000000000000 VR00:08 0000000000000000
0100 ; 009 TR00:09 0000000000000000 VR00:09 0000000000000000
0100 ; 00a TR00:0a 0000000000000000 VR00:0a 0000000000000000
0100 ; 00b TR00:0b 0000000000000000 VR00:0b 0000000000000000
0100 ; 00c TR00:0c 0000000000000000 VR00:0c 0000000000000000
0100 ; 00d TR00:0d 0000000000000000 VR00:0d 0000000000000000
0100 ; 00e TR00:0e 0000000000000000 VR00:0e 0000000000000000
0100 ; 00f TR00:0f 0000000000000000 VR00:0f 0000000000000000
0100 ; 010 TR00:10 0000000000000000 VR00:10 0000000000000000
0100 ; 011 TR00:11 0000000000000000 VR00:11 0000000000000000
0100 ; 012 TR00:12 0000000000000000 VR00:12 0000000000000000
0100 ; 013 TR00:13 0000000000000000 VR00:13 0000000000000000
0100 ; 014 TR00:14 0000000000000000 VR00:14 0000000000000000
0100 ; 015 TR00:15 0000000000000000 VR00:15 0000000000000000
0100 ; 016 TR00:16 0000000000000000 VR00:16 0000000000000000
0100 ; 017 TR00:17 0000000000000000 VR00:17 0000000000000000
0100 ; 018 TR00:18 0000000000000000 VR00:18 0000000000000000
0100 ; 019 TR00:19 0000000000000000 VR00:19 0000000000000000
0100 ; 01a TR00:1a 0000000000000000 VR00:1a 0000000000000000
0100 ; 01b TR00:1b 0000000000000000 VR00:1b 0000000000000000
0100 ; 01c TR00:1c 0000000000000000 VR00:1c 0000000000000000
0100 ; 01d TR00:1d 0000000000000000 VR00:1d 0000000000000000
0100 ; 01e TR00:1e 0000000000000000 VR00:1e 0000000000000000
0100 ; 01f TR00:1f 0000000000000000 VR00:1f 0000000000000000
0100 ; 020 TR01:00 0000000000000000 VR01:00 0000000000000000
0100 ; 021 TR01:01 0000000000000000 VR01:01 0000000000000000
0100 ; 022 TR01:02 0000000000000000 VR01:02 0000000000000000
0100 ; 023 TR01:03 0000000000000000 VR01:03 0000000000000000
0100 ; 024 TR01:04 0000000000000000 VR01:04 0000000000000000
0100 ; 025 TR01:05 0000000000000000 VR01:05 0000000000000000
0100 ; 026 TR01:06 0000000000000000 VR01:06 0000000000000000
0100 ; 027 TR01:07 0000000000000000 VR01:07 0000000000000000
0100 ; 028 TR01:08 0000000000000000 VR01:08 0000000000000000
0100 ; 029 TR01:09 0000000000000000 VR01:09 0000000000000000
0100 ; 02a TR01:0a 0000000000000000 VR01:0a 0000000000000000
0100 ; 02b TR01:0b 0000000000000000 VR01:0b 0000000000000000
0100 ; 02c TR01:0c 0000000000000000 VR01:0c 0000000000000000
0100 ; 02d TR01:0d 0000000000000000 VR01:0d 0000000000000000
0100 ; 02e TR01:0e 0000000000000000 VR01:0e 0000000000000000
0100 ; 02f TR01:0f 0000000000000000 VR01:0f 0000000000000000
0100 ; 030 TR01:10 0000000000000000 VR01:10 0000000000000000
0100 ; 031 TR01:11 0000000000000000 VR01:11 0000000000000000
0100 ; 032 TR01:12 0000000000000000 VR01:12 0000000000000000
0100 ; 033 TR01:13 0000000000000000 VR01:13 0000000000000000
0100 ; 034 TR01:14 0000000000000000 VR01:14 0000000000000000
0100 ; 035 TR01:15 0000000000000000 VR01:15 0000000000000000
0100 ; 036 TR01:16 0000000000000000 VR01:16 0000000000000000
0100 ; 037 TR01:17 0000000000000000 VR01:17 0000000000000000
0100 ; 038 TR01:18 0000000000000000 VR01:18 0000000000000000
0100 ; 039 TR01:19 0000000000000000 VR01:19 0000000000000000
0100 ; 03a TR01:1a 0000000000000000 VR01:1a 0000000000000000
0100 ; 03b TR01:1b 0000000000000000 VR01:1b 0000000000000000
0100 ; 03c TR01:1c 0000000000000000 VR01:1c 0000000000000000
0100 ; 03d TR01:1d 0000000000000000 VR01:1d 0000000000000000
0100 ; 03e TR01:1e 0000000000000000 VR01:1e 0000000000000000
0100 ; 03f TR01:1f 0000000000000000 VR01:1f 0000000000000000
0100 ; 040 TR02:00 0000000000000000 VR02:00 0000000000000000
0100 ; 041 TR02:01 0000000000000000 VR02:01 0000000000000000
0100 ; 042 TR02:02 0000000000000000 VR02:02 0000000000000000
0100 ; 043 TR02:03 0000000000000000 VR02:03 0000000000000000
0100 ; 044 TR02:04 0000000000000000 VR02:04 0000000000000000
0100 ; 045 TR02:05 0000000000000000 VR02:05 0000000000000000
0100 ; 046 TR02:06 0000000000000000 VR02:06 0000000000000000
0100 ; 047 TR02:07 0000000000000000 VR02:07 0000000000000000
0100 ; 048 TR02:08 0000000000000000 VR02:08 0000000000000000
0100 ; 049 TR02:09 0000000000000000 VR02:09 0000000000000000
0100 ; 04a TR02:0a 0000000000000000 VR02:0a 0000000000000000
0100 ; 04b TR02:0b 0000000000000000 VR02:0b 0000000000000000
0100 ; 04c TR02:0c 0000000000000000 VR02:0c 0000000000000000
0100 ; 04d TR02:0d 0000000000000000 VR02:0d 0000000000000000
0100 ; 04e TR02:0e 0000000000000000 VR02:0e 0000000000000000
0100 ; 04f TR02:0f 0000000000000000 VR02:0f 0000000000000000
0100 ; 050 TR02:10 0000000000000000 VR02:10 0000000000000000
0100 ; 051 TR02:11 0000000000000000 VR02:11 0000000000000000
0100 ; 052 TR02:12 0000000000000000 VR02:12 0000000000000000
0100 ; 053 TR02:13 0000000000000000 VR02:13 0000000000000000
0100 ; 054 TR02:14 0000000000000000 VR02:14 0000000000000000
0100 ; 055 TR02:15 0000000000000000 VR02:15 0000000000000000
0100 ; 056 TR02:16 0000000000000000 VR02:16 0000000000000000
0100 ; 057 TR02:17 0000000000000000 VR02:17 0000000000000000
0100 ; 058 TR02:18 0000000000000000 VR02:18 0000000000000000
0100 ; 059 TR02:19 0000000000000000 VR02:19 0000000000000000
0100 ; 05a TR02:1a 0000000000000000 VR02:1a 0000000000000000
0100 ; 05b TR02:1b 0000000000000000 VR02:1b 0000000000000000
0100 ; 05c TR02:1c 0000000000000000 VR02:1c 0000000000000000
0100 ; 05d TR02:1d 0000000000000000 VR02:1d 0000000000000000
0100 ; 05e TR02:1e 0000000000000000 VR02:1e 0000000000000000
0100 ; 05f TR02:1f 0000000000000000 VR02:1f 0000000000000000
0100 ; 060 TR03:00 0000000000000000 VR03:00 0000000000000000
0100 ; 061 TR03:01 0000000000000000 VR03:01 0000000000000000
0100 ; 062 TR03:02 0000000000000000 VR03:02 0000000000000000
0100 ; 063 TR03:03 0000000000000000 VR03:03 0000000000000000
0100 ; 064 TR03:04 0000000000000000 VR03:04 0000000000000000
0100 ; 065 TR03:05 0000000000000000 VR03:05 0000000000000000
0100 ; 066 TR03:06 0000000000000000 VR03:06 0000000000000000
0100 ; 067 TR03:07 0000000000000000 VR03:07 0000000000000000
0100 ; 068 TR03:08 0000000000000000 VR03:08 0000000000000000
0100 ; 069 TR03:09 0000000000000000 VR03:09 0000000000000000
0100 ; 06a TR03:0a 0000000000000000 VR03:0a 0000000000000000
0100 ; 06b TR03:0b 0000000000000000 VR03:0b 0000000000000000
0100 ; 06c TR03:0c 0000000000000000 VR03:0c 0000000000000000
0100 ; 06d TR03:0d 0000000000000000 VR03:0d 0000000000000000
0100 ; 06e TR03:0e 0000000000000000 VR03:0e 0000000000000000
0100 ; 06f TR03:0f 0000000000000000 VR03:0f 0000000000000000
0100 ; 070 TR03:10 0000000000000000 VR03:10 0000000000000000
0100 ; 071 TR03:11 0000000000000000 VR03:11 0000000000000000
0100 ; 072 TR03:12 0000000000000000 VR03:12 0000000000000000
0100 ; 073 TR03:13 0000000000000000 VR03:13 0000000000000000
0100 ; 074 TR03:14 0000000000000000 VR03:14 0000000000000000
0100 ; 075 TR03:15 0000000000000000 VR03:15 0000000000000000
0100 ; 076 TR03:16 0000000000000000 VR03:16 0000000000000000
0100 ; 077 TR03:17 0000000000000000 VR03:17 0000000000000000
0100 ; 078 TR03:18 0000000000000000 VR03:18 0000000000000000
0100 ; 079 TR03:19 0000000000000000 VR03:19 0000000000000000
0100 ; 07a TR03:1a 0000000000000000 VR03:1a 0000000000000000
0100 ; 07b TR03:1b 0000000000000000 VR03:1b 0000000000000000
0100 ; 07c TR03:1c 0000000000000000 VR03:1c 0000000000000000
0100 ; 07d TR03:1d 0000000000000000 VR03:1d 0000000000000000
0100 ; 07e TR03:1e 0000000000000000 VR03:1e 0000000000000000
0100 ; 07f TR03:1f 0000000000000000 VR03:1f 0000000000000000
0100 ; 080 TR04:00 0000000000000001 VR04:00 0000000000000001
0100 ; 081 TR04:01 0000000000000002 VR04:01 0000000000000002
0100 ; 082 TR04:02 0000000000000004 VR04:02 0000000000000004
0100 ; 083 TR04:03 0000000000000008 VR04:03 0000000000000008
0100 ; 084 TR04:04 0000000000000010 VR04:04 0000000000000010
0100 ; 085 TR04:05 0000000000000020 VR04:05 0000000000000020
0100 ; 086 TR04:06 0000000000000040 VR04:06 0000000000000040
0100 ; 087 TR04:07 0000000000000080 VR04:07 0000000000000080
0100 ; 088 TR04:08 0000000000000100 VR04:08 0000000000000100
0100 ; 089 TR04:09 0000000000000200 VR04:09 0000000000000200
0100 ; 08a TR04:0a 0000000000000400 VR04:0a 0000000000000400
0100 ; 08b TR04:0b 0000000000000800 VR04:0b 0000000000000800
0100 ; 08c TR04:0c 0000000000001000 VR04:0c 0000000000001000
0100 ; 08d TR04:0d 0000000000002000 VR04:0d 0000000000002000
0100 ; 08e TR04:0e 0000000000004000 VR04:0e 0000000000004000
0100 ; 08f TR04:0f 0000000000008000 VR04:0f 0000000000008000
0100 ; 090 TR04:10 0000000000010000 VR04:10 0000000000010000
0100 ; 091 TR04:11 0000000000020000 VR04:11 0000000000020000
0100 ; 092 TR04:12 0000000000040000 VR04:12 0000000000040000
0100 ; 093 TR04:13 0000000000080000 VR04:13 0000000000080000
0100 ; 094 TR04:14 0000000000100000 VR04:14 0000000000100000
0100 ; 095 TR04:15 0000000000200000 VR04:15 0000000000200000
0100 ; 096 TR04:16 0000000000400000 VR04:16 0000000000400000
0100 ; 097 TR04:17 0000000000800000 VR04:17 0000000000800000
0100 ; 098 TR04:18 0000000001000000 VR04:18 0000000001000000
0100 ; 099 TR04:19 0000000002000000 VR04:19 0000000002000000
0100 ; 09a TR04:1a 0000000004000000 VR04:1a 0000000004000000
0100 ; 09b TR04:1b 0000000008000000 VR04:1b 0000000008000000
0100 ; 09c TR04:1c 0000000010000000 VR04:1c 0000000010000000
0100 ; 09d TR04:1d 0000000020000000 VR04:1d 0000000020000000
0100 ; 09e TR04:1e 0000000040000000 VR04:1e 0000000040000000
0100 ; 09f TR04:1f 0000000080000000 VR04:1f 0000000080000000
0100 ; 0a0 TR05:00 0000000100000000 VR05:00 0000000100000000
0100 ; 0a1 TR05:01 0000000200000000 VR05:01 0000000200000000
0100 ; 0a2 TR05:02 0000000400000000 VR05:02 0000000400000000
0100 ; 0a3 TR05:03 0000000800000000 VR05:03 0000000800000000
0100 ; 0a4 TR05:04 0000001000000000 VR05:04 0000001000000000
0100 ; 0a5 TR05:05 0000002000000000 VR05:05 0000002000000000
0100 ; 0a6 TR05:06 0000004000000000 VR05:06 0000004000000000
0100 ; 0a7 TR05:07 0000008000000000 VR05:07 0000008000000000
0100 ; 0a8 TR05:08 0000010000000000 VR05:08 0000010000000000
0100 ; 0a9 TR05:09 0000020000000000 VR05:09 0000020000000000
0100 ; 0aa TR05:0a 0000040000000000 VR05:0a 0000040000000000
0100 ; 0ab TR05:0b 0000080000000000 VR05:0b 0000080000000000
0100 ; 0ac TR05:0c 0000100000000000 VR05:0c 0000100000000000
0100 ; 0ad TR05:0d 0000200000000000 VR05:0d 0000200000000000
0100 ; 0ae TR05:0e 0000400000000000 VR05:0e 0000400000000000
0100 ; 0af TR05:0f 0000800000000000 VR05:0f 0000800000000000
0100 ; 0b0 TR05:10 0001000000000000 VR05:10 0001000000000000
0100 ; 0b1 TR05:11 0002000000000000 VR05:11 0002000000000000
0100 ; 0b2 TR05:12 0004000000000000 VR05:12 0004000000000000
0100 ; 0b3 TR05:13 0008000000000000 VR05:13 0008000000000000
0100 ; 0b4 TR05:14 0010000000000000 VR05:14 0010000000000000
0100 ; 0b5 TR05:15 0020000000000000 VR05:15 0020000000000000
0100 ; 0b6 TR05:16 0040000000000000 VR05:16 0040000000000000
0100 ; 0b7 TR05:17 0080000000000000 VR05:17 0080000000000000
0100 ; 0b8 TR05:18 0100000000000000 VR05:18 0100000000000000
0100 ; 0b9 TR05:19 0200000000000000 VR05:19 0200000000000000
0100 ; 0ba TR05:1a 0400000000000000 VR05:1a 0400000000000000
0100 ; 0bb TR05:1b 0800000000000000 VR05:1b 0800000000000000
0100 ; 0bc TR05:1c 1000000000000000 VR05:1c 1000000000000000
0100 ; 0bd TR05:1d 2000000000000000 VR05:1d 2000000000000000
0100 ; 0be TR05:1e 4000000000000000 VR05:1e 4000000000000000
0100 ; 0bf TR05:1f 8000000000000000 VR05:1f 8000000000000000
0100 ; 0c0 TR06:00 0000000000000000 VR06:00 0000000000000000
0100 ; 0c1 TR06:01 0000000000000000 VR06:01 0000000000000000
0100 ; 0c2 TR06:02 0000000000000000 VR06:02 0000000000000000
0100 ; 0c3 TR06:03 0000000000000000 VR06:03 0000000000000000
0100 ; 0c4 TR06:04 0000000000000000 VR06:04 0000000000000000
0100 ; 0c5 TR06:05 0000000000000000 VR06:05 0000000000000000
0100 ; 0c6 TR06:06 0000000000000000 VR06:06 0000000000000000
0100 ; 0c7 TR06:07 0000000000000000 VR06:07 0000000000000000
0100 ; 0c8 TR06:08 0000000000000000 VR06:08 0000000000000000
0100 ; 0c9 TR06:09 0000000000000000 VR06:09 0000000000000000
0100 ; 0ca TR06:0a 0000000000000000 VR06:0a 0000000000000000
0100 ; 0cb TR06:0b 0000000000000000 VR06:0b 0000000000000000
0100 ; 0cc TR06:0c 0000000000000000 VR06:0c 0000000000000000
0100 ; 0cd TR06:0d 0000000000000000 VR06:0d 0000000000000000
0100 ; 0ce TR06:0e 0000000000000000 VR06:0e 0000000000000000
0100 ; 0cf TR06:0f 0000000000000000 VR06:0f 0000000000000000
0100 ; 0d0 TR06:10 0000000000000000 VR06:10 0000000000000000
0100 ; 0d1 TR06:11 0000000000000000 VR06:11 0000000000000000
0100 ; 0d2 TR06:12 0000000000000000 VR06:12 0000000000000000
0100 ; 0d3 TR06:13 0000000000000000 VR06:13 0000000000000000
0100 ; 0d4 TR06:14 0000000000000000 VR06:14 0000000000000000
0100 ; 0d5 TR06:15 0000000000000000 VR06:15 0000000000000000
0100 ; 0d6 TR06:16 0000000000000000 VR06:16 0000000000000000
0100 ; 0d7 TR06:17 0000000000000000 VR06:17 0000000000000000
0100 ; 0d8 TR06:18 0000000000000000 VR06:18 0000000000000000
0100 ; 0d9 TR06:19 0000000000000000 VR06:19 0000000000000000
0100 ; 0da TR06:1a 0000000000000000 VR06:1a 0000000000000000
0100 ; 0db TR06:1b 0000000000000000 VR06:1b 0000000000000000
0100 ; 0dc TR06:1c 0000000000000000 VR06:1c 0000000000000000
0100 ; 0dd TR06:1d 0000000000000000 VR06:1d 0000000000000000
0100 ; 0de TR06:1e 0000000000000000 VR06:1e 0000000000000000
0100 ; 0df TR06:1f 0000000000000000 VR06:1f 0000000000000000
0100 ; 0e0 TR07:00 0000000000000000 VR07:00 0000000000000000
0100 ; 0e1 TR07:01 0000000000000000 VR07:01 0000000000000000
0100 ; 0e2 TR07:02 0000000000000000 VR07:02 0000000000000000
0100 ; 0e3 TR07:03 0000000000000000 VR07:03 0000000000000000
0100 ; 0e4 TR07:04 0000000000000000 VR07:04 0000000000000000
0100 ; 0e5 TR07:05 0000000000000000 VR07:05 0000000000000000
0100 ; 0e6 TR07:06 0000000000000000 VR07:06 0000000000000000
0100 ; 0e7 TR07:07 0000000000000000 VR07:07 0000000000000000
0100 ; 0e8 TR07:08 0000000000000000 VR07:08 0000000000000000
0100 ; 0e9 TR07:09 0000000000000000 VR07:09 0000000000000000
0100 ; 0ea TR07:0a 0000000000000000 VR07:0a 0000000000000000
0100 ; 0eb TR07:0b 0000000000000000 VR07:0b 0000000000000000
0100 ; 0ec TR07:0c 0000000000000000 VR07:0c 0000000000000000
0100 ; 0ed TR07:0d 0000000000000000 VR07:0d 0000000000000000
0100 ; 0ee TR07:0e 0000000000000000 VR07:0e 0000000000000000
0100 ; 0ef TR07:0f 0000000000000000 VR07:0f 0000000000000000
0100 ; 0f0 TR07:10 0000000000000000 VR07:10 0000000000000000
0100 ; 0f1 TR07:11 0000000000000000 VR07:11 0000000000000000
0100 ; 0f2 TR07:12 0000000000000000 VR07:12 0000000000000000
0100 ; 0f3 TR07:13 0000000000000000 VR07:13 0000000000000000
0100 ; 0f4 TR07:14 0000000000000000 VR07:14 0000000000000000
0100 ; 0f5 TR07:15 0000000000000000 VR07:15 0000000000000000
0100 ; 0f6 TR07:16 0000000000000000 VR07:16 0000000000000000
0100 ; 0f7 TR07:17 0000000000000000 VR07:17 0000000000000000
0100 ; 0f8 TR07:18 0000000000000000 VR07:18 0000000000000000
0100 ; 0f9 TR07:19 0000000000000000 VR07:19 0000000000000000
0100 ; 0fa TR07:1a 0000000000000000 VR07:1a 0000000000000000
0100 ; 0fb TR07:1b 0000000000000000 VR07:1b 0000000000000000
0100 ; 0fc TR07:1c 0000000000000000 VR07:1c 0000000000000000
0100 ; 0fd TR07:1d 0000000000000000 VR07:1d 0000000000000000
0100 ; 0fe TR07:1e 0000000000000000 VR07:1e 0000000000000000
0100 ; 0ff TR07:1f 0000000000000000 VR07:1f 0000000000000000
0100 ; 100 TR08:00 0000000000000000 VR08:00 0000000000000000
0100 ; 101 TR08:01 0000000000000000 VR08:01 0000000000000000
0100 ; 102 TR08:02 0000000000000000 VR08:02 0000000000000000
0100 ; 103 TR08:03 0000000000000000 VR08:03 0000000000000000
0100 ; 104 TR08:04 0000000000000000 VR08:04 0000000000000000
0100 ; 105 TR08:05 0000000000000000 VR08:05 0000000000000000
0100 ; 106 TR08:06 0000000000000000 VR08:06 0000000000000000
0100 ; 107 TR08:07 0000000000000000 VR08:07 0000000000000000
0100 ; 108 TR08:08 0000000000000000 VR08:08 0000000000000000
0100 ; 109 TR08:09 0000000000000000 VR08:09 0000000000000000
0100 ; 10a TR08:0a 0000000000000000 VR08:0a 0000000000000000
0100 ; 10b TR08:0b 0000000000000000 VR08:0b 0000000000000000
0100 ; 10c TR08:0c 0000000000000000 VR08:0c 0000000000000000
0100 ; 10d TR08:0d 0000000000000000 VR08:0d 0000000000000000
0100 ; 10e TR08:0e 0000000000000000 VR08:0e 0000000000000000
0100 ; 10f TR08:0f 0000000000000000 VR08:0f 0000000000000000
0100 ; 110 TR08:10 0000000000000000 VR08:10 0000000000000000
0100 ; 111 TR08:11 0000000000000000 VR08:11 0000000000000000
0100 ; 112 TR08:12 0000000000000000 VR08:12 0000000000000000
0100 ; 113 TR08:13 0000000000000000 VR08:13 0000000000000000
0100 ; 114 TR08:14 0000000000000000 VR08:14 0000000000000000
0100 ; 115 TR08:15 0000000000000000 VR08:15 0000000000000000
0100 ; 116 TR08:16 0000000000000000 VR08:16 0000000000000000
0100 ; 117 TR08:17 0000000000000000 VR08:17 0000000000000000
0100 ; 118 TR08:18 0000000000000000 VR08:18 0000000000000000
0100 ; 119 TR08:19 0000000000000000 VR08:19 0000000000000000
0100 ; 11a TR08:1a 0000000000000000 VR08:1a 0000000000000000
0100 ; 11b TR08:1b 0000000000000000 VR08:1b 0000000000000000
0100 ; 11c TR08:1c 0000000000000000 VR08:1c 0000000000000000
0100 ; 11d TR08:1d 0000000000000000 VR08:1d 0000000000000000
0100 ; 11e TR08:1e 0000000000000000 VR08:1e 0000000000000000
0100 ; 11f TR08:1f 0000000000000000 VR08:1f 0000000000000000
0100 ; 120 TR09:00 0000000000000000 VR09:00 0000000000000000
0100 ; 121 TR09:01 0000000000000000 VR09:01 0000000000000000
0100 ; 122 TR09:02 0000000000000000 VR09:02 0000000000000000
0100 ; 123 TR09:03 0000000000000000 VR09:03 0000000000000000
0100 ; 124 TR09:04 0000000000000000 VR09:04 0000000000000000
0100 ; 125 TR09:05 0000000000000000 VR09:05 0000000000000000
0100 ; 126 TR09:06 0000000000000000 VR09:06 0000000000000000
0100 ; 127 TR09:07 0000000000000000 VR09:07 0000000000000000
0100 ; 128 TR09:08 0000000000000000 VR09:08 0000000000000000
0100 ; 129 TR09:09 0000000000000000 VR09:09 0000000000000000
0100 ; 12a TR09:0a 0000000000000000 VR09:0a 0000000000000000
0100 ; 12b TR09:0b 0000000000000000 VR09:0b 0000000000000000
0100 ; 12c TR09:0c 0000000000000000 VR09:0c 0000000000000000
0100 ; 12d TR09:0d 0000000000000000 VR09:0d 0000000000000000
0100 ; 12e TR09:0e 0000000000000000 VR09:0e 0000000000000000
0100 ; 12f TR09:0f 0000000000000000 VR09:0f 0000000000000000
0100 ; 130 TR09:10 0000000000000000 VR09:10 0000000000000000
0100 ; 131 TR09:11 0000000000000000 VR09:11 0000000000000000
0100 ; 132 TR09:12 0000000000000000 VR09:12 0000000000000000
0100 ; 133 TR09:13 0000000000000000 VR09:13 0000000000000000
0100 ; 134 TR09:14 0000000000000000 VR09:14 0000000000000000
0100 ; 135 TR09:15 0000000000000000 VR09:15 0000000000000000
0100 ; 136 TR09:16 0000000000000000 VR09:16 0000000000000000
0100 ; 137 TR09:17 0000000000000000 VR09:17 0000000000000000
0100 ; 138 TR09:18 0000000000000000 VR09:18 0000000000000000
0100 ; 139 TR09:19 0000000000000000 VR09:19 0000000000000000
0100 ; 13a TR09:1a 0000000000000000 VR09:1a 0000000000000000
0100 ; 13b TR09:1b 0000000000000000 VR09:1b 0000000000000000
0100 ; 13c TR09:1c 0000000000000000 VR09:1c 0000000000000000
0100 ; 13d TR09:1d 0000000000000000 VR09:1d 0000000000000000
0100 ; 13e TR09:1e 0000000000000000 VR09:1e 0000000000000000
0100 ; 13f TR09:1f 0000000000000000 VR09:1f 0000000000000000
0100 ; 140 TR0a:00 0000000000000000 VR0a:00 0000000000000000
0100 ; 141 TR0a:01 0000000000000000 VR0a:01 0000000000000000
0100 ; 142 TR0a:02 0000000000000000 VR0a:02 0000000000000000
0100 ; 143 TR0a:03 0000000000000000 VR0a:03 0000000000000000
0100 ; 144 TR0a:04 0000000000000000 VR0a:04 0000000000000000
0100 ; 145 TR0a:05 0000000000000000 VR0a:05 0000000000000000
0100 ; 146 TR0a:06 0000000000000000 VR0a:06 0000000000000000
0100 ; 147 TR0a:07 0000000000000000 VR0a:07 0000000000000000
0100 ; 148 TR0a:08 0000000000000000 VR0a:08 0000000000000000
0100 ; 149 TR0a:09 0000000000000000 VR0a:09 0000000000000000
0100 ; 14a TR0a:0a 0000000000000000 VR0a:0a 0000000000000000
0100 ; 14b TR0a:0b 0000000000000000 VR0a:0b 0000000000000000
0100 ; 14c TR0a:0c 0000000000000000 VR0a:0c 0000000000000000
0100 ; 14d TR0a:0d 0000000000000000 VR0a:0d 0000000000000000
0100 ; 14e TR0a:0e 0000000000000000 VR0a:0e 0000000000000000
0100 ; 14f TR0a:0f 0000000000000000 VR0a:0f 0000000000000000
0100 ; 150 TR0a:10 0000000000000000 VR0a:10 0000000000000000
0100 ; 151 TR0a:11 0000000000000000 VR0a:11 0000000000000000
0100 ; 152 TR0a:12 0000000000000000 VR0a:12 0000000000000000
0100 ; 153 TR0a:13 0000000000000000 VR0a:13 0000000000000000
0100 ; 154 TR0a:14 0000000000000000 VR0a:14 0000000000000000
0100 ; 155 TR0a:15 0000000000000000 VR0a:15 0000000000000000
0100 ; 156 TR0a:16 0000000000000000 VR0a:16 0000000000000000
0100 ; 157 TR0a:17 0000000000000000 VR0a:17 0000000000000000
0100 ; 158 TR0a:18 0000000000000000 VR0a:18 0000000000000000
0100 ; 159 TR0a:19 0000000000000000 VR0a:19 0000000000000000
0100 ; 15a TR0a:1a 0000000000000000 VR0a:1a 0000000000000000
0100 ; 15b TR0a:1b 0000000000000000 VR0a:1b 0000000000000000
0100 ; 15c TR0a:1c 0000000000000000 VR0a:1c 0000000000000000
0100 ; 15d TR0a:1d 0000000000000000 VR0a:1d 0000000000000000
0100 ; 15e TR0a:1e 0000000000000000 VR0a:1e 0000000000000000
0100 ; 15f TR0a:1f 0000000000000000 VR0a:1f 0000000000000000
0100 ; 160 TR0b:00 0000000000000000 VR0b:00 0000000000000000
0100 ; 161 TR0b:01 0000000000000000 VR0b:01 0000000000000000
0100 ; 162 TR0b:02 0000000000000000 VR0b:02 0000000000000000
0100 ; 163 TR0b:03 0000000000000000 VR0b:03 0000000000000000
0100 ; 164 TR0b:04 0000000000000000 VR0b:04 0000000000000000
0100 ; 165 TR0b:05 0000000000000000 VR0b:05 0000000000000000
0100 ; 166 TR0b:06 0000000000000000 VR0b:06 0000000000000000
0100 ; 167 TR0b:07 0000000000000000 VR0b:07 0000000000000000
0100 ; 168 TR0b:08 0000000000000000 VR0b:08 0000000000000000
0100 ; 169 TR0b:09 0000000000000000 VR0b:09 0000000000000000
0100 ; 16a TR0b:0a 0000000000000000 VR0b:0a 0000000000000000
0100 ; 16b TR0b:0b 0000000000000000 VR0b:0b 0000000000000000
0100 ; 16c TR0b:0c 0000000000000000 VR0b:0c 0000000000000000
0100 ; 16d TR0b:0d 0000000000000000 VR0b:0d 0000000000000000
0100 ; 16e TR0b:0e 0000000000000000 VR0b:0e 0000000000000000
0100 ; 16f TR0b:0f 0000000000000000 VR0b:0f 0000000000000000
0100 ; 170 TR0b:10 0000000000000000 VR0b:10 0000000000000000
0100 ; 171 TR0b:11 0000000000000000 VR0b:11 0000000000000000
0100 ; 172 TR0b:12 0000000000000000 VR0b:12 0000000000000000
0100 ; 173 TR0b:13 0000000000000000 VR0b:13 0000000000000000
0100 ; 174 TR0b:14 0000000000000000 VR0b:14 0000000000000000
0100 ; 175 TR0b:15 0000000000000000 VR0b:15 0000000000000000
0100 ; 176 TR0b:16 0000000000000000 VR0b:16 0000000000000000
0100 ; 177 TR0b:17 0000000000000000 VR0b:17 0000000000000000
0100 ; 178 TR0b:18 0000000000000000 VR0b:18 0000000000000000
0100 ; 179 TR0b:19 0000000000000000 VR0b:19 0000000000000000
0100 ; 17a TR0b:1a 0000000000000000 VR0b:1a 0000000000000000
0100 ; 17b TR0b:1b 0000000000000000 VR0b:1b 0000000000000000
0100 ; 17c TR0b:1c 0000000000000000 VR0b:1c 0000000000000000
0100 ; 17d TR0b:1d 0000000000000000 VR0b:1d 0000000000000000
0100 ; 17e TR0b:1e 0000000000000000 VR0b:1e 0000000000000000
0100 ; 17f TR0b:1f 0000000000000000 VR0b:1f 0000000000000000
0100 ; 180 TR0c:00 0000000000000000 VR0c:00 0000000000000000
0100 ; 181 TR0c:01 0000000000000000 VR0c:01 0000000000000000
0100 ; 182 TR0c:02 0000000000000000 VR0c:02 0000000000000000
0100 ; 183 TR0c:03 0000000000000000 VR0c:03 0000000000000000
0100 ; 184 TR0c:04 0000000000000000 VR0c:04 0000000000000000
0100 ; 185 TR0c:05 0000000000000000 VR0c:05 0000000000000000
0100 ; 186 TR0c:06 0000000000000000 VR0c:06 0000000000000000
0100 ; 187 TR0c:07 0000000000000000 VR0c:07 0000000000000000
0100 ; 188 TR0c:08 0000000000000000 VR0c:08 0000000000000000
0100 ; 189 TR0c:09 0000000000000000 VR0c:09 0000000000000000
0100 ; 18a TR0c:0a 0000000000000000 VR0c:0a 0000000000000000
0100 ; 18b TR0c:0b 0000000000000000 VR0c:0b 0000000000000000
0100 ; 18c TR0c:0c 0000000000000000 VR0c:0c 0000000000000000
0100 ; 18d TR0c:0d 0000000000000000 VR0c:0d 0000000000000000
0100 ; 18e TR0c:0e 0000000000000000 VR0c:0e 0000000000000000
0100 ; 18f TR0c:0f 0000000000000000 VR0c:0f 0000000000000000
0100 ; 190 TR0c:10 0000000000000000 VR0c:10 0000000000000000
0100 ; 191 TR0c:11 0000000000000000 VR0c:11 0000000000000000
0100 ; 192 TR0c:12 0000000000000000 VR0c:12 0000000000000000
0100 ; 193 TR0c:13 0000000000000000 VR0c:13 0000000000000000
0100 ; 194 TR0c:14 0000000000000000 VR0c:14 0000000000000000
0100 ; 195 TR0c:15 0000000000000000 VR0c:15 0000000000000000
0100 ; 196 TR0c:16 0000000000000000 VR0c:16 0000000000000000
0100 ; 197 TR0c:17 0000000000000000 VR0c:17 0000000000000000
0100 ; 198 TR0c:18 0000000000000000 VR0c:18 0000000000000000
0100 ; 199 TR0c:19 0000000000000000 VR0c:19 0000000000000000
0100 ; 19a TR0c:1a 0000000000000000 VR0c:1a 0000000000000000
0100 ; 19b TR0c:1b 0000000000000000 VR0c:1b 0000000000000000
0100 ; 19c TR0c:1c 0000000000000000 VR0c:1c 0000000000000000
0100 ; 19d TR0c:1d 0000000000000000 VR0c:1d 0000000000000000
0100 ; 19e TR0c:1e 0000000000000000 VR0c:1e 0000000000000000
0100 ; 19f TR0c:1f 0000000000000000 VR0c:1f 0000000000000000
0100 ; 1a0 TR0d:00 0000000000000000 VR0d:00 0000000000000000
0100 ; 1a1 TR0d:01 0000000000000000 VR0d:01 0000000000000000
0100 ; 1a2 TR0d:02 0000000000000000 VR0d:02 0000000000000000
0100 ; 1a3 TR0d:03 0000000000000000 VR0d:03 0000000000000000
0100 ; 1a4 TR0d:04 0000000000000000 VR0d:04 0000000000000000
0100 ; 1a5 TR0d:05 0000000000000000 VR0d:05 0000000000000000
0100 ; 1a6 TR0d:06 0000000000000000 VR0d:06 0000000000000000
0100 ; 1a7 TR0d:07 0000000000000000 VR0d:07 0000000000000000
0100 ; 1a8 TR0d:08 0000000000000000 VR0d:08 0000000000000000
0100 ; 1a9 TR0d:09 0000000000000000 VR0d:09 0000000000000000
0100 ; 1aa TR0d:0a 0000000000000000 VR0d:0a 0000000000000000
0100 ; 1ab TR0d:0b 0000000000000000 VR0d:0b 0000000000000000
0100 ; 1ac TR0d:0c 0000000000000000 VR0d:0c 0000000000000000
0100 ; 1ad TR0d:0d 0000000000000000 VR0d:0d 0000000000000000
0100 ; 1ae TR0d:0e 0000000000000000 VR0d:0e 0000000000000000
0100 ; 1af TR0d:0f 0000000000000000 VR0d:0f 0000000000000000
0100 ; 1b0 TR0d:10 0000000000000000 VR0d:10 0000000000000000
0100 ; 1b1 TR0d:11 0000000000000000 VR0d:11 0000000000000000
0100 ; 1b2 TR0d:12 0000000000000000 VR0d:12 0000000000000000
0100 ; 1b3 TR0d:13 0000000000000000 VR0d:13 0000000000000000
0100 ; 1b4 TR0d:14 0000000000000000 VR0d:14 0000000000000000
0100 ; 1b5 TR0d:15 0000000000000000 VR0d:15 0000000000000000
0100 ; 1b6 TR0d:16 0000000000000000 VR0d:16 0000000000000000
0100 ; 1b7 TR0d:17 0000000000000000 VR0d:17 0000000000000000
0100 ; 1b8 TR0d:18 0000000000000000 VR0d:18 0000000000000000
0100 ; 1b9 TR0d:19 0000000000000000 VR0d:19 0000000000000000
0100 ; 1ba TR0d:1a 0000000000000000 VR0d:1a 0000000000000000
0100 ; 1bb TR0d:1b 0000000000000000 VR0d:1b 0000000000000000
0100 ; 1bc TR0d:1c 0000000000000000 VR0d:1c 0000000000000000
0100 ; 1bd TR0d:1d 0000000000000000 VR0d:1d 0000000000000000
0100 ; 1be TR0d:1e 0000000000000000 VR0d:1e 0000000000000000
0100 ; 1bf TR0d:1f 0000000000000000 VR0d:1f 0000000000000000
0100 ; 1c0 TR0e:00 0000000000000000 VR0e:00 0000000000000000
0100 ; 1c1 TR0e:01 0000000000000000 VR0e:01 0000000000000000
0100 ; 1c2 TR0e:02 0000000000000000 VR0e:02 0000000000000000
0100 ; 1c3 TR0e:03 0000000000000000 VR0e:03 0000000000000000
0100 ; 1c4 TR0e:04 0000000000000000 VR0e:04 0000000000000000
0100 ; 1c5 TR0e:05 0000000000000000 VR0e:05 0000000000000000
0100 ; 1c6 TR0e:06 0000000000000000 VR0e:06 0000000000000000
0100 ; 1c7 TR0e:07 0000000000000000 VR0e:07 0000000000000000
0100 ; 1c8 TR0e:08 0000000000000000 VR0e:08 0000000000000000
0100 ; 1c9 TR0e:09 0000000000000000 VR0e:09 0000000000000000
0100 ; 1ca TR0e:0a 0000000000000000 VR0e:0a 0000000000000000
0100 ; 1cb TR0e:0b 0000000000000000 VR0e:0b 0000000000000000
0100 ; 1cc TR0e:0c 0000000000000000 VR0e:0c 0000000000000000
0100 ; 1cd TR0e:0d 0000000000000000 VR0e:0d 0000000000000000
0100 ; 1ce TR0e:0e 0000000000000000 VR0e:0e 0000000000000000
0100 ; 1cf TR0e:0f 0000000000000000 VR0e:0f 0000000000000000
0100 ; 1d0 TR0e:10 0000000000000000 VR0e:10 0000000000000000
0100 ; 1d1 TR0e:11 0000000000000000 VR0e:11 0000000000000000
0100 ; 1d2 TR0e:12 0000000000000000 VR0e:12 0000000000000000
0100 ; 1d3 TR0e:13 0000000000000000 VR0e:13 0000000000000000
0100 ; 1d4 TR0e:14 0000000000000000 VR0e:14 0000000000000000
0100 ; 1d5 TR0e:15 0000000000000000 VR0e:15 0000000000000000
0100 ; 1d6 TR0e:16 0000000000000000 VR0e:16 0000000000000000
0100 ; 1d7 TR0e:17 0000000000000000 VR0e:17 0000000000000000
0100 ; 1d8 TR0e:18 0000000000000000 VR0e:18 0000000000000000
0100 ; 1d9 TR0e:19 0000000000000000 VR0e:19 0000000000000000
0100 ; 1da TR0e:1a 0000000000000000 VR0e:1a 0000000000000000
0100 ; 1db TR0e:1b 0000000000000000 VR0e:1b 0000000000000000
0100 ; 1dc TR0e:1c 0000000000000000 VR0e:1c 0000000000000000
0100 ; 1dd TR0e:1d 0000000000000000 VR0e:1d 0000000000000000
0100 ; 1de TR0e:1e 0000000000000000 VR0e:1e 0000000000000000
0100 ; 1df TR0e:1f 0000000000000000 VR0e:1f 0000000000000000
0100 ; 1e0 TR0f:00 0000000000000000 VR0f:00 0000000000000000
0100 ; 1e1 TR0f:01 0000000000000000 VR0f:01 0000000000000000
0100 ; 1e2 TR0f:02 0000000000000000 VR0f:02 0000000000000000
0100 ; 1e3 TR0f:03 0000000000000000 VR0f:03 0000000000000000
0100 ; 1e4 TR0f:04 0000000000000000 VR0f:04 0000000000000000
0100 ; 1e5 TR0f:05 0000000000000000 VR0f:05 0000000000000000
0100 ; 1e6 TR0f:06 0000000000000000 VR0f:06 0000000000000000
0100 ; 1e7 TR0f:07 0000000000000000 VR0f:07 0000000000000000
0100 ; 1e8 TR0f:08 0000000000000000 VR0f:08 0000000000000000
0100 ; 1e9 TR0f:09 0000000000000000 VR0f:09 0000000000000000
0100 ; 1ea TR0f:0a 0000000000000000 VR0f:0a 0000000000000000
0100 ; 1eb TR0f:0b 0000000000000000 VR0f:0b 0000000000000000
0100 ; 1ec TR0f:0c 0000000000000000 VR0f:0c 0000000000000000
0100 ; 1ed TR0f:0d 0000000000000000 VR0f:0d 0000000000000000
0100 ; 1ee TR0f:0e 0000000000000000 VR0f:0e 0000000000000000
0100 ; 1ef TR0f:0f 0000000000000000 VR0f:0f 0000000000000000
0100 ; 1f0 TR0f:10 0000000000000000 VR0f:10 0000000000000000
0100 ; 1f1 TR0f:11 0000000000000000 VR0f:11 0000000000000000
0100 ; 1f2 TR0f:12 0000000000000000 VR0f:12 0000000000000000
0100 ; 1f3 TR0f:13 0000000000000000 VR0f:13 0000000000000000
0100 ; 1f4 TR0f:14 0000000000000000 VR0f:14 0000000000000000
0100 ; 1f5 TR0f:15 0000000000000000 VR0f:15 0000000000000000
0100 ; 1f6 TR0f:16 0000000000000000 VR0f:16 0000000000000000
0100 ; 1f7 TR0f:17 0000000000000000 VR0f:17 0000000000000000
0100 ; 1f8 TR0f:18 0000000000000000 VR0f:18 0000000000000000
0100 ; 1f9 TR0f:19 0000000000000000 VR0f:19 0000000000000000
0100 ; 1fa TR0f:1a 0000000000000000 VR0f:1a 0000000000000000
0100 ; 1fb TR0f:1b 0000000000000000 VR0f:1b 0000000000000000
0100 ; 1fc TR0f:1c 0000000000000000 VR0f:1c 0000000000000000
0100 ; 1fd TR0f:1d 0000000000000000 VR0f:1d 0000000000000000
0100 ; 1fe TR0f:1e 0000000000000000 VR0f:1e 0000000000000000
0100 ; 1ff TR0f:1f 0000000000000000 VR0f:1f 0000000000000000
0100 ; 200 TR10:00 0000000000000000 VR10:00 0000000000000000
0100 ; 201 TR10:01 0000000000000001 VR10:01 0000000000000001
0100 ; 202 TR10:02 ffffffffffffffff VR10:02 ffffffffffffffff
0100 ; 203 TR10:03 7fffffffffffffff VR10:03 7fffffffffffffff
0100 ; 204 TR10:04 ffffffff00000000 VR10:04 fffffffffffffffe
0100 ; 205 TR10:05 00000000000003ff VR10:05 ffffffff00000000
0100 ; 206 TR10:06 fffffffffffffc00 VR10:06 ffffffffffff0000
0100 ; 207 TR10:07 8000000000000000 VR10:07 00000000ffff0000
0100 ; 208 TR10:08 000000000000003f VR10:08 00000000000003ff
0100 ; 209 TR10:09 000000000000ffff VR10:09 fffffffffffffc00
0100 ; 20a TR10:0a 00000000001f8000 VR10:0a 8000000000000000
0100 ; 20b TR10:0b 00000000081f8000 VR10:0b 000000000000003f
0100 ; 20c TR10:0c 000000000000007f VR10:0c 000000000000ffff
0100 ; 20d TR10:0d 800000000000007f VR10:0d 000000000000007f
0100 ; 20e TR10:0e ffffffffffffff7f VR10:0e ffffffffffffff80
0100 ; 20f TR10:0f ffffffffffffff80 VR10:0f ff00000000000000
0100 ; 210 TR10:10 0c00000000000000 VR10:10 fe00000000000000
0100 ; 211 TR10:11 0600000000000000 VR10:11 000000000000fff0
0100 ; 212 TR10:12 0500000000000000 VR10:12 0350035003510352
0100 ; 213 TR10:13 0000000000000500 VR10:13 00000000000003f1
0100 ; 214 TR10:14 fffffffff0000000 VR10:14 0000ffff00000000
0100 ; 215 TR10:15 ffffffffff9f8007 VR10:15 0000010000008000
0100 ; 216 TR10:16 ffffffffff9f8000 VR10:16 00000000000f0000
0100 ; 217 TR10:17 0000000000002710 VR10:17 ffffffffffc00000
0100 ; 218 TR10:18 0340034003400340 VR10:18 ffffffffffff0000
0100 ; 219 TR10:19 01ff000000000000 VR10:19 ffffffff0000ffff
0100 ; 21a TR10:1a 0fff000000000000 VR10:1a ffff0000ffffffff
0100 ; 21b TR10:1b 000000000000006c VR10:1b 0000ffffffffffff
0100 ; 21c TR10:1c 0000000000000074 VR10:1c 00000000000000ff
0100 ; 21d TR10:1d 0000000000000038 VR10:1d 000000000000ff00
0100 ; 21e TR10:1e 0000000000000028 VR10:1e 0000000000ff0000
0100 ; 21f TR10:1f 0000000000000010 VR10:1f ffff000000000000
0100 ; 220 TR11:00 5a5a5a5a5a5a5a5a VR11:00 5a5a5a5a5a5a5a5a
0100 ; 221 TR11:01 a5a5a5a5a5a5a5a5 VR11:01 a5a5a5a5a5a5a5a5
0100 ; 222 TR11:02 36c936c936c936c9 VR11:02 36c936c936c936c9
0100 ; 223 TR11:03 6c936c936c936c93 VR11:03 6c936c936c936c93
0100 ; 224 TR11:04 c936c936c936c936 VR11:04 c936c936c936c936
0100 ; 225 TR11:05 936c936c936c936c VR11:05 936c936c936c936c
0100 ; 226 TR11:06 1248124812481248 VR11:06 1248124812481248
0100 ; 227 TR11:07 2481248124812481 VR11:07 2481248124812481
0100 ; 228 TR11:08 4812481248124812 VR11:08 4812481248124812
0100 ; 229 TR11:09 8124812481248124 VR11:09 8124812481248124
0100 ; 22a TR11:0a 7edb7edb7edb7edb VR11:0a 7edb7edb7edb7edb
0100 ; 22b TR11:0b edb7edb7edb7edb7 VR11:0b edb7edb7edb7edb7
0100 ; 22c TR11:0c db7edb7edb7edb7e VR11:0c db7edb7edb7edb7e
0100 ; 22d TR11:0d b7edb7edb7edb7ed VR11:0d b7edb7edb7edb7ed
0100 ; 22e TR11:0e 5a5a5a5a5a5a5a5b VR11:0e 5a5a5a5a5a5a5a5b
0100 ; 22f TR11:0f a5a5a5a5a5a5a5a6 VR11:0f a5a5a5a5a5a5a5a6
0100 ; 230 TR11:10 36c936c936c936ca VR11:10 36c936c936c936ca
0100 ; 231 TR11:11 6c936c936c936c94 VR11:11 6c936c936c936c94
0100 ; 232 TR11:12 c936c936c936c937 VR11:12 c936c936c936c937
0100 ; 233 TR11:13 936c936c936c936d VR11:13 936c936c936c936d
0100 ; 234 TR11:14 5a5a5a5a5a5a5a59 VR11:14 5a5a5a5a5a5a5a59
0100 ; 235 TR11:15 a5a5a5a5a5a5a5a4 VR11:15 a5a5a5a5a5a5a5a4
0100 ; 236 TR11:16 36c936c936c936c8 VR11:16 36c936c936c936c8
0100 ; 237 TR11:17 6c936c936c936c92 VR11:17 6c936c936c936c92
0100 ; 238 TR11:18 c936c936c936c935 VR11:18 c936c936c936c935
0100 ; 239 TR11:19 936c936c936c936b VR11:19 936c936c936c936b
0100 ; 23a TR11:1a 1239123912391239 VR11:1a 1239123912391239
0100 ; 23b TR11:1b 2391239123912391 VR11:1b 2391239123912391
0100 ; 23c TR11:1c 3912391239123912 VR11:1c 3912391239123912
0100 ; 23d TR11:1d 9123912391239123 VR11:1d 9123912391239123
0100 ; 23e TR11:1e 1239123912391238 VR11:1e 1239123912391238
0100 ; 23f TR11:1f 2391239123912390 VR11:1f 2391239123912390
0100 ; 240 TR12:00 3912391239123911 VR12:00 3912391239123911
0100 ; 241 TR12:01 9123912391239124 VR12:01 9123912391239124
0100 ; 242 TR12:02 6edc6edc6edc6edc VR12:02 6edc6edc6edc6edc
0100 ; 243 TR12:03 edc6edc6edc6edc6 VR12:03 edc6edc6edc6edc6
0100 ; 244 TR12:04 dc6edc6edc6edc6e VR12:04 dc6edc6edc6edc6e
0100 ; 245 TR12:05 c6edc6edc6edc6ed VR12:05 c6edc6edc6edc6ed
0100 ; 246 TR12:06 6edc6edc6edc6edb VR12:06 6edc6edc6edc6edb
0100 ; 247 TR12:07 edc6edc6edc6edc7 VR12:07 edc6edc6edc6edc7
0100 ; 248 TR12:08 dc6edc6edc6edc6f VR12:08 dc6edc6edc6edc6f
0100 ; 249 TR12:09 c6edc6edc6edc6ee VR12:09 c6edc6edc6edc6ee
0100 ; 24a TR12:0a b4b4b4b4b4b4b4b4 VR12:0a b4b4b4b4b4b4b4b4
0100 ; 24b TR12:0b b4b4b4b4b4b4b4b5 VR12:0b b4b4b4b4b4b4b4b5
0100 ; 24c TR12:0c 4b4b4b4b4b4b4b4a VR12:0c 4b4b4b4b4b4b4b4a
0100 ; 24d TR12:0d 4b4b4b4b4b4b4b4b VR12:0d 4b4b4b4b4b4b4b4b
0100 ; 24e TR12:0e 6d926d926d926d92 VR12:0e 6d926d926d926d92
0100 ; 24f TR12:0f 6d926d926d926d93 VR12:0f 6d926d926d926d93
0100 ; 250 TR12:10 d926d926d926d926 VR12:10 d926d926d926d926
0100 ; 251 TR12:11 d926d926d926d927 VR12:11 d926d926d926d927
0100 ; 252 TR12:12 926d926d926d926c VR12:12 926d926d926d926c
0100 ; 253 TR12:13 926d926d926d926d VR12:13 926d926d926d926d
0100 ; 254 TR12:14 26d926d926d926d8 VR12:14 26d926d926d926d8
0100 ; 255 TR12:15 26d926d926d926d9 VR12:15 26d926d926d926d9
0100 ; 256 TR12:16 36c936c900000000 VR12:16 36c936c900000000
0100 ; 257 TR12:17 36c936c9ffffffff VR12:17 36c936c9ffffffff
0100 ; 258 TR12:18 36c936c95a5a5a5a VR12:18 36c936c95a5a5a5a
0100 ; 259 TR12:19 36c936c9c936c936 VR12:19 36c936c9c936c936
0100 ; 25a TR12:1a 36c936c9a5a5a5a5 VR12:1a 36c936c9a5a5a5a5
0100 ; 25b TR12:1b 36c936c912481248 VR12:1b 36c936c912481248
0100 ; 25c TR12:1c 36c936c97edb7edb VR12:1c 36c936c97edb7edb
0100 ; 25d TR12:1d 36c936c96c936c93 VR12:1d 36c936c96c936c93
0100 ; 25e TR12:1e 36c936c9edb7edb7 VR12:1e 36c936c9edb7edb7
0100 ; 25f TR12:1f 36c936c981248124 VR12:1f 36c936c981248124
0100 ; 260 TR13:00 36c936c9936c936c VR13:00 36c936c9936c936c
0100 ; 261 TR13:01 36c936c948124812 VR13:01 36c936c948124812
0100 ; 262 TR13:02 36c936c924812481 VR13:02 36c936c924812481
0100 ; 263 TR13:03 36c936c9db7edb7e VR13:03 36c936c9db7edb7e
0100 ; 264 TR13:04 36c936c9b7edb7ed VR13:04 36c936c9b7edb7ed
0100 ; 265 TR13:05 00000000ffffffff VR13:05 00000000ffffffff
0100 ; 266 TR13:06 36c936c96d926d92 VR13:06 36c936c96d926d92
0100 ; 267 TR13:07 36c936c96d926d93 VR13:07 36c936c96d926d93
0100 ; 268 TR13:08 36c936c991239123 VR13:08 36c936c991239123
0100 ; 269 TR13:09 36c936c991239124 VR13:09 36c936c991239124
0100 ; 26a TR13:0a 36c936c9dc6edc6f VR13:0a 36c936c9dc6edc6f
0100 ; 26b TR13:0b 36c936c9dc6edc6e VR13:0b 36c936c9dc6edc6e
0100 ; 26c TR13:0c 5a5a5a5a00000000 VR13:0c 5a5a5a5a00000000
0100 ; 26d TR13:0d 5a5a5a5affffffff VR13:0d 5a5a5a5affffffff
0100 ; 26e TR13:0e 5a5a5a5a36c936c9 VR13:0e 5a5a5a5a36c936c9
0100 ; 26f TR13:0f 5a5a5a5ac936c936 VR13:0f 5a5a5a5ac936c936
0100 ; 270 TR13:10 5a5a5a5aa5a5a5a5 VR13:10 5a5a5a5aa5a5a5a5
0100 ; 271 TR13:11 5a5a5a5a12481248 VR13:11 5a5a5a5a12481248
0100 ; 272 TR13:12 5a5a5a5a7edb7edb VR13:12 5a5a5a5a7edb7edb
0100 ; 273 TR13:13 5a5a5a5a6c936c93 VR13:13 5a5a5a5a6c936c93
0100 ; 274 TR13:14 5a5a5a5aedb7edb7 VR13:14 5a5a5a5aedb7edb7
0100 ; 275 TR13:15 5a5a5a5a81248124 VR13:15 5a5a5a5a81248124
0100 ; 276 TR13:16 5a5a5a5a936c936c VR13:16 5a5a5a5a936c936c
0100 ; 277 TR13:17 5a5a5a5a48124812 VR13:17 5a5a5a5a48124812
0100 ; 278 TR13:18 5a5a5a5a24812481 VR13:18 5a5a5a5a24812481
0100 ; 279 TR13:19 5a5a5a5adb7edb7e VR13:19 5a5a5a5adb7edb7e
0100 ; 27a TR13:1a 5a5a5a5ab7edb7ed VR13:1a 5a5a5a5ab7edb7ed
0100 ; 27b TR13:1b 5a5a5a5a6d926d92 VR13:1b 5a5a5a5a6d926d92
0100 ; 27c TR13:1c 5a5a5a5a6d926d93 VR13:1c 5a5a5a5a6d926d93
0100 ; 27d TR13:1d 5a5a5a5a91239123 VR13:1d 5a5a5a5a91239123
0100 ; 27e TR13:1e 5a5a5a5a91239124 VR13:1e 5a5a5a5a91239124
0100 ; 27f TR13:1f 5a5a5a5adc6edc6f VR13:1f 5a5a5a5adc6edc6f
0100 ; 280 TR14:00 5a5a5a5adc6edc6e VR14:00 5a5a5a5adc6edc6e
0100 ; 281 TR14:01 5a5a5a5a36c936ca VR14:01 5a5a5a5a36c936ca
0100 ; 282 TR14:02 5a5a5a5a36c936c8 VR14:02 5a5a5a5a36c936c8
0100 ; 283 TR14:03 a5a5a5a536c936c9 VR14:03 0000ffffffffffff
0100 ; 284 TR14:04 6c936c935a5a5a5a VR14:04 00005a5a5a5a5a5a
0100 ; 285 TR14:05 c936c9365a5a5a5a VR14:05 0000a5a5a5a5a5a5
0100 ; 286 TR14:06 936c936c5a5a5a5a VR14:06 000036c936c936c9
0100 ; 287 TR14:07 0000000007ffff80 VR14:07 00006c936c936c93
0100 ; 288 TR14:08 000000000000000f VR14:08 0000c936c936c936
0100 ; 289 TR14:09 ffffffff07ffff80 VR14:09 0000936c936c936c
0100 ; 28a TR14:0a 0000000000000007 VR14:0a 000000000000fe02
0100 ; 28b TR14:0b f0f0f0f000000000 VR14:0b 0000000000008101
0100 ; 28c TR14:0c d000d000d000d000 VR14:0c 0000000080000002
0100 ; 28d TR14:0d 0fff0fff0fff0fff VR14:0d 0000800000020000
0100 ; 28e TR14:0e 0000000000000780 VR14:0e 8000000200000000
0100 ; 28f TR14:0f e001e201e401e601 VR14:0f 36c96c93c936936c
0100 ; 290 TR14:10 4000400040004000 VR14:10 5a5aa5a55a5aa5a5
0100 ; 291 TR14:11 000000000000003b VR14:11 5a5aa5a5a5a55a5a
0100 ; 292 TR14:12 0000000000000003 VR14:12 000000001355ecaa
0100 ; 293 TR14:13 0000000000000006 VR14:13 000000002372dc8d
0100 ; 294 TR14:14 000000000000000c VR14:14 000000002651d9ae
0100 ; 295 TR14:15 0000000000000018 VR14:15 000000003407cbf8
0100 ; 296 TR14:16 0000000000000030 VR14:16 000000004640b9bf
0100 ; 297 TR14:17 0000000000000044 VR14:17 000000004703b8fc
0100 ; 298 TR14:18 0000000000000060 VR14:18 000000005f63a09c
0100 ; 299 TR14:19 0000000000000064 VR14:19 0000000082317dce
0100 ; 29a TR14:1a fffffffffff80000 VR14:1a 00000000fffe0001
0100 ; 29b TR14:1b 0000000000000014 VR14:1b a5a5a5a536c936c9
0100 ; 29c TR14:1c 000000000000003e VR14:1c 6c936c935a5a5a5a
0100 ; 29d TR14:1d 00000000f0000000 VR14:1d c936c9365a5a5a5a
0100 ; 29e TR14:1e 00000000f7800000 VR14:1e 936c936c5a5a5a5a
0100 ; 29f TR14:1f 0000000004000000 VR14:1f 0000000000000000
0100 ; 2a0 TR15:00 0000000000000000 VR15:00 0000000000000000
0100 ; 2a1 TR15:01 0000000000000000 VR15:01 000000000000000f
0100 ; 2a2 TR15:02 0000000000000000 VR15:02 000000000007fff0
0100 ; 2a3 TR15:03 0000000000000000 VR15:03 00ffffff00000000
0100 ; 2a4 TR15:04 0000000000000000 VR15:04 0000000000000070
0100 ; 2a5 TR15:05 0000000000000000 VR15:05 e801ea01ec01ee01
0100 ; 2a6 TR15:06 0000000000000000 VR15:06 d000d000d000d000
0100 ; 2a7 TR15:07 0000000000000000 VR15:07 0fff0fff0fff0fff
0100 ; 2a8 TR15:08 0000000000000000 VR15:08 4000400040004000
0100 ; 2a9 TR15:09 0000000000000000 VR15:09 0000000000000013
0100 ; 2aa TR15:0a 0000000000000000 VR15:0a 0000000000000018
0100 ; 2ab TR15:0b 0000000000000000 VR15:0b 00ffffff0007ffff
0100 ; 2ac TR15:0c 0000000000000000 VR15:0c ffffffffefffffff
0100 ; 2ad TR15:0d 0000000000000000 VR15:0d 000000000000000a
0100 ; 2ae TR15:0e 0000000000000000 VR15:0e 000000000007c000
0100 ; 2af TR15:0f 0000000000000000 VR15:0f 0000000000000044
0100 ; 2b0 TR15:10 0000000000000000 VR15:10 0010000000000100
0100 ; 2b1 TR15:11 0000000000000000 VR15:11 0001ffff00000000
0100 ; 2b2 TR15:12 0000000000000000 VR15:12 0000003300000000
0100 ; 2b3 TR15:13 0000000000000000 VR15:13 0000000300000000
0100 ; 2b4 TR15:14 0000000000000000 VR15:14 ffffffffffffe0ff
0100 ; 2b5 TR15:15 0000000000000000 VR15:15 0000000000000f80
0100 ; 2b6 TR15:16 0000000000000000 VR15:16 000000000000001d
0100 ; 2b7 TR15:17 0000000000000000 VR15:17 000000000000001e
0100 ; 2b8 TR15:18 0000000000000000 VR15:18 000000000000001f
0100 ; 2b9 TR15:19 0000000000000000 VR15:19 ffffffffffffff00
0100 ; 2ba TR15:1a 0000000000000000 VR15:1a 0014001500160017
0100 ; 2bb TR15:1b 0000000000000000 VR15:1b 0000000000000000
0100 ; 2bc TR15:1c 0000000000000000 VR15:1c 0000000000000003
0100 ; 2bd TR15:1d 0000000000000000 VR15:1d 0000000000000005
0100 ; 2be TR15:1e 0000000000000000 VR15:1e 0000000000000006
0100 ; 2bf TR15:1f 0000000000000000 VR15:1f 0000000000000007
0100 ; 2c0 TR16:00 000000000000001d VR16:00 0000000000000000
0100 ; 2c1 TR16:01 ffffffff7fffffff VR16:01 0000000000000360
0100 ; 2c2 TR16:02 ffffffffbfffffff VR16:02 000000000000039f
0100 ; 2c3 TR16:03 ffffffffdfffffff VR16:03 000000001fffffff
0100 ; 2c4 TR16:04 ffffffffefffffff VR16:04 111111111fffffff
0100 ; 2c5 TR16:05 fffffffff7ffffff VR16:05 0000000000000000
0100 ; 2c6 TR16:06 0000000060000000 VR16:06 fffffff100000000
0100 ; 2c7 TR16:07 0000000048000000 VR16:07 fffffff111111111
0100 ; 2c8 TR16:08 0000000028000000 VR16:08 1111111111111111
0100 ; 2c9 TR16:09 000000000007ffff VR16:09 0000000100000005
0100 ; 2ca TR16:0a 0000000000000005 VR16:0a 000000007ffeffff
0100 ; 2cb TR16:0b 0000000000000016 VR16:0b 000000000000000d
0100 ; 2cc TR16:0c 0000000000000024 VR16:0c 0000000000000032
0100 ; 2cd TR16:0d 000000000000000d VR16:0d 0000000000000064
0100 ; 2ce TR16:0e 000000000000000e VR16:0e 0300030003000300
0100 ; 2cf TR16:0f 0000000000000015 VR16:0f 0310031003100310
0100 ; 2d0 TR16:10 000000000000005f VR16:10 0320032003200320
0100 ; 2d1 TR16:11 000000000000006f VR16:11 0330033003300330
0100 ; 2d2 TR16:12 0000000000000077 VR16:12 ffffffff07ffffff
0100 ; 2d3 TR16:13 000000000000007a VR16:13 ffffffff07ffff80
0100 ; 2d4 TR16:14 000000000000007b VR16:14 00000000000001ff
0100 ; 2d5 TR16:15 000000000000007d VR16:15 0000001fffffe000
0100 ; 2d6 TR16:16 000000000000007e VR16:16 fffc000000002000
0100 ; 2d7 TR16:17 000000000000001e VR16:17 ffffc00000010000
0100 ; 2d8 TR16:18 000000000000002e VR16:18 ffffffffffffe040
0100 ; 2d9 TR16:19 0000000000000013 VR16:19 000000f000000000
0100 ; 2da TR16:1a 000000000000001f VR16:1a 0340034003400340
0100 ; 2db TR16:1b 00000000000fc000 VR16:1b 0000000000000fff
0100 ; 2dc TR16:1c 0000003c60000000 VR16:1c 000000000000000b
0100 ; 2dd TR16:1d fffffbffffffffff VR16:1d 0000000000000009
0100 ; 2de TR16:1e 0350035003500350 VR16:1e 00000000ffffff80
0100 ; 2df TR16:1f 00000000000003f1 VR16:1f 000000000006ffa0
0100 ; 2e0 TR17:00 0010001100120013 VR17:00 00000000000003f0
0100 ; 2e1 TR17:01 0020002100220023 VR17:01 00000000000003fe
0100 ; 2e2 TR17:02 8000820084008600 VR17:02 0000000000001f80
0100 ; 2e3 TR17:03 a000a200a400a600 VR17:03 000000000000003e
0100 ; 2e4 TR17:04 000000000000039f VR17:04 000000000001f800
0100 ; 2e5 TR17:05 00000000000003df VR17:05 0001ff0000000000
0100 ; 2e6 TR17:06 0000000000000005 VR17:06 000000000001e041
0100 ; 2e7 TR17:07 000000001fffffff VR17:07 000000000001e000
0100 ; 2e8 TR17:08 111111111fffffff VR17:08 000000000000000e
0100 ; 2e9 TR17:09 0000000100000001 VR17:09 0000000000000019
0100 ; 2ea TR17:0a fffffff100000000 VR17:0a 0000000000000012
0100 ; 2eb TR17:0b fffffff111111111 VR17:0b 00ffff0000000000
0100 ; 2ec TR17:0c 1111111111111111 VR17:0c 000000000000003d
0100 ; 2ed TR17:0d 0000000000000000 VR17:0d 000000000000000c
0100 ; 2ee TR17:0e 0000000100000005 VR17:0e 0000000000000020
0100 ; 2ef TR17:0f 0100010101020000 VR17:0f 0000000000002000
0100 ; 2f0 TR17:10 0010001000100000 VR17:10 ffffffffffc02080
0100 ; 2f1 TR17:11 8f8f000000000000 VR17:11 0000001fffc02000
0100 ; 2f2 TR17:12 4f4f000000000000 VR17:12 0000001fffc00000
0100 ; 2f3 TR17:13 fc00000000000000 VR17:13 0007ff000000a000
0100 ; 2f4 TR17:14 fd00000000000000 VR17:14 0000020000002000
0100 ; 2f5 TR17:15 fe00000000000000 VR17:15 0000000000000000
0100 ; 2f6 TR17:16 ffff000000000000 VR17:16 0000000000000005
0100 ; 2f7 TR17:17 0300030003000300 VR17:17 0000000100000001
0100 ; 2f8 TR17:18 0310031003100310 VR17:18 00000000000007ff
0100 ; 2f9 TR17:19 0320032003200320 VR17:19 ffffffffff002080
0100 ; 2fa TR17:1a 0330033003300330 VR17:1a 0000000000000043
0100 ; 2fb TR17:1b 00000000000003f0 VR17:1b 0000200000000043
0100 ; 2fc TR17:1c 00000000000003fe VR17:1c 0000001fff000000
0100 ; 2fd TR17:1d ffffffffffffe07f VR17:1d 0000001fff002000
0100 ; 2fe TR17:1e 0000000000000e00 VR17:1e 0101010101010101
0100 ; 2ff TR17:1f 0000000000000000 VR17:1f ffffffffff000000
0100 ; 300 TR18:00 000000000e000000 VR18:00 ffffffffffffe007
0100 ; 301 TR18:01 000000001e000000 VR18:01 ffffffff00001fff
0100 ; 302 TR18:02 0000000006000000 VR18:02 00000000000001e0
0100 ; 303 TR18:03 0000000000000000 VR18:03 000000000000104c
0100 ; 304 TR18:04 0000000000000000 VR18:04 0000000000000004
0100 ; 305 TR18:05 0000000000000000 VR18:05 0000000000000008
0100 ; 306 TR18:06 0000000000000000 VR18:06 000ffcf00000a000
0100 ; 307 TR18:07 0000000000000000 VR18:07 000fff000000a000
0100 ; 308 TR18:08 0000000000000000 VR18:08 0000003000000000
0100 ; 309 TR18:09 0000000000000000 VR18:09 0000000002000100
0100 ; 30a TR18:0a 0000000000000000 VR18:0a 000000002000104c
0100 ; 30b TR18:0b 0000000000000000 VR18:0b 0000000000000f00
0100 ; 30c TR18:0c 0000000000000000 VR18:0c 0000000022000000
0100 ; 30d TR18:0d 0000000000000000 VR18:0d 000000002200104c
0100 ; 30e TR18:0e 0000000000000000 VR18:0e 000000000200104c
0100 ; 30f TR18:0f 0000000000000000 VR18:0f 0000000000000000
0100 ; 310 TR18:10 0000000000000000 VR18:10 0000000000000000
0100 ; 311 TR18:11 0000000000000000 VR18:11 0000000000000000
0100 ; 312 TR18:12 0000000000000000 VR18:12 0000000000000000
0100 ; 313 TR18:13 0000000000000000 VR18:13 0000000000000000
0100 ; 314 TR18:14 0000000000000000 VR18:14 0000000000000000
0100 ; 315 TR18:15 0000000000000000 VR18:15 0000000000000000
0100 ; 316 TR18:16 0000000000000000 VR18:16 0000000000000000
0100 ; 317 TR18:17 0000000000000000 VR18:17 0000000000000000
0100 ; 318 TR18:18 0000000000000000 VR18:18 0000000000000000
0100 ; 319 TR18:19 0000000000000000 VR18:19 0000000000000000
0100 ; 31a TR18:1a 0000000000000000 VR18:1a 0000000000000000
0100 ; 31b TR18:1b 0000000000000000 VR18:1b 0000000000000000
0100 ; 31c TR18:1c 0000000000000000 VR18:1c 0000000000000000
0100 ; 31d TR18:1d 0000000000000000 VR18:1d 0000000000000000
0100 ; 31e TR18:1e 0000000000000000 VR18:1e 0000000000000000
0100 ; 31f TR18:1f 0000000000000000 VR18:1f 0000000000000000
0100 ; 320 TR19:00 0000000000000001 VR19:00 0000000000000000
0100 ; 321 TR19:01 0000000000000000 VR19:01 0000000000000000
0100 ; 322 TR19:02 0000000000000000 VR19:02 0000000000000000
0100 ; 323 TR19:03 0000000000000000 VR19:03 0000000000000000
0100 ; 324 TR19:04 0000000000000000 VR19:04 0000000000000000
0100 ; 325 TR19:05 0000000000000000 VR19:05 0000000000000000
0100 ; 326 TR19:06 0000000000000000 VR19:06 0000000000000000
0100 ; 327 TR19:07 0000000000000000 VR19:07 0000000000000000
0100 ; 328 TR19:08 0000000000000000 VR19:08 0000000000000000
0100 ; 329 TR19:09 0000000000000000 VR19:09 0000000000000000
0100 ; 32a TR19:0a 0000000000000000 VR19:0a 0000000000000000
0100 ; 32b TR19:0b 0000000000000000 VR19:0b 0000000000000000
0100 ; 32c TR19:0c 0000000000000000 VR19:0c 0000000000000000
0100 ; 32d TR19:0d 0000000000000000 VR19:0d 0000000000000000
0100 ; 32e TR19:0e 0000000000000000 VR19:0e 0000000000000000
0100 ; 32f TR19:0f 0000000000000000 VR19:0f 0000000000000000
0100 ; 330 TR19:10 0000000000000000 VR19:10 0000000000000000
0100 ; 331 TR19:11 0000000000000000 VR19:11 0000000000000000
0100 ; 332 TR19:12 0000000000000000 VR19:12 0000000000000000
0100 ; 333 TR19:13 0000000000000000 VR19:13 0000000000000000
0100 ; 334 TR19:14 0000000000000000 VR19:14 0000000000000000
0100 ; 335 TR19:15 0000000000000000 VR19:15 0000000000000000
0100 ; 336 TR19:16 0000000000000000 VR19:16 0000000000000000
0100 ; 337 TR19:17 0000000000000000 VR19:17 0000000000000000
0100 ; 338 TR19:18 0000000000000000 VR19:18 0000000000000000
0100 ; 339 TR19:19 0000000000000000 VR19:19 0000000000000000
0100 ; 33a TR19:1a 0000000000000000 VR19:1a 0000000000000000
0100 ; 33b TR19:1b 0000000000000000 VR19:1b 0000000000000000
0100 ; 33c TR19:1c 0000000000000000 VR19:1c 0000000000000000
0100 ; 33d TR19:1d 0000000000000000 VR19:1d 0000000000000000
0100 ; 33e TR19:1e 0000000000000000 VR19:1e 0000000000000000
0100 ; 33f TR19:1f 0000000000000000 VR19:1f 0000000000000000
0100 ; 340 TR1a:00 0000000000000000 VR1a:00 0000000000000000
0100 ; 341 TR1a:01 0000000000000000 VR1a:01 0000000000000000
0100 ; 342 TR1a:02 0000000000000000 VR1a:02 0000000000000000
0100 ; 343 TR1a:03 0000000000000000 VR1a:03 0000000000000000
0100 ; 344 TR1a:04 0000000000000000 VR1a:04 0000000000000000
0100 ; 345 TR1a:05 0000000000000000 VR1a:05 0000000000000000
0100 ; 346 TR1a:06 0000000000000000 VR1a:06 0000000000000000
0100 ; 347 TR1a:07 0000000000000000 VR1a:07 0000000000000000
0100 ; 348 TR1a:08 0000000000000000 VR1a:08 0000000000000000
0100 ; 349 TR1a:09 0000000000000000 VR1a:09 0000000000000000
0100 ; 34a TR1a:0a 0000000000000000 VR1a:0a 0000000000000000
0100 ; 34b TR1a:0b 0000000000000000 VR1a:0b 0000000000000000
0100 ; 34c TR1a:0c 0000000000000000 VR1a:0c 0000000000000000
0100 ; 34d TR1a:0d 0000000000000000 VR1a:0d 0000000000000000
0100 ; 34e TR1a:0e 0000000000000000 VR1a:0e 0000000000000000
0100 ; 34f TR1a:0f 0000000000000000 VR1a:0f 0000000000000000
0100 ; 350 TR1a:10 0000000000000000 VR1a:10 0000000000000000
0100 ; 351 TR1a:11 0000000000000000 VR1a:11 0000000000000000
0100 ; 352 TR1a:12 0000000000000000 VR1a:12 0000000000000000
0100 ; 353 TR1a:13 0000000000000000 VR1a:13 0000000000000000
0100 ; 354 TR1a:14 0000000000000000 VR1a:14 0000000000000000
0100 ; 355 TR1a:15 0000000000000000 VR1a:15 0000000000000000
0100 ; 356 TR1a:16 0000000000000000 VR1a:16 0000000000000000
0100 ; 357 TR1a:17 0000000000000000 VR1a:17 0000000000000000
0100 ; 358 TR1a:18 0000000000000000 VR1a:18 0000000000000000
0100 ; 359 TR1a:19 0000000000000000 VR1a:19 0000000000000000
0100 ; 35a TR1a:1a 0000000000000000 VR1a:1a 0000000000000000
0100 ; 35b TR1a:1b 0000000000000000 VR1a:1b 0000000000000000
0100 ; 35c TR1a:1c 0000000000000000 VR1a:1c 0000000000000000
0100 ; 35d TR1a:1d 0000000000000000 VR1a:1d 0000000000000000
0100 ; 35e TR1a:1e 0000000000000000 VR1a:1e 0000000000000000
0100 ; 35f TR1a:1f 0000000000000000 VR1a:1f 0000000000000000
0100 ; 360 TR1b:00 0000000000000000 VR1b:00 0000000000000001
0100 ; 361 TR1b:01 0000000000000000 VR1b:01 0000000000000003
0100 ; 362 TR1b:02 0000000000000000 VR1b:02 0000000000000007
0100 ; 363 TR1b:03 0000000000000000 VR1b:03 000000000000000f
0100 ; 364 TR1b:04 0000000000000000 VR1b:04 000000000000001f
0100 ; 365 TR1b:05 0000000000000000 VR1b:05 000000000000003f
0100 ; 366 TR1b:06 0000000000000000 VR1b:06 000000000000007f
0100 ; 367 TR1b:07 0000000000000000 VR1b:07 00000000000000ff
0100 ; 368 TR1b:08 0000000000000000 VR1b:08 00000000000001ff
0100 ; 369 TR1b:09 0000000000000000 VR1b:09 00000000000003ff
0100 ; 36a TR1b:0a 0000000000000000 VR1b:0a 00000000000007ff
0100 ; 36b TR1b:0b 0000000000000000 VR1b:0b 0000000000000fff
0100 ; 36c TR1b:0c 0000000000000000 VR1b:0c 0000000000001fff
0100 ; 36d TR1b:0d 0000000000000000 VR1b:0d 0000000000003fff
0100 ; 36e TR1b:0e 0000000000000000 VR1b:0e 0000000000007fff
0100 ; 36f TR1b:0f 0000000000000000 VR1b:0f 000000000000ffff
0100 ; 370 TR1b:10 0000000000000000 VR1b:10 000000000001ffff
0100 ; 371 TR1b:11 0000000000000000 VR1b:11 000000000003ffff
0100 ; 372 TR1b:12 0000000000000000 VR1b:12 000000000007ffff
0100 ; 373 TR1b:13 0000000000000000 VR1b:13 00000000000fffff
0100 ; 374 TR1b:14 0000000000000000 VR1b:14 00000000001fffff
0100 ; 375 TR1b:15 0000000000000000 VR1b:15 00000000003fffff
0100 ; 376 TR1b:16 0000000000000000 VR1b:16 00000000007fffff
0100 ; 377 TR1b:17 0000000000000000 VR1b:17 0000000000ffffff
0100 ; 378 TR1b:18 0000000000000000 VR1b:18 0000000001ffffff
0100 ; 379 TR1b:19 0000000000000000 VR1b:19 0000000003ffffff
0100 ; 37a TR1b:1a 0000000000000000 VR1b:1a 0000000007ffffff
0100 ; 37b TR1b:1b 0000000000000000 VR1b:1b 000000000fffffff
0100 ; 37c TR1b:1c 0000000000000000 VR1b:1c 000000001fffffff
0100 ; 37d TR1b:1d 0000000000000000 VR1b:1d 000000003fffffff
0100 ; 37e TR1b:1e 0000000000000000 VR1b:1e 000000007fffffff
0100 ; 37f TR1b:1f 0000000000000000 VR1b:1f 00000000ffffffff
0100 ; 380 TR1c:00 0000000000000000 VR1c:00 00000001ffffffff
0100 ; 381 TR1c:01 0000000000000000 VR1c:01 00000003ffffffff
0100 ; 382 TR1c:02 0000000000000000 VR1c:02 00000007ffffffff
0100 ; 383 TR1c:03 0000000000000000 VR1c:03 0000000fffffffff
0100 ; 384 TR1c:04 0000000000000000 VR1c:04 0000001fffffffff
0100 ; 385 TR1c:05 0000000000000000 VR1c:05 0000003fffffffff
0100 ; 386 TR1c:06 0000000000000000 VR1c:06 0000007fffffffff
0100 ; 387 TR1c:07 0000000000000000 VR1c:07 000000ffffffffff
0100 ; 388 TR1c:08 0000000000000000 VR1c:08 000001ffffffffff
0100 ; 389 TR1c:09 0000000000000000 VR1c:09 000003ffffffffff
0100 ; 38a TR1c:0a 0000000000000000 VR1c:0a 000007ffffffffff
0100 ; 38b TR1c:0b 0000000000000000 VR1c:0b 00000fffffffffff
0100 ; 38c TR1c:0c 0000000000000000 VR1c:0c 00001fffffffffff
0100 ; 38d TR1c:0d 0000000000000000 VR1c:0d 00003fffffffffff
0100 ; 38e TR1c:0e 0000000000000000 VR1c:0e 00007fffffffffff
0100 ; 38f TR1c:0f 0000000000000000 VR1c:0f 0000ffffffffffff
0100 ; 390 TR1c:10 0000000000000000 VR1c:10 0001ffffffffffff
0100 ; 391 TR1c:11 0000000000000000 VR1c:11 0003ffffffffffff
0100 ; 392 TR1c:12 0000000000000000 VR1c:12 0007ffffffffffff
0100 ; 393 TR1c:13 0000000000000000 VR1c:13 000fffffffffffff
0100 ; 394 TR1c:14 0000000000000000 VR1c:14 001fffffffffffff
0100 ; 395 TR1c:15 0000000000000000 VR1c:15 003fffffffffffff
0100 ; 396 TR1c:16 0000000000000000 VR1c:16 007fffffffffffff
0100 ; 397 TR1c:17 0000000000000000 VR1c:17 00ffffffffffffff
0100 ; 398 TR1c:18 0000000000000000 VR1c:18 01ffffffffffffff
0100 ; 399 TR1c:19 0000000000000000 VR1c:19 03ffffffffffffff
0100 ; 39a TR1c:1a 0000000000000000 VR1c:1a 07ffffffffffffff
0100 ; 39b TR1c:1b 0000000000000000 VR1c:1b 0fffffffffffffff
0100 ; 39c TR1c:1c 0000000000000000 VR1c:1c 1fffffffffffffff
0100 ; 39d TR1c:1d 0000000000000000 VR1c:1d 3fffffffffffffff
0100 ; 39e TR1c:1e 0000000000000000 VR1c:1e 7fffffffffffffff
0100 ; 39f TR1c:1f 0000000000000000 VR1c:1f ffffffffffffffff
0100 ; 3a0 TR1d:00 0000000000000001 VR1d:00 ffffffffffffffff
0100 ; 3a1 TR1d:01 0000000000000003 VR1d:01 ffffffffffffffff
0100 ; 3a2 TR1d:02 0000000000000007 VR1d:02 ffffffffffffffff
0100 ; 3a3 TR1d:03 000000000000000f VR1d:03 ffffffffffffffff
0100 ; 3a4 TR1d:04 000000000000001f VR1d:04 ffffffffffffffff
0100 ; 3a5 TR1d:05 000000000000003f VR1d:05 ffffffffffffffff
0100 ; 3a6 TR1d:06 000000000000007f VR1d:06 ffffffffffffffff
0100 ; 3a7 TR1d:07 00000000000000ff VR1d:07 ffffffffffffffff
0100 ; 3a8 TR1d:08 00000000000001ff VR1d:08 ffffffffffffffff
0100 ; 3a9 TR1d:09 00000000000003ff VR1d:09 ffffffffffffffff
0100 ; 3aa TR1d:0a 00000000000007ff VR1d:0a ffffffffffffffff
0100 ; 3ab TR1d:0b 0000000000000fff VR1d:0b ffffffffffffffff
0100 ; 3ac TR1d:0c 0000000000001fff VR1d:0c ffffffffffffffff
0100 ; 3ad TR1d:0d 0000000000003fff VR1d:0d ffffffffffffffff
0100 ; 3ae TR1d:0e 0000000000007fff VR1d:0e ffffffffffffffff
0100 ; 3af TR1d:0f 000000000000ffff VR1d:0f ffffffffffffffff
0100 ; 3b0 TR1d:10 000000000001ffff VR1d:10 ffffffffffffffff
0100 ; 3b1 TR1d:11 000000000003ffff VR1d:11 ffffffffffffffff
0100 ; 3b2 TR1d:12 000000000007ffff VR1d:12 ffffffffffffffff
0100 ; 3b3 TR1d:13 00000000000fffff VR1d:13 ffffffffffffffff
0100 ; 3b4 TR1d:14 00000000001fffff VR1d:14 ffffffffffffffff
0100 ; 3b5 TR1d:15 00000000003fffff VR1d:15 ffffffffffffffff
0100 ; 3b6 TR1d:16 00000000007fffff VR1d:16 ffffffffffffffff
0100 ; 3b7 TR1d:17 0000000000ffffff VR1d:17 ffffffffffffffff
0100 ; 3b8 TR1d:18 0000000001ffffff VR1d:18 ffffffffffffffff
0100 ; 3b9 TR1d:19 0000000003ffffff VR1d:19 ffffffffffffffff
0100 ; 3ba TR1d:1a 0000000007ffffff VR1d:1a ffffffffffffffff
0100 ; 3bb TR1d:1b 000000000fffffff VR1d:1b ffffffffffffffff
0100 ; 3bc TR1d:1c 000000001fffffff VR1d:1c ffffffffffffffff
0100 ; 3bd TR1d:1d 000000003fffffff VR1d:1d ffffffffffffffff
0100 ; 3be TR1d:1e 000000007fffffff VR1d:1e ffffffffffffffff
0100 ; 3bf TR1d:1f 00000000ffffffff VR1d:1f ffffffffffffffff
0100 ; 3c0 TR1e:00 00000001ffffffff VR1e:00 ffffffffffffffff
0100 ; 3c1 TR1e:01 00000003ffffffff VR1e:01 ffffffffffffffff
0100 ; 3c2 TR1e:02 00000007ffffffff VR1e:02 ffffffffffffffff
0100 ; 3c3 TR1e:03 0000000fffffffff VR1e:03 ffffffffffffffff
0100 ; 3c4 TR1e:04 0000001fffffffff VR1e:04 ffffffffffffffff
0100 ; 3c5 TR1e:05 0000003fffffffff VR1e:05 ffffffffffffffff
0100 ; 3c6 TR1e:06 0000007fffffffff VR1e:06 ffffffffffffffff
0100 ; 3c7 TR1e:07 000000ffffffffff VR1e:07 ffffffffffffffff
0100 ; 3c8 TR1e:08 000001ffffffffff VR1e:08 ffffffffffffffff
0100 ; 3c9 TR1e:09 000003ffffffffff VR1e:09 ffffffffffffffff
0100 ; 3ca TR1e:0a 000007ffffffffff VR1e:0a ffffffffffffffff
0100 ; 3cb TR1e:0b 00000fffffffffff VR1e:0b ffffffffffffffff
0100 ; 3cc TR1e:0c 00001fffffffffff VR1e:0c ffffffffffffffff
0100 ; 3cd TR1e:0d 00003fffffffffff VR1e:0d ffffffffffffffff
0100 ; 3ce TR1e:0e 00007fffffffffff VR1e:0e ffffffffffffffff
0100 ; 3cf TR1e:0f 0000ffffffffffff VR1e:0f ffffffffffffffff
0100 ; 3d0 TR1e:10 0001ffffffffffff VR1e:10 ffffffffffffffff
0100 ; 3d1 TR1e:11 0003ffffffffffff VR1e:11 ffffffffffffffff
0100 ; 3d2 TR1e:12 0007ffffffffffff VR1e:12 ffffffffffffffff
0100 ; 3d3 TR1e:13 000fffffffffffff VR1e:13 ffffffffffffffff
0100 ; 3d4 TR1e:14 001fffffffffffff VR1e:14 ffffffffffffffff
0100 ; 3d5 TR1e:15 003fffffffffffff VR1e:15 ffffffffffffffff
0100 ; 3d6 TR1e:16 007fffffffffffff VR1e:16 ffffffffffffffff
0100 ; 3d7 TR1e:17 00ffffffffffffff VR1e:17 ffffffffffffffff
0100 ; 3d8 TR1e:18 01ffffffffffffff VR1e:18 ffffffffffffffff
0100 ; 3d9 TR1e:19 03ffffffffffffff VR1e:19 ffffffffffffffff
0100 ; 3da TR1e:1a 07ffffffffffffff VR1e:1a ffffffffffffffff
0100 ; 3db TR1e:1b 0fffffffffffffff VR1e:1b ffffffffffffffff
0100 ; 3dc TR1e:1c 1fffffffffffffff VR1e:1c ffffffffffffffff
0100 ; 3dd TR1e:1d 3fffffffffffffff VR1e:1d ffffffffffffffff
0100 ; 3de TR1e:1e 7fffffffffffffff VR1e:1e ffffffffffffffff
0100 ; 3df TR1e:1f ffffffffffffffff VR1e:1f ffffffffffffffff
0100 ; 3e0 TCSA0 00c80013b36f5ba4 VCSA0 00050022444a4c20
0100 ; 3e1 TCSA1 0000000000000000 VCSA1 0000000000000000
0100 ; 3e2 TCSA2 0000000000000000 VCSA2 0000000000000000
0100 ; 3e3 TCSA3 0000000000000000 VCSA3 0000000000000000
0100 ; 3e4 TCSA4 0000000000000000 VCSA4 0000000000000000
0100 ; 3e5 TCSA5 0000000000000000 VCSA5 0000000000000000
0100 ; 3e6 TCSA6 0000000000000000 VCSA6 0000000000000000
0100 ; 3e7 TCSA7 0000000000000000 VCSA7 0000000000000000
0100 ; 3e8 TCSA8 0000000000000000 VCSA8 0000000000000000
0100 ; 3e9 TCSA9 0000000000000000 VCSA9 0000000000000000
0100 ; 3ea TCSAa 0000000000000000 VCSAa 0000000000000000
0100 ; 3eb TCSAb 0000000000000000 VCSAb 0000000000000000
0100 ; 3ec TCSAc 0000000000000000 VCSAc 0000000000000000
0100 ; 3ed TCSAd 0000000000000000 VCSAd 0000000000000000
0100 ; 3ee TCSAe 0000000000000000 VCSAe 0000000000000000
0100 ; 3ef TCSAf 0000000000000000 VCSAf 0000000000000000
0100 ; 3f0 TGP0 0000000000000000 VGP0 0000000000000000
0100 ; 3f1 TGP1 0000000000000000 VGP1 0000000000000000
0100 ; 3f2 TGP2 0000000000000000 VGP2 0000000000000000
0100 ; 3f3 TGP3 0000000000000000 VGP3 0000000000000000
0100 ; 3f4 TGP4 0000000000000000 VGP4 0000000000000000
0100 ; 3f5 TGP5 0000000000000000 VGP5 0000000000000000
0100 ; 3f6 TGP6 0000000000000000 VGP6 0000000000000000
0100 ; 3f7 TGP7 0000000000000000 VGP7 0000000000000000
0100 ; 3f8 TGP8 0000000000000000 VGP8 0000000000000000
0100 ; 3f9 TGP9 0000000000000000 VGP9 0000000000000000
0100 ; 3fa TGPa 0000000000000000 VGPa 0000000000000000
0100 ; 3fb TGPb 0000000000000000 VGPb 0000000000000000
0100 ; 3fc TGPc 0000000000000000 VGPc 0000000000000000
0100 ; 3fd TGPd 0000000000000000 VGPd 0000000000000000
0100 ; 3fe TGPe 0000000000000000 VGPe 0000000000000000
0100 ; 3ff TGPf 0000000000000000 VGPf 0000000000000000
0100 ;
0100 ; Defaults not shown:
0100 ; ===================
0100 ; dispatch_csa_free 0
0100 ; dispatch_ibuff_fill 0
0100 ; dispatch_ignore 0
0100 ; dispatch_mem_strt 4 MEMORY NOT STARTED
0100 ; dispatch_uses_tos 0
0100 ; fiu_fill_mode_src 1
0100 ; fiu_len_fill_lit 7f zero-fill 0x3f
0100 ; fiu_len_fill_reg_ctl 3 len=unchanged, fill=unchanged
0100 ; fiu_length_src 1 length_literal
0100 ; fiu_load_mdr 0 load_mdr
0100 ; fiu_load_oreg 0 load_oreg
0100 ; fiu_load_tar 0 load_tar
0100 ; fiu_load_var 0 load_var
0100 ; fiu_mem_start 19 nop_0x19
0100 ; fiu_offs_lit 00
0100 ; fiu_offset_src 1 offset_literal
0100 ; fiu_op_sel 0 extract
0100 ; fiu_oreg_src 1 merge data register
0100 ; fiu_rdata_src 1 mdr
0100 ; fiu_tivi_src 0 tar_var
0100 ; fiu_vmux_sel 2 VI
0100 ; ioc_adrbs 0 fiu
0100 ; ioc_fiubs 3 seq
0100 ; ioc_load_wdr 1
0100 ; ioc_random 0 noop
0100 ; ioc_tvbs 0 typ+val
0100 ; seq_b_timing 2 Late Condition, Hint True (or unconditional branch)
0100 ; seq_br_type 6 Continue
0100 ; seq_branch_adr 0000
0100 ; seq_cond_sel 46 SEQ.previously_latched_cond
0100 ; seq_en_micro 1
0100 ; seq_int_reads 3 TOP OF THE MICRO STACK
0100 ; seq_latch 0
0100 ; seq_lex_adr 0
0100 ; seq_random 00 ?
0100 ; typ_a_adr 00 GP00
0100 ; typ_alu_func 1f ZEROS
0100 ; typ_b_adr 00 GP00
0100 ; typ_c_adr 29 WRITE_DISABLE
0100 ; typ_c_lit 3
0100 ; typ_c_mux_sel 1 WDR
0100 ; typ_c_source 1 MUX
0100 ; typ_csa_cntl 6 NOP
0100 ; typ_frame 0
0100 ; typ_mar_cntl 0 NOP
0100 ; typ_priv_check 7 NOP
0100 ; typ_rand f INC_DEC_128
0100 ; val_a_adr 00 GP00
0100 ; val_alu_func 1f ZEROS
0100 ; val_b_adr 00 GP00
0100 ; val_c_adr 29 WRITE_DISABLE
0100 ; val_c_mux_sel 3 WDR
0100 ; val_c_source 1 MUX
0100 ; val_frame 0
0100 ; val_m_a_src 3 Bits 48…63
0100 ; val_m_b_src 3 Bits 48…63
0100 ; val_rand 0 NO_OP
0100 ;
0100 ; Early macro event: ME_STOP_MACH
0100 ; --------------------------------------------------------------------------------------
0100 DIAGNOSTIC_START:
0100 ME_STOP_MACH:
; VAL { PASS_COUNTER := ZEROS },
; GOTO DIAGNOSTIC_DRIVER.START,
0100 0100 seq_br_type 3 Unconditional Branch; Flow J 0x300
seq_branch_adr 0300 START
val_c_adr 3f GP00
val_c_mux_sel 2 ALU
0101 END_DIAGNOSTIC_PASS:
; VAL { ALU_BUS := PASS_A (PASS_COUNTER) },
; IF VAL (ALU_BUS /= 0) THE USUALLY GOTO NOT_FIRST_PASS,
0101 0101 seq_br_type 1 Branch True; Flow J cc=True 0x103
seq_branch_adr 0103 NOT_FIRST_PASS
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 0 PASS_A
0102 COMPLETED_FULL_TEST:
; -- Halt at end of first pass --
; HALT,
0102 0102 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
0103 NOT_FIRST_PASS:
; VAL { PASS_COUNTER := INC_A (PASS_COUNTER) },
; GOTO DIAGNOSTIC_DRIVER.START,
0103 0103 seq_br_type 3 Unconditional Branch; Flow J 0x300
seq_branch_adr 0300 START
val_alu_func 7 INC_A
val_c_adr 3f GP00
val_c_mux_sel 2 ALU
0104 0104 seq_br_type 3 Unconditional Branch; Flow J 0x322
seq_branch_adr 0322 0x0322
0105 0105 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
0106 0106 seq_br_type 3 Unconditional Branch; Flow J 0x324
seq_branch_adr 0324 0x0324
0107 0107 <halt> ; Flow R
0108 ; --------------------------------------------------------------------------------------
0108 ; Early macro event: ME_GP_TIME
0108 ; --------------------------------------------------------------------------------------
0108 ME_GP_TIME:
0108 0108 ioc_random f disable delay timer; Flow C cc=True 0x2ecd
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 07 GP07
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0109 0109 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
seq_en_micro 0
typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
val_alu_func 13 ONES
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
010a 010a ioc_random b clear delay event
010b 010b fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
010c 010c <halt> ; Flow R
010d 010d <halt> ; Flow R
010e 010e <halt> ; Flow R
010f 010f <halt> ; Flow R
0110 ; --------------------------------------------------------------------------------------
0110 ; Early macro event: ME_SL_TIME
0110 ; --------------------------------------------------------------------------------------
0110 ME_SL_TIME:
0110 0110 ioc_random d disable slice timer; Flow C cc=True 0x2ecb
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2ecb SLICE_MACRO_EVENT_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 08 GP08
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0111 0111 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
seq_en_micro 0
typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
val_alu_func 13 ONES
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
0112 0112 ioc_random a clear slice event
seq_en_micro 0
0113 0113 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
0114 0114 <halt> ; Flow R
0115 0115 <halt> ; Flow R
0116 0116 <halt> ; Flow R
0117 0117 <halt> ; Flow R
0118 ; --------------------------------------------------------------------------------------
0118 ; Early macro event: ME_SPARE1
0118 ; --------------------------------------------------------------------------------------
0118 ME_SPARE1:
0118 0118 <halt> ; Flow R
0119 0119 <halt> ; Flow R
011a 011a <halt> ; Flow R
011b 011b <halt> ; Flow R
011c 011c <halt> ; Flow R
011d 011d <halt> ; Flow R
011e 011e <halt> ; Flow R
011f 011f <halt> ; Flow R
0120 ; --------------------------------------------------------------------------------------
0120 ; Early macro event: ME_PACKET
0120 ; --------------------------------------------------------------------------------------
0120 ME_PACKET:
0120 0120 <halt> ; Flow R
0121 0121 seq_br_type a Unconditional Return; Flow R
0122 0122 <halt> ; Flow R
0123 0123 <halt> ; Flow R
0124 0124 <halt> ; Flow R
0125 0125 <halt> ; Flow R
0126 0126 <halt> ; Flow R
0127 0127 <halt> ; Flow R
0128 ; --------------------------------------------------------------------------------------
0128 ; Early macro event: ME_STATUS
0128 ; --------------------------------------------------------------------------------------
0128 ME_STATUS:
0128 0128 <halt> ; Flow R
0129 0129 seq_br_type a Unconditional Return; Flow R
012a 012a <halt> ; Flow R
012b 012b <halt> ; Flow R
012c 012c <halt> ; Flow R
012d 012d <halt> ; Flow R
012e 012e <halt> ; Flow R
012f 012f <halt> ; Flow R
0130 ; --------------------------------------------------------------------------------------
0130 ; Early macro event: ME_SPARE0
0130 ; --------------------------------------------------------------------------------------
0130 ME_SPARE0:
0130 0130 <halt> ; Flow R
0131 0131 <halt> ; Flow R
0132 0132 <halt> ; Flow R
0133 0133 <halt> ; Flow R
0134 0134 <halt> ; Flow R
0135 0135 <halt> ; Flow R
0136 0136 <halt> ; Flow R
0137 0137 <halt> ; Flow R
0138 ; --------------------------------------------------------------------------------------
0138 ; Early macro event: ME_REFRESH
0138 ; --------------------------------------------------------------------------------------
0138 ME_REFRESH:
0138 0138 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
0139 0139 <default>
013a 013a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
013b 013b <halt> ; Flow R
013c 013c <halt> ; Flow R
013d 013d <halt> ; Flow R
013e 013e <halt> ; Flow R
013f 013f <halt> ; Flow R
0140 ; --------------------------------------------------------------------------------------
0140 ; Late macro event: ML_IBUF_empty
0140 ; --------------------------------------------------------------------------------------
0140 ML_IBUF_empty:
0140 0140 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
0141 0141 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22c2
seq_br_type 5 Call True
seq_branch_adr 22c2 IFILL_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 0d GP0d
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
val_alu_func 13 ONES
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
0142 0142 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
val_a_adr 25 VR13:05
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 13
0143 0143 val_a_adr 0f GP0f
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
val_frame 4
0144 0144 val_a_adr 0b GP0b
val_alu_func 1e A_AND_B
val_b_adr 3e VR16:1e
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
val_frame 16
0145 ; --------------------------------------------------------------------------------------
0145 ; Micro event: UE_MACHINE_STARTUP
0145 ; --------------------------------------------------------------------------------------
0145 UE_MACHINE_STARTUP:
0145 0145 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22bc
seq_br_type 5 Call True
seq_branch_adr 22bc PC_UPDATE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0b GP0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0146 0146 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_cond_sel 55 SEQ.E_MACRO_PEND
seq_int_reads 0 TYP VAL BUS
seq_random 28 Load_ibuff+Load_save_offset+?
typ_b_adr 0e GP0e
typ_mar_cntl e LOAD_MAR_CONTROL
val_b_adr 0e GP0e
0147 0147 <halt> ; Flow R
0148 ; --------------------------------------------------------------------------------------
0148 ; Late macro event: ML_break_class
0148 ; --------------------------------------------------------------------------------------
0148 ML_break_class:
0148 0148 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0c GP0c
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0149 0149 seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 10 Load_break_mask+?
typ_b_adr 22 TR10:02
typ_frame 10
val_alu_func 13 ONES
val_b_adr 22 VR10:02
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 10
014a 014a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
014b 014b <halt> ; Flow R
014c 014c <halt> ; Flow R
014d 014d <halt> ; Flow R
014e 014e <halt> ; Flow R
014f 014f <halt> ; Flow R
0150 ; --------------------------------------------------------------------------------------
0150 ; Late macro event: ML_pullup
0150 ; --------------------------------------------------------------------------------------
0150 ML_pullup:
0150 0150 <halt> ; Flow R
0151 0151 <halt> ; Flow R
0152 0152 <halt> ; Flow R
0153 0153 <halt> ; Flow R
0154 0154 <halt> ; Flow R
0155 0155 <halt> ; Flow R
0156 0156 <halt> ; Flow R
0157 0157 <halt> ; Flow R
0158 ; --------------------------------------------------------------------------------------
0158 ; Late macro event: ML_TOS_INVLD
0158 ; --------------------------------------------------------------------------------------
0158 ML_TOS_INVLD:
0158 0158 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d9
seq_br_type 5 Call True
seq_branch_adr 22d9 TOS_OP_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 08 GP08
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0159 0159 seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
015a 015a seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 08 Validate_tos_optimizer+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
015b 015b fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
015c 015c <halt> ; Flow R
015d 015d <halt> ; Flow R
015e 015e <halt> ; Flow R
015f 015f <halt> ; Flow R
0160 ; --------------------------------------------------------------------------------------
0160 ; Late macro event: ML_Resolve Reference
0160 ; --------------------------------------------------------------------------------------
0160 ML_Resolve Reference:
0160 0160 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d6
seq_br_type 5 Call True
seq_branch_adr 22d6 RES_REF_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 07 GP07
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0161 0161 seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
0162 0162 seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 09 GP09
val_b_adr 09 GP09
0163 0163 seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
0164 0164 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
0165 0165 <halt> ; Flow R
0166 0166 <halt> ; Flow R
0167 0167 <halt> ; Flow R
0168 ; --------------------------------------------------------------------------------------
0168 ; Late macro event: ML_SEQ_STOP
0168 ; --------------------------------------------------------------------------------------
0168 ML_SEQ_STOP:
0168 0168 <halt> ; Flow R
0169 0169 <halt> ; Flow R
016a 016a <halt> ; Flow R
016b 016b <halt> ; Flow R
016c 016c <halt> ; Flow R
016d 016d <halt> ; Flow R
016e 016e <halt> ; Flow R
016f 016f <halt> ; Flow R
0170 ; --------------------------------------------------------------------------------------
0170 ; Late macro event: ML_CSA_Underflow
0170 ; --------------------------------------------------------------------------------------
0170 ML_CSA_Underflow:
0170 0170 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d4
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0171 0171 seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
0172 0172 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_csa_cntl 3 POP_CSA
typ_mar_cntl e LOAD_MAR_CONTROL
0173 0173 <halt> ; Flow R
0174 0174 <halt> ; Flow R
0175 0175 <halt> ; Flow R
0176 0176 <halt> ; Flow R
0177 0177 <halt> ; Flow R
0178 ; --------------------------------------------------------------------------------------
0178 ; Late macro event: ML_CSA_overflow
0178 ; --------------------------------------------------------------------------------------
0178 ML_CSA_overflow:
0178 0178 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
0179 0179 seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
017a 017a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_csa_cntl 2 PUSH_CSA
typ_mar_cntl e LOAD_MAR_CONTROL
017b 017b <halt> ; Flow R
017c 017c <halt> ; Flow R
017d 017d <halt> ; Flow R
017e 017e <halt> ; Flow R
017f 017f <halt> ; Flow R
0180 ; --------------------------------------------------------------------------------------
0180 ; Micro event: UE_MEM_EXP
0180 ; --------------------------------------------------------------------------------------
0180 UE_MEM_EXP:
0180 0180 <halt> ; Flow R
0181 0181 seq_br_type a Unconditional Return; Flow R
0182 0182 <halt> ; Flow R
0183 0183 <halt> ; Flow R
0184 0184 <halt> ; Flow R
0185 0185 <halt> ; Flow R
0186 0186 <halt> ; Flow R
0187 0187 <halt> ; Flow R
0188 ; --------------------------------------------------------------------------------------
0188 ; Micro event: UE_ECC
0188 ; --------------------------------------------------------------------------------------
0188 UE_ECC:
0188 0188 seq_br_type 1 Branch True; Flow J cc=True 0x200
seq_branch_adr 0200 0x0200
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 20 VR1a:00
val_alu_func 0 PASS_A
val_frame 1a
0189 0189 <halt> ; Flow R
018a 018a seq_br_type 3 Unconditional Branch; Flow J 0x189
seq_branch_adr 0189 0x0189
018b 018b <halt> ; Flow R
018c 018c <halt> ; Flow R
018d 018d <halt> ; Flow R
018e 018e <halt> ; Flow R
018f 018f <halt> ; Flow R
0190 ; --------------------------------------------------------------------------------------
0190 ; Micro event: UE_BKPT
0190 ; --------------------------------------------------------------------------------------
0190 UE_BKPT:
0190 0190 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
0191 0191 seq_br_type a Unconditional Return; Flow R
0192 0192 <halt> ; Flow R
0193 0193 <halt> ; Flow R
0194 0194 <halt> ; Flow R
0195 0195 <halt> ; Flow R
0196 0196 <halt> ; Flow R
0197 0197 <halt> ; Flow R
0198 ; --------------------------------------------------------------------------------------
0198 ; Micro event: UE_CHK_EXIT
0198 ; --------------------------------------------------------------------------------------
0198 UE_CHK_EXIT:
0198 0198 <halt> ; Flow R
0199 0199 <halt> ; Flow R
019a 019a <halt> ; Flow R
019b 019b <halt> ; Flow R
019c 019c <halt> ; Flow R
019d 019d <halt> ; Flow R
019e 019e <halt> ; Flow R
019f 019f <halt> ; Flow R
01a0 ; --------------------------------------------------------------------------------------
01a0 ; Micro event: UE_FIELD_ERROR
01a0 ; --------------------------------------------------------------------------------------
01a0 UE_FIELD_ERROR:
01a0 01a0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False
seq_br_type 9 Return False
seq_branch_adr 01a1 0x01a1
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 03 GP03
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
01a1 01a1 ioc_random 14 clear cpu running; Flow R
seq_br_type 3 Unconditional Branch
seq_branch_adr 01a1 0x01a1
seq_random 01 Halt+?
01a2 01a2 <halt> ; Flow R
01a3 01a3 <halt> ; Flow R
01a4 01a4 <halt> ; Flow R
01a5 01a5 <halt> ; Flow R
01a6 01a6 <halt> ; Flow R
01a7 01a7 <halt> ; Flow R
01a8 ; --------------------------------------------------------------------------------------
01a8 ; Micro event: UE_CLASS
01a8 ; --------------------------------------------------------------------------------------
01a8 UE_CLASS:
01a8 01a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169c
seq_br_type 5 Call True
seq_branch_adr 169c CLASS_EVENT_FAILED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 10 NOT_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
01a9 01a9 typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
01aa 01aa seq_br_type a Unconditional Return; Flow R
typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
01ab 01ab <halt> ; Flow R
01ac 01ac <halt> ; Flow R
01ad 01ad <halt> ; Flow R
01ae 01ae <halt> ; Flow R
01af 01af <halt> ; Flow R
01b0 ; --------------------------------------------------------------------------------------
01b0 ; Micro event: UE_BIN_EQ
01b0 ; --------------------------------------------------------------------------------------
01b0 UE_BIN_EQ:
01b0 01b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1ca
seq_br_type 5 Call True
seq_branch_adr 01ca 0x01ca
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_frame 4
01b1 01b1 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
val_alu_func 1a PASS_B
val_b_adr 20 VR04:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
01b2 01b2 <halt> ; Flow R
01b3 01b3 <halt> ; Flow R
01b4 01b4 <halt> ; Flow R
01b5 01b5 <halt> ; Flow R
01b6 01b6 <halt> ; Flow R
01b7 01b7 <halt> ; Flow R
01b8 ; --------------------------------------------------------------------------------------
01b8 ; Micro event: UE_BIN_OP
01b8 ; --------------------------------------------------------------------------------------
01b8 UE_BIN_OP:
01b8 01b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1ca
seq_br_type 5 Call True
seq_branch_adr 01ca 0x01ca
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR04:01
typ_frame 4
01b9 01b9 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
val_alu_func 1a PASS_B
val_b_adr 21 VR04:01
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
01ba 01ba <halt> ; Flow R
01bb 01bb <halt> ; Flow R
01bc 01bc <halt> ; Flow R
01bd 01bd <halt> ; Flow R
01be 01be <halt> ; Flow R
01bf 01bf <halt> ; Flow R
01c0 ; --------------------------------------------------------------------------------------
01c0 ; Micro event: UE_TOS_OP
01c0 ; --------------------------------------------------------------------------------------
01c0 UE_TOS_OP:
01c0 01c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1ca
seq_br_type 5 Call True
seq_branch_adr 01ca 0x01ca
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
01c1 01c1 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
val_alu_func 1a PASS_B
val_b_adr 23 VR04:03
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
01c2 01c2 <halt> ; Flow R
01c3 01c3 <halt> ; Flow R
01c4 01c4 <halt> ; Flow R
01c5 01c5 <halt> ; Flow R
01c6 01c6 <halt> ; Flow R
01c7 01c7 <halt> ; Flow R
01c8 ; --------------------------------------------------------------------------------------
01c8 ; Micro event: UE_TOSI_OP
01c8 ; --------------------------------------------------------------------------------------
01c8 UE_TOSI_OP:
01c8 01c8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1ca
seq_br_type 5 Call True
seq_branch_adr 01ca 0x01ca
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_frame 4
01c9 01c9 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
val_alu_func 1a PASS_B
val_b_adr 22 VR04:02
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
01ca ; --------------------------------------------------------------------------------------
01ca ; Comes from:
01ca ; 01b0 C True from color UE_BIN_EQ
01ca ; 01b8 C True from color UE_BIN_OP
01ca ; 01c0 C True from color UE_TOS_OP
01ca ; 01c8 C True from color UE_TOSI_OP
01ca ; --------------------------------------------------------------------------------------
01ca 01ca ioc_random 14 clear cpu running; Flow R
seq_br_type 3 Unconditional Branch
seq_branch_adr 01ca 0x01ca
seq_random 01 Halt+?
01cb 01cb <halt> ; Flow R
01cc 01cc <halt> ; Flow R
01cd 01cd <halt> ; Flow R
01ce 01ce <halt> ; Flow R
01cf 01cf <halt> ; Flow R
01d0 ; --------------------------------------------------------------------------------------
01d0 ; Micro event: UE_PAGE_X
01d0 ; --------------------------------------------------------------------------------------
01d0 UE_PAGE_X:
01d0 01d0 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
01d1 01d1 fiu_mem_start c start_if_incmplt; Flow R
fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_br_type a Unconditional Return
seq_cond_sel 6e INCOMPLETE_MEMORY_CYCLE_FOR_PAGE_CROSSING
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
01d2 01d2 <halt> ; Flow R
01d3 01d3 <halt> ; Flow R
01d4 01d4 <halt> ; Flow R
01d5 01d5 <halt> ; Flow R
01d6 01d6 <halt> ; Flow R
01d7 01d7 <halt> ; Flow R
01d8 ; --------------------------------------------------------------------------------------
01d8 ; Micro event: UE_CHK_SYS
01d8 ; --------------------------------------------------------------------------------------
01d8 UE_CHK_SYS:
01d8 01d8 <halt> ; Flow R
01d9 01d9 seq_br_type a Unconditional Return; Flow R
01da 01da <halt> ; Flow R
01db 01db <halt> ; Flow R
01dc 01dc <halt> ; Flow R
01dd 01dd <halt> ; Flow R
01de 01de <halt> ; Flow R
01df 01df <halt> ; Flow R
01e0 ; --------------------------------------------------------------------------------------
01e0 ; Micro event: UE_NEW_PAK
01e0 ; --------------------------------------------------------------------------------------
01e0 UE_NEW_PAK:
01e0 01e0 <halt> ; Flow R
01e1 01e1 seq_br_type a Unconditional Return; Flow R
01e2 01e2 <halt> ; Flow R
01e3 01e3 <halt> ; Flow R
01e4 01e4 <halt> ; Flow R
01e5 01e5 <halt> ; Flow R
01e6 01e6 <halt> ; Flow R
01e7 01e7 <halt> ; Flow R
01e8 ; --------------------------------------------------------------------------------------
01e8 ; Micro event: UE_NEW_STS
01e8 ; --------------------------------------------------------------------------------------
01e8 UE_NEW_STS:
01e8 01e8 <halt> ; Flow R
01e9 01e9 seq_br_type a Unconditional Return; Flow R
01ea 01ea <halt> ; Flow R
01eb 01eb <halt> ; Flow R
01ec 01ec <halt> ; Flow R
01ed 01ed <halt> ; Flow R
01ee 01ee <halt> ; Flow R
01ef 01ef <halt> ; Flow R
01f0 ; --------------------------------------------------------------------------------------
01f0 ; Micro event: UE_XFER_CP
01f0 ; --------------------------------------------------------------------------------------
01f0 UE_XFER_CP:
01f0 01f0 <halt> ; Flow R
01f1 01f1 seq_br_type a Unconditional Return; Flow R
01f2 01f2 <halt> ; Flow R
01f3 01f3 <halt> ; Flow R
01f4 01f4 <halt> ; Flow R
01f5 01f5 <halt> ; Flow R
01f6 01f6 <halt> ; Flow R
01f7 01f7 <halt> ; Flow R
01f8 ; --------------------------------------------------------------------------------------
01f8 ; 0x0002-0x0006 Illegal -
01f8 ; 0x0009-0x000f Illegal -
01f8 ; 0x0024-0x0030 Illegal -
01f8 ; 0x0037-0x0038 Illegal -
01f8 ; 0x003f-0x0040 Illegal -
01f8 ; 0x0047-0x0048 Illegal -
01f8 ; 0x004f-0x0050 Illegal -
01f8 ; 0x0057-0x0058 Illegal -
01f8 ; 0x005f-0x0067 Illegal -
01f8 ; 0x0077-0x007f Illegal -
01f8 ; 0x0083-0x0086 Illegal -
01f8 ; 0x0094 Illegal -
01f8 ; 0x00ae-0x00b2 Illegal -
01f8 ; 0x00c0-0x00c3 Illegal -
01f8 ; 0x00df Illegal -
01f8 ; 0x0103-0x0105 Illegal -
01f8 ; 0x0108 Illegal -
01f8 ; 0x0113 Illegal -
01f8 ; 0x0130-0x0131 Illegal -
01f8 ; 0x0134-0x0135 Illegal -
01f8 ; 0x0138-0x013b Illegal -
01f8 ; 0x0150-0x015a Illegal -
01f8 ; 0x0173-0x0176 Illegal -
01f8 ; 0x0183-0x0188 Illegal -
01f8 ; 0x018c Illegal -
01f8 ; 0x0193-0x019a Illegal -
01f8 ; 0x01b3-0x01bd Illegal -
01f8 ; 0x01c8-0x01c9 Illegal -
01f8 ; 0x01e3-0x01ea Illegal -
01f8 ; 0x0203-0x0204 Illegal -
01f8 ; 0x0207 Illegal -
01f8 ; 0x0283-0x028f Illegal -
01f8 ; 0x0293-0x0298 Illegal -
01f8 ; 0x02a3 Illegal -
01f8 ; 0x02a6-0x02a7 Illegal -
01f8 ; 0x02ac-0x02af Illegal -
01f8 ; 0x02b3-0x02bd Illegal -
01f8 ; 0x02c3-0x02c5 Illegal -
01f8 ; 0x02c8 Illegal -
01f8 ; 0x02ca Illegal -
01f8 ; 0x02cc-0x02cd Illegal -
01f8 ; 0x02d3-0x02fa Illegal -
01f8 ; 0x0301-0x0302 Illegal -
01f8 ; 0x0308-0x030f Illegal -
01f8 ; 0x0313-0x0314 Illegal -
01f8 ; 0x0317 Illegal -
01f8 ; 0x031a Illegal -
01f8 ; 0x031f Illegal -
01f8 ; 0x0323 Illegal -
01f8 ; 0x0329 Illegal -
01f8 ; 0x032c Illegal -
01f8 ; 0x032f Illegal -
01f8 ; 0x0331-0x0332 Illegal -
01f8 ; 0x0338-0x033f Illegal -
01f8 ; 0x0344-0x0345 Illegal -
01f8 ; 0x034a Illegal -
01f8 ; 0x034d Illegal -
01f8 ; 0x0357 Illegal -
01f8 ; 0x035a Illegal -
01f8 ; 0x035f-0x0369 Illegal -
01f8 ; 0x0370-0x0373 Illegal -
01f8 ; 0x0375-0x0376 Illegal -
01f8 ; 0x0379 Illegal -
01f8 ; 0x037c Illegal -
01f8 ; 0x037f-0x0383 Illegal -
01f8 ; 0x0388-0x038b Illegal -
01f8 ; 0x0390-0x0394 Illegal -
01f8 ; 0x03aa Illegal -
01f8 ; 0x03af-0x03b4 Illegal -
01f8 ; 0x03c0-0x03c3 Illegal -
01f8 ; 0x03c8-0x03cb Illegal -
01f8 ; 0x03d0 Illegal -
01f8 ; 0x03d7 Illegal -
01f8 ; 0x03e2 Illegal -
01f8 ; 0x03e7 Illegal -
01f8 ; 0x03f4 Illegal -
01f8 ; 0x03ff Illegal -
01f8 ; 0x1e00-0x1fff Illegal -
01f8 ; 0x3100-0x33ff Illegal -
01f8 ; 0x3500-0x35ff Illegal -
01f8 ; 0x3900-0x3bff Illegal -
01f8 ; 0x3d00-0x3dff Illegal -
01f8 ; 0x4040-0x40ff Illegal -
01f8 ; 0x0007 Action Break_Optional
01f8 ; 0x0008 Action Idle
01f8 ; 0x0018-0x001f QQUnknown InMicrocode
01f8 ; 0x0070-0x0076 QQUnknown InMicrocode
01f8 ; 0x0080-0x0082 QQUnknown InMicrocode
01f8 ; 0x00a8-0x00ac QQUnknown InMicrocode
01f8 ; 0x0128 QQUnknown InMicrocode
01f8 ; 0x0205 QQUnknown InMicrocode
01f8 ; 0x0031 Store_Top Heap_Access,At_Offset_1
01f8 ; 0x0032 Store_Top Heap_Access,At_Offset_2
01f8 ; 0x0033 Store_Top Heap_Access,At_Offset_3
01f8 ; 0x0034 Store_Top Heap_Access,At_Offset_4
01f8 ; 0x0035 Store_Top Heap_Access,At_Offset_5
01f8 ; 0x0036 Store_Top Heap_Access,At_Offset_6
01f8 ; 0x0039 Store_Top Access,At_Offset_1
01f8 ; 0x003a Store_Top Access,At_Offset_2
01f8 ; 0x003b Store_Top Access,At_Offset_3
01f8 ; 0x003c Store_Top Access,At_Offset_4
01f8 ; 0x003d Store_Top Access,At_Offset_5
01f8 ; 0x003e Store_Top Access,At_Offset_6
01f8 ; 0x0041 Store_Top_Unchecked Float,At_Offset_1
01f8 ; 0x0042 Store_Top_Unchecked Float,At_Offset_2
01f8 ; 0x0043 Store_Top_Unchecked Float,At_Offset_3
01f8 ; 0x0044 Store_Top_Unchecked Float,At_Offset_4
01f8 ; 0x0045 Store_Top_Unchecked Float,At_Offset_5
01f8 ; 0x0046 Store_Top_Unchecked Float,At_Offset_6
01f8 ; 0x0049 Store_Top Float,At_Offset_1
01f8 ; 0x004a Store_Top Float,At_Offset_2
01f8 ; 0x004b Store_Top Float,At_Offset_3
01f8 ; 0x004c Store_Top Float,At_Offset_4
01f8 ; 0x004d Store_Top Float,At_Offset_5
01f8 ; 0x004e Store_Top Float,At_Offset_6
01f8 ; 0x0051 Store_Top_Unchecked Discrete,At_Offset_1
01f8 ; 0x0052 Store_Top_Unchecked Discrete,At_Offset_2
01f8 ; 0x0053 Store_Top_Unchecked Discrete,At_Offset_3
01f8 ; 0x0054 Store_Top_Unchecked Discrete,At_Offset_4
01f8 ; 0x0055 Store_Top_Unchecked Discrete,At_Offset_5
01f8 ; 0x0056 Store_Top_Unchecked Discrete,At_Offset_6
01f8 ; 0x0059 Store_Top Discrete,At_Offset_1
01f8 ; 0x005a Store_Top Discrete,At_Offset_2
01f8 ; 0x005b Store_Top Discrete,At_Offset_3
01f8 ; 0x005c Store_Top Discrete,At_Offset_4
01f8 ; 0x005d Store_Top Discrete,At_Offset_5
01f8 ; 0x005e Store_Top Discrete,At_Offset_6
01f8 ; 0x0068 Action Establish_Frame
01f8 ; 0x0069 Action Query_Frame
01f8 ; 0x006a Action Alter_Break_Mask
01f8 ; 0x006b Action Query_Break_Address
01f8 ; 0x006c Action Query_Break_Mask
01f8 ; 0x006d Action Query_Break_Cause
01f8 ; 0x006e Action Exit_Break
01f8 ; 0x006f Action Break_Unconditional
01f8 ; 0x0087 Execute Discrete,Diana_Spare2
01f8 ; 0x0088 Execute Heap_Access,Diana_Spare2
01f8 ; 0x0089 Execute Discrete,Diana_Spare1
01f8 ; 0x008a Execute Discrete,Diana_Spare0
01f8 ; 0x008b Execute Heap_Access,Diana_Seq_Type_Get_Head
01f8 ; 0x008c Execute Heap_Access,Diana_Put_Node_On_Seq_Type
01f8 ; 0x008d Execute Heap_Access,Diana_Allocate_Tree_Node
01f8 ; 0x008e Execute Discrete,Diana_Arity_For_Kind
01f8 ; 0x008f Execute Discrete,Diana_Map_Kind_To_Vci
01f8 ; 0x0090 Action Store_String_Extended,pse
01f8 ; 0x0091 Action Push_String_Extended_Indexed,pse
01f8 ; 0x0092 Action Push_String_Extended,pse
01f8 ; 0x0093 PushFullAddress InMicrocode,caddr
01f8 ; 0x0095 Execute Package,Field_Reference_Dynamic
01f8 ; 0x0096 Execute Package,Field_Execute_Dynamic
01f8 ; 0x0097 Execute Package,Field_Write_Dynamic
01f8 ; 0x0098 Execute Package,Field_Read_Dynamic
01f8 ; 0x0099 Action Reference_Dynamic
01f8 ; 0x009a Action Call_Dynamic
01f8 ; 0x009b Action Store_Dynamic
01f8 ; 0x009c Action Load_Dynamic
01f8 ; 0x009d Action Jump_Nonzero_Dynamic
01f8 ; 0x009e Action Jump_Zero_Dynamic
01f8 ; 0x009f Action Jump_Dynamic
01f8 ; 0x00a0 Action Push_Structure_Extended,abs,mark
01f8 ; 0x00a1 Action Push_Float_Extended
01f8 ; 0x00a2 Action Push_Discrete_Extended
01f8 ; 0x00a3 Action Loop_Decreasing_Extended,abs,>JC
01f8 ; 0x00a4 Action Loop_Increasing_Extended,abs,>JC
01f8 ; 0x00a5 Action Jump_Nonzero_Extended,abs,>JC
01f8 ; 0x00a6 Action Jump_Zero_Extended,abs,>JC
01f8 ; 0x00a7 Action Jump_Extended,abs,>J
01f8 ; 0x00ad Action InMicrocode,Package,Field_Execute_Dynamic
01f8 ; 0x00b3 Action Increase_Priority
01f8 ; 0x00b4 Action Name_Partner
01f8 ; 0x00b5 Action Make_Parent
01f8 ; 0x00b6 Action Make_Scope
01f8 ; 0x00b7 Action Make_Self
01f8 ; 0x00b8 Action Set_Priority
01f8 ; 0x00b9 Action Get_Priority
01f8 ; 0x00ba Action Initiate_Delay
01f8 ; 0x00bb Action Signal_Completion,>R
01f8 ; 0x00bc Action Signal_Activated
01f8 ; 0x00bd Action Activate_Heap_Tasks
01f8 ; 0x00be Action Activate_Tasks
01f8 ; 0x00bf Action Accept_Activation
01f8 ; 0x00c4 Action Make_Default
01f8 ; 0x00c5 Action Set_Block_Start
01f8 ; 0x00c6 Action Check_Subprogram_Elaborated
01f8 ; 0x00c7 Action Elaborate_Subprogram
01f8 ; 0x00c8 Action Pop_Auxiliary_Range
01f8 ; 0x00c9 Action Pop_Auxiliary_Loop
01f8 ; 0x00ca Action Exit_Nullary_Function,>R
01f8 ; 0x00cb Action Pop_Block_With_Result
01f8 ; 0x00cc Action Pop_Block
01f8 ; 0x00cd Action Spare6_Action
01f8 ; 0x00ce Action Pop_Auxiliary
01f8 ; 0x00cf Action Mark_Auxiliary
01f8 ; 0x00d0 Action Swap_Control
01f8 ; 0x00d1 Pop_Control Pop_Count_1
01f8 ; 0x00d2 Pop_Control Pop_Count_2
01f8 ; 0x00d3 Pop_Control Pop_Count_3
01f8 ; 0x00d4 Pop_Control Pop_Count_4
01f8 ; 0x00d5 Pop_Control Pop_Count_5
01f8 ; 0x00d6 Pop_Control Pop_Count_6
01f8 ; 0x00d7 Pop_Control Pop_Count_7
01f8 ; 0x00d8 Load_Top At_Offset_0
01f8 ; 0x00d9 Load_Top At_Offset_1
01f8 ; 0x00da Load_Top At_Offset_2
01f8 ; 0x00db Load_Top At_Offset_3
01f8 ; 0x00dc Load_Top At_Offset_4
01f8 ; 0x00dd Load_Top At_Offset_5
01f8 ; 0x00de Load_Top At_Offset_6
01f8 ; 0x00e0-0x00ff Load_Encached eon
01f8 ; 0x0106 Execute Exception,Address
01f8 ; 0x0107 Execute Exception,Get_Name
01f8 ; 0x0109 Execute Exception,Is_Instruction_Error
01f8 ; 0x010a Execute Exception,Is_Tasking_Error
01f8 ; 0x010b Execute Exception,Is_Storage_Error
01f8 ; 0x010c Execute Exception,Is_Program_Error
01f8 ; 0x010d Execute Exception,Is_Numeric_Error
01f8 ; 0x010e Execute Exception,Is_Constraint_Error
01f8 ; 0x010f Execute Exception,Equal
01f8 ; 0x0114 Execute Access,Size
01f8 ; 0x0115 Execute Any,Structure_Clear
01f8 ; 0x0116 Execute Any,Address_Of_Type
01f8 ; 0x0117 Execute Any,Structure_Query
01f8 ; 0x0118 Execute Any,Write_Unchecked
01f8 ; 0x0119 Execute Any,Check_In_Formal_Type
01f8 ; 0x011a Execute Any,Not_In_Type
01f8 ; 0x011b Execute Any,In_Type
01f8 ; 0x011c Execute Any,Convert_Unchecked
01f8 ; 0x011d Execute Any,Convert_To_Formal
01f8 ; 0x011e Execute Any,Convert
01f8 ; 0x011f Execute Any,Is_Scalar
01f8 ; 0x0123 Execute Any,Make_Aligned
01f8 ; 0x0124 Execute Any,Is_Constrained
01f8 ; 0x0125 Execute Any,Set_Constraint
01f8 ; 0x0126 Execute Any,Has_Default_Initialization
01f8 ; 0x0127 Execute Any,Run_Initialization_Utility
01f8 ; 0x0129 Execute Any,Make_Visible
01f8 ; 0x012a Execute Any,Change_Utility
01f8 ; 0x012b Execute Any,Spare14
01f8 ; 0x012c Execute Any,Size
01f8 ; 0x012d Execute Any,Address
01f8 ; 0x012e Execute Any,Not_Equal
01f8 ; 0x012f Execute Any,Equal
01f8 ; 0x0132 Execute Family,Count
01f8 ; 0x0133 Execute Family,Rendezvous
01f8 ; 0x0136 Execute Entry,Count
01f8 ; 0x0137 Execute Entry,Rendezvous
01f8 ; 0x013c Execute Select,Terminate_Guard_Write
01f8 ; 0x013d Execute Select,Timed_Duration_Write
01f8 ; 0x013e Execute Select,Timed_Guard_Write
01f8 ; 0x013f Execute Select,Rendezvous
01f8 ; 0x0140 Execute Discrete,Divide_And_Scale
01f8 ; 0x0141 Execute Discrete,Multiply_And_Scale
01f8 ; 0x0142 Execute Heap_Access,Diana_Find_Permanent_Attribute
01f8 ; 0x0143 Execute Heap_Access,Adaptive_Balanced_Tree_Lookup
01f8 ; 0x0144 Execute Heap_Access,Get_Name
01f8 ; 0x0145 Execute Heap_Access,Diana_Tree_Kind
01f8 ; 0x0146 Execute Heap_Access,Hash
01f8 ; 0x0147 Execute Heap_Access,Construct_Segment
01f8 ; 0x0148 Execute Heap_Access,Get_Offset
01f8 ; 0x0149 Execute Float,Less_Equal_Zero
01f8 ; 0x014a Execute Float,Greater_Equal_Zero
01f8 ; 0x014b Execute Float,Less_Zero
01f8 ; 0x014c Execute Float,Greater_Zero
01f8 ; 0x014d Execute Float,Not_Equal_Zero
01f8 ; 0x014e Execute Float,Equal_Zero
01f8 ; 0x014f Execute Float,Not_In_Range
01f8 ; 0x015b Execute Variant_Record,Make_Constrained
01f8 ; 0x015c Execute Variant_Record,Is_Constrained_Object
01f8 ; 0x015d Execute Variant_Record,Field_Type_Dynamic
01f8 ; 0x015e Execute Variant_Record,Field_Reference_Dynamic
01f8 ; 0x015f Execute Variant_Record,Field_Write_Dynamic
01f8 ; 0x0160 Execute Variant_Record,Field_Read_Dynamic
01f8 ; 0x0161 Execute Variant_Record,Check_In_Formal_Type
01f8 ; 0x0162 Execute Variant_Record,Check_In_Type
01f8 ; 0x0163 Execute Variant_Record,Not_In_Type
01f8 ; 0x0164 Execute Variant_Record,In_Type
01f8 ; 0x0165 Execute Variant_Record,Convert
01f8 ; 0x0166 Execute Variant_Record,Component_Offset
01f8 ; 0x0167 Execute Variant_Record,Structure_Query
01f8 ; 0x0168 Execute Variant_Record,Reference_Makes_Copy
01f8 ; 0x0169 Execute Variant_Record,Read_Discriminant_Constraint
01f8 ; 0x016a Execute Variant_Record,Indirects_Appended
01f8 ; 0x016b Execute Variant_Record,Read_Variant
01f8 ; 0x016c Execute Variant_Record,Is_Constrained
01f8 ; 0x016d Execute Variant_Record,Structure_Write
01f8 ; 0x016e Execute Variant_Record,Not_Equal
01f8 ; 0x016f Execute Variant_Record,Equal
01f8 ; 0x0177 Execute Record,Field_Type_Dynamic
01f8 ; 0x0178 Execute Record,Field_Reference_Dynamic
01f8 ; 0x0179 Execute Record,Field_Write_Dynamic
01f8 ; 0x017a Execute Record,Field_Read_Dynamic
01f8 ; 0x017b Execute Record,Convert
01f8 ; 0x017c Execute Record,Component_Offset
01f8 ; 0x017d Execute Record,Structure_Write
01f8 ; 0x017e Execute Record,Not_Equal
01f8 ; 0x017f Execute Record,Equal
01f8 ; 0x0189 Execute Subvector,Field_Reference
01f8 ; 0x018a Execute Subvector,Field_Write
01f8 ; 0x018b Execute Subvector,Field_Read
01f8 ; 0x018d Execute Subarray,Field_Reference
01f8 ; 0x018e Execute Subarray,Field_Write
01f8 ; 0x018f Execute Subarray,Field_Read
01f8 ; 0x019b Execute Matrix,Check_In_Type
01f8 ; 0x019c Execute Matrix,Not_In_Type
01f8 ; 0x019d Execute Matrix,In_Type
01f8 ; 0x019e Execute Matrix,Convert_To_Formal
01f8 ; 0x019f Execute Matrix,Convert
01f8 ; 0x01a3 Execute Matrix,Subarray
01f8 ; 0x01a4 Execute Matrix,Structure_Write
01f8 ; 0x01a5 Execute Matrix,Field_Reference
01f8 ; 0x01a6 Execute Matrix,Field_Write
01f8 ; 0x01a7 Execute Matrix,Field_Read
01f8 ; 0x01a8 Execute Matrix,Element_Type
01f8 ; 0x01a9 Execute Matrix,Reverse_Bounds
01f8 ; 0x01aa Execute Matrix,Bounds
01f8 ; 0x01ab Execute Matrix,Length
01f8 ; 0x01ac Execute Matrix,Last
01f8 ; 0x01ad Execute Matrix,First
01f8 ; 0x01ae Execute Matrix,Not_Equal
01f8 ; 0x01af Execute Matrix,Equal
01f8 ; 0x01be Execute Vector,Hash
01f8 ; 0x01bf Execute Vector,Less_Equal
01f8 ; 0x01c3 Execute Vector,Check_In_Type
01f8 ; 0x01c4 Execute Vector,Not_In_Type
01f8 ; 0x01c5 Execute Vector,In_Type
01f8 ; 0x01c6 Execute Vector,Convert_To_Formal
01f8 ; 0x01c7 Execute Vector,Convert
01f8 ; 0x01ca Execute Vector,Prepend
01f8 ; 0x01cb Execute Vector,Append
01f8 ; 0x01cc Execute Vector,Catenate
01f8 ; 0x01cd Execute Vector,Slice_Reference
01f8 ; 0x01ce Execute Vector,Slice_Write
01f8 ; 0x01cf Execute Vector,Slice_Read
01f8 ; 0x01d3 Execute Vector,And
01f8 ; 0x01d4 Execute Vector,Structure_Write
01f8 ; 0x01d5 Execute Vector,Field_Reference
01f8 ; 0x01d6 Execute Vector,Field_Write
01f8 ; 0x01d7 Execute Vector,Field_Read
01f8 ; 0x01d8 Execute Vector,Element_Type
01f8 ; 0x01d9 Execute Vector,Reverse_Bounds
01f8 ; 0x01da Execute Vector,Bounds
01f8 ; 0x01db Execute Vector,Length
01f8 ; 0x01dc Execute Vector,Last
01f8 ; 0x01dd Execute Vector,First
01f8 ; 0x01de Execute Vector,Not_Equal
01f8 ; 0x01df Execute Vector,Equal
01f8 ; 0x01eb Execute Array,Check_In_Type
01f8 ; 0x01ec Execute Array,Not_In_Type
01f8 ; 0x01ed Execute Array,In_Type
01f8 ; 0x01ee Execute Array,Convert_To_Formal
01f8 ; 0x01ef Execute Array,Convert
01f8 ; 0x01f3 Execute Array,Subarray
01f8 ; 0x01f4 Execute Array,Structure_Write
01f8 ; 0x01f5 Execute Array,Field_Reference
01f8 ; 0x01f6 Execute Array,Field_Write
01f8 ; 0x01f7 Execute Array,Field_Read
01f8 ; 0x01f8 Execute Array,Element_Type
01f8 ; 0x01f9 Execute Array,Reverse_Bounds
01f8 ; 0x01fa Execute Array,Bounds
01f8 ; 0x01fb Execute Array,Length
01f8 ; 0x01fc Execute Array,Last
01f8 ; 0x01fd Execute Array,First
01f8 ; 0x01fe Execute Array,Not_Equal
01f8 ; 0x01ff Execute Array,Equal
01f8 ; 0x0206 Execute Module,Check_Elaborated
01f8 ; 0x0208 Execute Task,Abort_Multiple
01f8 ; 0x0209 Execute Task,Abort
01f8 ; 0x020a Execute Module,Get_Name
01f8 ; 0x020b Execute Module,Is_Terminated
01f8 ; 0x020c Execute Module,Is_Callable
01f8 ; 0x020d Execute Module,Elaborate
01f8 ; 0x020e Execute Module,Augment_Imports
01f8 ; 0x020f Execute Module,Activate
01f8 ; 0x0213 Execute Heap_Access,Check_In_Type
01f8 ; 0x0214 Execute Heap_Access,Not_In_Type
01f8 ; 0x0215 Execute Heap_Access,In_Type
01f8 ; 0x0216 Execute Heap_Access,Convert
01f8 ; 0x0217 Execute Heap_Access,All_Reference
01f8 ; 0x0218 Execute Heap_Access,All_Write
01f8 ; 0x0219 Execute Heap_Access,All_Read
01f8 ; 0x021a Execute Heap_Access,Element_Type
01f8 ; 0x021b Execute Heap_Access,Set_Null
01f8 ; 0x021c Execute Heap_Access,Not_Null
01f8 ; 0x021d Execute Heap_Access,Is_Null
01f8 ; 0x021e Execute Heap_Access,Maximum
01f8 ; 0x021f Execute Heap_Access,Equal
01f8 ; 0x0220 Execute Access,Deallocate
01f8 ; 0x0221 Execute Access,Allow_Deallocate
01f8 ; 0x0222 Execute Access,Convert_Reference
01f8 ; 0x0223 Execute Access,Check_In_Type
01f8 ; 0x0224 Execute Access,Not_In_Type
01f8 ; 0x0225 Execute Access,In_Type
01f8 ; 0x0226 Execute Access,Convert
01f8 ; 0x0227 Execute Access,All_Reference
01f8 ; 0x0228 Execute Access,All_Write
01f8 ; 0x0229 Execute Access,All_Read
01f8 ; 0x022a Execute Access,Element_Type
01f8 ; 0x022b Execute Access,Set_Null
01f8 ; 0x022c Execute Access,Not_Null
01f8 ; 0x022d Execute Access,Is_Null
01f8 ; 0x022e Execute Access,Not_Equal
01f8 ; 0x022f Execute Access,Equal
01f8 ; 0x0230 Execute Float,In_Range
01f8 ; 0x0231 Execute Float,Write_Unchecked
01f8 ; 0x0232 Execute Float,Check_In_Type
01f8 ; 0x0233 Execute Float,Not_In_Type
01f8 ; 0x0234 Execute Float,In_Type
01f8 ; 0x0235 Execute Float,Round_To_Discrete
01f8 ; 0x0236 Execute Float,Truncate_To_Discrete
01f8 ; 0x0237 Execute Float,Convert_From_Discrete
01f8 ; 0x0238 Execute Float,Convert
01f8 ; 0x0239 Execute Float,Exponentiate
01f8 ; 0x023a Execute Float,Divide
01f8 ; 0x023b Execute Float,Times
01f8 ; 0x023c Execute Float,Minus
01f8 ; 0x023d Execute Float,Plus
01f8 ; 0x023e Execute Float,Absolute_Value
01f8 ; 0x023f Execute Float,Unary_Minus
01f8 ; 0x0240 Execute Float,Last
01f8 ; 0x0241 Execute Float,First
01f8 ; 0x0242 Execute Float,Less_Equal
01f8 ; 0x0243 Execute Float,Greater_Equal
01f8 ; 0x0244 Execute Float,Less
01f8 ; 0x0245 Execute Float,Greater
01f8 ; 0x0246 Execute Float,Not_Equal
01f8 ; 0x0247 Execute Float,Equal
01f8 ; 0x0248 Execute Discrete,Check_In_Integer
01f8 ; 0x0249 Execute Discrete,Case_In_Range
01f8 ; 0x024a Execute Discrete,Is_Unsigned
01f8 ; 0x024b Execute Discrete,Count_Trailing_Zeros
01f8 ; 0x024c Execute Discrete,Count_Leading_Zeros
01f8 ; 0x024d Execute Discrete,Count_Nonzero_Bits
01f8 ; 0x024e Execute Discrete,Extract_Bits
01f8 ; 0x024f Execute Discrete,Insert_Bits
01f8 ; 0x0250 Execute Discrete,Rotate
01f8 ; 0x0251 Execute Discrete,Logical_Shift
01f8 ; 0x0252 Execute Discrete,Arithmetic_Shift
01f8 ; 0x0253 Execute Discrete,Binary_Scale
01f8 ; 0x0254 Execute Discrete,Partial_Minus
01f8 ; 0x0255 Execute Discrete,Partial_Plus
01f8 ; 0x0256 Execute Discrete,Instruction_Read
01f8 ; 0x0257 Execute Discrete,Raise,>R
01f8 ; 0x0258 Execute Discrete,Test_And_Set_Next
01f8 ; 0x0259 Execute Discrete,Test_And_Set_Previous
01f8 ; 0x025a Execute Discrete,Write_Unchecked
01f8 ; 0x025b Execute Discrete,Check_In_Type
01f8 ; 0x025c Execute Discrete,ReverseBounds_Check
01f8 ; 0x025d Execute Discrete,Bounds_Check
01f8 ; 0x025e Execute Discrete,Convert
01f8 ; 0x025f Execute Discrete,Not_In_Type
01f8 ; 0x0263 Execute Discrete,Above_Bound
01f8 ; 0x0264 Execute Discrete,Below_Bound
01f8 ; 0x0265 Execute Discrete,Reverse_Bounds
01f8 ; 0x0266 Execute Discrete,Bounds
01f8 ; 0x0267 Execute Discrete,Predecessor
01f8 ; 0x0268 Execute Discrete,Successor
01f8 ; 0x0269 Execute Discrete,Last
01f8 ; 0x026a Execute Discrete,First
01f8 ; 0x026b Execute Discrete,Maximum
01f8 ; 0x026c Execute Discrete,Minimum
01f8 ; 0x026d Execute Discrete,Exponentiate
01f8 ; 0x026e Execute Discrete,Modulo
01f8 ; 0x026f Execute Discrete,Remainder
01f8 ; 0x0273 Execute Discrete,Plus
01f8 ; 0x0274 Execute Discrete,Absolute_Value
01f8 ; 0x0275 Execute Discrete,Unary_Minus
01f8 ; 0x0276 Execute Discrete,Complement
01f8 ; 0x0277 Execute Discrete,Xor
01f8 ; 0x0278 Execute Discrete,Or
01f8 ; 0x0279 Execute Discrete,And
01f8 ; 0x027a Execute Discrete,Less_Equal
01f8 ; 0x027b Execute Discrete,Greater_Equal
01f8 ; 0x027c Execute Discrete,Less
01f8 ; 0x027d Execute Discrete,Greater
01f8 ; 0x027e Execute Discrete,Not_Equal
01f8 ; 0x027f Execute Discrete,Equal
01f8 ; 0x0299 Declare_Subprogram For_Accept,subp
01f8 ; 0x029a Declare_Subprogram For_Outer_Call,Visible,Unelaborated,subp
01f8 ; 0x029b Declare_Subprogram For_Outer_Call,Unelaborated,subp
01f8 ; 0x029c Declare_Subprogram For_Outer_Call,Visible,subp
01f8 ; 0x029d Declare_Subprogram For_Outer_Call,subp
01f8 ; 0x029e Declare_Subprogram For_Call,Unelaborated,subp
01f8 ; 0x029f Declare_Subprogram For_Call,subp
01f8 ; 0x02a4 Declare_Subprogram For_Outer_Call,Visible,With_Address
01f8 ; 0x02a5 Declare_Subprogram For_Outer_Call,With_Address
01f8 ; 0x02a8 Declare_Subprogram For_Call,Visible,Unelaborated,With_Address
01f8 ; 0x02a9 Declare_Subprogram For_Call,Unelaborated,With_Address
01f8 ; 0x02aa Declare_Subprogram For_Call,Visible,With_Address
01f8 ; 0x02ab Declare_Subprogram For_Call,With_Address
01f8 ; 0x02be Declare_Variable Float,Visible,With_Value,With_Constraint
01f8 ; 0x02bf Declare_Variable Float,With_Value,With_Constraint
01f8 ; 0x02c6 Declare_Variable Any,Visible
01f8 ; 0x02c7 Declare_Variable Any
01f8 ; 0x02c9 Declare_Variable Family
01f8 ; 0x02cb Declare_Variable Entry
01f8 ; 0x02ce Declare_Variable Select,Choice_Open
01f8 ; 0x02cf Declare_Variable Select
01f8 ; 0x02fb Declare_Variable Variant_Record,Visible,With_Constraint
01f8 ; 0x02fc Declare_Variable Variant_Record,With_Constraint
01f8 ; 0x02fd Declare_Variable Variant_Record,Duplicate
01f8 ; 0x02fe Declare_Variable Variant_Record,Visible
01f8 ; 0x02ff Declare_Variable Variant_Record
01f8 ; 0x0303 Complete_Type Variant_Record,By_Component_Completion
01f8 ; 0x0304 Complete_Type Variant_Record,By_Completing_Constraint
01f8 ; 0x0305 Complete_Type Variant_Record,By_Constraining_Incomplete
01f8 ; 0x0306 Complete_Type Variant_Record,By_Renaming
01f8 ; 0x0307 Complete_Type Variant_Record,By_Defining
01f8 ; 0x0311 Declare_Type Variant_Record,Constrained_Incomplete
01f8 ; 0x0312 Declare_Type Variant_Record,Constrained_Incomplete,Visible
01f8 ; 0x0315 Declare_Type Variant_Record,Defined_Incomplete
01f8 ; 0x0316 Declare_Type Variant_Record,Defined_Incomplete,Visible
01f8 ; 0x0318 Declare_Type Variant_Record,Incomplete
01f8 ; 0x0319 Declare_Type Variant_Record,Incomplete,Visible
01f8 ; 0x031b Declare_Type Variant_Record,Constrained
01f8 ; 0x031c Declare_Type Variant_Record,Constrained,Visible
01f8 ; 0x031d Declare_Type Variant_Record,Defined
01f8 ; 0x031e Declare_Type Variant_Record,Defined,Visible
01f8 ; 0x0321 Declare_Variable Record,Visible
01f8 ; 0x0322 Declare_Variable Record
01f8 ; 0x0324 Complete_Type Record,By_Component_Completion
01f8 ; 0x0325 Complete_Type Record,By_Renaming
01f8 ; 0x0326 Complete_Type Record,By_Defining
01f8 ; 0x0327 Declare_Type Record,Defined_Incomplete
01f8 ; 0x0328 Declare_Type Record,Defined_Incomplete,Visible
01f8 ; 0x032a Declare_Type Record,Incomplete
01f8 ; 0x032b Declare_Type Record,Incomplete,Visible
01f8 ; 0x032d Declare_Type Record,Defined
01f8 ; 0x032e Declare_Type Record,Defined,Visible
01f8 ; 0x0333 Declare_Variable Array,Visible,With_Constraint
01f8 ; 0x0334 Declare_Variable Array,With_Constraint
01f8 ; 0x0335 Declare_Variable Array,Duplicate
01f8 ; 0x0336 Declare_Variable Array,Visible
01f8 ; 0x0337 Declare_Variable Array
01f8 ; 0x0341 Complete_Type Array,By_Constraining
01f8 ; 0x0342 Complete_Type Array,By_Renaming
01f8 ; 0x0343 Complete_Type Array,By_Defining
01f8 ; 0x0346 Declare_Type Array,Constrained_Incomplete,Bounds_With_Object
01f8 ; 0x0347 Declare_Type Array,Constrained_Incomplete,Visible,Bounds_With_Object
01f8 ; 0x0348 Declare_Type Array,Defined_Incomplete,Bounds_With_Object
01f8 ; 0x0349 Declare_Type Array,Defined_Incomplete,Visible,Bounds_With_Object
01f8 ; 0x034b Declare_Type Array,Incomplete,Bounds_With_Object
01f8 ; 0x034c Declare_Type Array,Incomplete,Visible,Bounds_With_Object
01f8 ; 0x034e Declare_Type Array,Constrained,Bounds_With_Object
01f8 ; 0x034f Declare_Type Array,Constrained,Visible,Bounds_With_Object
01f8 ; 0x0353 Declare_Type Array,Constrained_Incomplete
01f8 ; 0x0354 Declare_Type Array,Constrained_Incomplete,Visible
01f8 ; 0x0355 Declare_Type Array,Defined_Incomplete
01f8 ; 0x0356 Declare_Type Array,Defined_Incomplete,Visible
01f8 ; 0x0358 Declare_Type Array,Incomplete
01f8 ; 0x0359 Declare_Type Array,Incomplete,Visible
01f8 ; 0x035b Declare_Type Array,Constrained
01f8 ; 0x035c Declare_Type Array,Constrained,Visible
01f8 ; 0x035d Declare_Type Array,Defined
01f8 ; 0x035e Declare_Type Array,Defined,Visible
01f8 ; 0x036a Declare_Variable Task,On_Processor,As_Component
01f8 ; 0x036b Declare_Variable Task,As_Component
01f8 ; 0x036c Declare_Variable Task,Visible,On_Processor
01f8 ; 0x036d Declare_Variable Task,On_Processor
01f8 ; 0x036e Declare_Variable Task,Visible
01f8 ; 0x036f Declare_Variable Task
01f8 ; 0x0374 Complete_Type Task,By_Renaming
01f8 ; 0x0377 Declare_Type Task,Incomplete
01f8 ; 0x0378 Declare_Type Task,Incomplete,Visible
01f8 ; 0x037a Declare_Type Task,Defined,Not_Elaborated
01f8 ; 0x037b Declare_Type Task,Defined,Visible,Not_Elaborated
01f8 ; 0x037d Declare_Type Task,Defined
01f8 ; 0x037e Declare_Type Task,Defined,Visible
01f8 ; 0x0384 Declare_Variable Package,Visible,On_Processor
01f8 ; 0x0385 Declare_Variable Package,On_Processor
01f8 ; 0x0386 Declare_Variable Package,Visible
01f8 ; 0x0387 Declare_Variable Package
01f8 ; 0x038c Declare_Type Package,Defined,Not_Elaborated
01f8 ; 0x038d Declare_Type Package,Defined,Visible,Not_Elaborated
01f8 ; 0x038e Declare_Type Package,Defined
01f8 ; 0x038f Declare_Type Package,Defined,Visible
01f8 ; 0x0395 Declare_Variable Heap_Access,Visible,By_Allocation,With_Value
01f8 ; 0x0396 Declare_Variable Heap_Access,By_Allocation,With_Value
01f8 ; 0x0397 Declare_Variable Heap_Access,Visible,By_Allocation,With_Subtype
01f8 ; 0x0398 Declare_Variable Heap_Access,By_Allocation,With_Subtype
01f8 ; 0x0399 Declare_Variable Heap_Access,Visible,By_Allocation,With_Constraint
01f8 ; 0x039a Declare_Variable Heap_Access,By_Allocation,With_Constraint
01f8 ; 0x039b Declare_Variable Heap_Access,Visible,By_Allocation
01f8 ; 0x039c Declare_Variable Heap_Access,By_Allocation
01f8 ; 0x039d Declare_Variable Heap_Access,Duplicate
01f8 ; 0x039e Declare_Variable Heap_Access,Visible
01f8 ; 0x039f Declare_Variable Heap_Access
01f8 ; 0x03a0 Complete_Type Heap_Access,By_Component_Completion
01f8 ; 0x03a1 Complete_Type Heap_Access,By_Constraining
01f8 ; 0x03a2 Complete_Type Heap_Access,By_Renaming
01f8 ; 0x03a3 Complete_Type Heap_Access,By_Defining
01f8 ; 0x03a4 Declare_Type Heap_Access,Incomplete,Values_Relative,With_Size
01f8 ; 0x03a5 Declare_Type Heap_Access,Incomplete,Values_Relative
01f8 ; 0x03a6 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative
01f8 ; 0x03a7 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative,With_Size
01f8 ; 0x03a8 Declare_Type Heap_Access,Incomplete
01f8 ; 0x03a9 Declare_Type Heap_Access,Incomplete,Visible
01f8 ; 0x03ab Declare_Type Heap_Access,Constrained
01f8 ; 0x03ac Declare_Type Heap_Access,Constrained,Visible
01f8 ; 0x03ad Declare_Type Heap_Access,Defined
01f8 ; 0x03ae Declare_Type Heap_Access,Defined,Visible
01f8 ; 0x03b5 Declare_Variable Access,Visible,By_Allocation,With_Value
01f8 ; 0x03b6 Declare_Variable Access,By_Allocation,With_Value
01f8 ; 0x03b7 Declare_Variable Access,Visible,By_Allocation,With_Subtype
01f8 ; 0x03b8 Declare_Variable Access,By_Allocation,With_Subtype
01f8 ; 0x03b9 Declare_Variable Access,Visible,By_Allocation,With_Constraint
01f8 ; 0x03ba Declare_Variable Access,By_Allocation,With_Constraint
01f8 ; 0x03bb Declare_Variable Access,Visible,By_Allocation
01f8 ; 0x03bc Declare_Variable Access,By_Allocation
01f8 ; 0x03bd Declare_Variable Access,Duplicate
01f8 ; 0x03be Declare_Variable Access,Visible
01f8 ; 0x03bf Declare_Variable Access
01f8 ; 0x03c4 Complete_Type Access,By_Component_Completion
01f8 ; 0x03c5 Complete_Type Access,By_Constraining
01f8 ; 0x03c6 Complete_Type Access,By_Renaming
01f8 ; 0x03c7 Complete_Type Access,By_Defining
01f8 ; 0x03cc Declare_Type Access,Incomplete,Accesses_Protected
01f8 ; 0x03cd Declare_Type Access,Incomplete,Visible,Accesses_Protected
01f8 ; 0x03ce Declare_Type Access,Incomplete
01f8 ; 0x03cf Declare_Type Access,Incomplete,Visible
01f8 ; 0x03d1 Declare_Type Access,Constrained
01f8 ; 0x03d2 Declare_Type Access,Constrained,Visible
01f8 ; 0x03d3 Declare_Type Access,Defined,Accesses_Protected
01f8 ; 0x03d4 Declare_Type Access,Defined,Visible,Accesses_Protected
01f8 ; 0x03d5 Declare_Type Access,Defined
01f8 ; 0x03d6 Declare_Type Access,Defined,Visible
01f8 ; 0x03d8 Declare_Variable Float,Duplicate
01f8 ; 0x03d9 Declare_Variable Float,Visible
01f8 ; 0x03da Declare_Variable Float
01f8 ; 0x03db Declare_Variable Float,Visible,With_Value
01f8 ; 0x03dc Complete_Type Float,By_Constraining
01f8 ; 0x03dd Complete_Type Float,By_Renaming
01f8 ; 0x03de Complete_Type Float,By_Defining
01f8 ; 0x03df Declare_Variable Float,With_Value
01f8 ; 0x03e0 Declare_Type Float,Incomplete
01f8 ; 0x03e1 Declare_Type Float,Incomplete,Visible
01f8 ; 0x03e3 Declare_Type Float,Constrained
01f8 ; 0x03e4 Declare_Type Float,Constrained,Visible
01f8 ; 0x03e5 Declare_Type Float,Defined
01f8 ; 0x03e6 Declare_Type Float,Defined,Visible
01f8 ; 0x03e8 Declare_Variable Discrete,Visible,With_Value,With_Constraint
01f8 ; 0x03e9 Declare_Variable Discrete,Duplicate
01f8 ; 0x03ea Declare_Variable Discrete,Visible
01f8 ; 0x03eb Declare_Variable Discrete
01f8 ; 0x03ec Declare_Variable Discrete,With_Value,With_Constraint
01f8 ; 0x03ed Complete_Type Discrete,By_Constraining
01f8 ; 0x03ee Complete_Type Discrete,By_Renaming
01f8 ; 0x03ef Complete_Type Discrete,By_Defining
01f8 ; 0x03f0 Declare_Variable Discrete,Visible,With_Value
01f8 ; 0x03f1 Declare_Variable Discrete,With_Value
01f8 ; 0x03f2 Declare_Variable Discrete,Incomplete,Unsigned
01f8 ; 0x03f3 Declare_Variable Discrete,Incomplete,Visible,Unsigned
01f8 ; 0x03f5 Declare_Variable Discrete,Incomplete
01f8 ; 0x03f6 Declare_Variable Discrete,Incomplete,Visible
01f8 ; 0x03f7 Declare_Type InMicrocode,Discrete
01f8 ; 0x03fc Declare_Type InMicrocode,Discrete
01f8 ; 0x03f8 Declare_Type Discrete,Constrained
01f8 ; 0x03f9 Declare_Type Discrete,Constrained,Visible
01f8 ; 0x03fa Declare_Type Discrete,Defined,With_Size
01f8 ; 0x03fb Declare_Type Discrete,Defined,Visible,With_Size
01f8 ; 0x03fd Declare_Type Discrete,Defined
01f8 ; 0x03fe Declare_Type Discrete,Defined,Visible
01f8 ; 0x0800-0x08ff Execute_Immediate Raise,uimmediate,>R
01f8 ; 0x0900-0x093f Execute_Immediate Binary_Scale,limitedpos
01f8 ; 0x0940-0x097f Execute_Immediate Logical_Shift,limitedneg
01f8 ; 0x0980-0x09bf Execute_Immediate Logical_Shift,limitedpos
01f8 ; 0x09c0-0x09ff Execute_Immediate Binary_Scale,limitedneg
01f8 ; 0x0a00-0x0aff Execute_Immediate Plus,s8
01f8 ; 0x0b00-0x0bff Execute_Immediate Case_Compare,uimmediate
01f8 ; 0x0c00-0x0cff Execute_Immediate Greater_Equal,uimmediate
01f8 ; 0x0d00-0x0dff Execute_Immediate Less,uimmediate
01f8 ; 0x0e00-0x0eff Execute_Immediate Not_Equal,uimmediate
01f8 ; 0x0f00-0x0fbf Execute_Immediate Equal,uimmediate
01f8 ; 0x1000-0x10ff Execute Select,Guard_Write,fieldnum
01f8 ; 0x1100-0x11ff Execute Select,Member_Write,fieldnum
01f8 ; 0x1200-0x12ff Execute Task,Family_Timed,fieldnum
01f8 ; 0x1300-0x13ff Execute Task,Family_Cond,fieldnum
01f8 ; 0x1400-0x14ff Execute Task,Family_Call,fieldnum
01f8 ; 0x1500-0x15ff Execute Task,Timed_Call,fieldnum
01f8 ; 0x1600-0x16ff Execute Task,Conditional_Call,fieldnum
01f8 ; 0x1700-0x17ff Execute Task,Entry_Call,fieldnum
01f8 ; 0x1800-0x18ff Execute Package,Field_Execute,fieldnum
01f8 ; 0x1900-0x19ff Execute Package,Field_Reference,fieldnum
01f8 ; 0x1a00-0x1aff Execute Package,Field_Write,fieldnum
01f8 ; 0x1b00-0x1bff Execute Package,Field_Read,fieldnum
01f8 ; 0x1c00-0x1cff Execute_Immediate Run_Utility,uimmediate
01f8 ; 0x1d00-0x1dff Execute_Immediate Reference_Lex_1,uimmediate
01f8 ; 0x2000-0x20ff Execute Variant_Record,Set_Variant,fieldnum
01f8 ; 0x2100-0x21ff Execute Variant_Record,Set_Bounds,fieldnum
01f8 ; 0x2200-0x22ff Execute Variant_Record,Field_Constrain,fieldnum
01f8 ; 0x2300-0x23ff Execute Variant_Record,Field_Type,fieldnum
01f8 ; 0x2400-0x24ff Execute Variant_Record,Field_Reference,Fixed,Direct,fieldnum
01f8 ; 0x2500-0x25ff Execute Variant_Record,Field_Reference,Fixed,Indirect,fieldnum
01f8 ; 0x2600-0x26ff Execute Variant_Record,Field_Reference,Variant,Direct,fieldnum
01f8 ; 0x2700-0x27ff Execute Variant_Record,Field_Reference,Variant,Indirect,fieldnum
01f8 ; 0x2800-0x28ff Execute Variant_Record,Field_Write,Fixed,Direct,fieldnum
01f8 ; 0x2900-0x29ff Execute Variant_Record,Field_Write,Fixed,Indirect,fieldnum
01f8 ; 0x2a00-0x2aff Execute Variant_Record,Field_Write,Variant,Direct,fieldnum
01f8 ; 0x2b00-0x2bff Execute Variant_Record,Field_Write,Variant,Indirect,fieldnum
01f8 ; 0x2c00-0x2cff Execute Variant_Record,Field_Read,Fixed,Direct,fieldnum
01f8 ; 0x2d00-0x2dff Execute Variant_Record,Field_Append,Fixed,Indirect,fieldnum
01f8 ; 0x2e00-0x2eff Execute Variant_Record,Field_Read,Variant,Direct,fieldnum
01f8 ; 0x2f00-0x2fff Execute Variant_Record,Field_Append,Variant,Indirect,fieldnum
01f8 ; 0x3000-0x30ff Execute Record,Field_Type,fieldnum
01f8 ; 0x3400-0x34ff Execute Record,Field_Reference,fieldnum
01f8 ; 0x3600-0x37ff Loop_Decreasing pcrelneg,>JC
01f8 ; 0x3800-0x38ff Execute Record,Field_Write,fieldnum
01f8 ; 0x3c00-0x3cff Execute Record,Field_Read,fieldnum
01f8 ; 0x3e00-0x3fff Loop_Increasing pcrelneg,>JC
01f8 ; 0x4100-0x41ff End_Rendezvous >R,parmcnt
01f8 ; 0x4200-0x42ff Exit_Subprogram From_Utility,With_Result,>R,topoffset
01f8 ; 0x4300-0x43ff Exit_Subprogram From_Utility,>R,topoffset
01f8 ; 0x4400-0x44ff Exit_Subprogram With_Result,>R,topoffset
01f8 ; 0x4500-0x45ff Exit_Subprogram topoffset,>R
01f8 ; 0x4600-0x47ff Jump_Case case_max
01f8 ; 0x4800-0x4fff Short_Literal slit
01f8 ; 0x5000-0x57ff Indirect_Literal Any,pcrel,literal
01f8 ; 0x5800-0x5fff Indirect_Literal Float,pcrel,dbl
01f8 ; 0x6000-0x67ff Indirect_Literal Discrete,pcrel,literal
01f8 ; 0x6800-0x6fff Jump_Zero pcrel,>JC
01f8 ; 0x7000-0x77ff Jump_Nonzero pcrel,>JC
01f8 ; 0x7800-0x7fff Jump pcrel,>J
01f8 ; 0x8040-0x81ff Call llvl,ldelta
01f8 ; 0x8240-0x83ff Call llvl,ldelta
01f8 ; 0x8440-0x85ff Call llvl,ldelta
01f8 ; 0x8640-0x9fff Call llvl,ldelta
01f8 ; 0xa040-0xa1ff Reference zdelta
01f8 ; 0xa240-0xa3ff Store_Unchecked llvl,ldelta
01f8 ; 0xa440-0xa5ff Store_Unchecked llvl,ldelta
01f8 ; 0xa640-0xbfff Store_Unchecked llvl,ldelta
01f8 ; 0xc000-0xcfff Store llvl,ldelta
01f8 ; 0xd040-0xdfff Store llvl,ldelta
01f8 ; 0xfe40-0xffff Load llvl,ldelta
01f8 ; --------------------------------------------------------------------------------------
01f8 MACRO_01f8_QQUnknown_InMicrocode:
01f8 MACRO_Action_Accept_Activation:
01f8 MACRO_Action_Activate_Heap_Tasks:
01f8 MACRO_Action_Activate_Tasks:
01f8 MACRO_Action_Alter_Break_Mask:
01f8 MACRO_Action_Break_Optional:
01f8 MACRO_Action_Break_Unconditional:
01f8 MACRO_Action_Call_Dynamic:
01f8 MACRO_Action_Check_Subprogram_Elaborated:
01f8 MACRO_Action_Elaborate_Subprogram:
01f8 MACRO_Action_Establish_Frame:
01f8 MACRO_Action_Exit_Break:
01f8 MACRO_Action_Exit_Nullary_Function,>R:
01f8 MACRO_Action_Get_Priority:
01f8 MACRO_Action_Idle:
01f8 MACRO_Action_InMicrocode,Package,Field_Execute_Dynamic:
01f8 MACRO_Action_Increase_Priority:
01f8 MACRO_Action_Initiate_Delay:
01f8 MACRO_Action_Jump_Dynamic:
01f8 MACRO_Action_Jump_Extended,abs,>J:
01f8 MACRO_Action_Jump_Nonzero_Dynamic:
01f8 MACRO_Action_Jump_Nonzero_Extended,abs,>JC:
01f8 MACRO_Action_Jump_Zero_Dynamic:
01f8 MACRO_Action_Jump_Zero_Extended,abs,>JC:
01f8 MACRO_Action_Load_Dynamic:
01f8 MACRO_Action_Loop_Decreasing_Extended,abs,>JC:
01f8 MACRO_Action_Loop_Increasing_Extended,abs,>JC:
01f8 MACRO_Action_Make_Default:
01f8 MACRO_Action_Make_Parent:
01f8 MACRO_Action_Make_Scope:
01f8 MACRO_Action_Make_Self:
01f8 MACRO_Action_Mark_Auxiliary:
01f8 MACRO_Action_Name_Partner:
01f8 MACRO_Action_Pop_Auxiliary:
01f8 MACRO_Action_Pop_Auxiliary_Loop:
01f8 MACRO_Action_Pop_Auxiliary_Range:
01f8 MACRO_Action_Pop_Block:
01f8 MACRO_Action_Pop_Block_With_Result:
01f8 MACRO_Action_Push_Discrete_Extended:
01f8 MACRO_Action_Push_Float_Extended:
01f8 MACRO_Action_Push_String_Extended,pse:
01f8 MACRO_Action_Push_String_Extended_Indexed,pse:
01f8 MACRO_Action_Push_Structure_Extended,abs,mark:
01f8 MACRO_Action_Query_Break_Address:
01f8 MACRO_Action_Query_Break_Cause:
01f8 MACRO_Action_Query_Break_Mask:
01f8 MACRO_Action_Query_Frame:
01f8 MACRO_Action_Reference_Dynamic:
01f8 MACRO_Action_Set_Block_Start:
01f8 MACRO_Action_Set_Priority:
01f8 MACRO_Action_Signal_Activated:
01f8 MACRO_Action_Signal_Completion,>R:
01f8 MACRO_Action_Spare6_Action:
01f8 MACRO_Action_Store_Dynamic:
01f8 MACRO_Action_Store_String_Extended,pse:
01f8 MACRO_Action_Swap_Control:
01f8 MACRO_Call_llvl,ldelta:
01f8 MACRO_Complete_Type_Access,By_Component_Completion:
01f8 MACRO_Complete_Type_Access,By_Constraining:
01f8 MACRO_Complete_Type_Access,By_Defining:
01f8 MACRO_Complete_Type_Access,By_Renaming:
01f8 MACRO_Complete_Type_Array,By_Constraining:
01f8 MACRO_Complete_Type_Array,By_Defining:
01f8 MACRO_Complete_Type_Array,By_Renaming:
01f8 MACRO_Complete_Type_Discrete,By_Constraining:
01f8 MACRO_Complete_Type_Discrete,By_Defining:
01f8 MACRO_Complete_Type_Discrete,By_Renaming:
01f8 MACRO_Complete_Type_Float,By_Constraining:
01f8 MACRO_Complete_Type_Float,By_Defining:
01f8 MACRO_Complete_Type_Float,By_Renaming:
01f8 MACRO_Complete_Type_Heap_Access,By_Component_Completion:
01f8 MACRO_Complete_Type_Heap_Access,By_Constraining:
01f8 MACRO_Complete_Type_Heap_Access,By_Defining:
01f8 MACRO_Complete_Type_Heap_Access,By_Renaming:
01f8 MACRO_Complete_Type_Record,By_Component_Completion:
01f8 MACRO_Complete_Type_Record,By_Defining:
01f8 MACRO_Complete_Type_Record,By_Renaming:
01f8 MACRO_Complete_Type_Task,By_Renaming:
01f8 MACRO_Complete_Type_Variant_Record,By_Completing_Constraint:
01f8 MACRO_Complete_Type_Variant_Record,By_Component_Completion:
01f8 MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete:
01f8 MACRO_Complete_Type_Variant_Record,By_Defining:
01f8 MACRO_Complete_Type_Variant_Record,By_Renaming:
01f8 MACRO_Declare_Subprogram_For_Accept,subp:
01f8 MACRO_Declare_Subprogram_For_Call,Unelaborated,With_Address:
01f8 MACRO_Declare_Subprogram_For_Call,Unelaborated,subp:
01f8 MACRO_Declare_Subprogram_For_Call,Visible,Unelaborated,With_Address:
01f8 MACRO_Declare_Subprogram_For_Call,Visible,With_Address:
01f8 MACRO_Declare_Subprogram_For_Call,With_Address:
01f8 MACRO_Declare_Subprogram_For_Call,subp:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,Unelaborated,subp:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,Unelaborated,subp:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,With_Address:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,Visible,subp:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,With_Address:
01f8 MACRO_Declare_Subprogram_For_Outer_Call,subp:
01f8 MACRO_Declare_Type_Access,Constrained:
01f8 MACRO_Declare_Type_Access,Constrained,Visible:
01f8 MACRO_Declare_Type_Access,Defined:
01f8 MACRO_Declare_Type_Access,Defined,Accesses_Protected:
01f8 MACRO_Declare_Type_Access,Defined,Visible:
01f8 MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected:
01f8 MACRO_Declare_Type_Access,Incomplete:
01f8 MACRO_Declare_Type_Access,Incomplete,Accesses_Protected:
01f8 MACRO_Declare_Type_Access,Incomplete,Visible:
01f8 MACRO_Declare_Type_Access,Incomplete,Visible,Accesses_Protected:
01f8 MACRO_Declare_Type_Array,Constrained:
01f8 MACRO_Declare_Type_Array,Constrained,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Constrained,Visible:
01f8 MACRO_Declare_Type_Array,Constrained,Visible,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Constrained_Incomplete:
01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible:
01f8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Defined:
01f8 MACRO_Declare_Type_Array,Defined,Visible:
01f8 MACRO_Declare_Type_Array,Defined_Incomplete:
01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Visible:
01f8 MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Incomplete:
01f8 MACRO_Declare_Type_Array,Incomplete,Bounds_With_Object:
01f8 MACRO_Declare_Type_Array,Incomplete,Visible:
01f8 MACRO_Declare_Type_Array,Incomplete,Visible,Bounds_With_Object:
01f8 MACRO_Declare_Type_Discrete,Constrained:
01f8 MACRO_Declare_Type_Discrete,Constrained,Visible:
01f8 MACRO_Declare_Type_Discrete,Defined:
01f8 MACRO_Declare_Type_Discrete,Defined,Visible:
01f8 MACRO_Declare_Type_Discrete,Defined,Visible,With_Size:
01f8 MACRO_Declare_Type_Discrete,Defined,With_Size:
01f8 MACRO_Declare_Type_Float,Constrained:
01f8 MACRO_Declare_Type_Float,Constrained,Visible:
01f8 MACRO_Declare_Type_Float,Defined:
01f8 MACRO_Declare_Type_Float,Defined,Visible:
01f8 MACRO_Declare_Type_Float,Incomplete:
01f8 MACRO_Declare_Type_Float,Incomplete,Visible:
01f8 MACRO_Declare_Type_Heap_Access,Constrained:
01f8 MACRO_Declare_Type_Heap_Access,Constrained,Visible:
01f8 MACRO_Declare_Type_Heap_Access,Defined:
01f8 MACRO_Declare_Type_Heap_Access,Defined,Visible:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative,With_Size:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative:
01f8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative,With_Size:
01f8 MACRO_Declare_Type_InMicrocode,Discrete:
01f8 MACRO_Declare_Type_Package,Defined:
01f8 MACRO_Declare_Type_Package,Defined,Not_Elaborated:
01f8 MACRO_Declare_Type_Package,Defined,Visible:
01f8 MACRO_Declare_Type_Package,Defined,Visible,Not_Elaborated:
01f8 MACRO_Declare_Type_Record,Defined:
01f8 MACRO_Declare_Type_Record,Defined,Visible:
01f8 MACRO_Declare_Type_Record,Defined_Incomplete:
01f8 MACRO_Declare_Type_Record,Defined_Incomplete,Visible:
01f8 MACRO_Declare_Type_Record,Incomplete:
01f8 MACRO_Declare_Type_Record,Incomplete,Visible:
01f8 MACRO_Declare_Type_Task,Defined:
01f8 MACRO_Declare_Type_Task,Defined,Not_Elaborated:
01f8 MACRO_Declare_Type_Task,Defined,Visible:
01f8 MACRO_Declare_Type_Task,Defined,Visible,Not_Elaborated:
01f8 MACRO_Declare_Type_Task,Incomplete:
01f8 MACRO_Declare_Type_Task,Incomplete,Visible:
01f8 MACRO_Declare_Type_Variant_Record,Constrained:
01f8 MACRO_Declare_Type_Variant_Record,Constrained,Visible:
01f8 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete:
01f8 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete,Visible:
01f8 MACRO_Declare_Type_Variant_Record,Defined:
01f8 MACRO_Declare_Type_Variant_Record,Defined,Visible:
01f8 MACRO_Declare_Type_Variant_Record,Defined_Incomplete:
01f8 MACRO_Declare_Type_Variant_Record,Defined_Incomplete,Visible:
01f8 MACRO_Declare_Type_Variant_Record,Incomplete:
01f8 MACRO_Declare_Type_Variant_Record,Incomplete,Visible:
01f8 MACRO_Declare_Variable_Access:
01f8 MACRO_Declare_Variable_Access,By_Allocation:
01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Constraint:
01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Subtype:
01f8 MACRO_Declare_Variable_Access,By_Allocation,With_Value:
01f8 MACRO_Declare_Variable_Access,Duplicate:
01f8 MACRO_Declare_Variable_Access,Visible:
01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation:
01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint:
01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype:
01f8 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value:
01f8 MACRO_Declare_Variable_Any:
01f8 MACRO_Declare_Variable_Any,Visible:
01f8 MACRO_Declare_Variable_Array:
01f8 MACRO_Declare_Variable_Array,Duplicate:
01f8 MACRO_Declare_Variable_Array,Visible:
01f8 MACRO_Declare_Variable_Array,Visible,With_Constraint:
01f8 MACRO_Declare_Variable_Array,With_Constraint:
01f8 MACRO_Declare_Variable_Discrete:
01f8 MACRO_Declare_Variable_Discrete,Duplicate:
01f8 MACRO_Declare_Variable_Discrete,Incomplete:
01f8 MACRO_Declare_Variable_Discrete,Incomplete,Unsigned:
01f8 MACRO_Declare_Variable_Discrete,Incomplete,Visible:
01f8 MACRO_Declare_Variable_Discrete,Incomplete,Visible,Unsigned:
01f8 MACRO_Declare_Variable_Discrete,Visible:
01f8 MACRO_Declare_Variable_Discrete,Visible,With_Value:
01f8 MACRO_Declare_Variable_Discrete,Visible,With_Value,With_Constraint:
01f8 MACRO_Declare_Variable_Discrete,With_Value:
01f8 MACRO_Declare_Variable_Discrete,With_Value,With_Constraint:
01f8 MACRO_Declare_Variable_Entry:
01f8 MACRO_Declare_Variable_Family:
01f8 MACRO_Declare_Variable_Float:
01f8 MACRO_Declare_Variable_Float,Duplicate:
01f8 MACRO_Declare_Variable_Float,Visible:
01f8 MACRO_Declare_Variable_Float,Visible,With_Value:
01f8 MACRO_Declare_Variable_Float,Visible,With_Value,With_Constraint:
01f8 MACRO_Declare_Variable_Float,With_Value:
01f8 MACRO_Declare_Variable_Float,With_Value,With_Constraint:
01f8 MACRO_Declare_Variable_Heap_Access:
01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation:
01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint:
01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype:
01f8 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value:
01f8 MACRO_Declare_Variable_Heap_Access,Duplicate:
01f8 MACRO_Declare_Variable_Heap_Access,Visible:
01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation:
01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint:
01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype:
01f8 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value:
01f8 MACRO_Declare_Variable_Package:
01f8 MACRO_Declare_Variable_Package,On_Processor:
01f8 MACRO_Declare_Variable_Package,Visible:
01f8 MACRO_Declare_Variable_Package,Visible,On_Processor:
01f8 MACRO_Declare_Variable_Record:
01f8 MACRO_Declare_Variable_Record,Visible:
01f8 MACRO_Declare_Variable_Select:
01f8 MACRO_Declare_Variable_Select,Choice_Open:
01f8 MACRO_Declare_Variable_Task:
01f8 MACRO_Declare_Variable_Task,As_Component:
01f8 MACRO_Declare_Variable_Task,On_Processor:
01f8 MACRO_Declare_Variable_Task,On_Processor,As_Component:
01f8 MACRO_Declare_Variable_Task,Visible:
01f8 MACRO_Declare_Variable_Task,Visible,On_Processor:
01f8 MACRO_Declare_Variable_Variant_Record:
01f8 MACRO_Declare_Variable_Variant_Record,Duplicate:
01f8 MACRO_Declare_Variable_Variant_Record,Visible:
01f8 MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint:
01f8 MACRO_Declare_Variable_Variant_Record,With_Constraint:
01f8 MACRO_End_Rendezvous_>R,parmcnt:
01f8 MACRO_Execute_Access,All_Read:
01f8 MACRO_Execute_Access,All_Reference:
01f8 MACRO_Execute_Access,All_Write:
01f8 MACRO_Execute_Access,Allow_Deallocate:
01f8 MACRO_Execute_Access,Check_In_Type:
01f8 MACRO_Execute_Access,Convert:
01f8 MACRO_Execute_Access,Convert_Reference:
01f8 MACRO_Execute_Access,Deallocate:
01f8 MACRO_Execute_Access,Element_Type:
01f8 MACRO_Execute_Access,Equal:
01f8 MACRO_Execute_Access,In_Type:
01f8 MACRO_Execute_Access,Is_Null:
01f8 MACRO_Execute_Access,Not_Equal:
01f8 MACRO_Execute_Access,Not_In_Type:
01f8 MACRO_Execute_Access,Not_Null:
01f8 MACRO_Execute_Access,Set_Null:
01f8 MACRO_Execute_Access,Size:
01f8 MACRO_Execute_Any,Address:
01f8 MACRO_Execute_Any,Address_Of_Type:
01f8 MACRO_Execute_Any,Change_Utility:
01f8 MACRO_Execute_Any,Check_In_Formal_Type:
01f8 MACRO_Execute_Any,Convert:
01f8 MACRO_Execute_Any,Convert_To_Formal:
01f8 MACRO_Execute_Any,Convert_Unchecked:
01f8 MACRO_Execute_Any,Equal:
01f8 MACRO_Execute_Any,Has_Default_Initialization:
01f8 MACRO_Execute_Any,In_Type:
01f8 MACRO_Execute_Any,Is_Constrained:
01f8 MACRO_Execute_Any,Is_Scalar:
01f8 MACRO_Execute_Any,Make_Aligned:
01f8 MACRO_Execute_Any,Make_Visible:
01f8 MACRO_Execute_Any,Not_Equal:
01f8 MACRO_Execute_Any,Not_In_Type:
01f8 MACRO_Execute_Any,Run_Initialization_Utility:
01f8 MACRO_Execute_Any,Set_Constraint:
01f8 MACRO_Execute_Any,Size:
01f8 MACRO_Execute_Any,Spare14:
01f8 MACRO_Execute_Any,Structure_Clear:
01f8 MACRO_Execute_Any,Structure_Query:
01f8 MACRO_Execute_Any,Write_Unchecked:
01f8 MACRO_Execute_Array,Bounds:
01f8 MACRO_Execute_Array,Check_In_Type:
01f8 MACRO_Execute_Array,Convert:
01f8 MACRO_Execute_Array,Convert_To_Formal:
01f8 MACRO_Execute_Array,Element_Type:
01f8 MACRO_Execute_Array,Equal:
01f8 MACRO_Execute_Array,Field_Read:
01f8 MACRO_Execute_Array,Field_Reference:
01f8 MACRO_Execute_Array,Field_Write:
01f8 MACRO_Execute_Array,First:
01f8 MACRO_Execute_Array,In_Type:
01f8 MACRO_Execute_Array,Last:
01f8 MACRO_Execute_Array,Length:
01f8 MACRO_Execute_Array,Not_Equal:
01f8 MACRO_Execute_Array,Not_In_Type:
01f8 MACRO_Execute_Array,Reverse_Bounds:
01f8 MACRO_Execute_Array,Structure_Write:
01f8 MACRO_Execute_Array,Subarray:
01f8 MACRO_Execute_Discrete,Above_Bound:
01f8 MACRO_Execute_Discrete,Absolute_Value:
01f8 MACRO_Execute_Discrete,And:
01f8 MACRO_Execute_Discrete,Arithmetic_Shift:
01f8 MACRO_Execute_Discrete,Below_Bound:
01f8 MACRO_Execute_Discrete,Binary_Scale:
01f8 MACRO_Execute_Discrete,Bounds:
01f8 MACRO_Execute_Discrete,Bounds_Check:
01f8 MACRO_Execute_Discrete,Case_In_Range:
01f8 MACRO_Execute_Discrete,Check_In_Integer:
01f8 MACRO_Execute_Discrete,Check_In_Type:
01f8 MACRO_Execute_Discrete,Complement:
01f8 MACRO_Execute_Discrete,Convert:
01f8 MACRO_Execute_Discrete,Count_Leading_Zeros:
01f8 MACRO_Execute_Discrete,Count_Nonzero_Bits:
01f8 MACRO_Execute_Discrete,Count_Trailing_Zeros:
01f8 MACRO_Execute_Discrete,Diana_Arity_For_Kind:
01f8 MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci:
01f8 MACRO_Execute_Discrete,Diana_Spare0:
01f8 MACRO_Execute_Discrete,Diana_Spare1:
01f8 MACRO_Execute_Discrete,Diana_Spare2:
01f8 MACRO_Execute_Discrete,Divide_And_Scale:
01f8 MACRO_Execute_Discrete,Equal:
01f8 MACRO_Execute_Discrete,Exponentiate:
01f8 MACRO_Execute_Discrete,Extract_Bits:
01f8 MACRO_Execute_Discrete,First:
01f8 MACRO_Execute_Discrete,Greater:
01f8 MACRO_Execute_Discrete,Greater_Equal:
01f8 MACRO_Execute_Discrete,Insert_Bits:
01f8 MACRO_Execute_Discrete,Instruction_Read:
01f8 MACRO_Execute_Discrete,Is_Unsigned:
01f8 MACRO_Execute_Discrete,Last:
01f8 MACRO_Execute_Discrete,Less:
01f8 MACRO_Execute_Discrete,Less_Equal:
01f8 MACRO_Execute_Discrete,Logical_Shift:
01f8 MACRO_Execute_Discrete,Maximum:
01f8 MACRO_Execute_Discrete,Minimum:
01f8 MACRO_Execute_Discrete,Modulo:
01f8 MACRO_Execute_Discrete,Multiply_And_Scale:
01f8 MACRO_Execute_Discrete,Not_Equal:
01f8 MACRO_Execute_Discrete,Not_In_Type:
01f8 MACRO_Execute_Discrete,Or:
01f8 MACRO_Execute_Discrete,Partial_Minus:
01f8 MACRO_Execute_Discrete,Partial_Plus:
01f8 MACRO_Execute_Discrete,Plus:
01f8 MACRO_Execute_Discrete,Predecessor:
01f8 MACRO_Execute_Discrete,Raise,>R:
01f8 MACRO_Execute_Discrete,Remainder:
01f8 MACRO_Execute_Discrete,ReverseBounds_Check:
01f8 MACRO_Execute_Discrete,Reverse_Bounds:
01f8 MACRO_Execute_Discrete,Rotate:
01f8 MACRO_Execute_Discrete,Successor:
01f8 MACRO_Execute_Discrete,Test_And_Set_Next:
01f8 MACRO_Execute_Discrete,Test_And_Set_Previous:
01f8 MACRO_Execute_Discrete,Unary_Minus:
01f8 MACRO_Execute_Discrete,Write_Unchecked:
01f8 MACRO_Execute_Discrete,Xor:
01f8 MACRO_Execute_Entry,Count:
01f8 MACRO_Execute_Entry,Rendezvous:
01f8 MACRO_Execute_Exception,Address:
01f8 MACRO_Execute_Exception,Equal:
01f8 MACRO_Execute_Exception,Get_Name:
01f8 MACRO_Execute_Exception,Is_Constraint_Error:
01f8 MACRO_Execute_Exception,Is_Instruction_Error:
01f8 MACRO_Execute_Exception,Is_Numeric_Error:
01f8 MACRO_Execute_Exception,Is_Program_Error:
01f8 MACRO_Execute_Exception,Is_Storage_Error:
01f8 MACRO_Execute_Exception,Is_Tasking_Error:
01f8 MACRO_Execute_Family,Count:
01f8 MACRO_Execute_Family,Rendezvous:
01f8 MACRO_Execute_Float,Absolute_Value:
01f8 MACRO_Execute_Float,Check_In_Type:
01f8 MACRO_Execute_Float,Convert:
01f8 MACRO_Execute_Float,Convert_From_Discrete:
01f8 MACRO_Execute_Float,Divide:
01f8 MACRO_Execute_Float,Equal:
01f8 MACRO_Execute_Float,Equal_Zero:
01f8 MACRO_Execute_Float,Exponentiate:
01f8 MACRO_Execute_Float,First:
01f8 MACRO_Execute_Float,Greater:
01f8 MACRO_Execute_Float,Greater_Equal:
01f8 MACRO_Execute_Float,Greater_Equal_Zero:
01f8 MACRO_Execute_Float,Greater_Zero:
01f8 MACRO_Execute_Float,In_Range:
01f8 MACRO_Execute_Float,In_Type:
01f8 MACRO_Execute_Float,Last:
01f8 MACRO_Execute_Float,Less:
01f8 MACRO_Execute_Float,Less_Equal:
01f8 MACRO_Execute_Float,Less_Equal_Zero:
01f8 MACRO_Execute_Float,Less_Zero:
01f8 MACRO_Execute_Float,Minus:
01f8 MACRO_Execute_Float,Not_Equal:
01f8 MACRO_Execute_Float,Not_Equal_Zero:
01f8 MACRO_Execute_Float,Not_In_Range:
01f8 MACRO_Execute_Float,Not_In_Type:
01f8 MACRO_Execute_Float,Plus:
01f8 MACRO_Execute_Float,Round_To_Discrete:
01f8 MACRO_Execute_Float,Times:
01f8 MACRO_Execute_Float,Truncate_To_Discrete:
01f8 MACRO_Execute_Float,Unary_Minus:
01f8 MACRO_Execute_Float,Write_Unchecked:
01f8 MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup:
01f8 MACRO_Execute_Heap_Access,All_Read:
01f8 MACRO_Execute_Heap_Access,All_Reference:
01f8 MACRO_Execute_Heap_Access,All_Write:
01f8 MACRO_Execute_Heap_Access,Check_In_Type:
01f8 MACRO_Execute_Heap_Access,Construct_Segment:
01f8 MACRO_Execute_Heap_Access,Convert:
01f8 MACRO_Execute_Heap_Access,Diana_Allocate_Tree_Node:
01f8 MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute:
01f8 MACRO_Execute_Heap_Access,Diana_Put_Node_On_Seq_Type:
01f8 MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head:
01f8 MACRO_Execute_Heap_Access,Diana_Spare2:
01f8 MACRO_Execute_Heap_Access,Diana_Tree_Kind:
01f8 MACRO_Execute_Heap_Access,Element_Type:
01f8 MACRO_Execute_Heap_Access,Equal:
01f8 MACRO_Execute_Heap_Access,Get_Name:
01f8 MACRO_Execute_Heap_Access,Get_Offset:
01f8 MACRO_Execute_Heap_Access,Hash:
01f8 MACRO_Execute_Heap_Access,In_Type:
01f8 MACRO_Execute_Heap_Access,Is_Null:
01f8 MACRO_Execute_Heap_Access,Maximum:
01f8 MACRO_Execute_Heap_Access,Not_In_Type:
01f8 MACRO_Execute_Heap_Access,Not_Null:
01f8 MACRO_Execute_Heap_Access,Set_Null:
01f8 MACRO_Execute_Immediate_Binary_Scale,limitedneg:
01f8 MACRO_Execute_Immediate_Binary_Scale,limitedpos:
01f8 MACRO_Execute_Immediate_Case_Compare,uimmediate:
01f8 MACRO_Execute_Immediate_Equal,uimmediate:
01f8 MACRO_Execute_Immediate_Greater_Equal,uimmediate:
01f8 MACRO_Execute_Immediate_Less,uimmediate:
01f8 MACRO_Execute_Immediate_Logical_Shift,limitedneg:
01f8 MACRO_Execute_Immediate_Logical_Shift,limitedpos:
01f8 MACRO_Execute_Immediate_Not_Equal,uimmediate:
01f8 MACRO_Execute_Immediate_Plus,s8:
01f8 MACRO_Execute_Immediate_Raise,uimmediate,>R:
01f8 MACRO_Execute_Immediate_Reference_Lex_1,uimmediate:
01f8 MACRO_Execute_Immediate_Run_Utility,uimmediate:
01f8 MACRO_Execute_Matrix,Bounds:
01f8 MACRO_Execute_Matrix,Check_In_Type:
01f8 MACRO_Execute_Matrix,Convert:
01f8 MACRO_Execute_Matrix,Convert_To_Formal:
01f8 MACRO_Execute_Matrix,Element_Type:
01f8 MACRO_Execute_Matrix,Equal:
01f8 MACRO_Execute_Matrix,Field_Read:
01f8 MACRO_Execute_Matrix,Field_Reference:
01f8 MACRO_Execute_Matrix,Field_Write:
01f8 MACRO_Execute_Matrix,First:
01f8 MACRO_Execute_Matrix,In_Type:
01f8 MACRO_Execute_Matrix,Last:
01f8 MACRO_Execute_Matrix,Length:
01f8 MACRO_Execute_Matrix,Not_Equal:
01f8 MACRO_Execute_Matrix,Not_In_Type:
01f8 MACRO_Execute_Matrix,Reverse_Bounds:
01f8 MACRO_Execute_Matrix,Structure_Write:
01f8 MACRO_Execute_Matrix,Subarray:
01f8 MACRO_Execute_Module,Activate:
01f8 MACRO_Execute_Module,Augment_Imports:
01f8 MACRO_Execute_Module,Check_Elaborated:
01f8 MACRO_Execute_Module,Elaborate:
01f8 MACRO_Execute_Module,Get_Name:
01f8 MACRO_Execute_Module,Is_Callable:
01f8 MACRO_Execute_Module,Is_Terminated:
01f8 MACRO_Execute_Package,Field_Execute,fieldnum:
01f8 MACRO_Execute_Package,Field_Execute_Dynamic:
01f8 MACRO_Execute_Package,Field_Read,fieldnum:
01f8 MACRO_Execute_Package,Field_Read_Dynamic:
01f8 MACRO_Execute_Package,Field_Reference,fieldnum:
01f8 MACRO_Execute_Package,Field_Reference_Dynamic:
01f8 MACRO_Execute_Package,Field_Write,fieldnum:
01f8 MACRO_Execute_Package,Field_Write_Dynamic:
01f8 MACRO_Execute_Record,Component_Offset:
01f8 MACRO_Execute_Record,Convert:
01f8 MACRO_Execute_Record,Equal:
01f8 MACRO_Execute_Record,Field_Read,fieldnum:
01f8 MACRO_Execute_Record,Field_Read_Dynamic:
01f8 MACRO_Execute_Record,Field_Reference,fieldnum:
01f8 MACRO_Execute_Record,Field_Reference_Dynamic:
01f8 MACRO_Execute_Record,Field_Type,fieldnum:
01f8 MACRO_Execute_Record,Field_Type_Dynamic:
01f8 MACRO_Execute_Record,Field_Write,fieldnum:
01f8 MACRO_Execute_Record,Field_Write_Dynamic:
01f8 MACRO_Execute_Record,Not_Equal:
01f8 MACRO_Execute_Record,Structure_Write:
01f8 MACRO_Execute_Select,Guard_Write,fieldnum:
01f8 MACRO_Execute_Select,Member_Write,fieldnum:
01f8 MACRO_Execute_Select,Rendezvous:
01f8 MACRO_Execute_Select,Terminate_Guard_Write:
01f8 MACRO_Execute_Select,Timed_Duration_Write:
01f8 MACRO_Execute_Select,Timed_Guard_Write:
01f8 MACRO_Execute_Subarray,Field_Read:
01f8 MACRO_Execute_Subarray,Field_Reference:
01f8 MACRO_Execute_Subarray,Field_Write:
01f8 MACRO_Execute_Subvector,Field_Read:
01f8 MACRO_Execute_Subvector,Field_Reference:
01f8 MACRO_Execute_Subvector,Field_Write:
01f8 MACRO_Execute_Task,Abort:
01f8 MACRO_Execute_Task,Abort_Multiple:
01f8 MACRO_Execute_Task,Conditional_Call,fieldnum:
01f8 MACRO_Execute_Task,Entry_Call,fieldnum:
01f8 MACRO_Execute_Task,Family_Call,fieldnum:
01f8 MACRO_Execute_Task,Family_Cond,fieldnum:
01f8 MACRO_Execute_Task,Family_Timed,fieldnum:
01f8 MACRO_Execute_Task,Timed_Call,fieldnum:
01f8 MACRO_Execute_Variant_Record,Check_In_Formal_Type:
01f8 MACRO_Execute_Variant_Record,Check_In_Type:
01f8 MACRO_Execute_Variant_Record,Component_Offset:
01f8 MACRO_Execute_Variant_Record,Convert:
01f8 MACRO_Execute_Variant_Record,Equal:
01f8 MACRO_Execute_Variant_Record,Field_Append,Fixed,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Append,Variant,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Constrain,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Read_Dynamic:
01f8 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Reference_Dynamic:
01f8 MACRO_Execute_Variant_Record,Field_Type,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Type_Dynamic:
01f8 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum:
01f8 MACRO_Execute_Variant_Record,Field_Write_Dynamic:
01f8 MACRO_Execute_Variant_Record,In_Type:
01f8 MACRO_Execute_Variant_Record,Indirects_Appended:
01f8 MACRO_Execute_Variant_Record,Is_Constrained:
01f8 MACRO_Execute_Variant_Record,Is_Constrained_Object:
01f8 MACRO_Execute_Variant_Record,Make_Constrained:
01f8 MACRO_Execute_Variant_Record,Not_Equal:
01f8 MACRO_Execute_Variant_Record,Not_In_Type:
01f8 MACRO_Execute_Variant_Record,Read_Discriminant_Constraint:
01f8 MACRO_Execute_Variant_Record,Read_Variant:
01f8 MACRO_Execute_Variant_Record,Reference_Makes_Copy:
01f8 MACRO_Execute_Variant_Record,Set_Bounds,fieldnum:
01f8 MACRO_Execute_Variant_Record,Set_Variant,fieldnum:
01f8 MACRO_Execute_Variant_Record,Structure_Query:
01f8 MACRO_Execute_Variant_Record,Structure_Write:
01f8 MACRO_Execute_Vector,And:
01f8 MACRO_Execute_Vector,Append:
01f8 MACRO_Execute_Vector,Bounds:
01f8 MACRO_Execute_Vector,Catenate:
01f8 MACRO_Execute_Vector,Check_In_Type:
01f8 MACRO_Execute_Vector,Convert:
01f8 MACRO_Execute_Vector,Convert_To_Formal:
01f8 MACRO_Execute_Vector,Element_Type:
01f8 MACRO_Execute_Vector,Equal:
01f8 MACRO_Execute_Vector,Field_Read:
01f8 MACRO_Execute_Vector,Field_Reference:
01f8 MACRO_Execute_Vector,Field_Write:
01f8 MACRO_Execute_Vector,First:
01f8 MACRO_Execute_Vector,Hash:
01f8 MACRO_Execute_Vector,In_Type:
01f8 MACRO_Execute_Vector,Last:
01f8 MACRO_Execute_Vector,Length:
01f8 MACRO_Execute_Vector,Less_Equal:
01f8 MACRO_Execute_Vector,Not_Equal:
01f8 MACRO_Execute_Vector,Not_In_Type:
01f8 MACRO_Execute_Vector,Prepend:
01f8 MACRO_Execute_Vector,Reverse_Bounds:
01f8 MACRO_Execute_Vector,Slice_Read:
01f8 MACRO_Execute_Vector,Slice_Reference:
01f8 MACRO_Execute_Vector,Slice_Write:
01f8 MACRO_Execute_Vector,Structure_Write:
01f8 MACRO_Exit_Subprogram_From_Utility,>R,topoffset:
01f8 MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset:
01f8 MACRO_Exit_Subprogram_With_Result,>R,topoffset:
01f8 MACRO_Exit_Subprogram_topoffset,>R:
01f8 MACRO_Illegal_-:
01f8 MACRO_Indirect_Literal_Any,pcrel,literal:
01f8 MACRO_Indirect_Literal_Discrete,pcrel,literal:
01f8 MACRO_Indirect_Literal_Float,pcrel,dbl:
01f8 MACRO_Jump_Case_case_max:
01f8 MACRO_Jump_Nonzero_pcrel,>JC:
01f8 MACRO_Jump_Zero_pcrel,>JC:
01f8 MACRO_Jump_pcrel,>J:
01f8 MACRO_Load_Encached_eon:
01f8 MACRO_Load_Top_At_Offset_0:
01f8 MACRO_Load_Top_At_Offset_1:
01f8 MACRO_Load_Top_At_Offset_2:
01f8 MACRO_Load_Top_At_Offset_3:
01f8 MACRO_Load_Top_At_Offset_4:
01f8 MACRO_Load_Top_At_Offset_5:
01f8 MACRO_Load_Top_At_Offset_6:
01f8 MACRO_Load_llvl,ldelta:
01f8 MACRO_Loop_Decreasing_pcrelneg,>JC:
01f8 MACRO_Loop_Increasing_pcrelneg,>JC:
01f8 MACRO_Pop_Control_Pop_Count_1:
01f8 MACRO_Pop_Control_Pop_Count_2:
01f8 MACRO_Pop_Control_Pop_Count_3:
01f8 MACRO_Pop_Control_Pop_Count_4:
01f8 MACRO_Pop_Control_Pop_Count_5:
01f8 MACRO_Pop_Control_Pop_Count_6:
01f8 MACRO_Pop_Control_Pop_Count_7:
01f8 MACRO_PushFullAddress_InMicrocode,caddr:
01f8 MACRO_Reference_zdelta:
01f8 MACRO_Short_Literal_slit:
01f8 MACRO_Store_Top_Access,At_Offset_1:
01f8 MACRO_Store_Top_Access,At_Offset_2:
01f8 MACRO_Store_Top_Access,At_Offset_3:
01f8 MACRO_Store_Top_Access,At_Offset_4:
01f8 MACRO_Store_Top_Access,At_Offset_5:
01f8 MACRO_Store_Top_Access,At_Offset_6:
01f8 MACRO_Store_Top_Discrete,At_Offset_1:
01f8 MACRO_Store_Top_Discrete,At_Offset_2:
01f8 MACRO_Store_Top_Discrete,At_Offset_3:
01f8 MACRO_Store_Top_Discrete,At_Offset_4:
01f8 MACRO_Store_Top_Discrete,At_Offset_5:
01f8 MACRO_Store_Top_Discrete,At_Offset_6:
01f8 MACRO_Store_Top_Float,At_Offset_1:
01f8 MACRO_Store_Top_Float,At_Offset_2:
01f8 MACRO_Store_Top_Float,At_Offset_3:
01f8 MACRO_Store_Top_Float,At_Offset_4:
01f8 MACRO_Store_Top_Float,At_Offset_5:
01f8 MACRO_Store_Top_Float,At_Offset_6:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_1:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_2:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_3:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_4:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_5:
01f8 MACRO_Store_Top_Heap_Access,At_Offset_6:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_1:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_2:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_3:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_4:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_5:
01f8 MACRO_Store_Top_Unchecked_Discrete,At_Offset_6:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_1:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_2:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_3:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_4:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_5:
01f8 MACRO_Store_Top_Unchecked_Float,At_Offset_6:
01f8 MACRO_Store_Unchecked_llvl,ldelta:
01f8 MACRO_Store_llvl,ldelta:
01f8 01f8 dispatch_brk_class 0 ; Flow R
dispatch_csa_valid 0
dispatch_uadr 01f8
ioc_random 14 clear cpu running
seq_en_micro 0
seq_random 01 Halt+?
01f9 01f9 seq_br_type a Unconditional Return; Flow R
01fa 01fa <halt> ; Flow R
01fb 01fb <halt> ; Flow R
01fc 01fc <halt> ; Flow R
01fd 01fd <halt> ; Flow R
01fe 01fe <halt> ; Flow R
01ff 01ff <halt> ; Flow R
0200 ; --------------------------------------------------------------------------------------
0200 ; 0200 - 022D EVENTS
0200 ; --------------------------------------------------------------------------------------
0200 0200 ioc_fiubs 2 typ ; Flow J cc=True 0x203
seq_br_type 1 Branch True
seq_branch_adr 0203 0x0203
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 14 ZEROS
typ_alu_func 1a PASS_B
typ_b_adr 20 TR1a:00
typ_c_adr 1f TOP - 0x0
typ_c_source 0 FIU_BUS
typ_frame 1a
0201 0201 <halt> ; Flow R
0202 0202 seq_br_type 3 Unconditional Branch; Flow J 0x201
seq_branch_adr 0201 0x0201
seq_en_micro 0
0203 0203 fiu_tivi_src c mar_0xc; Flow C cc=True 0x221
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 0221 0x0221
seq_cond_sel 6d MAR_MODIFIED
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
0204 0204 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
ioc_fiubs 0 fiu
seq_en_micro 0
typ_b_adr 05 GP05
typ_mar_cntl 4 RESTORE_MAR
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_source 0 FIU_BUS
0205 0205 seq_b_timing 0 Early Condition; Flow J cc=True 0x225
seq_br_type 1 Branch True
seq_branch_adr 0225 0x0225
seq_cond_sel 62 FIU.WRITE_LAST
seq_en_micro 0
typ_c_adr 38 GP07
val_c_adr 38 GP07
0206 0206 ioc_random 11 disable ecc event; Flow J cc=False 0x217
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 0217 0x0217
seq_cond_sel 7a IOC.CHECKBIT_ERROR~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
0207 0207 fiu_load_tar 1 hold_tar; Flow J cc=True 0x223
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
seq_b_timing 0 Early Condition
seq_br_type 1 Branch True
seq_branch_adr 0223 0x0223
seq_cond_sel 78 IOC.MULTIBIT_ERROR
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
0208 0208 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x227
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
ioc_random 9 read timer/checkbits/errorid
ioc_tvbs 4 ioc+ioc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 0227 0x0227
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
val_a_adr 21 VR1a:01
val_alu_func 0 PASS_A
val_frame 1a
0209 0209 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
typ_c_adr 36 GP09
typ_c_source 0 FIU_BUS
020a 020a seq_en_micro 0
typ_a_adr 09 GP09
typ_alu_func 10 NOT_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
020b 020b fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
ioc_fiubs 2 typ
seq_en_micro 0
typ_a_adr 09 GP09
020c 020c fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
seq_en_micro 0
020d 020d ioc_tvbs 3 fiu+fiu
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
020e 020e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x22b
seq_br_type 1 Branch True
seq_branch_adr 022b 0x022b
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 04 GP04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 04 GP04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
020f 020f fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
seq_en_micro 0
typ_b_adr 08 GP08
val_b_adr 08 GP08
0210 0210 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
typ_c_adr 36 GP09
typ_c_source 0 FIU_BUS
0211 0211 seq_en_micro 0
typ_a_adr 09 GP09
typ_alu_func 10 NOT_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
0212 0212 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
ioc_fiubs 2 typ
seq_en_micro 0
typ_a_adr 09 GP09
0213 0213 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
seq_en_micro 0
0214 0214 ioc_tvbs 3 fiu+fiu
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
0215 0215 seq_b_timing 0 Early Condition; Flow J cc=False 0x21d
seq_br_type 0 Branch False
seq_branch_adr 021d 0x021d
seq_cond_sel 61 FIU.PHYSICAL_LAST~
seq_en_micro 0
0216 0216 <halt> ; Flow R
0217 0217 seq_b_timing 0 Early Condition; Flow J cc=False 0x229
seq_br_type 0 Branch False
seq_branch_adr 0229 0x0229
seq_cond_sel 78 IOC.MULTIBIT_ERROR
seq_en_micro 0
0218 0218 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229
seq_br_type 5 Call True
seq_branch_adr 0229 0x0229
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 21 VR1a:01
val_alu_func 0 PASS_A
val_frame 1a
0219 0219 fiu_len_fill_lit 40 zero-fill 0x0
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
ioc_random 9 read timer/checkbits/errorid
ioc_tvbs 4 ioc+ioc
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
val_c_adr 1e VR1a:01
val_c_mux_sel 2 ALU
val_frame 1a
021a 021a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
021b 021b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229
seq_br_type 5 Call True
seq_branch_adr 0229 0x0229
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR1a:0b
val_frame 1a
021c 021c seq_br_type 3 Unconditional Branch; Flow J 0x215
seq_branch_adr 0215 0x0215
seq_en_micro 0
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
021d 021d fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
021e 021e ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 08 GP08
typ_mar_cntl 1 RESTORE_RDR
val_b_adr 08 GP08
021f 021f fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 05 GP05
typ_mar_cntl 4 RESTORE_MAR
val_a_adr 05 GP05
val_alu_func 0 PASS_A
0220 0220 fiu_mem_start c start_if_incmplt; Flow R
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_br_type a Unconditional Return
seq_cond_sel 6c INCOMPLETE_MEMORY_CYCLE
seq_en_micro 0
typ_b_adr 07 GP07
val_b_adr 07 GP07
0221 ; --------------------------------------------------------------------------------------
0221 ; Comes from:
0221 ; 0203 C True from color UE_ECC
0221 ; --------------------------------------------------------------------------------------
0221 0221 seq_b_timing 0 Early Condition; Flow R cc=True
seq_br_type 8 Return True
seq_branch_adr 0222 0x0222
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_a_adr 3d TR04:1d
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 27 VR04:07
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0222 0222 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0223 0223 <halt> ; Flow R
0224 0224 seq_br_type 3 Unconditional Branch; Flow J 0x223
seq_branch_adr 0223 0x0223
0225 0225 <halt> ; Flow R
0226 0226 seq_br_type 3 Unconditional Branch; Flow J 0x225
seq_branch_adr 0225 0x0225
0227 ; --------------------------------------------------------------------------------------
0227 ; Comes from:
0227 ; 0208 C True from color UE_ECC
0227 ; --------------------------------------------------------------------------------------
0227 0227 <halt> ; Flow R
0228 0228 seq_br_type a Unconditional Return; Flow R
0229 0229 <halt> ; Flow R
022a 022a seq_br_type a Unconditional Return; Flow R
022b 022b <halt> ; Flow R
022c 022c seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 03 GP03
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 03 GP03
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
022d 022d seq_br_type 3 Unconditional Branch; Flow J 0x215
seq_branch_adr 0215 0x0215
022e 022e <halt> ; Flow R
022f 022f <halt> ; Flow R
0230 0230 <halt> ; Flow R
0231 0231 <halt> ; Flow R
0232 0232 <halt> ; Flow R
0233 0233 <halt> ; Flow R
0234 0234 <halt> ; Flow R
0235 0235 <halt> ; Flow R
0236 0236 <halt> ; Flow R
0237 0237 <halt> ; Flow R
0238 0238 <halt> ; Flow R
0239 0239 <halt> ; Flow R
023a 023a <halt> ; Flow R
023b 023b <halt> ; Flow R
023c 023c <halt> ; Flow R
023d 023d <halt> ; Flow R
023e 023e <halt> ; Flow R
023f 023f <halt> ; Flow R
0240 0240 <halt> ; Flow R
0241 0241 <halt> ; Flow R
0242 0242 <halt> ; Flow R
0243 0243 <halt> ; Flow R
0244 0244 <halt> ; Flow R
0245 0245 <halt> ; Flow R
0246 0246 <halt> ; Flow R
0247 0247 <halt> ; Flow R
0248 0248 <halt> ; Flow R
0249 0249 <halt> ; Flow R
024a 024a <halt> ; Flow R
024b 024b <halt> ; Flow R
024c 024c <halt> ; Flow R
024d 024d <halt> ; Flow R
024e 024e <halt> ; Flow R
024f 024f <halt> ; Flow R
0250 0250 <halt> ; Flow R
0251 0251 <halt> ; Flow R
0252 0252 <halt> ; Flow R
0253 0253 <halt> ; Flow R
0254 0254 <halt> ; Flow R
0255 0255 <halt> ; Flow R
0256 0256 <halt> ; Flow R
0257 0257 <halt> ; Flow R
0258 0258 <halt> ; Flow R
0259 0259 <halt> ; Flow R
025a 025a <halt> ; Flow R
025b 025b <halt> ; Flow R
025c 025c <halt> ; Flow R
025d 025d <halt> ; Flow R
025e 025e <halt> ; Flow R
025f 025f <halt> ; Flow R
0260 0260 <halt> ; Flow R
0261 0261 <halt> ; Flow R
0262 0262 <halt> ; Flow R
0263 0263 <halt> ; Flow R
0264 0264 <halt> ; Flow R
0265 0265 <halt> ; Flow R
0266 0266 <halt> ; Flow R
0267 0267 <halt> ; Flow R
0268 0268 <halt> ; Flow R
0269 0269 <halt> ; Flow R
026a 026a <halt> ; Flow R
026b 026b <halt> ; Flow R
026c 026c <halt> ; Flow R
026d 026d <halt> ; Flow R
026e 026e <halt> ; Flow R
026f 026f <halt> ; Flow R
0270 0270 <halt> ; Flow R
0271 0271 <halt> ; Flow R
0272 0272 <halt> ; Flow R
0273 0273 <halt> ; Flow R
0274 0274 <halt> ; Flow R
0275 0275 <halt> ; Flow R
0276 0276 <halt> ; Flow R
0277 0277 <halt> ; Flow R
0278 0278 <halt> ; Flow R
0279 0279 <halt> ; Flow R
027a 027a <halt> ; Flow R
027b 027b <halt> ; Flow R
027c 027c <halt> ; Flow R
027d 027d <halt> ; Flow R
027e 027e <halt> ; Flow R
027f 027f <halt> ; Flow R
0280 0280 <halt> ; Flow R
0281 0281 <halt> ; Flow R
0282 0282 <halt> ; Flow R
0283 0283 <halt> ; Flow R
0284 0284 <halt> ; Flow R
0285 0285 <halt> ; Flow R
0286 0286 <halt> ; Flow R
0287 0287 <halt> ; Flow R
0288 0288 <halt> ; Flow R
0289 0289 <halt> ; Flow R
028a 028a <halt> ; Flow R
028b 028b <halt> ; Flow R
028c 028c <halt> ; Flow R
028d 028d <halt> ; Flow R
028e 028e <halt> ; Flow R
028f 028f <halt> ; Flow R
0290 0290 <halt> ; Flow R
0291 0291 <halt> ; Flow R
0292 0292 <halt> ; Flow R
0293 0293 <halt> ; Flow R
0294 0294 <halt> ; Flow R
0295 0295 <halt> ; Flow R
0296 0296 <halt> ; Flow R
0297 0297 <halt> ; Flow R
0298 0298 <halt> ; Flow R
0299 0299 <halt> ; Flow R
029a 029a <halt> ; Flow R
029b 029b <halt> ; Flow R
029c 029c <halt> ; Flow R
029d 029d <halt> ; Flow R
029e 029e <halt> ; Flow R
029f 029f <halt> ; Flow R
02a0 02a0 <halt> ; Flow R
02a1 02a1 <halt> ; Flow R
02a2 02a2 <halt> ; Flow R
02a3 02a3 <halt> ; Flow R
02a4 02a4 <halt> ; Flow R
02a5 02a5 <halt> ; Flow R
02a6 02a6 <halt> ; Flow R
02a7 02a7 <halt> ; Flow R
02a8 02a8 <halt> ; Flow R
02a9 02a9 <halt> ; Flow R
02aa 02aa <halt> ; Flow R
02ab 02ab <halt> ; Flow R
02ac 02ac <halt> ; Flow R
02ad 02ad <halt> ; Flow R
02ae 02ae <halt> ; Flow R
02af 02af <halt> ; Flow R
02b0 02b0 <halt> ; Flow R
02b1 02b1 <halt> ; Flow R
02b2 02b2 <halt> ; Flow R
02b3 02b3 <halt> ; Flow R
02b4 02b4 <halt> ; Flow R
02b5 02b5 <halt> ; Flow R
02b6 02b6 <halt> ; Flow R
02b7 02b7 <halt> ; Flow R
02b8 02b8 <halt> ; Flow R
02b9 02b9 <halt> ; Flow R
02ba 02ba <halt> ; Flow R
02bb 02bb <halt> ; Flow R
02bc 02bc <halt> ; Flow R
02bd 02bd <halt> ; Flow R
02be 02be <halt> ; Flow R
02bf 02bf <halt> ; Flow R
02c0 02c0 <halt> ; Flow R
02c1 02c1 <halt> ; Flow R
02c2 02c2 <halt> ; Flow R
02c3 02c3 <halt> ; Flow R
02c4 02c4 <halt> ; Flow R
02c5 02c5 <halt> ; Flow R
02c6 02c6 <halt> ; Flow R
02c7 02c7 <halt> ; Flow R
02c8 02c8 <halt> ; Flow R
02c9 02c9 <halt> ; Flow R
02ca 02ca <halt> ; Flow R
02cb 02cb <halt> ; Flow R
02cc 02cc <halt> ; Flow R
02cd 02cd <halt> ; Flow R
02ce 02ce <halt> ; Flow R
02cf 02cf <halt> ; Flow R
02d0 02d0 <halt> ; Flow R
02d1 02d1 <halt> ; Flow R
02d2 02d2 <halt> ; Flow R
02d3 02d3 <halt> ; Flow R
02d4 02d4 <halt> ; Flow R
02d5 02d5 <halt> ; Flow R
02d6 02d6 <halt> ; Flow R
02d7 02d7 <halt> ; Flow R
02d8 02d8 <halt> ; Flow R
02d9 02d9 <halt> ; Flow R
02da 02da <halt> ; Flow R
02db 02db <halt> ; Flow R
02dc 02dc <halt> ; Flow R
02dd 02dd <halt> ; Flow R
02de 02de <halt> ; Flow R
02df 02df <halt> ; Flow R
02e0 02e0 <halt> ; Flow R
02e1 02e1 <halt> ; Flow R
02e2 02e2 <halt> ; Flow R
02e3 02e3 <halt> ; Flow R
02e4 02e4 <halt> ; Flow R
02e5 02e5 <halt> ; Flow R
02e6 02e6 <halt> ; Flow R
02e7 02e7 <halt> ; Flow R
02e8 02e8 <halt> ; Flow R
02e9 02e9 <halt> ; Flow R
02ea 02ea <halt> ; Flow R
02eb 02eb <halt> ; Flow R
02ec 02ec <halt> ; Flow R
02ed 02ed <halt> ; Flow R
02ee 02ee <halt> ; Flow R
02ef 02ef <halt> ; Flow R
02f0 02f0 <halt> ; Flow R
02f1 02f1 <halt> ; Flow R
02f2 02f2 <halt> ; Flow R
02f3 02f3 <halt> ; Flow R
02f4 02f4 <halt> ; Flow R
02f5 02f5 <halt> ; Flow R
02f6 02f6 <halt> ; Flow R
02f7 02f7 <halt> ; Flow R
02f8 02f8 <halt> ; Flow R
02f9 02f9 <halt> ; Flow R
02fa 02fa <halt> ; Flow R
02fb 02fb <halt> ; Flow R
02fc 02fc <halt> ; Flow R
02fd 02fd <halt> ; Flow R
02fe 02fe <halt> ; Flow R
02ff 02ff <halt> ; Flow R
0300 ; --------------------------------------------------------------------------------------
0300 ; 0300 - 0325 DIAGNOSTIC_DRIVER
0300 ; --------------------------------------------------------------------------------------
0300 START:
0300 0300 fiu_tivi_src 8 type_var; DISABLE (MICRO_EVENTS),
; TYP {TYP_BUS := 16#FFFF_FFFF_FFFF_FFFF# },
; VAL {ADDRESS_BUS := PASS_A (16#FFFF_FFFF_FFFF_FFFF#) },
; RESTORE_MAR_REFRESH,
; %IF CPU_KIND.MODEL_200_CPU
; IOC {SET (CPU_BUSY_LIGHT) },
; %END
ioc_adrbs 1 val
ioc_random 13 set cpu running
seq_en_micro 0
typ_b_adr 22 TR10:02
typ_frame 10
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_a_adr 22 VR10:02
val_alu_func 0 PASS_A
val_frame 10
0301 SCAVENGER_INIT:
0301 0301 fiu_mem_start 13 start_available_query
ioc_adrbs 2 typ
ioc_fiubs 2 typ
seq_en_micro 0
typ_a_adr 20 TR04:00
typ_c_adr 28 LOOP_COUNTER
typ_c_source 0 FIU_BUS
typ_frame 4
typ_mar_cntl f LOAD_MAR_RESERVED
0302 0302 seq_en_micro 0
val_a_adr 29 VR04:09
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0303 0303 fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 37 VR05:17
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 5
0304 0304 fiu_mem_start 17 scavenger_write; Flow J cc=False 0x303
fiu_tivi_src 1 tar_val
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 0303 0x0303
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_b_adr 38 VR05:18
val_frame 5
val_rand 2 DEC_LOOP_COUNTER
0305 0305 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x302
ioc_adrbs 1 val
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 0302 0x0302
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
0306 0306 ioc_random d disable slice timer
seq_en_micro 0
0307 0307 ioc_random f disable delay timer
seq_en_micro 0
0308 0308 ioc_random 6 load slice timer
seq_en_micro 0
typ_b_adr 20 TR10:00
typ_frame 10
0309 0309 ioc_random 7 load delay timer
seq_en_micro 0
typ_b_adr 20 TR10:00
typ_frame 10
030a 030a ioc_random a clear slice event
seq_en_micro 0
030b 030b ioc_random b clear delay event
seq_en_micro 0
030c 030c seq_br_type 3 Unconditional Branch; Flow J 0x30d
seq_branch_adr 030d START_VAL_TEST
030d START_VAL_TEST:
; ACKNOWLEDGE_REFRESH,
; CALL VAL_TEST.VAL_TEST,
030d 030d fiu_mem_start 18 acknowledge_refresh; Flow C 0x400
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 0400 VAL_TEST
; GOTO START_TYP_TEST,
030e 030e seq_br_type 3 Unconditional Branch; Flow J 0x30f
seq_branch_adr 030f START_TYP_TEST
030f START_TYP_TEST:
; ACKNOWLEDGE_REFRESH,
; CALL TYP_TEST.TYP_TEST,
030f 030f fiu_mem_start 18 acknowledge_refresh; Flow C 0xc00
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 0c00 0x0c00
0310 0310 seq_br_type 3 Unconditional Branch; Flow J 0x311
seq_branch_adr 0311 0x0311
0311 0311 fiu_mem_start 18 acknowledge_refresh; Flow C 0x1300
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 1300 0x1300
0312 0312 seq_br_type 3 Unconditional Branch; Flow J 0x313
seq_branch_adr 0313 0x0313
0313 0313 fiu_mem_start 18 acknowledge_refresh; Flow C 0x1800
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 1800 0x1800
0314 0314 seq_br_type 3 Unconditional Branch; Flow J 0x315
seq_branch_adr 0315 0x0315
0315 0315 fiu_mem_start 18 acknowledge_refresh; Flow C 0x1a00
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 1a00 0x1a00
0316 0316 seq_br_type 3 Unconditional Branch; Flow J 0x317
seq_branch_adr 0317 0x0317
0317 0317 fiu_mem_start 18 acknowledge_refresh; Flow J 0x1e00
fiu_tivi_src c mar_0xc
seq_br_type 3 Unconditional Branch
seq_branch_adr 1e00 0x1e00
0318 0318 fiu_mem_start 18 acknowledge_refresh; Flow C 0x1ee3
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 1ee3 0x1ee3
0319 0319 seq_br_type 3 Unconditional Branch; Flow J 0x31a
seq_branch_adr 031a 0x031a
031a 031a fiu_mem_start 18 acknowledge_refresh; Flow C 0x2400
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2400 0x2400
031b 031b seq_br_type 3 Unconditional Branch; Flow J 0x31c
seq_branch_adr 031c 0x031c
031c 031c fiu_mem_start 18 acknowledge_refresh; Flow C 0x2800
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2800 0x2800
031d 031d seq_br_type 3 Unconditional Branch; Flow J 0x31e
seq_branch_adr 031e 0x031e
031e 031e fiu_mem_start 18 acknowledge_refresh; Flow C 0x2b00
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2b00 0x2b00
031f 031f seq_br_type 3 Unconditional Branch; Flow J 0x320
seq_branch_adr 0320 0x0320
0320 0320 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2e00
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2e00 0x2e00
0321 0321 seq_br_type 3 Unconditional Branch; Flow J 0x101
seq_branch_adr 0101 END_DIAGNOSTIC_PASS
0322 0322 fiu_mem_start 18 acknowledge_refresh; Flow C 0x3000
fiu_tivi_src c mar_0xc
ioc_random 13 set cpu running
seq_br_type 7 Unconditional Call
seq_branch_adr 3000 0x3000
0323 0323 seq_br_type 3 Unconditional Branch; Flow J 0x105
seq_branch_adr 0105 0x0105
0324 0324 fiu_mem_start 18 acknowledge_refresh; Flow C 0x3000
fiu_tivi_src c mar_0xc
ioc_random 13 set cpu running
seq_br_type 7 Unconditional Call
seq_branch_adr 3000 0x3000
0325 0325 seq_br_type 3 Unconditional Branch; Flow J 0x106
seq_branch_adr 0106 0x0106
0326 0326 <halt> ; Flow R
0327 0327 <halt> ; Flow R
0328 0328 <halt> ; Flow R
0329 0329 <halt> ; Flow R
032a 032a <halt> ; Flow R
032b 032b <halt> ; Flow R
032c 032c <halt> ; Flow R
032d 032d <halt> ; Flow R
032e 032e <halt> ; Flow R
032f 032f <halt> ; Flow R
0330 0330 <halt> ; Flow R
0331 0331 <halt> ; Flow R
0332 0332 <halt> ; Flow R
0333 0333 <halt> ; Flow R
0334 0334 <halt> ; Flow R
0335 0335 <halt> ; Flow R
0336 0336 <halt> ; Flow R
0337 0337 <halt> ; Flow R
0338 0338 <halt> ; Flow R
0339 0339 <halt> ; Flow R
033a 033a <halt> ; Flow R
033b 033b <halt> ; Flow R
033c 033c <halt> ; Flow R
033d 033d <halt> ; Flow R
033e 033e <halt> ; Flow R
033f 033f <halt> ; Flow R
0340 0340 <halt> ; Flow R
0341 0341 <halt> ; Flow R
0342 0342 <halt> ; Flow R
0343 0343 <halt> ; Flow R
0344 0344 <halt> ; Flow R
0345 0345 <halt> ; Flow R
0346 0346 <halt> ; Flow R
0347 0347 <halt> ; Flow R
0348 0348 <halt> ; Flow R
0349 0349 <halt> ; Flow R
034a 034a <halt> ; Flow R
034b 034b <halt> ; Flow R
034c 034c <halt> ; Flow R
034d 034d <halt> ; Flow R
034e 034e <halt> ; Flow R
034f 034f <halt> ; Flow R
0350 0350 <halt> ; Flow R
0351 0351 <halt> ; Flow R
0352 0352 <halt> ; Flow R
0353 0353 <halt> ; Flow R
0354 0354 <halt> ; Flow R
0355 0355 <halt> ; Flow R
0356 0356 <halt> ; Flow R
0357 0357 <halt> ; Flow R
0358 0358 <halt> ; Flow R
0359 0359 <halt> ; Flow R
035a 035a <halt> ; Flow R
035b 035b <halt> ; Flow R
035c 035c <halt> ; Flow R
035d 035d <halt> ; Flow R
035e 035e <halt> ; Flow R
035f 035f <halt> ; Flow R
0360 0360 <halt> ; Flow R
0361 0361 <halt> ; Flow R
0362 0362 <halt> ; Flow R
0363 0363 <halt> ; Flow R
0364 0364 <halt> ; Flow R
0365 0365 <halt> ; Flow R
0366 0366 <halt> ; Flow R
0367 0367 <halt> ; Flow R
0368 0368 <halt> ; Flow R
0369 0369 <halt> ; Flow R
036a 036a <halt> ; Flow R
036b 036b <halt> ; Flow R
036c 036c <halt> ; Flow R
036d 036d <halt> ; Flow R
036e 036e <halt> ; Flow R
036f 036f <halt> ; Flow R
0370 0370 <halt> ; Flow R
0371 0371 <halt> ; Flow R
0372 0372 <halt> ; Flow R
0373 0373 <halt> ; Flow R
0374 0374 <halt> ; Flow R
0375 0375 <halt> ; Flow R
0376 0376 <halt> ; Flow R
0377 0377 <halt> ; Flow R
0378 0378 <halt> ; Flow R
0379 0379 <halt> ; Flow R
037a 037a <halt> ; Flow R
037b 037b <halt> ; Flow R
037c 037c <halt> ; Flow R
037d 037d <halt> ; Flow R
037e 037e <halt> ; Flow R
037f 037f <halt> ; Flow R
0380 0380 <halt> ; Flow R
0381 0381 <halt> ; Flow R
0382 0382 <halt> ; Flow R
0383 0383 <halt> ; Flow R
0384 0384 <halt> ; Flow R
0385 0385 <halt> ; Flow R
0386 0386 <halt> ; Flow R
0387 0387 <halt> ; Flow R
0388 0388 <halt> ; Flow R
0389 0389 <halt> ; Flow R
038a 038a <halt> ; Flow R
038b 038b <halt> ; Flow R
038c 038c <halt> ; Flow R
038d 038d <halt> ; Flow R
038e 038e <halt> ; Flow R
038f 038f <halt> ; Flow R
0390 0390 <halt> ; Flow R
0391 0391 <halt> ; Flow R
0392 0392 <halt> ; Flow R
0393 0393 <halt> ; Flow R
0394 0394 <halt> ; Flow R
0395 0395 <halt> ; Flow R
0396 0396 <halt> ; Flow R
0397 0397 <halt> ; Flow R
0398 0398 <halt> ; Flow R
0399 0399 <halt> ; Flow R
039a 039a <halt> ; Flow R
039b 039b <halt> ; Flow R
039c 039c <halt> ; Flow R
039d 039d <halt> ; Flow R
039e 039e <halt> ; Flow R
039f 039f <halt> ; Flow R
03a0 03a0 <halt> ; Flow R
03a1 03a1 <halt> ; Flow R
03a2 03a2 <halt> ; Flow R
03a3 03a3 <halt> ; Flow R
03a4 03a4 <halt> ; Flow R
03a5 03a5 <halt> ; Flow R
03a6 03a6 <halt> ; Flow R
03a7 03a7 <halt> ; Flow R
03a8 03a8 <halt> ; Flow R
03a9 03a9 <halt> ; Flow R
03aa 03aa <halt> ; Flow R
03ab 03ab <halt> ; Flow R
03ac 03ac <halt> ; Flow R
03ad 03ad <halt> ; Flow R
03ae 03ae <halt> ; Flow R
03af 03af <halt> ; Flow R
03b0 03b0 <halt> ; Flow R
03b1 03b1 <halt> ; Flow R
03b2 03b2 <halt> ; Flow R
03b3 03b3 <halt> ; Flow R
03b4 03b4 <halt> ; Flow R
03b5 03b5 <halt> ; Flow R
03b6 03b6 <halt> ; Flow R
03b7 03b7 <halt> ; Flow R
03b8 03b8 <halt> ; Flow R
03b9 03b9 <halt> ; Flow R
03ba 03ba <halt> ; Flow R
03bb 03bb <halt> ; Flow R
03bc 03bc <halt> ; Flow R
03bd 03bd <halt> ; Flow R
03be 03be <halt> ; Flow R
03bf 03bf <halt> ; Flow R
03c0 03c0 <halt> ; Flow R
03c1 03c1 <halt> ; Flow R
03c2 03c2 <halt> ; Flow R
03c3 03c3 <halt> ; Flow R
03c4 03c4 <halt> ; Flow R
03c5 03c5 <halt> ; Flow R
03c6 03c6 <halt> ; Flow R
03c7 03c7 <halt> ; Flow R
03c8 03c8 <halt> ; Flow R
03c9 03c9 <halt> ; Flow R
03ca 03ca <halt> ; Flow R
03cb 03cb <halt> ; Flow R
03cc 03cc <halt> ; Flow R
03cd 03cd <halt> ; Flow R
03ce 03ce <halt> ; Flow R
03cf 03cf <halt> ; Flow R
03d0 03d0 <halt> ; Flow R
03d1 03d1 <halt> ; Flow R
03d2 03d2 <halt> ; Flow R
03d3 03d3 <halt> ; Flow R
03d4 03d4 <halt> ; Flow R
03d5 03d5 <halt> ; Flow R
03d6 03d6 <halt> ; Flow R
03d7 03d7 <halt> ; Flow R
03d8 03d8 <halt> ; Flow R
03d9 03d9 <halt> ; Flow R
03da 03da <halt> ; Flow R
03db 03db <halt> ; Flow R
03dc 03dc <halt> ; Flow R
03dd 03dd <halt> ; Flow R
03de 03de <halt> ; Flow R
03df 03df <halt> ; Flow R
03e0 03e0 <halt> ; Flow R
03e1 03e1 <halt> ; Flow R
03e2 03e2 <halt> ; Flow R
03e3 03e3 <halt> ; Flow R
03e4 03e4 <halt> ; Flow R
03e5 03e5 <halt> ; Flow R
03e6 03e6 <halt> ; Flow R
03e7 03e7 <halt> ; Flow R
03e8 03e8 <halt> ; Flow R
03e9 03e9 <halt> ; Flow R
03ea 03ea <halt> ; Flow R
03eb 03eb <halt> ; Flow R
03ec 03ec <halt> ; Flow R
03ed 03ed <halt> ; Flow R
03ee 03ee <halt> ; Flow R
03ef 03ef <halt> ; Flow R
03f0 03f0 <halt> ; Flow R
03f1 03f1 <halt> ; Flow R
03f2 03f2 <halt> ; Flow R
03f3 03f3 <halt> ; Flow R
03f4 03f4 <halt> ; Flow R
03f5 03f5 <halt> ; Flow R
03f6 03f6 <halt> ; Flow R
03f7 03f7 <halt> ; Flow R
03f8 03f8 <halt> ; Flow R
03f9 03f9 <halt> ; Flow R
03fa 03fa <halt> ; Flow R
03fb 03fb <halt> ; Flow R
03fc 03fc <halt> ; Flow R
03fd 03fd <halt> ; Flow R
03fe 03fe <halt> ; Flow R
03ff 03ff <halt> ; Flow R
0400 ; --------------------------------------------------------------------------------------
0400 ; 0400 - 0B08 VAL_TEST
0400 ; Comes from:
0400 ; 030d C from color DIAGNOSTIC_START
0400 ; --------------------------------------------------------------------------------------
0400 COND_FALSE:
0400 VAL_TEST:
; IF VAL (FALSE) THEN CALL COND_ERROR,
0400 0400 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 17 VAL.FALSE(early)
; IF NOT VAL (FALSE) THEN GOTO COND_FALSE_A,
0401 0401 seq_b_timing 0 Early Condition; Flow J cc=False 0x403
seq_br_type 0 Branch False
seq_branch_adr 0403 COND_FALSE_A
seq_cond_sel 17 VAL.FALSE(early)
; CALL COND_ERROR,
0402 0402 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0403 COND_FALSE_A:
0403 COND_TRUE:
; IF VAL (TRUE) THEN GOTO COND_TRUE_A,
0403 0403 seq_b_timing 0 Early Condition; Flow J cc=True 0x405
seq_br_type 1 Branch True
seq_branch_adr 0405 COND_TRUE_A
seq_cond_sel 16 VAL.TRUE(early)
; CALL COND_ERROR,
0404 0404 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0405 COND_TRUE_A:
; IF NOT VAL (TRUE) THEN CALL COND_ERROR,
0405 0405 seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 16 VAL.TRUE(early)
0406 0406 seq_cond_sel 17 VAL.FALSE(early)
0407 0407 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
0408 0408 seq_cond_sel 17 VAL.FALSE(early)
0409 0409 seq_b_timing 0 Early Condition; Flow J cc=False 0x40b
seq_br_type 0 Branch False
seq_branch_adr 040b 0x040b
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
040a 040a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
040b 040b seq_cond_sel 16 VAL.TRUE(early)
040c 040c seq_b_timing 0 Early Condition; Flow J cc=True 0x40e
seq_br_type 1 Branch True
seq_branch_adr 040e 0x040e
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
040d 040d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
040e 040e seq_cond_sel 16 VAL.TRUE(early)
040f 040f seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
0410 0410 <default>
0411 0411 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0412 0412 seq_b_timing 0 Early Condition; Flow J cc=False 0x414
seq_br_type 0 Branch False
seq_branch_adr 0414 0x0414
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0413 0413 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0414 0414 val_alu_func 13 ONES
0415 0415 seq_b_timing 0 Early Condition; Flow J cc=True 0x417
seq_br_type 1 Branch True
seq_branch_adr 0417 0x0417
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_alu_func 13 ONES
0416 0416 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0417 0417 seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_alu_func 13 ONES
0418 0418 seq_b_timing 0 Early Condition; Flow J cc=True 0x41a
seq_br_type 1 Branch True
seq_branch_adr 041a 0x041a
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0419 0419 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
041a 041a seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_alu_func 13 ONES
041b 041b seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
041c 041c seq_b_timing 0 Early Condition; Flow J cc=False 0x41e
seq_br_type 0 Branch False
seq_branch_adr 041e 0x041e
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_alu_func 13 ONES
041d 041d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
041e 041e val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
041f 041f seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
0420 0420 seq_b_timing 0 Early Condition; Flow J cc=False 0x422
seq_br_type 0 Branch False
seq_branch_adr 0422 0x0422
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
0421 0421 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0422 0422 val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0423 0423 seq_b_timing 0 Early Condition; Flow J cc=True 0x425
seq_br_type 1 Branch True
seq_branch_adr 0425 0x0425
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0424 0424 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0425 0425 seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0426 0426 seq_b_timing 0 Early Condition; Flow J cc=True 0x428
seq_br_type 1 Branch True
seq_branch_adr 0428 0x0428
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
0427 0427 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0428 0428 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0429 0429 seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
042a 042a seq_b_timing 0 Early Condition; Flow J cc=False 0x42c
seq_br_type 0 Branch False
seq_branch_adr 042c 0x042c
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
042b 042b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
042c 042c val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
042d 042d seq_b_timing 0 Early Condition; Flow J cc=True 0x42f
seq_br_type 1 Branch True
seq_branch_adr 042f 0x042f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
042e 042e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
042f 042f seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
0430 0430 val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
0431 0431 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
0432 0432 seq_b_timing 0 Early Condition; Flow J cc=False 0x434
seq_br_type 0 Branch False
seq_branch_adr 0434 0x0434
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
0433 0433 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0434 0434 seq_b_timing 0 Early Condition; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
0435 0435 seq_b_timing 0 Early Condition; Flow J cc=True 0x437
seq_br_type 1 Branch True
seq_branch_adr 0437 0x0437
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
0436 0436 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0437 0437 seq_b_timing 0 Early Condition; Flow J cc=False 0x439
seq_br_type 0 Branch False
seq_branch_adr 0439 0x0439
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
0438 0438 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0439 0439 seq_b_timing 0 Early Condition; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
043a 043a seq_br_type 1 Branch True; Flow J cc=True 0x43c
seq_branch_adr 043c 0x043c
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 20 VR10:00
val_frame 10
043b 043b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
043c 043c seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 20 VR10:00
val_frame 10
043d 043d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x43f
seq_br_type 1 Branch True
seq_branch_adr 043f 0x043f
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 20 VR10:00
val_frame 10
043e 043e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
043f 043f seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 20 VR10:00
val_frame 10
0440 0440 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 22 VR10:02
val_frame 10
0441 0441 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x443
seq_br_type 0 Branch False
seq_branch_adr 0443 0x0443
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 22 VR10:02
val_frame 10
0442 0442 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0443 0443 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 22 VR10:02
val_frame 10
0444 0444 seq_br_type 0 Branch False; Flow J cc=False 0x446
seq_branch_adr 0446 0x0446
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 20 VR10:00
val_b_adr 22 VR10:02
val_frame 10
0445 0445 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0446 0446 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 20 VR10:00
val_frame 10
0447 0447 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x449
seq_br_type 0 Branch False
seq_branch_adr 0449 0x0449
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 20 VR10:00
val_frame 10
0448 0448 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0449 0449 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 20 VR10:00
val_frame 10
044a 044a seq_br_type 0 Branch False; Flow J cc=False 0x44c
seq_branch_adr 044c 0x044c
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 20 VR10:00
val_frame 10
044b 044b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
044c 044c seq_br_type 1 Branch True; Flow J cc=True 0x44e
seq_branch_adr 044e 0x044e
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 22 VR10:02
val_frame 10
044d 044d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
044e 044e seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 22 VR10:02
val_frame 10
044f 044f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x451
seq_br_type 1 Branch True
seq_branch_adr 0451 0x0451
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 22 VR10:02
val_frame 10
0450 0450 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0451 0451 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late)
val_a_adr 22 VR10:02
val_b_adr 22 VR10:02
val_frame 10
0452 0452 seq_br_type 1 Branch True; Flow J cc=True 0x454
seq_branch_adr 0454 0x0454
seq_cond_sel 00 VAL.ALU_ZERO(late)
0453 0453 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0454 0454 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
0455 0455 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_alu_func 13 ONES
0456 0456 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x458
seq_br_type 0 Branch False
seq_branch_adr 0458 0x0458
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_alu_func 13 ONES
0457 0457 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0458 0458 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x45a
seq_br_type 1 Branch True
seq_branch_adr 045a 0x045a
seq_cond_sel 00 VAL.ALU_ZERO(late)
0459 0459 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
045a 045a seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
045b 045b seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_alu_func 13 ONES
045c 045c seq_br_type 0 Branch False; Flow J cc=False 0x45e
seq_branch_adr 045e 0x045e
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_alu_func 13 ONES
045d 045d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
045e 045e seq_br_type 1 Branch True; Flow J cc=True 0x460
seq_branch_adr 0460 0x0460
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
045f 045f seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0460 0460 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0461 0461 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0462 0462 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x464
seq_br_type 0 Branch False
seq_branch_adr 0464 0x0464
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0463 0463 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0464 0464 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x466
seq_br_type 1 Branch True
seq_branch_adr 0466 0x0466
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0465 0465 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0466 0466 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0467 0467 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0468 0468 seq_br_type 0 Branch False; Flow J cc=False 0x46a
seq_branch_adr 046a 0x046a
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0469 0469 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
046a 046a seq_br_type 1 Branch True; Flow J cc=True 0x46c
seq_branch_adr 046c 0x046c
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 13 ONES
046b 046b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
046c 046c seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 13 ONES
046d 046d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
046e 046e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x470
seq_br_type 0 Branch False
seq_branch_adr 0470 0x0470
seq_cond_sel 01 VAL.ALU_NONZERO(late)
046f 046f seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0470 0470 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x472
seq_br_type 1 Branch True
seq_branch_adr 0472 0x0472
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 13 ONES
0471 0471 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0472 0472 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 13 ONES
0473 0473 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
0474 0474 seq_br_type 0 Branch False; Flow J cc=False 0x476
seq_branch_adr 0476 0x0476
seq_cond_sel 01 VAL.ALU_NONZERO(late)
0475 0475 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0476 0476 seq_br_type 1 Branch True; Flow J cc=True 0x478
seq_branch_adr 0478 0x0478
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0477 0477 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0478 0478 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0479 0479 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
047a 047a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x47c
seq_br_type 0 Branch False
seq_branch_adr 047c 0x047c
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
047b 047b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
047c 047c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x47e
seq_br_type 1 Branch True
seq_branch_adr 047e 0x047e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
047d 047d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
047e 047e seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
047f 047f seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0480 0480 seq_br_type 0 Branch False; Flow J cc=False 0x482
seq_branch_adr 0482 0x0482
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0481 0481 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0482 0482 seq_br_type 1 Branch True; Flow J cc=True 0x484
seq_branch_adr 0484 0x0484
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_alu_func 13 ONES
0483 0483 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0484 0484 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_alu_func 13 ONES
0485 0485 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
0486 0486 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x488
seq_br_type 0 Branch False
seq_branch_adr 0488 0x0488
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
0487 0487 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0488 0488 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x48a
seq_br_type 1 Branch True
seq_branch_adr 048a 0x048a
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_alu_func 13 ONES
0489 0489 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
048a 048a seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_alu_func 13 ONES
048b 048b seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
048c 048c seq_br_type 0 Branch False; Flow J cc=False 0x48e
seq_branch_adr 048e 0x048e
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
048d 048d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
048e 048e seq_br_type 1 Branch True; Flow J cc=True 0x490
seq_branch_adr 0490 0x0490
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
048f 048f seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0490 0490 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0491 0491 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0492 0492 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x494
seq_br_type 0 Branch False
seq_branch_adr 0494 0x0494
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0493 0493 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0494 0494 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x496
seq_br_type 1 Branch True
seq_branch_adr 0496 0x0496
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0495 0495 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0496 0496 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
0497 0497 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0498 0498 seq_br_type 0 Branch False; Flow J cc=False 0x49a
seq_branch_adr 049a 0x049a
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0499 0499 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
049a 049a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x49c
seq_br_type 0 Branch False
seq_branch_adr 049c 0x049c
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_alu_func 13 ONES
049b 049b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
049c 049c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_alu_func 13 ONES
049d 049d seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x49f
seq_br_type 0 Branch False
seq_branch_adr 049f 0x049f
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
049e 049e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
049f 049f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
04a0 04a0 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
04a1 04a1 seq_br_type 1 Branch True; Flow J cc=True 0x4a3
seq_branch_adr 04a3 0x04a3
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
04a2 04a2 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04a3 04a3 seq_br_type 0 Branch False; Flow J cc=False 0x4a5
seq_branch_adr 04a5 0x04a5
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_alu_func 13 ONES
04a4 04a4 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04a5 04a5 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_alu_func 13 ONES
04a6 04a6 seq_br_type 0 Branch False; Flow J cc=False 0x4a8
seq_branch_adr 04a8 0x04a8
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
04a7 04a7 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04a8 04a8 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
04a9 04a9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
04aa 04aa seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4ac
seq_br_type 1 Branch True
seq_branch_adr 04ac 0x04ac
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
04ab 04ab seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04ac 04ac seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4ae
seq_br_type 0 Branch False
seq_branch_adr 04ae 0x04ae
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
04ad 04ad seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04ae 04ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
04af 04af seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4b1
seq_br_type 0 Branch False
seq_branch_adr 04b1 0x04b1
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04b0 04b0 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04b1 04b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04b2 04b2 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 21 VR10:01
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04b3 04b3 seq_br_type 1 Branch True; Flow J cc=True 0x4b5
seq_branch_adr 04b5 0x04b5
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 21 VR10:01
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04b4 04b4 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04b5 04b5 seq_br_type 0 Branch False; Flow J cc=False 0x4b7
seq_branch_adr 04b7 0x04b7
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
04b6 04b6 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04b7 04b7 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_frame 10
04b8 04b8 seq_br_type 0 Branch False; Flow J cc=False 0x4ba
seq_branch_adr 04ba 0x04ba
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04b9 04b9 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04ba 04ba seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04bb 04bb seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 21 VR10:01
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04bc 04bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4be
seq_br_type 1 Branch True
seq_branch_adr 04be 0x04be
seq_cond_sel 0b VAL.ALU_LE_ZERO(late)
val_a_adr 21 VR10:01
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04bd 04bd seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04be 04be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04bf 04bf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4c1
seq_br_type 0 Branch False
seq_branch_adr 04c1 0x04c1
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04c0 04c0 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04c1 04c1 seq_br_type 1 Branch True; Flow J cc=True 0x4c3
seq_branch_adr 04c3 0x04c3
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04c2 04c2 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04c3 04c3 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04c4 04c4 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04c5 04c5 seq_br_type 0 Branch False; Flow J cc=False 0x4c7
seq_branch_adr 04c7 0x04c7
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04c6 04c6 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04c7 04c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4c9
seq_br_type 1 Branch True
seq_branch_adr 04c9 0x04c9
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04c8 04c8 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04c9 04c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04ca 04ca seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04cb 04cb seq_br_type 1 Branch True; Flow J cc=True 0x4cd
seq_branch_adr 04cd 0x04cd
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04cc 04cc seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04cd 04cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4cf
seq_br_type 0 Branch False
seq_branch_adr 04cf 0x04cf
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04ce 04ce seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04cf 04cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04d0 04d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04d1 04d1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4d3
seq_br_type 1 Branch True
seq_branch_adr 04d3 0x04d3
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
04d2 04d2 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04d3 04d3 seq_br_type 0 Branch False; Flow J cc=False 0x4d5
seq_branch_adr 04d5 0x04d5
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04d4 04d4 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04d5 04d5 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04d6 04d6 seq_br_type 0 Branch False; Flow J cc=False 0x4d8
seq_branch_adr 04d8 0x04d8
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 25 VR13:05
val_alu_func 7 INC_A
val_frame 13
04d7 04d7 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04d8 04d8 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 07 VAL.ALU_32_CO(late)
val_a_adr 2c VR15:0c
val_alu_func 7 INC_A
val_frame 15
04d9 04d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR10:0a
val_frame 10
04da 04da seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4dc
seq_br_type 0 Branch False
seq_branch_adr 04dc 0x04dc
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR10:0a
val_frame 10
04db 04db seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04dc 04dc seq_br_type 1 Branch True; Flow J cc=True 0x4de
seq_branch_adr 04de 0x04de
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04dd 04dd seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04de 04de seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04df 04df seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR10:0a
val_frame 10
04e0 04e0 seq_br_type 0 Branch False; Flow J cc=False 0x4e2
seq_branch_adr 04e2 0x04e2
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR10:0a
val_frame 10
04e1 04e1 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04e2 04e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x4e4
seq_br_type 1 Branch True
seq_branch_adr 04e4 0x04e4
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04e3 04e3 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04e4 04e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04e5 04e5 seq_br_type 1 Branch True; Flow J cc=True 0x4e7
seq_branch_adr 04e7 0x04e7
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
04e6 04e6 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04e7 04e7 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
04e8 04e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04e9 04e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4eb
seq_br_type 0 Branch False
seq_branch_adr 04eb 0x04eb
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04ea 04ea seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04eb 04eb seq_br_type 1 Branch True; Flow J cc=True 0x4ed
seq_branch_adr 04ed 0x04ed
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
04ec 04ec seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04ed 04ed seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
04ee 04ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04ef 04ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4f1
seq_br_type 0 Branch False
seq_branch_adr 04f1 0x04f1
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04f0 04f0 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04f1 04f1 seq_br_type 1 Branch True; Flow J cc=True 0x4f3
seq_branch_adr 04f3 0x04f3
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04f2 04f2 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04f3 04f3 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04f4 04f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
04f5 04f5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4f7
seq_br_type 0 Branch False
seq_branch_adr 04f7 0x04f7
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
04f6 04f6 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04f7 04f7 seq_br_type 1 Branch True; Flow J cc=True 0x4f9
seq_branch_adr 04f9 0x04f9
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04f8 04f8 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04f9 04f9 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
04fa 04fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04fb 04fb seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x4fd
seq_br_type 0 Branch False
seq_branch_adr 04fd 0x04fd
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
04fc 04fc seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04fd 04fd seq_br_type 1 Branch True; Flow J cc=True 0x4ff
seq_branch_adr 04ff 0x04ff
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
04fe 04fe seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
04ff 04ff seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
0500 0500 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0501 0501 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x503
seq_br_type 0 Branch False
seq_branch_adr 0503 0x0503
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0502 0502 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0503 0503 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0504 0504 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x506
seq_br_type 0 Branch False
seq_branch_adr 0506 0x0506
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0505 0505 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0506 0506 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 3f VR05:1f
val_alu_func 6 A_MINUS_B
val_b_adr 3f VR05:1f
val_frame 5
0507 0507 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x509
seq_br_type 0 Branch False
seq_branch_adr 0509 0x0509
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 3f VR05:1f
val_alu_func 6 A_MINUS_B
val_b_adr 3f VR05:1f
val_frame 5
0508 0508 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0509 0509 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x50b
seq_br_type 1 Branch True
seq_branch_adr 050b 0x050b
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
050a 050a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
050b 050b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
050c 050c seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
050d 050d seq_br_type 0 Branch False; Flow J cc=False 0x50f
seq_branch_adr 050f 0x050f
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
050e 050e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
050f 050f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x511
seq_br_type 1 Branch True
seq_branch_adr 0511 0x0511
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0510 0510 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0511 0511 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0512 0512 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0513 0513 seq_br_type 0 Branch False; Flow J cc=False 0x515
seq_branch_adr 0515 0x0515
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0514 0514 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0515 0515 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x517
seq_br_type 1 Branch True
seq_branch_adr 0517 0x0517
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0516 0516 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0517 0517 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
0518 0518 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
0519 0519 seq_br_type 0 Branch False; Flow J cc=False 0x51b
seq_branch_adr 051b 0x051b
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
051a 051a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
051b 051b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x51d
seq_br_type 1 Branch True
seq_branch_adr 051d 0x051d
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
051c 051c seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
051d 051d seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
051e 051e seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
051f 051f seq_br_type 0 Branch False; Flow J cc=False 0x521
seq_branch_adr 0521 0x0521
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0520 0520 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0521 0521 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x523
seq_br_type 1 Branch True
seq_branch_adr 0523 0x0523
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
0522 0522 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0523 0523 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 2a VR10:0a
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_frame 10
0524 0524 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0525 0525 seq_br_type 0 Branch False; Flow J cc=False 0x527
seq_branch_adr 0527 0x0527
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 2a VR10:0a
val_frame 10
0526 0526 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0527 0527 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0528 0528 seq_br_type 0 Branch False; Flow J cc=False 0x52a
seq_branch_adr 052a 0x052a
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 23 VR10:03
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR10:03
val_frame 10
0529 0529 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
052a 052a seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 3f VR05:1f
val_alu_func 6 A_MINUS_B
val_b_adr 3f VR05:1f
val_frame 5
052b 052b seq_br_type 0 Branch False; Flow J cc=False 0x52d
seq_branch_adr 052d 0x052d
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 3f VR05:1f
val_alu_func 6 A_MINUS_B
val_b_adr 3f VR05:1f
val_frame 5
052c 052c seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
052d 052d seq_br_type 1 Branch True; Flow J cc=True 0x52f
seq_branch_adr 052f 0x052f
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
052e 052e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
052f 052f seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
0530 0530 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_alu_func 13 ONES
0531 0531 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x533
seq_br_type 0 Branch False
seq_branch_adr 0533 0x0533
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_alu_func 13 ONES
0532 0532 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0533 0533 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 0 PASS_A
val_frame 10
0534 0534 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x536
seq_br_type 0 Branch False
seq_branch_adr 0536 0x0536
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 0 PASS_A
val_frame 10
0535 0535 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0536 0536 seq_br_type 1 Branch True; Flow J cc=True 0x538
seq_branch_adr 0538 0x0538
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 10 NOT_A
val_frame 10
0537 0537 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0538 0538 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 10 NOT_A
val_frame 10
0539 0539 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x53b
seq_br_type 1 Branch True
seq_branch_adr 053b 0x053b
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
053a 053a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
053b 053b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
053c 053c seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_alu_func 13 ONES
053d 053d seq_br_type 0 Branch False; Flow J cc=False 0x53f
seq_branch_adr 053f 0x053f
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_alu_func 13 ONES
053e 053e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
053f 053f seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 0 PASS_A
val_frame 10
0540 0540 seq_br_type 0 Branch False; Flow J cc=False 0x542
seq_branch_adr 0542 0x0542
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 0 PASS_A
val_frame 10
0541 0541 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0542 0542 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x544
seq_br_type 1 Branch True
seq_branch_adr 0544 0x0544
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 10 NOT_A
val_frame 10
0543 0543 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0544 0544 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 25 VR10:05
val_alu_func 10 NOT_A
val_frame 10
0545 0545 seq_br_type 1 Branch True; Flow J cc=True 0x547
seq_branch_adr 0547 0x0547
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
0546 0546 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0547 0547 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
0548 0548 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_alu_func 13 ONES
0549 0549 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x54b
seq_br_type 0 Branch False
seq_branch_adr 054b 0x054b
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_alu_func 13 ONES
054a 054a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
054b 054b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 0 PASS_A
val_frame 10
054c 054c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x54e
seq_br_type 0 Branch False
seq_branch_adr 054e 0x054e
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 0 PASS_A
val_frame 10
054d 054d seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
054e 054e seq_br_type 1 Branch True; Flow J cc=True 0x550
seq_branch_adr 0550 0x0550
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 10 NOT_A
val_frame 10
054f 054f seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0550 0550 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 10 NOT_A
val_frame 10
0551 0551 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x553
seq_br_type 1 Branch True
seq_branch_adr 0553 0x0553
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
0552 0552 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0553 0553 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
0554 0554 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_alu_func 13 ONES
0555 0555 seq_br_type 0 Branch False; Flow J cc=False 0x557
seq_branch_adr 0557 0x0557
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_alu_func 13 ONES
0556 0556 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0557 0557 seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 0 PASS_A
val_frame 10
0558 0558 seq_br_type 0 Branch False; Flow J cc=False 0x55a
seq_branch_adr 055a 0x055a
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 0 PASS_A
val_frame 10
0559 0559 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
055a 055a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x55c
seq_br_type 1 Branch True
seq_branch_adr 055c 0x055c
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 10 NOT_A
val_frame 10
055b 055b seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
055c 055c seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 26 VR10:06
val_alu_func 10 NOT_A
val_frame 10
055d 055d seq_br_type 1 Branch True; Flow J cc=True 0x55f
seq_branch_adr 055f 0x055f
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
055e 055e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
055f 055f seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
0560 0560 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_alu_func 13 ONES
0561 0561 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x563
seq_br_type 0 Branch False
seq_branch_adr 0563 0x0563
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_alu_func 13 ONES
0562 0562 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0563 0563 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadb
seq_br_type 5 Call True
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 0 PASS_A
val_frame 10
0564 0564 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x566
seq_br_type 0 Branch False
seq_branch_adr 0566 0x0566
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 0 PASS_A
val_frame 10
0565 0565 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0566 0566 seq_br_type 1 Branch True; Flow J cc=True 0x568
seq_branch_adr 0568 0x0568
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 10 NOT_A
val_frame 10
0567 0567 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0568 0568 seq_br_type 4 Call False; Flow C cc=False 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 10 NOT_A
val_frame 10
0569 0569 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x56b
seq_br_type 1 Branch True
seq_branch_adr 056b 0x056b
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
056a 056a seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
056b 056b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
056c 056c seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_alu_func 13 ONES
056d 056d seq_br_type 0 Branch False; Flow J cc=False 0x56f
seq_branch_adr 056f 0x056f
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_alu_func 13 ONES
056e 056e seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
056f 056f seq_br_type 5 Call True; Flow C cc=True 0xadb
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 0 PASS_A
val_frame 10
0570 0570 seq_br_type 0 Branch False; Flow J cc=False 0x572
seq_branch_adr 0572 0x0572
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 0 PASS_A
val_frame 10
0571 0571 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0572 0572 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x574
seq_br_type 1 Branch True
seq_branch_adr 0574 0x0574
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 10 NOT_A
val_frame 10
0573 0573 seq_br_type 7 Unconditional Call; Flow C 0xadb
seq_branch_adr 0adb COND_ERROR
0574 0574 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0xadb
seq_br_type 4 Call False
seq_branch_adr 0adb COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 27 VR10:07
val_alu_func 10 NOT_A
val_frame 10
0575 0575 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0576 0576 val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0577 0577 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_rand 2 DEC_LOOP_COUNTER
0578 0578 val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
0579 0579 seq_br_type 4 Call False; Flow C cc=False 0xadd
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 03 GP03
val_alu_func 7 INC_A
057a 057a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
057b 057b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
057c 057c val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
057d 057d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
057e 057e val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
057f 057f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 03 GP03
val_alu_func 0 PASS_A
0580 0580 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 1c DEC_A
0581 0581 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
0582 0582 val_a_adr 03 GP03
val_alu_func 1 A_PLUS_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
0583 0583 val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
0584 0584 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 03 GP03
val_alu_func 0 PASS_A
0585 0585 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 04 GP04
0586 0586 seq_b_timing 0 Early Condition; Flow J cc=False 0x581
seq_br_type 0 Branch False
seq_branch_adr 0581 0x0581
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
0587 0587 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0588 0588 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
val_rand 2 DEC_LOOP_COUNTER
0589 0589 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_rand 2 DEC_LOOP_COUNTER
058a 058a val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
058b 058b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
058c 058c val_a_adr 03 GP03
val_alu_func 1 A_PLUS_B
val_b_adr 04 GP04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
058d 058d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
058e 058e val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
058f 058f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadd
seq_br_type 5 Call True
seq_branch_adr 0add REG_FILE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 03 GP03
val_alu_func 0 PASS_A
0590 0590 seq_b_timing 0 Early Condition; Flow J cc=False 0x58a
seq_br_type 0 Branch False
seq_branch_adr 058a 0x058a
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
0591 0591 val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0592 0592 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0593 0593 val_alu_func 13 ONES
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0594 0594 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0595 0595 val_a_adr 20 VR11:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0596 0596 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0597 0597 val_a_adr 21 VR11:01
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0598 0598 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0599 0599 val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
059a 059a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
059b 059b val_a_adr 23 VR11:03
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
059c 059c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
059d 059d val_a_adr 24 VR11:04
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
059e 059e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
059f 059f val_a_adr 25 VR11:05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05a0 05a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05a1 05a1 val_alu_func 1a PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05a2 05a2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05a3 05a3 val_alu_func 1a PASS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05a4 05a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05a5 05a5 val_alu_func 1a PASS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05a6 05a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05a7 05a7 val_alu_func 1a PASS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05a8 05a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05a9 05a9 val_alu_func 1a PASS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05aa 05aa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05ab 05ab val_alu_func 1a PASS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ac 05ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05ad 05ad val_a_adr 20 VR11:00
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ae 05ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05af 05af val_a_adr 21 VR11:01
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05b0 05b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05b1 05b1 val_a_adr 22 VR11:02
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05b2 05b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05b3 05b3 val_a_adr 23 VR11:03
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05b4 05b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05b5 05b5 val_a_adr 24 VR11:04
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05b6 05b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05b7 05b7 val_a_adr 25 VR11:05
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05b8 05b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05b9 05b9 val_alu_func 15 NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ba 05ba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05bb 05bb val_alu_func 15 NOT_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05bc 05bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05bd 05bd val_alu_func 15 NOT_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05be 05be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05bf 05bf val_alu_func 15 NOT_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05c0 05c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05c1 05c1 val_alu_func 15 NOT_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05c2 05c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05c3 05c3 val_alu_func 15 NOT_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05c4 05c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05c5 05c5 val_a_adr 22 VR11:02
val_alu_func 1e A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05c6 05c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05c7 05c7 val_a_adr 20 VR11:00
val_alu_func 1e A_AND_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05c8 05c8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05c9 05c9 val_a_adr 23 VR11:03
val_alu_func 1e A_AND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ca 05ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05cb 05cb val_a_adr 21 VR11:01
val_alu_func 1e A_AND_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05cc 05cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05cd 05cd val_a_adr 24 VR11:04
val_alu_func 1e A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ce 05ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05cf 05cf val_a_adr 20 VR11:00
val_alu_func 1e A_AND_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05d0 05d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05d1 05d1 val_a_adr 25 VR11:05
val_alu_func 1e A_AND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05d2 05d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05d3 05d3 val_a_adr 21 VR11:01
val_alu_func 1e A_AND_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05d4 05d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05d5 05d5 val_a_adr 22 VR11:02
val_alu_func 1b A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05d6 05d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05d7 05d7 val_a_adr 20 VR11:00
val_alu_func 1b A_OR_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05d8 05d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05d9 05d9 val_a_adr 23 VR11:03
val_alu_func 1b A_OR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05da 05da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05db 05db val_a_adr 21 VR11:01
val_alu_func 1b A_OR_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05dc 05dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05dd 05dd val_a_adr 24 VR11:04
val_alu_func 1b A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05de 05de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05df 05df val_a_adr 20 VR11:00
val_alu_func 1b A_OR_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05e0 05e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05e1 05e1 val_a_adr 25 VR11:05
val_alu_func 1b A_OR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05e2 05e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05e3 05e3 val_a_adr 21 VR11:01
val_alu_func 1b A_OR_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05e4 05e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05e5 05e5 val_a_adr 22 VR11:02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05e6 05e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05e7 05e7 val_a_adr 20 VR11:00
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05e8 05e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05e9 05e9 val_a_adr 23 VR11:03
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ea 05ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05eb 05eb val_a_adr 21 VR11:01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ec 05ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05ed 05ed val_a_adr 24 VR11:04
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05ee 05ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05ef 05ef val_a_adr 20 VR11:00
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05f0 05f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05f1 05f1 val_a_adr 25 VR11:05
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05f2 05f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05f3 05f3 val_a_adr 21 VR11:01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05f4 05f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05f5 05f5 val_a_adr 22 VR11:02
val_alu_func 11 A_NAND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05f6 05f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05f7 05f7 val_a_adr 20 VR11:00
val_alu_func 11 A_NAND_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05f8 05f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05f9 05f9 val_a_adr 23 VR11:03
val_alu_func 11 A_NAND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05fa 05fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05fb 05fb val_a_adr 21 VR11:01
val_alu_func 11 A_NAND_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05fc 05fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05fd 05fd val_a_adr 24 VR11:04
val_alu_func 11 A_NAND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
05fe 05fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
05ff 05ff val_a_adr 20 VR11:00
val_alu_func 11 A_NAND_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0600 0600 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0601 0601 val_a_adr 25 VR11:05
val_alu_func 11 A_NAND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0602 0602 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0603 0603 val_a_adr 21 VR11:01
val_alu_func 11 A_NAND_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0604 0604 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0605 0605 val_a_adr 22 VR11:02
val_alu_func 14 A_NOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0606 0606 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0607 0607 val_a_adr 20 VR11:00
val_alu_func 14 A_NOR_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0608 0608 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0609 0609 val_a_adr 23 VR11:03
val_alu_func 14 A_NOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
060a 060a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
060b 060b val_a_adr 21 VR11:01
val_alu_func 14 A_NOR_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
060c 060c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
060d 060d val_a_adr 24 VR11:04
val_alu_func 14 A_NOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
060e 060e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
060f 060f val_a_adr 20 VR11:00
val_alu_func 14 A_NOR_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0610 0610 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0611 0611 val_a_adr 25 VR11:05
val_alu_func 14 A_NOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0612 0612 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0613 0613 val_a_adr 21 VR11:01
val_alu_func 14 A_NOR_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0614 0614 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0615 0615 val_a_adr 22 VR11:02
val_alu_func 16 A_XNOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0616 0616 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0617 0617 val_a_adr 20 VR11:00
val_alu_func 16 A_XNOR_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0618 0618 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0619 0619 val_a_adr 23 VR11:03
val_alu_func 16 A_XNOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
061a 061a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
061b 061b val_a_adr 21 VR11:01
val_alu_func 16 A_XNOR_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
061c 061c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
061d 061d val_a_adr 24 VR11:04
val_alu_func 16 A_XNOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
061e 061e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
061f 061f val_a_adr 20 VR11:00
val_alu_func 16 A_XNOR_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0620 0620 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0621 0621 val_a_adr 25 VR11:05
val_alu_func 16 A_XNOR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0622 0622 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0623 0623 val_a_adr 21 VR11:01
val_alu_func 16 A_XNOR_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0624 0624 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0625 0625 val_a_adr 22 VR11:02
val_alu_func 18 NOT_A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0626 0626 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0627 0627 val_a_adr 20 VR11:00
val_alu_func 18 NOT_A_AND_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0628 0628 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0629 0629 val_a_adr 23 VR11:03
val_alu_func 18 NOT_A_AND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
062a 062a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
062b 062b val_a_adr 21 VR11:01
val_alu_func 18 NOT_A_AND_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
062c 062c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
062d 062d val_a_adr 24 VR11:04
val_alu_func 18 NOT_A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
062e 062e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
062f 062f val_a_adr 20 VR11:00
val_alu_func 18 NOT_A_AND_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0630 0630 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0631 0631 val_a_adr 25 VR11:05
val_alu_func 18 NOT_A_AND_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0632 0632 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0633 0633 val_a_adr 21 VR11:01
val_alu_func 18 NOT_A_AND_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0634 0634 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0635 0635 val_a_adr 22 VR11:02
val_alu_func 1d A_AND_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0636 0636 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0637 0637 val_a_adr 20 VR11:00
val_alu_func 1d A_AND_NOT_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0638 0638 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0639 0639 val_a_adr 23 VR11:03
val_alu_func 1d A_AND_NOT_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
063a 063a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR11:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
063b 063b val_a_adr 21 VR11:01
val_alu_func 1d A_AND_NOT_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
063c 063c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
063d 063d val_a_adr 24 VR11:04
val_alu_func 1d A_AND_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
063e 063e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR11:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
063f 063f val_a_adr 20 VR11:00
val_alu_func 1d A_AND_NOT_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0640 0640 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0641 0641 val_a_adr 25 VR11:05
val_alu_func 1d A_AND_NOT_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0642 0642 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR11:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0643 0643 val_a_adr 21 VR11:01
val_alu_func 1d A_AND_NOT_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0644 0644 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR11:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0645 0645 val_a_adr 22 VR11:02
val_alu_func 12 NOT_A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0646 0646 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0647 0647 val_a_adr 20 VR11:00
val_alu_func 12 NOT_A_OR_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0648 0648 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0649 0649 val_a_adr 23 VR11:03
val_alu_func 12 NOT_A_OR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
064a 064a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
064b 064b val_a_adr 21 VR11:01
val_alu_func 12 NOT_A_OR_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
064c 064c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
064d 064d val_a_adr 24 VR11:04
val_alu_func 12 NOT_A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
064e 064e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
064f 064f val_a_adr 20 VR11:00
val_alu_func 12 NOT_A_OR_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0650 0650 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0651 0651 val_a_adr 25 VR11:05
val_alu_func 12 NOT_A_OR_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0652 0652 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0653 0653 val_a_adr 21 VR11:01
val_alu_func 12 NOT_A_OR_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0654 0654 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0655 0655 val_a_adr 22 VR11:02
val_alu_func 17 A_OR_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0656 0656 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0657 0657 val_a_adr 20 VR11:00
val_alu_func 17 A_OR_NOT_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0658 0658 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0659 0659 val_a_adr 23 VR11:03
val_alu_func 17 A_OR_NOT_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
065a 065a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
065b 065b val_a_adr 21 VR11:01
val_alu_func 17 A_OR_NOT_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
065c 065c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR11:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
065d 065d val_a_adr 24 VR11:04
val_alu_func 17 A_OR_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
065e 065e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
065f 065f val_a_adr 20 VR11:00
val_alu_func 17 A_OR_NOT_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0660 0660 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR11:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0661 0661 val_a_adr 25 VR11:05
val_alu_func 17 A_OR_NOT_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0662 0662 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR11:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0663 0663 val_a_adr 21 VR11:01
val_alu_func 17 A_OR_NOT_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0664 0664 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xadf
seq_br_type 5 Call True
seq_branch_adr 0adf LOGICAL_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR11:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0665 0665 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0666 0666 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0667 0667 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0668 0668 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR10:02
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0669 0669 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR10:02
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
066a 066a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
066b 066b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR10:03
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
066c 066c seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR10:03
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
066d 066d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR05:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
066e 066e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
066f 066f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0670 0670 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR11:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0671 0671 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0672 0672 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0673 0673 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2f VR11:0f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0674 0674 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0675 0675 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0676 0676 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR11:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0677 0677 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0678 0678 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0679 0679 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 31 VR11:11
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
067a 067a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
067b 067b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
067c 067c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR11:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
067d 067d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
067e 067e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
067f 067f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR11:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0680 0680 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0681 0681 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0682 0682 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0683 0683 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR04:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
0684 0684 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR04:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
0685 0685 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0686 0686 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 3f VR05:1f
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 5
0687 0687 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 3f VR05:1f
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 5
0688 0688 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR10:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0689 0689 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
068a 068a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
068b 068b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR11:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
068c 068c seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
068d 068d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
068e 068e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR11:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
068f 068f seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0690 0690 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0691 0691 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR11:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0692 0692 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0693 0693 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0694 0694 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 37 VR11:17
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0695 0695 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0696 0696 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0697 0697 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR11:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0698 0698 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0699 0699 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
069a 069a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 39 VR11:19
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
069b 069b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
069c 069c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR12:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
069d 069d seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
069e 069e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR12:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
069f 069f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06a0 06a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR12:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06a1 06a1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06a2 06a2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR12:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06a3 06a3 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06a4 06a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR12:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06a5 06a5 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06a6 06a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR12:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06a7 06a7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06a8 06a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR12:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06a9 06a9 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06aa 06aa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR12:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06ab 06ab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ac 06ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2f VR12:0f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06ad 06ad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ae 06ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 31 VR12:11
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06af 06af seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b0 06b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR12:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06b1 06b1 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b2 06b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR12:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06b3 06b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b4 06b4 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b5 06b5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06b6 06b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b7 06b7 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06b8 06b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06b9 06b9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ba 06ba seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06bb 06bb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR12:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06bc 06bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06bd 06bd seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06be 06be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR12:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06bf 06bf seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c0 06c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c1 06c1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR11:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06c2 06c2 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c3 06c3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c4 06c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR11:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06c5 06c5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c6 06c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c7 06c7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR12:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06c8 06c8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06c9 06c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ca 06ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR12:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06cb 06cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06cc 06cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06cd 06cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR12:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06ce 06ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06cf 06cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d0 06d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR12:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06d1 06d1 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d2 06d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d3 06d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR11:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06d4 06d4 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d5 06d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d6 06d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR11:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06d7 06d7 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d8 06d8 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06d9 06d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR12:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06da 06da seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06db 06db seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06dc 06dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR12:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06dd 06dd seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06de 06de seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06df 06df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR12:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06e0 06e0 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e1 06e1 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e2 06e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR12:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06e3 06e3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e4 06e4 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e5 06e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR12:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06e6 06e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e7 06e7 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06e8 06e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR12:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06e9 06e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ea 06ea seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06eb 06eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR12:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06ec 06ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ed 06ed seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ee 06ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR12:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06ef 06ef seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f0 06f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f1 06f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR11:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06f2 06f2 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f3 06f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f4 06f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR11:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
06f5 06f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f6 06f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f7 06f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR12:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06f8 06f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06f9 06f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 2 INC_A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06fa 06fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR12:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06fb 06fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06fc 06fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06fd 06fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
06fe 06fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
06ff 06ff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0700 0700 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0701 0701 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0702 0702 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0703 0703 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR11:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0704 0704 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0705 0705 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0706 0706 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR11:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0707 0707 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0708 0708 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0709 0709 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR12:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
070a 070a seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
070b 070b seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
070c 070c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR12:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
070d 070d seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
070e 070e seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 2 INC_A_PLUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
070f 070f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR11:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0710 0710 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0711 0711 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 2 INC_A_PLUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0712 0712 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR11:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0713 0713 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0714 0714 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0715 0715 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0716 0716 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0717 0717 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0718 0718 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR11:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0719 0719 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
071a 071a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
071b 071b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR11:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
071c 071c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
071d 071d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
071e 071e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR12:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
071f 071f seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0720 0720 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0721 0721 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR12:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0722 0722 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0723 0723 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0724 0724 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR12:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0725 0725 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0726 0726 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0727 0727 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR11:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0728 0728 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0729 0729 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 6 A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
072a 072a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR12:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
072b 072b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
072c 072c seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
072d 072d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR12:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
072e 072e seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
072f 072f seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0730 0730 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR12:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0731 0731 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0732 0732 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0733 0733 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR12:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0734 0734 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0735 0735 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0736 0736 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR11:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0737 0737 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0738 0738 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0739 0739 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR11:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
073a 073a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
073b 073b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
073c 073c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
073d 073d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
073e 073e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
073f 073f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR12:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0740 0740 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0741 0741 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 6 A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0742 0742 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR11:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0743 0743 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0744 0744 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0745 0745 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR12:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0746 0746 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0747 0747 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0748 0748 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR11:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0749 0749 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
074a 074a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
074b 074b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR11:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
074c 074c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
074d 074d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
074e 074e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR12:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
074f 074f seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0750 0750 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0751 0751 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR12:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0752 0752 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0753 0753 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0754 0754 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0755 0755 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0756 0756 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0757 0757 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR12:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0758 0758 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0759 0759 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 20 VR11:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
075a 075a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR12:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
075b 075b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
075c 075c seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
075d 075d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
075e 075e seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
075f 075f seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0760 0760 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR12:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0761 0761 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 23 VR11:03
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0762 0762 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 23 VR11:03
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0763 0763 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR12:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0764 0764 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0765 0765 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0766 0766 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR12:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0767 0767 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 24 VR11:04
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0768 0768 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 24 VR11:04
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0769 0769 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR11:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
076a 076a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
076b 076b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
076c 076c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR12:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
076d 076d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 25 VR11:05
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
076e 076e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 25 VR11:05
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
076f 076f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR12:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0770 0770 seq_br_type 4 Call False; Flow C cc=False 0xae1
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0771 0771 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 09 VAL.ALU_OVERFLOW(late)
val_a_adr 21 VR11:01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0772 0772 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae1
seq_br_type 5 Call True
seq_branch_adr 0ae1 ARITH_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR11:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0773 0773 seq_cond_sel 16 VAL.TRUE(early)
0774 0774 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0775 0775 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0776 0776 seq_cond_sel 16 VAL.TRUE(early)
0777 0777 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0778 0778 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0779 0779 seq_cond_sel 17 VAL.FALSE(early)
077a 077a seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
077b 077b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
077c 077c seq_cond_sel 17 VAL.FALSE(early)
077d 077d seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
077e 077e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
077f 077f seq_cond_sel 16 VAL.TRUE(early)
0780 0780 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0781 0781 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0782 0782 seq_cond_sel 16 VAL.TRUE(early)
0783 0783 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0784 0784 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0785 0785 seq_cond_sel 17 VAL.FALSE(early)
0786 0786 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
0787 0787 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0788 0788 seq_cond_sel 17 VAL.FALSE(early)
0789 0789 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
078a 078a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
078b 078b seq_cond_sel 16 VAL.TRUE(early)
078c 078c seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
078d 078d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
078e 078e seq_cond_sel 16 VAL.TRUE(early)
078f 078f seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0790 0790 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0791 0791 seq_cond_sel 17 VAL.FALSE(early)
0792 0792 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0793 0793 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0794 0794 seq_cond_sel 17 VAL.FALSE(early)
0795 0795 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0796 0796 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0797 0797 seq_cond_sel 16 VAL.TRUE(early)
0798 0798 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0799 0799 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
079a 079a seq_cond_sel 16 VAL.TRUE(early)
079b 079b seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
079c 079c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
079d 079d seq_cond_sel 17 VAL.FALSE(early)
079e 079e seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
079f 079f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07a0 07a0 seq_cond_sel 17 VAL.FALSE(early)
07a1 07a1 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07a2 07a2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07a3 07a3 seq_cond_sel 16 VAL.TRUE(early)
07a4 07a4 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07a5 07a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07a6 07a6 seq_cond_sel 16 VAL.TRUE(early)
07a7 07a7 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07a8 07a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07a9 07a9 seq_cond_sel 17 VAL.FALSE(early)
07aa 07aa seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07ab 07ab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07ac 07ac seq_cond_sel 17 VAL.FALSE(early)
07ad 07ad seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07ae 07ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07af 07af seq_cond_sel 16 VAL.TRUE(early)
07b0 07b0 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07b1 07b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07b2 07b2 seq_cond_sel 16 VAL.TRUE(early)
07b3 07b3 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07b4 07b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07b5 07b5 seq_cond_sel 17 VAL.FALSE(early)
07b6 07b6 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07b7 07b7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07b8 07b8 seq_cond_sel 17 VAL.FALSE(early)
07b9 07b9 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
07ba 07ba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07bb 07bb seq_cond_sel 16 VAL.TRUE(early)
07bc 07bc seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07bd 07bd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
07be 07be seq_cond_sel 16 VAL.TRUE(early)
07bf 07bf seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07c0 07c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
07c1 07c1 seq_cond_sel 17 VAL.FALSE(early)
07c2 07c2 seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07c3 07c3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07c4 07c4 seq_cond_sel 17 VAL.FALSE(early)
07c5 07c5 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07c6 07c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07c7 07c7 seq_cond_sel 16 VAL.TRUE(early)
07c8 07c8 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07c9 07c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07ca 07ca seq_cond_sel 16 VAL.TRUE(early)
07cb 07cb seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07cc 07cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR12:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07cd 07cd seq_cond_sel 17 VAL.FALSE(early)
07ce 07ce seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07cf 07cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
07d0 07d0 seq_cond_sel 17 VAL.FALSE(early)
07d1 07d1 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
07d2 07d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae3
seq_br_type 5 Call True
seq_branch_adr 0ae3 COND_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR11:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
07d3 07d3 val_a_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07d4 07d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR12:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07d5 07d5 val_a_adr 22 VR11:02
val_alu_func 13 ONES
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07d6 07d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 37 VR12:17
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07d7 07d7 val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07d8 07d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
07d9 07d9 val_a_adr 22 VR11:02
val_alu_func 1a PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07da 07da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR12:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07db 07db val_a_adr 22 VR11:02
val_alu_func 10 NOT_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07dc 07dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 39 VR12:19
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07dd 07dd val_a_adr 22 VR11:02
val_alu_func 15 NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07de 07de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR12:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07df 07df val_a_adr 22 VR11:02
val_alu_func 1e A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07e0 07e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR12:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07e1 07e1 val_a_adr 22 VR11:02
val_alu_func 1b A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07e2 07e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR12:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07e3 07e3 val_a_adr 22 VR11:02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07e4 07e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR12:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07e5 07e5 val_a_adr 22 VR11:02
val_alu_func 11 A_NAND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07e6 07e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR12:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07e7 07e7 val_a_adr 22 VR11:02
val_alu_func 14 A_NOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07e8 07e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR12:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
07e9 07e9 val_a_adr 22 VR11:02
val_alu_func 16 A_XNOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07ea 07ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR13:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07eb 07eb val_a_adr 22 VR11:02
val_alu_func 18 NOT_A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07ec 07ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR13:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07ed 07ed val_a_adr 22 VR11:02
val_alu_func 1d A_AND_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07ee 07ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR13:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07ef 07ef val_a_adr 22 VR11:02
val_alu_func 12 NOT_A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07f0 07f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR13:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07f1 07f1 val_a_adr 22 VR11:02
val_alu_func 17 A_OR_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07f2 07f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR13:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07f3 07f3 val_a_adr 22 VR10:02
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 9 PASS_A_HIGH
07f4 07f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR10:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
07f5 07f5 val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 9 PASS_A_HIGH
07f6 07f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR13:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07f7 07f7 val_a_adr 22 VR11:02
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07f8 07f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR13:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07f9 07f9 val_a_adr 22 VR11:02
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07fa 07fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR13:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07fb 07fb val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07fc 07fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR13:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07fd 07fd val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
07fe 07fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR13:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
07ff 07ff val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0800 0800 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR13:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0801 0801 val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0802 0802 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR13:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0803 0803 seq_cond_sel 16 VAL.TRUE(early)
0804 0804 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0805 0805 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0806 0806 seq_cond_sel 17 VAL.FALSE(early)
0807 0807 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0808 0808 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR12:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0809 0809 seq_cond_sel 16 VAL.TRUE(early)
080a 080a seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
080b 080b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR12:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
080c 080c seq_cond_sel 17 VAL.FALSE(early)
080d 080d seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
080e 080e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
080f 080f seq_cond_sel 16 VAL.TRUE(early)
0810 0810 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0811 0811 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0812 0812 seq_cond_sel 17 VAL.FALSE(early)
0813 0813 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func c PASS_A_ELSE_INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0814 0814 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR11:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0815 0815 seq_cond_sel 16 VAL.TRUE(early)
0816 0816 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0817 0817 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR11:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0818 0818 seq_cond_sel 17 VAL.FALSE(early)
0819 0819 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func d INC_A_ELSE_PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
081a 081a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
081b 081b seq_cond_sel 16 VAL.TRUE(early)
081c 081c seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
081d 081d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
081e 081e seq_cond_sel 17 VAL.FALSE(early)
081f 081f seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func e PASS_A_ELSE_DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0820 0820 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR11:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0821 0821 seq_cond_sel 16 VAL.TRUE(early)
0822 0822 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0823 0823 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR11:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0824 0824 seq_cond_sel 17 VAL.FALSE(early)
0825 0825 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func f DEC_A_ELSE__PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0826 0826 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0827 0827 seq_cond_sel 16 VAL.TRUE(early)
0828 0828 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0829 0829 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR13:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
082a 082a seq_cond_sel 17 VAL.FALSE(early)
082b 082b seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
082c 082c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR13:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
082d 082d seq_cond_sel 16 VAL.TRUE(early)
082e 082e seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
082f 082f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR13:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0830 0830 seq_cond_sel 17 VAL.FALSE(early)
0831 0831 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 9 PASS_A_HIGH
0832 0832 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR13:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0833 0833 val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0834 0834 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR13:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0835 0835 val_alu_func 13 ONES
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0836 0836 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2d VR13:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0837 0837 val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0838 0838 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0839 0839 val_alu_func 1a PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
083a 083a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
083b 083b val_a_adr 22 VR11:02
val_alu_func 10 NOT_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
083c 083c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2f VR13:0f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
083d 083d val_alu_func 15 NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
083e 083e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR13:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
083f 083f val_a_adr 22 VR11:02
val_alu_func 1e A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0840 0840 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 31 VR13:11
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0841 0841 val_a_adr 22 VR11:02
val_alu_func 1b A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0842 0842 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR13:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0843 0843 val_a_adr 22 VR11:02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0844 0844 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR13:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0845 0845 val_a_adr 22 VR11:02
val_alu_func 11 A_NAND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0846 0846 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR13:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0847 0847 val_a_adr 22 VR11:02
val_alu_func 14 A_NOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0848 0848 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR13:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0849 0849 val_a_adr 22 VR11:02
val_alu_func 16 A_XNOR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
084a 084a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR13:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
084b 084b val_a_adr 22 VR11:02
val_alu_func 18 NOT_A_AND_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
084c 084c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 37 VR13:17
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
084d 084d val_a_adr 22 VR11:02
val_alu_func 1d A_AND_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
084e 084e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR13:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
084f 084f val_a_adr 22 VR11:02
val_alu_func 12 NOT_A_OR_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0850 0850 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 39 VR13:19
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0851 0851 val_a_adr 22 VR11:02
val_alu_func 17 A_OR_NOT_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0852 0852 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR13:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0853 0853 val_a_adr 22 VR10:02
val_alu_func 7 INC_A
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand a PASS_B_HIGH
0854 0854 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR10:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0855 0855 val_a_adr 20 VR10:00
val_alu_func 1c DEC_A
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand a PASS_B_HIGH
0856 0856 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR13:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0857 0857 val_a_adr 22 VR11:02
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0858 0858 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR13:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0859 0859 val_a_adr 22 VR11:02
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
085a 085a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR13:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
085b 085b val_a_adr 22 VR11:02
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
085c 085c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR13:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
085d 085d val_a_adr 22 VR11:02
val_alu_func 2 INC_A_PLUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
085e 085e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR13:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
085f 085f val_a_adr 22 VR11:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0860 0860 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR13:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0861 0861 val_a_adr 22 VR11:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0862 0862 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR14:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0863 0863 seq_cond_sel 16 VAL.TRUE(early)
0864 0864 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0865 0865 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0866 0866 seq_cond_sel 17 VAL.FALSE(early)
0867 0867 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func a PASS_A_ELSE_PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0868 0868 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0869 0869 seq_cond_sel 16 VAL.TRUE(early)
086a 086a seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
086b 086b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
086c 086c seq_cond_sel 17 VAL.FALSE(early)
086d 086d seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func b PASS_B_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
086e 086e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
086f 086f seq_cond_sel 16 VAL.TRUE(early)
0870 0870 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func c PASS_A_ELSE_INC_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0871 0871 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0872 0872 seq_cond_sel 17 VAL.FALSE(early)
0873 0873 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func c PASS_A_ELSE_INC_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0874 0874 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR14:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0875 0875 seq_cond_sel 16 VAL.TRUE(early)
0876 0876 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func d INC_A_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0877 0877 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR14:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0878 0878 seq_cond_sel 17 VAL.FALSE(early)
0879 0879 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func d INC_A_ELSE_PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
087a 087a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
087b 087b seq_cond_sel 16 VAL.TRUE(early)
087c 087c seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func e PASS_A_ELSE_DEC_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
087d 087d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
087e 087e seq_cond_sel 17 VAL.FALSE(early)
087f 087f seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func e PASS_A_ELSE_DEC_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0880 0880 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR14:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0881 0881 seq_cond_sel 16 VAL.TRUE(early)
0882 0882 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func f DEC_A_ELSE__PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0883 0883 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR14:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0884 0884 seq_cond_sel 17 VAL.FALSE(early)
0885 0885 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func f DEC_A_ELSE__PASS_A
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0886 0886 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0887 0887 seq_cond_sel 16 VAL.TRUE(early)
0888 0888 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0889 0889 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR13:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
088a 088a seq_cond_sel 17 VAL.FALSE(early)
088b 088b seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 8 PLUS_ELSE_MINUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
088c 088c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR13:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
088d 088d seq_cond_sel 16 VAL.TRUE(early)
088e 088e seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
088f 088f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3f VR13:1f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0890 0890 seq_cond_sel 17 VAL.FALSE(early)
0891 0891 seq_en_micro 0
val_a_adr 22 VR11:02
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand a PASS_B_HIGH
0892 0892 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae5
seq_br_type 5 Call True
seq_branch_adr 0ae5 SPLIT_ALU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR13:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0893 0893 val_a_adr 14 ZEROS
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0894 0894 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae7
seq_br_type 5 Call True
seq_branch_adr 0ae7 A_PORT_ZERO_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0895 0895 seq_br_type 3 Unconditional Branch; Flow J 0x896
seq_branch_adr 0896 0x0896
0896 0896 ioc_fiubs 1 val
val_a_adr 14 ZEROS
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
0897 0897 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae7
seq_br_type 5 Call True
seq_branch_adr 0ae7 A_PORT_ZERO_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0898 0898 <default>
0899 0899 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
089a 089a seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
089b 089b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
089c 089c val_a_adr 28 VR10:08
val_alu_func 10 NOT_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
089d 089d seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
089e 089e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
089f 089f val_a_adr 28 VR10:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
08a0 08a0 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08a1 08a1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 28 VR10:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08a2 08a2 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08a3 08a3 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08a4 08a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08a5 08a5 val_a_adr 21 VR04:01
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08a6 08a6 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08a7 08a7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08a8 08a8 val_a_adr 22 VR04:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08a9 08a9 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08aa 08aa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 22 VR04:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08ab 08ab val_a_adr 23 VR04:03
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08ac 08ac seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08ad 08ad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 23 VR04:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08ae 08ae val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08af 08af seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08b0 08b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 24 VR04:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08b1 08b1 val_a_adr 25 VR04:05
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08b2 08b2 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08b3 08b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 25 VR04:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08b4 08b4 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08b5 08b5 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08b6 08b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 26 VR04:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08b7 08b7 val_a_adr 27 VR04:07
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08b8 08b8 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08b9 08b9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 27 VR04:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08ba 08ba val_a_adr 28 VR04:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08bb 08bb seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08bc 08bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 28 VR04:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08bd 08bd val_a_adr 29 VR04:09
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08be 08be seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08bf 08bf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 29 VR04:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
08c0 08c0 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
08c1 08c1 val_c_adr 3e GP01
val_c_mux_sel 2 ALU
08c2 08c2 seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 17 LOOP_COUNTER
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
08c3 08c3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08c4 08c4 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 01 GP01
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
08c5 08c5 seq_br_type 1 Branch True; Flow J cc=True 0x8c4
seq_branch_adr 08c4 0x08c4
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08c6 08c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 02 GP02
val_alu_func 19 X_XOR_B
val_b_adr 2a VR04:0a
val_frame 4
08c7 08c7 seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08c8 08c8 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
08c9 08c9 seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
08ca 08ca val_a_adr 28 VR10:08
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
08cb 08cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08cc 08cc seq_b_timing 0 Early Condition; Flow J cc=False 0x8cb
seq_br_type 0 Branch False
seq_branch_adr 08cb 0x08cb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
08cd 08cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08ce 08ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08cf 08cf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 02 GP02
val_alu_func 19 X_XOR_B
val_b_adr 29 VR10:09
val_frame 10
08d0 08d0 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08d1 08d1 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 20 VR10:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR10:00
val_frame 10
val_rand b DIVIDE
08d2 08d2 seq_b_timing 0 Early Condition; Flow C cc=False 0xae9
seq_br_type 4 Call False
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 20 VR10:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR10:00
val_frame 10
val_rand b DIVIDE
08d3 08d3 seq_b_timing 0 Early Condition; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
08d4 08d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xae9
seq_br_type 5 Call True
seq_branch_adr 0ae9 LOOP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 28 VR10:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08d5 08d5 val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
08d6 08d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08d7 08d7 val_a_adr 22 VR10:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
08d8 08d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08d9 08d9 val_a_adr 20 VR11:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08da 08da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08db 08db val_a_adr 21 VR11:01
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08dc 08dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08dd 08dd val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08de 08de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08df 08df val_a_adr 23 VR11:03
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08e0 08e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08e1 08e1 val_a_adr 24 VR11:04
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08e2 08e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08e3 08e3 val_a_adr 25 VR11:05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
08e4 08e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
08e5 08e5 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
08e6 08e6 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08e7 08e7 val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
08e8 08e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaeb
seq_br_type 5 Call True
seq_branch_adr 0aeb CMUX_PASS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08e9 08e9 seq_b_timing 0 Early Condition; Flow J cc=False 0x8e7
seq_br_type 0 Branch False
seq_branch_adr 08e7 0x08e7
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
08ea 08ea val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 10
08eb 08eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08ec 08ec val_a_adr 22 VR10:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 10
08ed 08ed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR10:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
08ee 08ee val_a_adr 20 VR11:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08ef 08ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2a VR12:0a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08f0 08f0 val_a_adr 21 VR11:01
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08f1 08f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR12:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08f2 08f2 val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08f3 08f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR12:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08f4 08f4 val_a_adr 23 VR11:03
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08f5 08f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 30 VR12:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08f6 08f6 val_a_adr 24 VR11:04
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08f7 08f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR12:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08f8 08f8 val_a_adr 25 VR11:05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_frame 11
08f9 08f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR12:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
08fa 08fa val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
08fb 08fb val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
08fc 08fc val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
08fd 08fd val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
08fe 08fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaed
seq_br_type 5 Call True
seq_branch_adr 0aed CMUX_LEFT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
08ff 08ff seq_b_timing 0 Early Condition; Flow J cc=False 0x8fd
seq_br_type 0 Branch False
seq_branch_adr 08fd 0x08fd
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 0 ALU << 1
val_rand 2 DEC_LOOP_COUNTER
0900 0900 val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 10
0901 0901 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0902 0902 val_a_adr 22 VR10:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 10
0903 0903 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR10:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0904 0904 val_a_adr 20 VR11:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
0905 0905 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR14:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0906 0906 val_a_adr 21 VR11:01
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
0907 0907 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR14:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0908 0908 val_a_adr 22 VR11:02
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
0909 0909 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 26 VR14:06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
090a 090a val_a_adr 23 VR11:03
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
090b 090b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR14:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
090c 090c val_a_adr 24 VR11:04
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
090d 090d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 28 VR14:08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
090e 090e val_a_adr 25 VR11:05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
val_frame 11
090f 090f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR14:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0910 0910 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0911 0911 val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0912 0912 val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
0913 0913 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0914 0914 val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0915 0915 seq_b_timing 0 Early Condition; Flow J cc=False 0x913
seq_br_type 0 Branch False
seq_branch_adr 0913 0x0913
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
0916 0916 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
0917 0917 val_a_adr 26 VR04:06
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR04:04
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0918 0918 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaef
seq_br_type 5 Call True
seq_branch_adr 0aef CMUX_RIGHT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0919 0919 val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
091a 091a val_a_adr 06 GP06
val_alu_func 3 LEFT_I_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
091b 091b seq_b_timing 0 Early Condition; Flow J cc=False 0x918
seq_br_type 0 Branch False
seq_branch_adr 0918 0x0918
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 1 ALU >> 16
091c 091c seq_br_type 3 Unconditional Branch; Flow J 0x91d
seq_branch_adr 091d 0x091d
091d 091d ioc_load_wdr 0
val_b_adr 20 VR10:00
val_frame 10
091e 091e val_c_adr 3e GP01
091f 091f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0920 0920 ioc_load_wdr 0
val_b_adr 22 VR10:02
val_frame 10
0921 0921 val_c_adr 3e GP01
0922 0922 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0923 0923 ioc_load_wdr 0
val_b_adr 20 VR11:00
val_frame 11
0924 0924 val_c_adr 3e GP01
0925 0925 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0926 0926 ioc_load_wdr 0 ; VAL {VAL_BUS := 16#A5A5A5A5A5A5A5A5# },
; LOAD_WDR,
val_b_adr 21 VR11:01
val_frame 11
0927 0927 val_c_adr 3e GP01 ; VAL {RESULT := WDR},
; VAL {BAD_BITS := RESULT XOR 16#A5A5A5A5A5A5A5A5# },
; IF VAL {RESULT /= 16#A5A5A5A5A5A5A5A5#) THEN
; RARELY CALL CMUX_WDR_ERROR,
0928 0928 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0929 0929 ioc_load_wdr 0 ; VAL {VAL_BUS := 16#A5A5A5A5A5A5A5A5# },
; LOAD_WDR,
val_b_adr 22 VR11:02
val_frame 11
092a 092a val_c_adr 3e GP01 ; VAL {RESULT := WDR},
; VAL {BAD_BITS := RESULT XOR 16#36C936C936C936C9# },
; IF VAL {RESULT /= 16#36C936C936C936C9#) THEN
; RARELY CALL CMUX_WDR_ERROR,
092b 092b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
092c 092c ioc_load_wdr 0
val_b_adr 23 VR11:03
val_frame 11
092d 092d val_c_adr 3e GP01
092e 092e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
092f 092f ioc_load_wdr 0
val_b_adr 24 VR11:04
val_frame 11
0930 0930 val_c_adr 3e GP01
0931 0931 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0932 0932 ioc_load_wdr 0
val_b_adr 25 VR11:05
val_frame 11
0933 0933 val_c_adr 3e GP01
0934 0934 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0935 0935 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0936 0936 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0937 0937 ioc_load_wdr 0
val_b_adr 05 GP05
0938 0938 val_c_adr 3e GP01
0939 0939 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf1
seq_br_type 5 Call True
seq_branch_adr 0af1 CMUX_WDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
093a 093a seq_b_timing 0 Early Condition; Flow J cc=False 0x937
seq_br_type 0 Branch False
seq_branch_adr 0937 0x0937
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
093b 093b <default>
093c 093c seq_br_type 3 Unconditional Branch; Flow J 0x93d
seq_branch_adr 093d 0x093d
093d 093d ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
093e 093e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
093f 093f ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
0940 0940 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0941 0941 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
0942 0942 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR11:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0943 0943 ioc_fiubs 1 val
val_a_adr 21 VR11:01
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
0944 0944 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR11:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0945 0945 ioc_fiubs 1 val
val_a_adr 22 VR11:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
0946 0946 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR11:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0947 0947 ioc_fiubs 1 val
val_a_adr 23 VR11:03
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
0948 0948 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR11:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
0949 0949 ioc_fiubs 1 val
val_a_adr 24 VR11:04
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
094a 094a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR11:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
094b 094b ioc_fiubs 1 val
val_a_adr 25 VR11:05
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 11
094c 094c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR11:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
094d 094d val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
094e 094e val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
094f 094f ioc_fiubs 1 val
val_a_adr 05 GP05
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
0950 0950 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf3
seq_br_type 5 Call True
seq_branch_adr 0af3 CMUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0951 0951 seq_b_timing 0 Early Condition; Flow J cc=False 0x94f
seq_br_type 0 Branch False
seq_branch_adr 094f 0x094f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0952 0952 ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 10
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0953 0953 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR10:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0954 0954 ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_alu_func 1a PASS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 10
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0955 0955 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR13:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0956 0956 ioc_fiubs 1 val
val_a_adr 22 VR11:02
val_alu_func 1a PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0957 0957 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR12:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
0958 0958 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0959 0959 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
095a 095a ioc_fiubs 1 val
val_a_adr 22 VR11:02
val_alu_func 1a PASS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
095b 095b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3a VR12:1a
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
095c 095c ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
095d 095d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR13:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
095e 095e ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
095f 095f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2f VR13:0f
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0960 0960 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0961 0961 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 36 VR13:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0962 0962 ioc_fiubs 1 val
val_a_adr 28 VR16:08
val_alu_func 1a PASS_B
val_b_adr 23 VR16:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 16
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0963 0963 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR16:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
0964 0964 ioc_fiubs 1 val
val_a_adr 37 VR17:17
val_alu_func 1a PASS_B
val_b_adr 36 VR17:16
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_c_source 0 FIU_BUS
val_frame 17
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0965 0965 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 29 VR16:09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
0966 0966 ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0967 0967 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR13:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
0968 0968 ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_alu_func 1a PASS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0969 0969 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 25 VR10:05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
096a 096a ioc_fiubs 1 val
val_a_adr 22 VR11:02
val_alu_func 1a PASS_B
val_b_adr 20 VR11:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
096b 096b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR13:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
096c 096c ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 22 VR11:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
096d 096d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 38 VR12:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 12
096e 096e ioc_fiubs 1 val
val_a_adr 22 VR11:02
val_alu_func 1a PASS_B
val_b_adr 21 VR11:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
096f 096f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3b VR14:1b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0970 0970 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 23 VR11:03
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0971 0971 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3c VR14:1c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0972 0972 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 24 VR11:04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0973 0973 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3d VR14:1d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0974 0974 ioc_fiubs 1 val
val_a_adr 20 VR11:00
val_alu_func 1a PASS_B
val_b_adr 25 VR11:05
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 11
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0975 0975 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf7
seq_br_type 5 Call True
seq_branch_adr 0af7 FIU_LOW_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 3e VR14:1e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0976 0976 ioc_fiubs 1 val
val_a_adr 28 VR16:08
val_alu_func 1a PASS_B
val_b_adr 26 VR16:06
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 16
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0977 0977 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 27 VR16:07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
0978 0978 ioc_fiubs 1 val
val_a_adr 37 VR17:17
val_alu_func 1a PASS_B
val_b_adr 35 VR17:15
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 17
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
0979 0979 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf5
seq_br_type 5 Call True
seq_branch_adr 0af5 FIU_HIGH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
097a 097a seq_cond_sel 17 VAL.FALSE(early)
097b 097b ioc_fiubs 1 val
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
097c 097c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
097d 097d seq_cond_sel 16 VAL.TRUE(early)
097e 097e ioc_fiubs 1 val
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
val_a_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
097f 097f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR10:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0980 0980 ioc_fiubs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0981 0981 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0982 0982 ioc_fiubs 1 val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0983 0983 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR10:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0984 0984 ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0985 0985 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR10:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0986 0986 ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0987 0987 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0988 0988 ioc_fiubs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0989 0989 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 24 VR10:04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
098a 098a ioc_fiubs 1 val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
098b 098b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
098c 098c ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
098d 098d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
098e 098e ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 22 VR10:02
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
098f 098f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0990 0990 ioc_fiubs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0991 0991 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0992 0992 seq_cond_sel 17 VAL.FALSE(early)
0993 0993 ioc_fiubs 1 val
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0994 0994 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0995 0995 seq_cond_sel 16 VAL.TRUE(early)
0996 0996 ioc_fiubs 1 val
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
val_a_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0997 0997 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0998 0998 ioc_fiubs 1 val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
0999 0999 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
099a 099a ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
099b 099b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
099c 099c ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
099d 099d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
099e 099e ioc_fiubs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
099f 099f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
09a0 09a0 ioc_fiubs 1 val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
09a1 09a1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09a2 09a2 ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
09a3 09a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09a4 09a4 ioc_fiubs 1 val
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 20 VR10:00
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 10
val_rand 3 CONDITION_TO_FIU
09a5 09a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaf9
seq_br_type 5 Call True
seq_branch_adr 0af9 FIU_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
09a6 09a6 <default>
09a7 09a7 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
09a8 09a8 val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 5 COUNT_ZEROS
09a9 09a9 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09aa 09aa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09ab 09ab seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09ac 09ac seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09ad 09ad seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09ae 09ae seq_en_micro 0
val_a_adr 15 ZERO_COUNTER
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
09af 09af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafb
seq_br_type 5 Call True
seq_branch_adr 0afb ZERO_COUNT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
09b0 09b0 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
09b1 09b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09b2 09b2 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_rand 5 COUNT_ZEROS
09b3 09b3 seq_en_micro 0
val_a_adr 15 ZERO_COUNTER
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
09b4 09b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafb
seq_br_type 5 Call True
seq_branch_adr 0afb ZERO_COUNT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
09b5 09b5 seq_b_timing 0 Early Condition; Flow J cc=False 0x9b1
seq_br_type 0 Branch False
seq_branch_adr 09b1 0x09b1
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
09b6 09b6 val_a_adr 26 VR04:06
val_alu_func 7 INC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
09b7 09b7 val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 5 COUNT_ZEROS
09b8 09b8 seq_en_micro 0
val_a_adr 15 ZERO_COUNTER
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
09b9 09b9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafb
seq_br_type 5 Call True
seq_branch_adr 0afb ZERO_COUNT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
09ba 09ba seq_b_timing 0 Early Condition; Flow J cc=False 0x9b8
seq_br_type 0 Branch False
seq_branch_adr 09b8 0x09b8
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 5 COUNT_ZEROS
09bb 09bb seq_br_type 3 Unconditional Branch; Flow J 0x9bc
seq_branch_adr 09bc 0x09bc
09bc 09bc val_alu_func 13 ONES
val_rand 5 COUNT_ZEROS
09bd 09bd ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 15 ZERO_COUNTER
val_alu_func 1a PASS_B
val_b_adr 20 VR04:00
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_frame 4
val_rand 5 COUNT_ZEROS
09be 09be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafb
seq_br_type 5 Call True
seq_branch_adr 0afb ZERO_COUNT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 15 ZERO_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 2b VR10:0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09bf 09bf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafb
seq_br_type 5 Call True
seq_branch_adr 0afb ZERO_COUNT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09c0 09c0 <default>
09c1 09c1 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
09c2 09c2 val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
09c3 09c3 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_rand 2 DEC_LOOP_COUNTER
09c4 09c4 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09c5 09c5 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09c6 09c6 seq_b_timing 0 Early Condition; Flow J cc=False 0x9c3
seq_br_type 0 Branch False
seq_branch_adr 09c3 0x09c3
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
09c7 09c7 val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
09c8 09c8 seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_rand 2 DEC_LOOP_COUNTER
09c9 09c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09ca 09ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09cb 09cb seq_b_timing 0 Early Condition; Flow J cc=False 0x9c8
seq_br_type 0 Branch False
seq_branch_adr 09c8 0x09c8
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
09cc 09cc val_a_adr 25 VR04:05
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
09cd 09cd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 10 VAL.ALU_32_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_rand 2 DEC_LOOP_COUNTER
09ce 09ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xafd
seq_br_type 5 Call True
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 11 VAL.ALU_40_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09cf 09cf seq_br_type 4 Call False; Flow C cc=False 0xafd
seq_branch_adr 0afd ZERO_COND_ERROR
seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
09d0 09d0 seq_b_timing 0 Early Condition; Flow J cc=False 0x9cd
seq_br_type 0 Branch False
seq_branch_adr 09cd 0x09cd
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
09d1 09d1 val_a_adr 28 VR10:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
09d2 09d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xaff
seq_br_type 5 Call True
seq_branch_adr 0aff REG_A_B_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
09d3 09d3 seq_b_timing 0 Early Condition; Flow J cc=False 0x9d2
seq_br_type 0 Branch False
seq_branch_adr 09d2 0x09d2
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
09d4 09d4 val_a_adr 22 VR10:02
val_b_adr 20 VR10:00
val_frame 10
val_rand c START_MULTIPLY
09d5 09d5 seq_en_micro 0
val_m_b_src 0 Bits 0…15
09d6 09d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
val_m_b_src 1 Bits 16…31
09d7 09d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
val_m_b_src 2 Bits 32…47
09d8 09d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
09d9 09d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
09da 09da val_a_adr 20 VR10:00
val_b_adr 22 VR10:02
val_frame 10
val_rand c START_MULTIPLY
09db 09db seq_en_micro 0
val_m_a_src 0 Bits 0…15
09dc 09dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
val_m_a_src 1 Bits 16…31
09dd 09dd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
val_m_a_src 2 Bits 32…47
09de 09de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
09df 09df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 0 PASS_A
09e0 09e0 val_a_adr 21 VR10:01
val_b_adr 22 VR10:02
val_frame 10
val_rand c START_MULTIPLY
09e1 09e1 seq_en_micro 0
val_m_b_src 0 Bits 0…15
09e2 09e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_m_b_src 1 Bits 16…31
09e3 09e3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_m_b_src 2 Bits 32…47
09e4 09e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09e5 09e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09e6 09e6 val_a_adr 22 VR10:02
val_b_adr 21 VR10:01
val_frame 10
val_rand c START_MULTIPLY
09e7 09e7 seq_en_micro 0
val_m_a_src 0 Bits 0…15
09e8 09e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_m_a_src 1 Bits 16…31
09e9 09e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_m_a_src 2 Bits 32…47
09ea 09ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09eb 09eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09ec 09ec val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
09ed 09ed val_a_adr 26 VR10:06
val_b_adr 03 GP03
val_frame 10
val_rand c START_MULTIPLY
09ee 09ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09ef 09ef val_a_adr 39 VR10:19
val_b_adr 03 GP03
val_frame 10
val_m_a_src 2 Bits 32…47
val_rand c START_MULTIPLY
09f0 09f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09f1 09f1 val_a_adr 3a VR10:1a
val_b_adr 03 GP03
val_frame 10
val_m_a_src 1 Bits 16…31
val_rand c START_MULTIPLY
09f2 09f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09f3 09f3 val_a_adr 3b VR10:1b
val_b_adr 03 GP03
val_frame 10
val_m_a_src 0 Bits 0…15
val_rand c START_MULTIPLY
09f4 09f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09f5 09f5 val_a_adr 2c VR10:0c
val_b_adr 03 GP03
val_frame 10
val_rand c START_MULTIPLY
09f6 09f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09f7 09f7 val_a_adr 27 VR10:07
val_b_adr 03 GP03
val_frame 10
val_m_a_src 2 Bits 32…47
val_rand c START_MULTIPLY
09f8 09f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09f9 09f9 val_a_adr 34 VR10:14
val_b_adr 03 GP03
val_frame 10
val_m_a_src 1 Bits 16…31
val_rand c START_MULTIPLY
09fa 09fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09fb 09fb val_a_adr 3f VR10:1f
val_b_adr 03 GP03
val_frame 10
val_m_a_src 0 Bits 0…15
val_rand c START_MULTIPLY
09fc 09fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
09fd 09fd val_a_adr 30 VR05:10
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
09fe 09fe val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
09ff 09ff val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0a00 0a00 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_a_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a01 0a01 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0a02 0a02 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_a_src 1 Bits 16…31
val_rand c START_MULTIPLY
0a03 0a03 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a04 0a04 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_a_src 2 Bits 32…47
val_rand c START_MULTIPLY
0a05 0a05 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a06 0a06 seq_en_micro 0
val_a_adr 06 GP06
val_b_adr 20 VR04:00
val_frame 4
val_rand c START_MULTIPLY
0a07 0a07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a08 0a08 val_a_adr 01 GP01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a09 0a09 seq_b_timing 0 Early Condition; Flow J cc=False 0xa00
seq_br_type 0 Branch False
seq_branch_adr 0a00 0x0a00
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
0a0a 0a0a val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
0a0b 0a0b val_a_adr 03 GP03
val_b_adr 26 VR10:06
val_frame 10
val_rand c START_MULTIPLY
0a0c 0a0c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a0d 0a0d val_a_adr 03 GP03
val_b_adr 39 VR10:19
val_frame 10
val_m_b_src 2 Bits 32…47
val_rand c START_MULTIPLY
0a0e 0a0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a0f 0a0f val_a_adr 03 GP03
val_b_adr 3a VR10:1a
val_frame 10
val_m_b_src 1 Bits 16…31
val_rand c START_MULTIPLY
0a10 0a10 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a11 0a11 val_a_adr 03 GP03
val_b_adr 3b VR10:1b
val_frame 10
val_m_b_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a12 0a12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a13 0a13 val_a_adr 03 GP03
val_b_adr 2c VR10:0c
val_frame 10
val_rand c START_MULTIPLY
0a14 0a14 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a15 0a15 val_a_adr 03 GP03
val_b_adr 27 VR10:07
val_frame 10
val_m_b_src 2 Bits 32…47
val_rand c START_MULTIPLY
0a16 0a16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a17 0a17 val_a_adr 03 GP03
val_b_adr 34 VR10:14
val_frame 10
val_m_b_src 1 Bits 16…31
val_rand c START_MULTIPLY
0a18 0a18 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a19 0a19 val_a_adr 03 GP03
val_b_adr 3f VR10:1f
val_frame 10
val_m_b_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a1a 0a1a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a1b 0a1b val_a_adr 30 VR05:10
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
0a1c 0a1c val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
0a1d 0a1d val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0a1e 0a1e seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_b_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a1f 0a1f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0a20 0a20 seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 1a PASS_B
val_b_adr 06 GP06
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_b_src 1 Bits 16…31
val_rand c START_MULTIPLY
0a21 0a21 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a22 0a22 seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 1a PASS_B
val_b_adr 06 GP06
val_c_adr 39 GP06
val_c_mux_sel 1 ALU >> 16
val_frame 4
val_m_b_src 2 Bits 32…47
val_rand c START_MULTIPLY
0a23 0a23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a24 0a24 seq_en_micro 0
val_a_adr 20 VR04:00
val_b_adr 06 GP06
val_frame 4
val_rand c START_MULTIPLY
0a25 0a25 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a26 0a26 val_a_adr 01 GP01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a27 0a27 seq_b_timing 0 Early Condition; Flow J cc=False 0xa1e
seq_br_type 0 Branch False
seq_branch_adr 0a1e 0x0a1e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
0a28 0a28 seq_en_micro 0
val_a_adr 20 VR10:00
val_b_adr 20 VR10:00
val_frame 10
val_rand c START_MULTIPLY
0a29 0a29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a2a 0a2a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_rand d PRODUCT_LEFT_16
0a2b 0a2b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
val_rand e PRODUCT_LEFT_32
0a2c 0a2c seq_en_micro 0
val_a_adr 20 VR04:00
val_b_adr 20 VR04:00
val_frame 4
val_rand c START_MULTIPLY
0a2d 0a2d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0a2e 0a2e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 30 VR04:10
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
val_rand d PRODUCT_LEFT_16
0a2f 0a2f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR05:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
val_rand e PRODUCT_LEFT_32
0a30 0a30 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0a31 0a31 val_a_adr 21 VR04:01
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
0a32 0a32 val_a_adr 21 VR05:01
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 5
0a33 0a33 val_a_adr 24 VR04:04
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0a34 0a34 seq_en_micro 0
val_a_adr 05 GP05
val_b_adr 06 GP06
val_rand c START_MULTIPLY
0a35 0a35 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand e PRODUCT_LEFT_32
0a36 0a36 seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 1 ALU >> 16
val_rand 2 DEC_LOOP_COUNTER
0a37 0a37 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 07 GP07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand d PRODUCT_LEFT_16
0a38 0a38 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 1 ALU >> 16
0a39 0a39 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 07 GP07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a3a 0a3a val_a_adr 01 GP01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a3b 0a3b val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
0a3c 0a3c seq_en_micro 0
val_a_adr 05 GP05
val_b_adr 06 GP06
val_rand c START_MULTIPLY
0a3d 0a3d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand e PRODUCT_LEFT_32
0a3e 0a3e seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 1 ALU >> 16
0a3f 0a3f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 07 GP07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand d PRODUCT_LEFT_16
0a40 0a40 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 1 ALU >> 16
0a41 0a41 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 07 GP07
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a42 0a42 val_a_adr 01 GP01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a43 0a43 seq_b_timing 0 Early Condition; Flow J cc=False 0xa34
seq_br_type 0 Branch False
seq_branch_adr 0a34 0x0a34
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 06 GP06
val_alu_func 3 LEFT_I_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
0a44 0a44 seq_en_micro 0
val_a_adr 2a VR14:0a
val_b_adr 2b VR14:0b
val_frame 14
val_rand c START_MULTIPLY
0a45 0a45 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2c VR14:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0a46 0a46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2d VR14:0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_rand d PRODUCT_LEFT_16
0a47 0a47 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 2e VR14:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_rand e PRODUCT_LEFT_32
0a48 0a48 seq_en_micro 0
val_a_adr 2f VR14:0f
val_b_adr 30 VR14:10
val_frame 14
val_m_a_src 0 Bits 0…15
val_m_b_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a49 0a49 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 32 VR14:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 1 Bits 16…31
val_m_b_src 2 Bits 32…47
0a4a 0a4a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 34 VR14:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 2 Bits 32…47
val_m_b_src 0 Bits 0…15
0a4b 0a4b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 37 VR14:17
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_b_src 2 Bits 32…47
0a4c 0a4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 35 VR14:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 0 Bits 0…15
val_m_b_src 1 Bits 16…31
0a4d 0a4d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 33 VR14:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 1 Bits 16…31
0a4e 0a4e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 36 VR14:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 2 Bits 32…47
val_m_b_src 1 Bits 16…31
0a4f 0a4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 39 VR14:19
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0a50 0a50 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 38 VR14:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0a51 0a51 seq_en_micro 0
val_a_adr 31 VR14:11
val_b_adr 2f VR14:0f
val_frame 14
val_m_b_src 0 Bits 0…15
val_rand c START_MULTIPLY
0a52 0a52 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 32 VR14:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_b_src 1 Bits 16…31
0a53 0a53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 34 VR14:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 0 Bits 0…15
val_m_b_src 2 Bits 32…47
0a54 0a54 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 37 VR14:17
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 0 Bits 0…15
0a55 0a55 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 35 VR14:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 1 Bits 16…31
val_m_b_src 0 Bits 0…15
0a56 0a56 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 33 VR14:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 1 Bits 16…31
val_m_b_src 1 Bits 16…31
0a57 0a57 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 36 VR14:16
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 2 Bits 32…47
val_m_b_src 2 Bits 32…47
0a58 0a58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 39 VR14:19
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
val_m_a_src 2 Bits 32…47
0a59 0a59 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 38 VR14:18
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 14
0a5a 0a5a val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0a5b 0a5b val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
0a5c 0a5c val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
0a5d 0a5d val_a_adr 25 VR04:05
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0a5e 0a5e seq_en_micro 0
val_a_adr 05 GP05
val_b_adr 06 GP06
val_rand c START_MULTIPLY
0a5f 0a5f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a60 0a60 seq_en_micro 0
val_a_adr 06 GP06
val_b_adr 05 GP05
val_rand c START_MULTIPLY
0a61 0a61 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a62 0a62 val_a_adr 01 GP01
val_alu_func 3 LEFT_I_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a63 0a63 val_a_adr 01 GP01
val_alu_func 1 A_PLUS_B
val_b_adr 06 GP06
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a64 0a64 val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
0a65 0a65 val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0a66 0a66 seq_b_timing 0 Early Condition; Flow J cc=False 0xa5e
seq_br_type 0 Branch False
seq_branch_adr 0a5e 0x0a5e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 07 GP07
val_alu_func 4 LEFT_I_A_INC
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
0a67 0a67 val_a_adr 20 VR05:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
0a68 0a68 val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 38 VR04:18
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
0a69 0a69 val_a_adr 3d VR10:1d
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
0a6a 0a6a val_a_adr 3e VR10:1e
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
0a6b 0a6b val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 3e VR10:1e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0a6c 0a6c val_a_adr 3c VR10:1c
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
0a6d 0a6d val_a_adr 3d VR10:1d
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
0a6e 0a6e val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a6f 0a6f fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0xa73
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 1 Branch True
seq_branch_adr 0a73 0x0a73
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 03 GP03
val_b_adr 04 GP04
val_rand c START_MULTIPLY
0a70 0a70 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a71 0a71 val_a_adr 03 GP03
val_alu_func 6 A_MINUS_B
val_b_adr 28 VR04:08
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
0a72 0a72 seq_br_type 3 Unconditional Branch; Flow J 0xa6f
seq_branch_adr 0a6f 0x0a6f
val_a_adr 01 GP01
val_alu_func 6 A_MINUS_B
val_b_adr 06 GP06
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0a73 0a73 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a74 0a74 val_a_adr 04 GP04
val_alu_func 6 A_MINUS_B
val_b_adr 28 VR04:08
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 4
0a75 0a75 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa6b
seq_br_type 0 Branch False
seq_branch_adr 0a6b 0x0a6b
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 06 GP06
val_alu_func 6 A_MINUS_B
val_b_adr 30 VR04:10
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
0a76 0a76 val_a_adr 2c VR10:0c
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0a77 0a77 val_a_adr 3a VR14:1a
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 14
0a78 0a78 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1c DEC_A
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand c START_MULTIPLY
0a79 0a79 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a7a 0a7a val_a_adr 05 GP05
val_alu_func 4 LEFT_I_A_INC
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
0a7b 0a7b seq_br_type 1 Branch True; Flow J cc=True 0xa78
seq_branch_adr 0a78 0x0a78
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 6 A_MINUS_B
val_b_adr 06 GP06
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a7c 0a7c val_a_adr 3d VR10:1d
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0a7d 0a7d val_a_adr 3c VR10:1c
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
0a7e 0a7e val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 3c VR10:1c
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0a7f 0a7f val_a_adr 3c VR10:1c
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
0a80 0a80 val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0a81 0a81 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0xa84
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 1 Branch True
seq_branch_adr 0a84 0x0a84
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 17 LOOP_COUNTER
val_b_adr 04 GP04
val_rand c START_MULTIPLY
0a82 0a82 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0a83 0a83 seq_br_type 3 Unconditional Branch; Flow J 0xa81
seq_branch_adr 0a81 0x0a81
val_a_adr 01 GP01
val_alu_func 6 A_MINUS_B
val_b_adr 04 GP04
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0a84 0a84 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb01
seq_br_type 5 Call True
seq_branch_adr 0b01 MULT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 16 PRODUCT
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a85 0a85 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xa7e
seq_br_type 0 Branch False
seq_branch_adr 0a7e 0x0a7e
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 04 GP04
val_alu_func 1c DEC_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
0a86 0a86 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0a87 0a87 val_a_adr 20 VR04:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_frame 4
0a88 0a88 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR04:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
val_rand b DIVIDE
0a89 0a89 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0a8a 0a8a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0a8b 0a8b seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 20 VR04:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_frame 4
0a8c 0a8c seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR04:00
val_frame 4
val_rand b DIVIDE
0a8d 0a8d seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0a8e 0a8e val_a_adr 20 VR04:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_frame 4
0a8f 0a8f seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0a90 0a90 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0a91 0a91 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR10:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0a92 0a92 val_a_adr 20 VR04:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_frame 4
0a93 0a93 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0a94 0a94 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0a95 0a95 val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR10:01
val_frame 10
0a96 0a96 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR04:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 4
val_rand b DIVIDE
0a97 0a97 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0a98 0a98 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0a99 0a99 val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR10:01
val_frame 10
0a9a 0a9a seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 20 VR04:00
val_frame 4
val_rand b DIVIDE
0a9b 0a9b seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0a9c 0a9c val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR10:01
val_frame 10
0a9d 0a9d seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0a9e 0a9e seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0a9f 0a9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR10:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0aa0 0aa0 val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 21 VR10:01
val_frame 10
0aa1 0aa1 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0aa2 0aa2 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0aa3 0aa3 val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0aa4 0aa4 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 21 VR10:01
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0aa5 0aa5 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0aa6 0aa6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0aa7 0aa7 val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0aa8 0aa8 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 21 VR10:01
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0aa9 0aa9 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0aaa 0aaa val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0aab 0aab seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 21 VR10:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0aac 0aac seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0aad 0aad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR10:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0aae 0aae val_a_adr 2a VR10:0a
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0aaf 0aaf seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 21 VR10:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0ab0 0ab0 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0ab1 0ab1 val_a_adr 22 VR10:02
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0ab2 0ab2 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 21 VR10:01
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0ab3 0ab3 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0ab4 0ab4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0ab5 0ab5 val_a_adr 22 VR10:02
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0ab6 0ab6 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 21 VR10:01
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0ab7 0ab7 seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0ab8 0ab8 val_a_adr 22 VR10:02
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0ab9 0ab9 seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 21 VR10:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0aba 0aba seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 13 VAL.Q_BIT(early)
seq_en_micro 0
0abb 0abb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR10:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0abc 0abc val_a_adr 22 VR10:02
val_alu_func 1 A_PLUS_B
val_b_adr 22 VR10:02
val_frame 10
0abd 0abd seq_b_timing 0 Early Condition; Flow C cc=False 0xb03
seq_br_type 4 Call False
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
val_a_adr 2a VR10:0a
val_alu_func 9 MINUS_ELSE_PLUS
val_b_adr 21 VR10:01
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand b DIVIDE
0abe 0abe seq_b_timing 0 Early Condition; Flow C cc=True 0xb03
seq_br_type 5 Call True
seq_branch_adr 0b03 DIV_ERROR
seq_cond_sel 15 VAL.M_BIT(early)
seq_en_micro 0
0abf 0abf fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_b_adr 20 VR10:00
val_frame 10
0ac0 0ac0 ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0ac1 0ac1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb05
seq_br_type 5 Call True
seq_branch_adr 0b05 VAL_BUS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0ac2 0ac2 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_b_adr 22 VR10:02
val_frame 10
0ac3 0ac3 ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
0ac4 0ac4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb05
seq_br_type 5 Call True
seq_branch_adr 0b05 VAL_BUS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0ac5 0ac5 fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_cond_sel 16 VAL.TRUE(early)
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_rand 6 IMMEDIATE_OP
0ac6 0ac6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
0ac7 0ac7 fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
val_rand 6 IMMEDIATE_OP
0ac8 0ac8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
0ac9 0ac9 val_a_adr 28 VR04:08
val_alu_func 1c DEC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
0aca 0aca val_a_adr 28 VR04:08
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
0acb 0acb fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_a_adr 39 VR15:19
val_alu_func 1b A_OR_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 15
0acc 0acc ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 6 IMMEDIATE_OP
0acd 0acd val_a_adr 17 LOOP_COUNTER
val_alu_func 1b A_OR_B
val_b_adr 20 VR10:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0ace 0ace seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0acf 0acf ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 6 IMMEDIATE_OP
0ad0 0ad0 val_a_adr 17 LOOP_COUNTER
val_alu_func 1b A_OR_B
val_b_adr 39 VR15:19
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 15
0ad1 0ad1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0ad2 0ad2 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_b_adr 04 GP04
0ad3 0ad3 ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 6 IMMEDIATE_OP
0ad4 0ad4 val_a_adr 17 LOOP_COUNTER
val_alu_func 1b A_OR_B
val_b_adr 20 VR10:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
0ad5 0ad5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0ad6 0ad6 ioc_tvbs 1 typ+fiu
val_alu_func 1a PASS_B
val_b_adr 22 VR10:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
val_rand 6 IMMEDIATE_OP
0ad7 0ad7 val_a_adr 17 LOOP_COUNTER
val_alu_func 1b A_OR_B
val_b_adr 39 VR15:19
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 15
0ad8 0ad8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xb07
seq_br_type 5 Call True
seq_branch_adr 0b07 IMMEDIATE_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
0ad9 0ad9 seq_b_timing 0 Early Condition; Flow J cc=False 0xacb
seq_br_type 0 Branch False
seq_branch_adr 0acb 0x0acb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 03 GP03
val_alu_func 1c DEC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
0ada 0ada seq_br_type a Unconditional Return; Flow R
0adb ; --------------------------------------------------------------------------------------
0adb ; Comes from:
0adb ; 0400 C True from color VAL_TEST
0adb ; 0402 C from color VAL_TEST
0adb ; 0404 C from color VAL_TEST
0adb ; 0405 C False from color VAL_TEST
0adb ; 0407 C True from color VAL_TEST
0adb ; 040a C from color VAL_TEST
0adb ; 040d C from color VAL_TEST
0adb ; 040f C False from color VAL_TEST
0adb ; 0411 C True from color VAL_TEST
0adb ; 0413 C from color VAL_TEST
0adb ; 0416 C from color VAL_TEST
0adb ; 0417 C False from color VAL_TEST
0adb ; 0419 C from color VAL_TEST
0adb ; 041a C True from color VAL_TEST
0adb ; 041b C False from color VAL_TEST
0adb ; 041d C from color VAL_TEST
0adb ; 041f C True from color VAL_TEST
0adb ; 0421 C from color VAL_TEST
0adb ; 0424 C from color VAL_TEST
0adb ; 0425 C False from color VAL_TEST
0adb ; 0427 C from color VAL_TEST
0adb ; 0428 C True from color VAL_TEST
0adb ; 0429 C False from color VAL_TEST
0adb ; 042b C from color VAL_TEST
0adb ; 042e C from color VAL_TEST
0adb ; 042f C False from color VAL_TEST
0adb ; 0431 C True from color VAL_TEST
0adb ; 0433 C from color VAL_TEST
0adb ; 0434 C True from color VAL_TEST
0adb ; 0436 C from color VAL_TEST
0adb ; 0438 C from color VAL_TEST
0adb ; 0439 C False from color VAL_TEST
0adb ; 043b C from color VAL_TEST
0adb ; 043c C False from color VAL_TEST
0adb ; 043e C from color VAL_TEST
0adb ; 043f C False from color VAL_TEST
0adb ; 0440 C True from color VAL_TEST
0adb ; 0442 C from color VAL_TEST
0adb ; 0443 C True from color VAL_TEST
0adb ; 0445 C from color VAL_TEST
0adb ; 0446 C True from color VAL_TEST
0adb ; 0448 C from color VAL_TEST
0adb ; 0449 C True from color VAL_TEST
0adb ; 044b C from color VAL_TEST
0adb ; 044d C from color VAL_TEST
0adb ; 044e C False from color VAL_TEST
0adb ; 0450 C from color VAL_TEST
0adb ; 0451 C False from color VAL_TEST
0adb ; 0453 C from color VAL_TEST
0adb ; 0454 C False from color VAL_TEST
0adb ; 0455 C True from color VAL_TEST
0adb ; 0457 C from color VAL_TEST
0adb ; 0459 C from color VAL_TEST
0adb ; 045a C False from color VAL_TEST
0adb ; 045b C True from color VAL_TEST
0adb ; 045d C from color VAL_TEST
0adb ; 045f C from color VAL_TEST
0adb ; 0460 C False from color VAL_TEST
0adb ; 0461 C True from color VAL_TEST
0adb ; 0463 C from color VAL_TEST
0adb ; 0465 C from color VAL_TEST
0adb ; 0466 C False from color VAL_TEST
0adb ; 0467 C True from color VAL_TEST
0adb ; 0469 C from color VAL_TEST
0adb ; 046b C from color VAL_TEST
0adb ; 046c C False from color VAL_TEST
0adb ; 046d C True from color VAL_TEST
0adb ; 046f C from color VAL_TEST
0adb ; 0471 C from color VAL_TEST
0adb ; 0472 C False from color VAL_TEST
0adb ; 0473 C True from color VAL_TEST
0adb ; 0475 C from color VAL_TEST
0adb ; 0477 C from color VAL_TEST
0adb ; 0478 C False from color VAL_TEST
0adb ; 0479 C True from color VAL_TEST
0adb ; 047b C from color VAL_TEST
0adb ; 047d C from color VAL_TEST
0adb ; 047e C False from color VAL_TEST
0adb ; 047f C True from color VAL_TEST
0adb ; 0481 C from color VAL_TEST
0adb ; 0483 C from color VAL_TEST
0adb ; 0484 C False from color VAL_TEST
0adb ; 0485 C True from color VAL_TEST
0adb ; 0487 C from color VAL_TEST
0adb ; 0489 C from color VAL_TEST
0adb ; 048a C False from color VAL_TEST
0adb ; 048b C True from color VAL_TEST
0adb ; 048d C from color VAL_TEST
0adb ; 048f C from color VAL_TEST
0adb ; 0490 C False from color VAL_TEST
0adb ; 0491 C True from color VAL_TEST
0adb ; 0493 C from color VAL_TEST
0adb ; 0495 C from color VAL_TEST
0adb ; 0496 C False from color VAL_TEST
0adb ; 0497 C True from color VAL_TEST
0adb ; 0499 C from color VAL_TEST
0adb ; 049b C from color VAL_TEST
0adb ; 049c C True from color VAL_TEST
0adb ; 049e C from color VAL_TEST
0adb ; 049f C True from color VAL_TEST
0adb ; 04a0 C False from color VAL_TEST
0adb ; 04a2 C from color VAL_TEST
0adb ; 04a4 C from color VAL_TEST
0adb ; 04a5 C True from color VAL_TEST
0adb ; 04a7 C from color VAL_TEST
0adb ; 04a8 C True from color VAL_TEST
0adb ; 04a9 C False from color VAL_TEST
0adb ; 04ab C from color VAL_TEST
0adb ; 04ad C from color VAL_TEST
0adb ; 04ae C True from color VAL_TEST
0adb ; 04b0 C from color VAL_TEST
0adb ; 04b1 C True from color VAL_TEST
0adb ; 04b2 C False from color VAL_TEST
0adb ; 04b4 C from color VAL_TEST
0adb ; 04b6 C from color VAL_TEST
0adb ; 04b7 C True from color VAL_TEST
0adb ; 04b9 C from color VAL_TEST
0adb ; 04ba C True from color VAL_TEST
0adb ; 04bb C False from color VAL_TEST
0adb ; 04bd C from color VAL_TEST
0adb ; 04be C True from color VAL_TEST
0adb ; 04c0 C from color VAL_TEST
0adb ; 04c2 C from color VAL_TEST
0adb ; 04c3 C False from color VAL_TEST
0adb ; 04c4 C True from color VAL_TEST
0adb ; 04c6 C from color VAL_TEST
0adb ; 04c8 C from color VAL_TEST
0adb ; 04c9 C False from color VAL_TEST
0adb ; 04ca C False from color VAL_TEST
0adb ; 04cc C from color VAL_TEST
0adb ; 04ce C from color VAL_TEST
0adb ; 04cf C True from color VAL_TEST
0adb ; 04d0 C False from color VAL_TEST
0adb ; 04d2 C from color VAL_TEST
0adb ; 04d4 C from color VAL_TEST
0adb ; 04d5 C True from color VAL_TEST
0adb ; 04d7 C from color VAL_TEST
0adb ; 04d8 C False from color VAL_TEST
0adb ; 04d9 C True from color VAL_TEST
0adb ; 04db C from color VAL_TEST
0adb ; 04dd C from color VAL_TEST
0adb ; 04de C False from color VAL_TEST
0adb ; 04df C True from color VAL_TEST
0adb ; 04e1 C from color VAL_TEST
0adb ; 04e3 C from color VAL_TEST
0adb ; 04e4 C False from color VAL_TEST
0adb ; 04e6 C from color VAL_TEST
0adb ; 04e7 C False from color VAL_TEST
0adb ; 04e8 C True from color VAL_TEST
0adb ; 04ea C from color VAL_TEST
0adb ; 04ec C from color VAL_TEST
0adb ; 04ed C False from color VAL_TEST
0adb ; 04ee C True from color VAL_TEST
0adb ; 04f0 C from color VAL_TEST
0adb ; 04f2 C from color VAL_TEST
0adb ; 04f3 C False from color VAL_TEST
0adb ; 04f4 C True from color VAL_TEST
0adb ; 04f6 C from color VAL_TEST
0adb ; 04f8 C from color VAL_TEST
0adb ; 04f9 C False from color VAL_TEST
0adb ; 04fa C True from color VAL_TEST
0adb ; 04fc C from color VAL_TEST
0adb ; 04fe C from color VAL_TEST
0adb ; 04ff C False from color VAL_TEST
0adb ; 0500 C True from color VAL_TEST
0adb ; 0502 C from color VAL_TEST
0adb ; 0503 C True from color VAL_TEST
0adb ; 0505 C from color VAL_TEST
0adb ; 0506 C True from color VAL_TEST
0adb ; 0508 C from color VAL_TEST
0adb ; 050a C from color VAL_TEST
0adb ; 050b C False from color VAL_TEST
0adb ; 050c C True from color VAL_TEST
0adb ; 050e C from color VAL_TEST
0adb ; 0510 C from color VAL_TEST
0adb ; 0511 C False from color VAL_TEST
0adb ; 0512 C True from color VAL_TEST
0adb ; 0514 C from color VAL_TEST
0adb ; 0516 C from color VAL_TEST
0adb ; 0517 C False from color VAL_TEST
0adb ; 0518 C True from color VAL_TEST
0adb ; 051a C from color VAL_TEST
0adb ; 051c C from color VAL_TEST
0adb ; 051d C False from color VAL_TEST
0adb ; 051e C True from color VAL_TEST
0adb ; 0520 C from color VAL_TEST
0adb ; 0522 C from color VAL_TEST
0adb ; 0523 C False from color VAL_TEST
0adb ; 0524 C True from color VAL_TEST
0adb ; 0526 C from color VAL_TEST
0adb ; 0527 C True from color VAL_TEST
0adb ; 0529 C from color VAL_TEST
0adb ; 052a C True from color VAL_TEST
0adb ; 052c C from color VAL_TEST
0adb ; 052e C from color VAL_TEST
0adb ; 052f C False from color VAL_TEST
0adb ; 0530 C True from color VAL_TEST
0adb ; 0532 C from color VAL_TEST
0adb ; 0533 C True from color VAL_TEST
0adb ; 0535 C from color VAL_TEST
0adb ; 0537 C from color VAL_TEST
0adb ; 0538 C False from color VAL_TEST
0adb ; 053a C from color VAL_TEST
0adb ; 053b C False from color VAL_TEST
0adb ; 053c C True from color VAL_TEST
0adb ; 053e C from color VAL_TEST
0adb ; 053f C True from color VAL_TEST
0adb ; 0541 C from color VAL_TEST
0adb ; 0543 C from color VAL_TEST
0adb ; 0544 C False from color VAL_TEST
0adb ; 0546 C from color VAL_TEST
0adb ; 0547 C False from color VAL_TEST
0adb ; 0548 C True from color VAL_TEST
0adb ; 054a C from color VAL_TEST
0adb ; 054b C True from color VAL_TEST
0adb ; 054d C from color VAL_TEST
0adb ; 054f C from color VAL_TEST
0adb ; 0550 C False from color VAL_TEST
0adb ; 0552 C from color VAL_TEST
0adb ; 0553 C False from color VAL_TEST
0adb ; 0554 C True from color VAL_TEST
0adb ; 0556 C from color VAL_TEST
0adb ; 0557 C True from color VAL_TEST
0adb ; 0559 C from color VAL_TEST
0adb ; 055b C from color VAL_TEST
0adb ; 055c C False from color VAL_TEST
0adb ; 055e C from color VAL_TEST
0adb ; 055f C False from color VAL_TEST
0adb ; 0560 C True from color VAL_TEST
0adb ; 0562 C from color VAL_TEST
0adb ; 0563 C True from color VAL_TEST
0adb ; 0565 C from color VAL_TEST
0adb ; 0567 C from color VAL_TEST
0adb ; 0568 C False from color VAL_TEST
0adb ; 056a C from color VAL_TEST
0adb ; 056b C False from color VAL_TEST
0adb ; 056c C True from color VAL_TEST
0adb ; 056e C from color VAL_TEST
0adb ; 056f C True from color VAL_TEST
0adb ; 0571 C from color VAL_TEST
0adb ; 0573 C from color VAL_TEST
0adb ; 0574 C False from color VAL_TEST
0adb ; --------------------------------------------------------------------------------------
0adb COND_ERROR:
; DISABLE(MICRO_EVENTS),
; HALT,
0adb 0adb <halt> ; Flow R
; RETURN,
0adc 0adc seq_br_type a Unconditional Return; Flow R
0add ; --------------------------------------------------------------------------------------
0add ; Comes from:
0add ; 0577 C True from color VAL_TEST
0add ; 0579 C False from color VAL_TEST
0add ; 057a C True from color VAL_TEST
0add ; 057b C True from color VAL_TEST
0add ; 057d C True from color VAL_TEST
0add ; 057f C True from color VAL_TEST
0add ; 0580 C True from color VAL_TEST
0add ; 0581 C True from color VAL_TEST
0add ; 0584 C True from color VAL_TEST
0add ; 0585 C True from color VAL_TEST
0add ; 0589 C True from color VAL_TEST
0add ; 058b C True from color VAL_TEST
0add ; 058d C True from color VAL_TEST
0add ; 058f C True from color VAL_TEST
0add ; --------------------------------------------------------------------------------------
0add REG_FILE_ERROR:
0add 0add <halt> ; Flow R
0ade 0ade seq_br_type a Unconditional Return; Flow R
0adf ; --------------------------------------------------------------------------------------
0adf ; Comes from:
0adf ; 0592 C True from color VAL_TEST
0adf ; 0594 C True from color VAL_TEST
0adf ; 0596 C True from color VAL_TEST
0adf ; 0598 C True from color VAL_TEST
0adf ; 059a C True from color VAL_TEST
0adf ; 059c C True from color VAL_TEST
0adf ; 059e C True from color VAL_TEST
0adf ; 05a0 C True from color VAL_TEST
0adf ; 05a2 C True from color VAL_TEST
0adf ; 05a4 C True from color VAL_TEST
0adf ; 05a6 C True from color VAL_TEST
0adf ; 05a8 C True from color VAL_TEST
0adf ; 05aa C True from color VAL_TEST
0adf ; 05ac C True from color VAL_TEST
0adf ; 05ae C True from color VAL_TEST
0adf ; 05b0 C True from color VAL_TEST
0adf ; 05b2 C True from color VAL_TEST
0adf ; 05b4 C True from color VAL_TEST
0adf ; 05b6 C True from color VAL_TEST
0adf ; 05b8 C True from color VAL_TEST
0adf ; 05ba C True from color VAL_TEST
0adf ; 05bc C True from color VAL_TEST
0adf ; 05be C True from color VAL_TEST
0adf ; 05c0 C True from color VAL_TEST
0adf ; 05c2 C True from color VAL_TEST
0adf ; 05c4 C True from color VAL_TEST
0adf ; 05c6 C True from color VAL_TEST
0adf ; 05c8 C True from color VAL_TEST
0adf ; 05ca C True from color VAL_TEST
0adf ; 05cc C True from color VAL_TEST
0adf ; 05ce C True from color VAL_TEST
0adf ; 05d0 C True from color VAL_TEST
0adf ; 05d2 C True from color VAL_TEST
0adf ; 05d4 C True from color VAL_TEST
0adf ; 05d6 C True from color VAL_TEST
0adf ; 05d8 C True from color VAL_TEST
0adf ; 05da C True from color VAL_TEST
0adf ; 05dc C True from color VAL_TEST
0adf ; 05de C True from color VAL_TEST
0adf ; 05e0 C True from color VAL_TEST
0adf ; 05e2 C True from color VAL_TEST
0adf ; 05e4 C True from color VAL_TEST
0adf ; 05e6 C True from color VAL_TEST
0adf ; 05e8 C True from color VAL_TEST
0adf ; 05ea C True from color VAL_TEST
0adf ; 05ec C True from color VAL_TEST
0adf ; 05ee C True from color VAL_TEST
0adf ; 05f0 C True from color VAL_TEST
0adf ; 05f2 C True from color VAL_TEST
0adf ; 05f4 C True from color VAL_TEST
0adf ; 05f6 C True from color VAL_TEST
0adf ; 05f8 C True from color VAL_TEST
0adf ; 05fa C True from color VAL_TEST
0adf ; 05fc C True from color VAL_TEST
0adf ; 05fe C True from color VAL_TEST
0adf ; 0600 C True from color VAL_TEST
0adf ; 0602 C True from color VAL_TEST
0adf ; 0604 C True from color VAL_TEST
0adf ; 0606 C True from color VAL_TEST
0adf ; 0608 C True from color VAL_TEST
0adf ; 060a C True from color VAL_TEST
0adf ; 060c C True from color VAL_TEST
0adf ; 060e C True from color VAL_TEST
0adf ; 0610 C True from color VAL_TEST
0adf ; 0612 C True from color VAL_TEST
0adf ; 0614 C True from color VAL_TEST
0adf ; 0616 C True from color VAL_TEST
0adf ; 0618 C True from color VAL_TEST
0adf ; 061a C True from color VAL_TEST
0adf ; 061c C True from color VAL_TEST
0adf ; 061e C True from color VAL_TEST
0adf ; 0620 C True from color VAL_TEST
0adf ; 0622 C True from color VAL_TEST
0adf ; 0624 C True from color VAL_TEST
0adf ; 0626 C True from color VAL_TEST
0adf ; 0628 C True from color VAL_TEST
0adf ; 062a C True from color VAL_TEST
0adf ; 062c C True from color VAL_TEST
0adf ; 062e C True from color VAL_TEST
0adf ; 0630 C True from color VAL_TEST
0adf ; 0632 C True from color VAL_TEST
0adf ; 0634 C True from color VAL_TEST
0adf ; 0636 C True from color VAL_TEST
0adf ; 0638 C True from color VAL_TEST
0adf ; 063a C True from color VAL_TEST
0adf ; 063c C True from color VAL_TEST
0adf ; 063e C True from color VAL_TEST
0adf ; 0640 C True from color VAL_TEST
0adf ; 0642 C True from color VAL_TEST
0adf ; 0644 C True from color VAL_TEST
0adf ; 0646 C True from color VAL_TEST
0adf ; 0648 C True from color VAL_TEST
0adf ; 064a C True from color VAL_TEST
0adf ; 064c C True from color VAL_TEST
0adf ; 064e C True from color VAL_TEST
0adf ; 0650 C True from color VAL_TEST
0adf ; 0652 C True from color VAL_TEST
0adf ; 0654 C True from color VAL_TEST
0adf ; 0656 C True from color VAL_TEST
0adf ; 0658 C True from color VAL_TEST
0adf ; 065a C True from color VAL_TEST
0adf ; 065c C True from color VAL_TEST
0adf ; 065e C True from color VAL_TEST
0adf ; 0660 C True from color VAL_TEST
0adf ; 0662 C True from color VAL_TEST
0adf ; 0664 C True from color VAL_TEST
0adf ; --------------------------------------------------------------------------------------
0adf LOGICAL_ALU_ERROR:
0adf 0adf <halt> ; Flow R
0ae0 0ae0 seq_br_type a Unconditional Return; Flow R
0ae1 ; --------------------------------------------------------------------------------------
0ae1 ; Comes from:
0ae1 ; 0665 C True from color VAL_TEST
0ae1 ; 0666 C True from color VAL_TEST
0ae1 ; 0667 C True from color VAL_TEST
0ae1 ; 0668 C False from color VAL_TEST
0ae1 ; 0669 C True from color VAL_TEST
0ae1 ; 066a C True from color VAL_TEST
0ae1 ; 066b C True from color VAL_TEST
0ae1 ; 066c C False from color VAL_TEST
0ae1 ; 066d C True from color VAL_TEST
0ae1 ; 066e C True from color VAL_TEST
0ae1 ; 066f C True from color VAL_TEST
0ae1 ; 0670 C True from color VAL_TEST
0ae1 ; 0671 C True from color VAL_TEST
0ae1 ; 0672 C True from color VAL_TEST
0ae1 ; 0673 C True from color VAL_TEST
0ae1 ; 0674 C True from color VAL_TEST
0ae1 ; 0675 C True from color VAL_TEST
0ae1 ; 0676 C True from color VAL_TEST
0ae1 ; 0677 C True from color VAL_TEST
0ae1 ; 0678 C True from color VAL_TEST
0ae1 ; 0679 C True from color VAL_TEST
0ae1 ; 067a C True from color VAL_TEST
0ae1 ; 067b C True from color VAL_TEST
0ae1 ; 067c C True from color VAL_TEST
0ae1 ; 067d C True from color VAL_TEST
0ae1 ; 067e C True from color VAL_TEST
0ae1 ; 067f C True from color VAL_TEST
0ae1 ; 0680 C True from color VAL_TEST
0ae1 ; 0681 C True from color VAL_TEST
0ae1 ; 0682 C True from color VAL_TEST
0ae1 ; 0683 C False from color VAL_TEST
0ae1 ; 0684 C True from color VAL_TEST
0ae1 ; 0685 C True from color VAL_TEST
0ae1 ; 0686 C False from color VAL_TEST
0ae1 ; 0687 C False from color VAL_TEST
0ae1 ; 0688 C True from color VAL_TEST
0ae1 ; 0689 C False from color VAL_TEST
0ae1 ; 068a C True from color VAL_TEST
0ae1 ; 068b C True from color VAL_TEST
0ae1 ; 068c C False from color VAL_TEST
0ae1 ; 068d C True from color VAL_TEST
0ae1 ; 068e C True from color VAL_TEST
0ae1 ; 068f C False from color VAL_TEST
0ae1 ; 0690 C True from color VAL_TEST
0ae1 ; 0691 C True from color VAL_TEST
0ae1 ; 0692 C False from color VAL_TEST
0ae1 ; 0693 C True from color VAL_TEST
0ae1 ; 0694 C True from color VAL_TEST
0ae1 ; 0695 C False from color VAL_TEST
0ae1 ; 0696 C True from color VAL_TEST
0ae1 ; 0697 C True from color VAL_TEST
0ae1 ; 0698 C False from color VAL_TEST
0ae1 ; 0699 C True from color VAL_TEST
0ae1 ; 069a C True from color VAL_TEST
0ae1 ; 069b C True from color VAL_TEST
0ae1 ; 069c C True from color VAL_TEST
0ae1 ; 069d C False from color VAL_TEST
0ae1 ; 069e C True from color VAL_TEST
0ae1 ; 069f C True from color VAL_TEST
0ae1 ; 06a0 C True from color VAL_TEST
0ae1 ; 06a1 C True from color VAL_TEST
0ae1 ; 06a2 C True from color VAL_TEST
0ae1 ; 06a3 C False from color VAL_TEST
0ae1 ; 06a4 C True from color VAL_TEST
0ae1 ; 06a5 C False from color VAL_TEST
0ae1 ; 06a6 C True from color VAL_TEST
0ae1 ; 06a7 C True from color VAL_TEST
0ae1 ; 06a8 C True from color VAL_TEST
0ae1 ; 06a9 C False from color VAL_TEST
0ae1 ; 06aa C True from color VAL_TEST
0ae1 ; 06ab C True from color VAL_TEST
0ae1 ; 06ac C True from color VAL_TEST
0ae1 ; 06ad C True from color VAL_TEST
0ae1 ; 06ae C True from color VAL_TEST
0ae1 ; 06af C False from color VAL_TEST
0ae1 ; 06b0 C True from color VAL_TEST
0ae1 ; 06b1 C False from color VAL_TEST
0ae1 ; 06b2 C True from color VAL_TEST
0ae1 ; 06b3 C True from color VAL_TEST
0ae1 ; 06b4 C False from color VAL_TEST
0ae1 ; 06b5 C True from color VAL_TEST
0ae1 ; 06b6 C True from color VAL_TEST
0ae1 ; 06b7 C False from color VAL_TEST
0ae1 ; 06b8 C True from color VAL_TEST
0ae1 ; 06b9 C True from color VAL_TEST
0ae1 ; 06ba C False from color VAL_TEST
0ae1 ; 06bb C True from color VAL_TEST
0ae1 ; 06bc C True from color VAL_TEST
0ae1 ; 06bd C False from color VAL_TEST
0ae1 ; 06be C True from color VAL_TEST
0ae1 ; 06bf C False from color VAL_TEST
0ae1 ; 06c0 C True from color VAL_TEST
0ae1 ; 06c1 C True from color VAL_TEST
0ae1 ; 06c2 C False from color VAL_TEST
0ae1 ; 06c3 C True from color VAL_TEST
0ae1 ; 06c4 C True from color VAL_TEST
0ae1 ; 06c5 C True from color VAL_TEST
0ae1 ; 06c6 C True from color VAL_TEST
0ae1 ; 06c7 C True from color VAL_TEST
0ae1 ; 06c8 C True from color VAL_TEST
0ae1 ; 06c9 C True from color VAL_TEST
0ae1 ; 06ca C True from color VAL_TEST
0ae1 ; 06cb C True from color VAL_TEST
0ae1 ; 06cc C True from color VAL_TEST
0ae1 ; 06cd C True from color VAL_TEST
0ae1 ; 06ce C True from color VAL_TEST
0ae1 ; 06cf C True from color VAL_TEST
0ae1 ; 06d0 C True from color VAL_TEST
0ae1 ; 06d1 C False from color VAL_TEST
0ae1 ; 06d2 C True from color VAL_TEST
0ae1 ; 06d3 C True from color VAL_TEST
0ae1 ; 06d4 C False from color VAL_TEST
0ae1 ; 06d5 C True from color VAL_TEST
0ae1 ; 06d6 C True from color VAL_TEST
0ae1 ; 06d7 C False from color VAL_TEST
0ae1 ; 06d8 C False from color VAL_TEST
0ae1 ; 06d9 C True from color VAL_TEST
0ae1 ; 06da C False from color VAL_TEST
0ae1 ; 06db C False from color VAL_TEST
0ae1 ; 06dc C True from color VAL_TEST
0ae1 ; 06dd C False from color VAL_TEST
0ae1 ; 06de C False from color VAL_TEST
0ae1 ; 06df C True from color VAL_TEST
0ae1 ; 06e0 C False from color VAL_TEST
0ae1 ; 06e1 C False from color VAL_TEST
0ae1 ; 06e2 C True from color VAL_TEST
0ae1 ; 06e3 C True from color VAL_TEST
0ae1 ; 06e4 C False from color VAL_TEST
0ae1 ; 06e5 C True from color VAL_TEST
0ae1 ; 06e6 C True from color VAL_TEST
0ae1 ; 06e7 C False from color VAL_TEST
0ae1 ; 06e8 C True from color VAL_TEST
0ae1 ; 06e9 C True from color VAL_TEST
0ae1 ; 06ea C False from color VAL_TEST
0ae1 ; 06eb C True from color VAL_TEST
0ae1 ; 06ec C True from color VAL_TEST
0ae1 ; 06ed C False from color VAL_TEST
0ae1 ; 06ee C True from color VAL_TEST
0ae1 ; 06ef C False from color VAL_TEST
0ae1 ; 06f0 C True from color VAL_TEST
0ae1 ; 06f1 C True from color VAL_TEST
0ae1 ; 06f2 C False from color VAL_TEST
0ae1 ; 06f3 C True from color VAL_TEST
0ae1 ; 06f4 C True from color VAL_TEST
0ae1 ; 06f5 C True from color VAL_TEST
0ae1 ; 06f6 C True from color VAL_TEST
0ae1 ; 06f7 C True from color VAL_TEST
0ae1 ; 06f8 C True from color VAL_TEST
0ae1 ; 06f9 C True from color VAL_TEST
0ae1 ; 06fa C True from color VAL_TEST
0ae1 ; 06fb C True from color VAL_TEST
0ae1 ; 06fc C True from color VAL_TEST
0ae1 ; 06fd C True from color VAL_TEST
0ae1 ; 06fe C True from color VAL_TEST
0ae1 ; 06ff C True from color VAL_TEST
0ae1 ; 0700 C True from color VAL_TEST
0ae1 ; 0701 C False from color VAL_TEST
0ae1 ; 0702 C True from color VAL_TEST
0ae1 ; 0703 C True from color VAL_TEST
0ae1 ; 0704 C False from color VAL_TEST
0ae1 ; 0705 C True from color VAL_TEST
0ae1 ; 0706 C True from color VAL_TEST
0ae1 ; 0707 C False from color VAL_TEST
0ae1 ; 0708 C False from color VAL_TEST
0ae1 ; 0709 C True from color VAL_TEST
0ae1 ; 070a C False from color VAL_TEST
0ae1 ; 070b C False from color VAL_TEST
0ae1 ; 070c C True from color VAL_TEST
0ae1 ; 070d C False from color VAL_TEST
0ae1 ; 070e C False from color VAL_TEST
0ae1 ; 070f C True from color VAL_TEST
0ae1 ; 0710 C False from color VAL_TEST
0ae1 ; 0711 C False from color VAL_TEST
0ae1 ; 0712 C True from color VAL_TEST
0ae1 ; 0713 C True from color VAL_TEST
0ae1 ; 0714 C True from color VAL_TEST
0ae1 ; 0715 C True from color VAL_TEST
0ae1 ; 0716 C False from color VAL_TEST
0ae1 ; 0717 C True from color VAL_TEST
0ae1 ; 0718 C True from color VAL_TEST
0ae1 ; 0719 C False from color VAL_TEST
0ae1 ; 071a C True from color VAL_TEST
0ae1 ; 071b C True from color VAL_TEST
0ae1 ; 071c C True from color VAL_TEST
0ae1 ; 071d C True from color VAL_TEST
0ae1 ; 071e C True from color VAL_TEST
0ae1 ; 071f C False from color VAL_TEST
0ae1 ; 0720 C False from color VAL_TEST
0ae1 ; 0721 C True from color VAL_TEST
0ae1 ; 0722 C True from color VAL_TEST
0ae1 ; 0723 C False from color VAL_TEST
0ae1 ; 0724 C True from color VAL_TEST
0ae1 ; 0725 C False from color VAL_TEST
0ae1 ; 0726 C False from color VAL_TEST
0ae1 ; 0727 C True from color VAL_TEST
0ae1 ; 0728 C True from color VAL_TEST
0ae1 ; 0729 C False from color VAL_TEST
0ae1 ; 072a C True from color VAL_TEST
0ae1 ; 072b C True from color VAL_TEST
0ae1 ; 072c C False from color VAL_TEST
0ae1 ; 072d C True from color VAL_TEST
0ae1 ; 072e C False from color VAL_TEST
0ae1 ; 072f C False from color VAL_TEST
0ae1 ; 0730 C True from color VAL_TEST
0ae1 ; 0731 C True from color VAL_TEST
0ae1 ; 0732 C False from color VAL_TEST
0ae1 ; 0733 C True from color VAL_TEST
0ae1 ; 0734 C False from color VAL_TEST
0ae1 ; 0735 C False from color VAL_TEST
0ae1 ; 0736 C True from color VAL_TEST
0ae1 ; 0737 C False from color VAL_TEST
0ae1 ; 0738 C True from color VAL_TEST
0ae1 ; 0739 C True from color VAL_TEST
0ae1 ; 073a C True from color VAL_TEST
0ae1 ; 073b C True from color VAL_TEST
0ae1 ; 073c C True from color VAL_TEST
0ae1 ; 073d C True from color VAL_TEST
0ae1 ; 073e C True from color VAL_TEST
0ae1 ; 073f C True from color VAL_TEST
0ae1 ; 0740 C False from color VAL_TEST
0ae1 ; 0741 C True from color VAL_TEST
0ae1 ; 0742 C True from color VAL_TEST
0ae1 ; 0743 C True from color VAL_TEST
0ae1 ; 0744 C True from color VAL_TEST
0ae1 ; 0745 C True from color VAL_TEST
0ae1 ; 0746 C False from color VAL_TEST
0ae1 ; 0747 C True from color VAL_TEST
0ae1 ; 0748 C True from color VAL_TEST
0ae1 ; 0749 C False from color VAL_TEST
0ae1 ; 074a C True from color VAL_TEST
0ae1 ; 074b C True from color VAL_TEST
0ae1 ; 074c C True from color VAL_TEST
0ae1 ; 074d C True from color VAL_TEST
0ae1 ; 074e C True from color VAL_TEST
0ae1 ; 074f C False from color VAL_TEST
0ae1 ; 0750 C False from color VAL_TEST
0ae1 ; 0751 C True from color VAL_TEST
0ae1 ; 0752 C True from color VAL_TEST
0ae1 ; 0753 C False from color VAL_TEST
0ae1 ; 0754 C True from color VAL_TEST
0ae1 ; 0755 C False from color VAL_TEST
0ae1 ; 0756 C False from color VAL_TEST
0ae1 ; 0757 C True from color VAL_TEST
0ae1 ; 0758 C True from color VAL_TEST
0ae1 ; 0759 C False from color VAL_TEST
0ae1 ; 075a C True from color VAL_TEST
0ae1 ; 075b C True from color VAL_TEST
0ae1 ; 075c C False from color VAL_TEST
0ae1 ; 075d C True from color VAL_TEST
0ae1 ; 075e C False from color VAL_TEST
0ae1 ; 075f C False from color VAL_TEST
0ae1 ; 0760 C True from color VAL_TEST
0ae1 ; 0761 C True from color VAL_TEST
0ae1 ; 0762 C False from color VAL_TEST
0ae1 ; 0763 C True from color VAL_TEST
0ae1 ; 0764 C False from color VAL_TEST
0ae1 ; 0765 C False from color VAL_TEST
0ae1 ; 0766 C True from color VAL_TEST
0ae1 ; 0767 C False from color VAL_TEST
0ae1 ; 0768 C True from color VAL_TEST
0ae1 ; 0769 C True from color VAL_TEST
0ae1 ; 076a C True from color VAL_TEST
0ae1 ; 076b C True from color VAL_TEST
0ae1 ; 076c C True from color VAL_TEST
0ae1 ; 076d C True from color VAL_TEST
0ae1 ; 076e C True from color VAL_TEST
0ae1 ; 076f C True from color VAL_TEST
0ae1 ; 0770 C False from color VAL_TEST
0ae1 ; 0771 C True from color VAL_TEST
0ae1 ; 0772 C True from color VAL_TEST
0ae1 ; --------------------------------------------------------------------------------------
0ae1 ARITH_ALU_ERROR:
0ae1 0ae1 <halt> ; Flow R
0ae2 0ae2 seq_br_type a Unconditional Return; Flow R
0ae3 ; --------------------------------------------------------------------------------------
0ae3 ; Comes from:
0ae3 ; 0775 C True from color VAL_TEST
0ae3 ; 0778 C True from color VAL_TEST
0ae3 ; 077b C True from color VAL_TEST
0ae3 ; 077e C True from color VAL_TEST
0ae3 ; 0781 C True from color VAL_TEST
0ae3 ; 0784 C True from color VAL_TEST
0ae3 ; 0787 C True from color VAL_TEST
0ae3 ; 078a C True from color VAL_TEST
0ae3 ; 078d C True from color VAL_TEST
0ae3 ; 0790 C True from color VAL_TEST
0ae3 ; 0793 C True from color VAL_TEST
0ae3 ; 0796 C True from color VAL_TEST
0ae3 ; 0799 C True from color VAL_TEST
0ae3 ; 079c C True from color VAL_TEST
0ae3 ; 079f C True from color VAL_TEST
0ae3 ; 07a2 C True from color VAL_TEST
0ae3 ; 07a5 C True from color VAL_TEST
0ae3 ; 07a8 C True from color VAL_TEST
0ae3 ; 07ab C True from color VAL_TEST
0ae3 ; 07ae C True from color VAL_TEST
0ae3 ; 07b1 C True from color VAL_TEST
0ae3 ; 07b4 C True from color VAL_TEST
0ae3 ; 07b7 C True from color VAL_TEST
0ae3 ; 07ba C True from color VAL_TEST
0ae3 ; 07bd C True from color VAL_TEST
0ae3 ; 07c0 C True from color VAL_TEST
0ae3 ; 07c3 C True from color VAL_TEST
0ae3 ; 07c6 C True from color VAL_TEST
0ae3 ; 07c9 C True from color VAL_TEST
0ae3 ; 07cc C True from color VAL_TEST
0ae3 ; 07cf C True from color VAL_TEST
0ae3 ; 07d2 C True from color VAL_TEST
0ae3 ; --------------------------------------------------------------------------------------
0ae3 COND_ALU_ERROR:
0ae3 0ae3 <halt> ; Flow R
0ae4 0ae4 seq_br_type a Unconditional Return; Flow R
0ae5 ; --------------------------------------------------------------------------------------
0ae5 ; Comes from:
0ae5 ; 07d4 C True from color VAL_TEST
0ae5 ; 07d6 C True from color VAL_TEST
0ae5 ; 07d8 C True from color VAL_TEST
0ae5 ; 07da C True from color VAL_TEST
0ae5 ; 07dc C True from color VAL_TEST
0ae5 ; 07de C True from color VAL_TEST
0ae5 ; 07e0 C True from color VAL_TEST
0ae5 ; 07e2 C True from color VAL_TEST
0ae5 ; 07e4 C True from color VAL_TEST
0ae5 ; 07e6 C True from color VAL_TEST
0ae5 ; 07e8 C True from color VAL_TEST
0ae5 ; 07ea C True from color VAL_TEST
0ae5 ; 07ec C True from color VAL_TEST
0ae5 ; 07ee C True from color VAL_TEST
0ae5 ; 07f0 C True from color VAL_TEST
0ae5 ; 07f2 C True from color VAL_TEST
0ae5 ; 07f4 C True from color VAL_TEST
0ae5 ; 07f6 C True from color VAL_TEST
0ae5 ; 07f8 C True from color VAL_TEST
0ae5 ; 07fa C True from color VAL_TEST
0ae5 ; 07fc C True from color VAL_TEST
0ae5 ; 07fe C True from color VAL_TEST
0ae5 ; 0800 C True from color VAL_TEST
0ae5 ; 0802 C True from color VAL_TEST
0ae5 ; 0805 C True from color VAL_TEST
0ae5 ; 0808 C True from color VAL_TEST
0ae5 ; 080b C True from color VAL_TEST
0ae5 ; 080e C True from color VAL_TEST
0ae5 ; 0811 C True from color VAL_TEST
0ae5 ; 0814 C True from color VAL_TEST
0ae5 ; 0817 C True from color VAL_TEST
0ae5 ; 081a C True from color VAL_TEST
0ae5 ; 081d C True from color VAL_TEST
0ae5 ; 0820 C True from color VAL_TEST
0ae5 ; 0823 C True from color VAL_TEST
0ae5 ; 0826 C True from color VAL_TEST
0ae5 ; 0829 C True from color VAL_TEST
0ae5 ; 082c C True from color VAL_TEST
0ae5 ; 082f C True from color VAL_TEST
0ae5 ; 0832 C True from color VAL_TEST
0ae5 ; 0834 C True from color VAL_TEST
0ae5 ; 0836 C True from color VAL_TEST
0ae5 ; 0838 C True from color VAL_TEST
0ae5 ; 083a C True from color VAL_TEST
0ae5 ; 083c C True from color VAL_TEST
0ae5 ; 083e C True from color VAL_TEST
0ae5 ; 0840 C True from color VAL_TEST
0ae5 ; 0842 C True from color VAL_TEST
0ae5 ; 0844 C True from color VAL_TEST
0ae5 ; 0846 C True from color VAL_TEST
0ae5 ; 0848 C True from color VAL_TEST
0ae5 ; 084a C True from color VAL_TEST
0ae5 ; 084c C True from color VAL_TEST
0ae5 ; 084e C True from color VAL_TEST
0ae5 ; 0850 C True from color VAL_TEST
0ae5 ; 0852 C True from color VAL_TEST
0ae5 ; 0854 C True from color VAL_TEST
0ae5 ; 0856 C True from color VAL_TEST
0ae5 ; 0858 C True from color VAL_TEST
0ae5 ; 085a C True from color VAL_TEST
0ae5 ; 085c C True from color VAL_TEST
0ae5 ; 085e C True from color VAL_TEST
0ae5 ; 0860 C True from color VAL_TEST
0ae5 ; 0862 C True from color VAL_TEST
0ae5 ; 0865 C True from color VAL_TEST
0ae5 ; 0868 C True from color VAL_TEST
0ae5 ; 086b C True from color VAL_TEST
0ae5 ; 086e C True from color VAL_TEST
0ae5 ; 0871 C True from color VAL_TEST
0ae5 ; 0874 C True from color VAL_TEST
0ae5 ; 0877 C True from color VAL_TEST
0ae5 ; 087a C True from color VAL_TEST
0ae5 ; 087d C True from color VAL_TEST
0ae5 ; 0880 C True from color VAL_TEST
0ae5 ; 0883 C True from color VAL_TEST
0ae5 ; 0886 C True from color VAL_TEST
0ae5 ; 0889 C True from color VAL_TEST
0ae5 ; 088c C True from color VAL_TEST
0ae5 ; 088f C True from color VAL_TEST
0ae5 ; 0892 C True from color VAL_TEST
0ae5 ; --------------------------------------------------------------------------------------
0ae5 SPLIT_ALU_ERROR:
0ae5 0ae5 <halt> ; Flow R
0ae6 0ae6 seq_br_type a Unconditional Return; Flow R
0ae7 ; --------------------------------------------------------------------------------------
0ae7 ; Comes from:
0ae7 ; 0894 C True from color VAL_TEST
0ae7 ; 0897 C True from color VAL_TEST
0ae7 ; --------------------------------------------------------------------------------------
0ae7 A_PORT_ZERO_ERROR:
0ae7 0ae7 <halt> ; Flow R
0ae8 0ae8 seq_br_type a Unconditional Return; Flow R
0ae9 ; --------------------------------------------------------------------------------------
0ae9 ; Comes from:
0ae9 ; 089a C False from color VAL_TEST
0ae9 ; 089b C True from color VAL_TEST
0ae9 ; 089d C False from color VAL_TEST
0ae9 ; 089e C True from color VAL_TEST
0ae9 ; 08a0 C True from color VAL_TEST
0ae9 ; 08a1 C True from color VAL_TEST
0ae9 ; 08a3 C True from color VAL_TEST
0ae9 ; 08a4 C True from color VAL_TEST
0ae9 ; 08a6 C True from color VAL_TEST
0ae9 ; 08a7 C True from color VAL_TEST
0ae9 ; 08a9 C True from color VAL_TEST
0ae9 ; 08aa C True from color VAL_TEST
0ae9 ; 08ac C True from color VAL_TEST
0ae9 ; 08ad C True from color VAL_TEST
0ae9 ; 08af C True from color VAL_TEST
0ae9 ; 08b0 C True from color VAL_TEST
0ae9 ; 08b2 C True from color VAL_TEST
0ae9 ; 08b3 C True from color VAL_TEST
0ae9 ; 08b5 C True from color VAL_TEST
0ae9 ; 08b6 C True from color VAL_TEST
0ae9 ; 08b8 C True from color VAL_TEST
0ae9 ; 08b9 C True from color VAL_TEST
0ae9 ; 08bb C True from color VAL_TEST
0ae9 ; 08bc C True from color VAL_TEST
0ae9 ; 08be C True from color VAL_TEST
0ae9 ; 08bf C True from color VAL_TEST
0ae9 ; 08c2 C False from color VAL_TEST
0ae9 ; 08c3 C True from color VAL_TEST
0ae9 ; 08c4 C True from color VAL_TEST
0ae9 ; 08c6 C True from color VAL_TEST
0ae9 ; 08c7 C False from color VAL_TEST
0ae9 ; 08c9 C False from color VAL_TEST
0ae9 ; 08cb C True from color VAL_TEST
0ae9 ; 08cd C True from color VAL_TEST
0ae9 ; 08ce C True from color VAL_TEST
0ae9 ; 08cf C True from color VAL_TEST
0ae9 ; 08d1 C True from color VAL_TEST
0ae9 ; 08d2 C False from color VAL_TEST
0ae9 ; 08d3 C True from color VAL_TEST
0ae9 ; 08d4 C True from color VAL_TEST
0ae9 ; --------------------------------------------------------------------------------------
0ae9 LOOP_ERROR:
0ae9 0ae9 <halt> ; Flow R
0aea 0aea seq_br_type a Unconditional Return; Flow R
0aeb ; --------------------------------------------------------------------------------------
0aeb ; Comes from:
0aeb ; 08d6 C True from color VAL_TEST
0aeb ; 08d8 C True from color VAL_TEST
0aeb ; 08da C True from color VAL_TEST
0aeb ; 08dc C True from color VAL_TEST
0aeb ; 08de C True from color VAL_TEST
0aeb ; 08e0 C True from color VAL_TEST
0aeb ; 08e2 C True from color VAL_TEST
0aeb ; 08e4 C True from color VAL_TEST
0aeb ; 08e8 C True from color VAL_TEST
0aeb ; --------------------------------------------------------------------------------------
0aeb CMUX_PASS_ERROR:
0aeb 0aeb <halt> ; Flow R
0aec 0aec seq_br_type a Unconditional Return; Flow R
0aed ; --------------------------------------------------------------------------------------
0aed ; Comes from:
0aed ; 08eb C True from color VAL_TEST
0aed ; 08ed C True from color VAL_TEST
0aed ; 08ef C True from color VAL_TEST
0aed ; 08f1 C True from color VAL_TEST
0aed ; 08f3 C True from color VAL_TEST
0aed ; 08f5 C True from color VAL_TEST
0aed ; 08f7 C True from color VAL_TEST
0aed ; 08f9 C True from color VAL_TEST
0aed ; 08fe C True from color VAL_TEST
0aed ; --------------------------------------------------------------------------------------
0aed CMUX_LEFT_ERROR:
0aed 0aed <halt> ; Flow R
0aee 0aee seq_br_type a Unconditional Return; Flow R
0aef ; --------------------------------------------------------------------------------------
0aef ; Comes from:
0aef ; 0901 C True from color VAL_TEST
0aef ; 0903 C True from color VAL_TEST
0aef ; 0905 C True from color VAL_TEST
0aef ; 0907 C True from color VAL_TEST
0aef ; 0909 C True from color VAL_TEST
0aef ; 090b C True from color VAL_TEST
0aef ; 090d C True from color VAL_TEST
0aef ; 090f C True from color VAL_TEST
0aef ; 0913 C True from color VAL_TEST
0aef ; 0918 C True from color VAL_TEST
0aef ; --------------------------------------------------------------------------------------
0aef CMUX_RIGHT_ERROR:
0aef 0aef <halt> ; Flow R
0af0 0af0 seq_br_type a Unconditional Return; Flow R
0af1 ; --------------------------------------------------------------------------------------
0af1 ; Comes from:
0af1 ; 091f C True from color VAL_TEST
0af1 ; 0922 C True from color VAL_TEST
0af1 ; 0925 C True from color VAL_TEST
0af1 ; 0928 C True from color VAL_TEST
0af1 ; 092b C True from color VAL_TEST
0af1 ; 092e C True from color VAL_TEST
0af1 ; 0931 C True from color VAL_TEST
0af1 ; 0934 C True from color VAL_TEST
0af1 ; 0939 C True from color VAL_TEST
0af1 ; --------------------------------------------------------------------------------------
0af1 CMUX_WDR_ERROR:
; DISABLE(MICRO_EVENTS),
; HALT,
0af1 0af1 <halt> ; Flow R
; RETURN,
0af2 0af2 seq_br_type a Unconditional Return; Flow R
0af3 ; --------------------------------------------------------------------------------------
0af3 ; Comes from:
0af3 ; 093e C True from color VAL_TEST
0af3 ; 0940 C True from color VAL_TEST
0af3 ; 0942 C True from color VAL_TEST
0af3 ; 0944 C True from color VAL_TEST
0af3 ; 0946 C True from color VAL_TEST
0af3 ; 0948 C True from color VAL_TEST
0af3 ; 094a C True from color VAL_TEST
0af3 ; 094c C True from color VAL_TEST
0af3 ; 0950 C True from color VAL_TEST
0af3 ; --------------------------------------------------------------------------------------
0af3 CMUX_FIU_ERROR:
0af3 0af3 <halt> ; Flow R
0af4 0af4 seq_br_type a Unconditional Return; Flow R
0af5 ; --------------------------------------------------------------------------------------
0af5 ; Comes from:
0af5 ; 0953 C True from color VAL_TEST
0af5 ; 0955 C True from color VAL_TEST
0af5 ; 0957 C True from color VAL_TEST
0af5 ; 0959 C True from color VAL_TEST
0af5 ; 095b C True from color VAL_TEST
0af5 ; 095d C True from color VAL_TEST
0af5 ; 095f C True from color VAL_TEST
0af5 ; 0961 C True from color VAL_TEST
0af5 ; 0963 C True from color VAL_TEST
0af5 ; 0965 C True from color VAL_TEST
0af5 ; 0977 C True from color VAL_TEST
0af5 ; 0979 C True from color VAL_TEST
0af5 ; --------------------------------------------------------------------------------------
0af5 FIU_HIGH_ERROR:
0af5 0af5 <halt> ; Flow R
0af6 0af6 seq_br_type a Unconditional Return; Flow R
0af7 ; --------------------------------------------------------------------------------------
0af7 ; Comes from:
0af7 ; 0967 C True from color VAL_TEST
0af7 ; 0969 C True from color VAL_TEST
0af7 ; 096b C True from color VAL_TEST
0af7 ; 096d C True from color VAL_TEST
0af7 ; 096f C True from color VAL_TEST
0af7 ; 0971 C True from color VAL_TEST
0af7 ; 0973 C True from color VAL_TEST
0af7 ; 0975 C True from color VAL_TEST
0af7 ; --------------------------------------------------------------------------------------
0af7 FIU_LOW_ERROR:
0af7 0af7 <halt> ; Flow R
0af8 0af8 seq_br_type a Unconditional Return; Flow R
0af9 ; --------------------------------------------------------------------------------------
0af9 ; Comes from:
0af9 ; 097c C True from color VAL_TEST
0af9 ; 097f C True from color VAL_TEST
0af9 ; 0981 C True from color VAL_TEST
0af9 ; 0983 C True from color VAL_TEST
0af9 ; 0985 C True from color VAL_TEST
0af9 ; 0987 C True from color VAL_TEST
0af9 ; 0989 C True from color VAL_TEST
0af9 ; 098b C True from color VAL_TEST
0af9 ; 098d C True from color VAL_TEST
0af9 ; 098f C True from color VAL_TEST
0af9 ; 0991 C True from color VAL_TEST
0af9 ; 0994 C True from color VAL_TEST
0af9 ; 0997 C True from color VAL_TEST
0af9 ; 0999 C True from color VAL_TEST
0af9 ; 099b C True from color VAL_TEST
0af9 ; 099d C True from color VAL_TEST
0af9 ; 099f C True from color VAL_TEST
0af9 ; 09a1 C True from color VAL_TEST
0af9 ; 09a3 C True from color VAL_TEST
0af9 ; 09a5 C True from color VAL_TEST
0af9 ; --------------------------------------------------------------------------------------
0af9 FIU_COND_ERROR:
0af9 0af9 <halt> ; Flow R
0afa 0afa seq_br_type a Unconditional Return; Flow R
0afb ; --------------------------------------------------------------------------------------
0afb ; Comes from:
0afb ; 09af C True from color VAL_TEST
0afb ; 09b4 C True from color VAL_TEST
0afb ; 09b9 C True from color VAL_TEST
0afb ; 09be C True from color VAL_TEST
0afb ; 09bf C True from color VAL_TEST
0afb ; --------------------------------------------------------------------------------------
0afb ZERO_COUNT_ERROR:
0afb 0afb <halt> ; Flow R
0afc 0afc seq_br_type a Unconditional Return; Flow R
0afd ; --------------------------------------------------------------------------------------
0afd ; Comes from:
0afd ; 09a9 C False from color VAL_TEST
0afd ; 09aa C True from color VAL_TEST
0afd ; 09ab C False from color VAL_TEST
0afd ; 09ac C False from color VAL_TEST
0afd ; 09ad C False from color VAL_TEST
0afd ; 09b1 C True from color VAL_TEST
0afd ; 09b2 C False from color VAL_TEST
0afd ; 09c3 C False from color VAL_TEST
0afd ; 09c4 C False from color VAL_TEST
0afd ; 09c5 C False from color VAL_TEST
0afd ; 09c8 C False from color VAL_TEST
0afd ; 09c9 C True from color VAL_TEST
0afd ; 09ca C True from color VAL_TEST
0afd ; 09cd C True from color VAL_TEST
0afd ; 09ce C True from color VAL_TEST
0afd ; 09cf C False from color VAL_TEST
0afd ; --------------------------------------------------------------------------------------
0afd ZERO_COND_ERROR:
0afd 0afd <halt> ; Flow R
0afe 0afe seq_br_type a Unconditional Return; Flow R
0aff ; --------------------------------------------------------------------------------------
0aff ; Comes from:
0aff ; 09d2 C True from color VAL_TEST
0aff ; --------------------------------------------------------------------------------------
0aff REG_A_B_ERROR:
0aff 0aff <halt> ; Flow R
0b00 0b00 seq_br_type a Unconditional Return; Flow R
0b01 ; --------------------------------------------------------------------------------------
0b01 ; Comes from:
0b01 ; 09d6 C True from color VAL_TEST
0b01 ; 09d7 C True from color VAL_TEST
0b01 ; 09d8 C True from color VAL_TEST
0b01 ; 09d9 C True from color VAL_TEST
0b01 ; 09dc C True from color VAL_TEST
0b01 ; 09dd C True from color VAL_TEST
0b01 ; 09de C True from color VAL_TEST
0b01 ; 09df C True from color VAL_TEST
0b01 ; 09e2 C True from color VAL_TEST
0b01 ; 09e3 C True from color VAL_TEST
0b01 ; 09e4 C True from color VAL_TEST
0b01 ; 09e5 C True from color VAL_TEST
0b01 ; 09e8 C True from color VAL_TEST
0b01 ; 09e9 C True from color VAL_TEST
0b01 ; 09ea C True from color VAL_TEST
0b01 ; 09eb C True from color VAL_TEST
0b01 ; 09ee C True from color VAL_TEST
0b01 ; 09f0 C True from color VAL_TEST
0b01 ; 09f2 C True from color VAL_TEST
0b01 ; 09f4 C True from color VAL_TEST
0b01 ; 09f6 C True from color VAL_TEST
0b01 ; 09f8 C True from color VAL_TEST
0b01 ; 09fa C True from color VAL_TEST
0b01 ; 09fc C True from color VAL_TEST
0b01 ; 0a01 C True from color VAL_TEST
0b01 ; 0a03 C True from color VAL_TEST
0b01 ; 0a05 C True from color VAL_TEST
0b01 ; 0a07 C True from color VAL_TEST
0b01 ; 0a0c C True from color VAL_TEST
0b01 ; 0a0e C True from color VAL_TEST
0b01 ; 0a10 C True from color VAL_TEST
0b01 ; 0a12 C True from color VAL_TEST
0b01 ; 0a14 C True from color VAL_TEST
0b01 ; 0a16 C True from color VAL_TEST
0b01 ; 0a18 C True from color VAL_TEST
0b01 ; 0a1a C True from color VAL_TEST
0b01 ; 0a1f C True from color VAL_TEST
0b01 ; 0a21 C True from color VAL_TEST
0b01 ; 0a23 C True from color VAL_TEST
0b01 ; 0a25 C True from color VAL_TEST
0b01 ; 0a29 C True from color VAL_TEST
0b01 ; 0a2a C True from color VAL_TEST
0b01 ; 0a2b C True from color VAL_TEST
0b01 ; 0a2d C True from color VAL_TEST
0b01 ; 0a2e C True from color VAL_TEST
0b01 ; 0a2f C True from color VAL_TEST
0b01 ; 0a35 C True from color VAL_TEST
0b01 ; 0a37 C True from color VAL_TEST
0b01 ; 0a39 C True from color VAL_TEST
0b01 ; 0a3d C True from color VAL_TEST
0b01 ; 0a3f C True from color VAL_TEST
0b01 ; 0a41 C True from color VAL_TEST
0b01 ; 0a45 C True from color VAL_TEST
0b01 ; 0a46 C True from color VAL_TEST
0b01 ; 0a47 C True from color VAL_TEST
0b01 ; 0a49 C True from color VAL_TEST
0b01 ; 0a4a C True from color VAL_TEST
0b01 ; 0a4b C True from color VAL_TEST
0b01 ; 0a4c C True from color VAL_TEST
0b01 ; 0a4d C True from color VAL_TEST
0b01 ; 0a4e C True from color VAL_TEST
0b01 ; 0a4f C True from color VAL_TEST
0b01 ; 0a50 C True from color VAL_TEST
0b01 ; 0a52 C True from color VAL_TEST
0b01 ; 0a53 C True from color VAL_TEST
0b01 ; 0a54 C True from color VAL_TEST
0b01 ; 0a55 C True from color VAL_TEST
0b01 ; 0a56 C True from color VAL_TEST
0b01 ; 0a57 C True from color VAL_TEST
0b01 ; 0a58 C True from color VAL_TEST
0b01 ; 0a59 C True from color VAL_TEST
0b01 ; 0a5f C True from color VAL_TEST
0b01 ; 0a61 C True from color VAL_TEST
0b01 ; 0a70 C True from color VAL_TEST
0b01 ; 0a73 C True from color VAL_TEST
0b01 ; 0a79 C True from color VAL_TEST
0b01 ; 0a82 C True from color VAL_TEST
0b01 ; 0a84 C True from color VAL_TEST
0b01 ; --------------------------------------------------------------------------------------
0b01 MULT_ERROR:
0b01 0b01 <halt> ; Flow R
0b02 0b02 seq_br_type a Unconditional Return; Flow R
0b03 ; --------------------------------------------------------------------------------------
0b03 ; Comes from:
0b03 ; 0a88 C True from color VAL_TEST
0b03 ; 0a89 C False from color VAL_TEST
0b03 ; 0a8a C True from color VAL_TEST
0b03 ; 0a8b C False from color VAL_TEST
0b03 ; 0a8c C True from color VAL_TEST
0b03 ; 0a8d C True from color VAL_TEST
0b03 ; 0a8f C True from color VAL_TEST
0b03 ; 0a90 C True from color VAL_TEST
0b03 ; 0a91 C True from color VAL_TEST
0b03 ; 0a93 C True from color VAL_TEST
0b03 ; 0a94 C True from color VAL_TEST
0b03 ; 0a96 C True from color VAL_TEST
0b03 ; 0a97 C True from color VAL_TEST
0b03 ; 0a98 C True from color VAL_TEST
0b03 ; 0a9a C False from color VAL_TEST
0b03 ; 0a9b C True from color VAL_TEST
0b03 ; 0a9d C True from color VAL_TEST
0b03 ; 0a9e C False from color VAL_TEST
0b03 ; 0a9f C True from color VAL_TEST
0b03 ; 0aa1 C False from color VAL_TEST
0b03 ; 0aa2 C True from color VAL_TEST
0b03 ; 0aa4 C False from color VAL_TEST
0b03 ; 0aa5 C True from color VAL_TEST
0b03 ; 0aa6 C True from color VAL_TEST
0b03 ; 0aa8 C True from color VAL_TEST
0b03 ; 0aa9 C True from color VAL_TEST
0b03 ; 0aab C False from color VAL_TEST
0b03 ; 0aac C False from color VAL_TEST
0b03 ; 0aad C True from color VAL_TEST
0b03 ; 0aaf C True from color VAL_TEST
0b03 ; 0ab0 C True from color VAL_TEST
0b03 ; 0ab2 C False from color VAL_TEST
0b03 ; 0ab3 C False from color VAL_TEST
0b03 ; 0ab4 C True from color VAL_TEST
0b03 ; 0ab6 C False from color VAL_TEST
0b03 ; 0ab7 C True from color VAL_TEST
0b03 ; 0ab9 C False from color VAL_TEST
0b03 ; 0aba C True from color VAL_TEST
0b03 ; 0abb C True from color VAL_TEST
0b03 ; 0abd C False from color VAL_TEST
0b03 ; 0abe C True from color VAL_TEST
0b03 ; --------------------------------------------------------------------------------------
0b03 DIV_ERROR:
0b03 0b03 <halt> ; Flow R
0b04 0b04 seq_br_type a Unconditional Return; Flow R
0b05 ; --------------------------------------------------------------------------------------
0b05 ; Comes from:
0b05 ; 0ac1 C True from color VAL_TEST
0b05 ; 0ac4 C True from color VAL_TEST
0b05 ; --------------------------------------------------------------------------------------
0b05 VAL_BUS_ERROR:
0b05 0b05 <halt> ; Flow R
0b06 0b06 seq_br_type a Unconditional Return; Flow R
0b07 ; --------------------------------------------------------------------------------------
0b07 ; Comes from:
0b07 ; 0ac6 C True from color VAL_TEST
0b07 ; 0ac8 C True from color VAL_TEST
0b07 ; 0ace C True from color VAL_TEST
0b07 ; 0ad1 C True from color VAL_TEST
0b07 ; 0ad5 C True from color VAL_TEST
0b07 ; 0ad8 C True from color VAL_TEST
0b07 ; --------------------------------------------------------------------------------------
0b07 IMMEDIATE_OP_ERROR:
0b07 0b07 <halt> ; Flow R
0b08 0b08 seq_br_type a Unconditional Return; Flow R
0b09 0b09 <halt> ; Flow R
0b0a 0b0a <halt> ; Flow R
0b0b 0b0b <halt> ; Flow R
0b0c 0b0c <halt> ; Flow R
0b0d 0b0d <halt> ; Flow R
0b0e 0b0e <halt> ; Flow R
0b0f 0b0f <halt> ; Flow R
0b10 0b10 <halt> ; Flow R
0b11 0b11 <halt> ; Flow R
0b12 0b12 <halt> ; Flow R
0b13 0b13 <halt> ; Flow R
0b14 0b14 <halt> ; Flow R
0b15 0b15 <halt> ; Flow R
0b16 0b16 <halt> ; Flow R
0b17 0b17 <halt> ; Flow R
0b18 0b18 <halt> ; Flow R
0b19 0b19 <halt> ; Flow R
0b1a 0b1a <halt> ; Flow R
0b1b 0b1b <halt> ; Flow R
0b1c 0b1c <halt> ; Flow R
0b1d 0b1d <halt> ; Flow R
0b1e 0b1e <halt> ; Flow R
0b1f 0b1f <halt> ; Flow R
0b20 0b20 <halt> ; Flow R
0b21 0b21 <halt> ; Flow R
0b22 0b22 <halt> ; Flow R
0b23 0b23 <halt> ; Flow R
0b24 0b24 <halt> ; Flow R
0b25 0b25 <halt> ; Flow R
0b26 0b26 <halt> ; Flow R
0b27 0b27 <halt> ; Flow R
0b28 0b28 <halt> ; Flow R
0b29 0b29 <halt> ; Flow R
0b2a 0b2a <halt> ; Flow R
0b2b 0b2b <halt> ; Flow R
0b2c 0b2c <halt> ; Flow R
0b2d 0b2d <halt> ; Flow R
0b2e 0b2e <halt> ; Flow R
0b2f 0b2f <halt> ; Flow R
0b30 0b30 <halt> ; Flow R
0b31 0b31 <halt> ; Flow R
0b32 0b32 <halt> ; Flow R
0b33 0b33 <halt> ; Flow R
0b34 0b34 <halt> ; Flow R
0b35 0b35 <halt> ; Flow R
0b36 0b36 <halt> ; Flow R
0b37 0b37 <halt> ; Flow R
0b38 0b38 <halt> ; Flow R
0b39 0b39 <halt> ; Flow R
0b3a 0b3a <halt> ; Flow R
0b3b 0b3b <halt> ; Flow R
0b3c 0b3c <halt> ; Flow R
0b3d 0b3d <halt> ; Flow R
0b3e 0b3e <halt> ; Flow R
0b3f 0b3f <halt> ; Flow R
0b40 0b40 <halt> ; Flow R
0b41 0b41 <halt> ; Flow R
0b42 0b42 <halt> ; Flow R
0b43 0b43 <halt> ; Flow R
0b44 0b44 <halt> ; Flow R
0b45 0b45 <halt> ; Flow R
0b46 0b46 <halt> ; Flow R
0b47 0b47 <halt> ; Flow R
0b48 0b48 <halt> ; Flow R
0b49 0b49 <halt> ; Flow R
0b4a 0b4a <halt> ; Flow R
0b4b 0b4b <halt> ; Flow R
0b4c 0b4c <halt> ; Flow R
0b4d 0b4d <halt> ; Flow R
0b4e 0b4e <halt> ; Flow R
0b4f 0b4f <halt> ; Flow R
0b50 0b50 <halt> ; Flow R
0b51 0b51 <halt> ; Flow R
0b52 0b52 <halt> ; Flow R
0b53 0b53 <halt> ; Flow R
0b54 0b54 <halt> ; Flow R
0b55 0b55 <halt> ; Flow R
0b56 0b56 <halt> ; Flow R
0b57 0b57 <halt> ; Flow R
0b58 0b58 <halt> ; Flow R
0b59 0b59 <halt> ; Flow R
0b5a 0b5a <halt> ; Flow R
0b5b 0b5b <halt> ; Flow R
0b5c 0b5c <halt> ; Flow R
0b5d 0b5d <halt> ; Flow R
0b5e 0b5e <halt> ; Flow R
0b5f 0b5f <halt> ; Flow R
0b60 0b60 <halt> ; Flow R
0b61 0b61 <halt> ; Flow R
0b62 0b62 <halt> ; Flow R
0b63 0b63 <halt> ; Flow R
0b64 0b64 <halt> ; Flow R
0b65 0b65 <halt> ; Flow R
0b66 0b66 <halt> ; Flow R
0b67 0b67 <halt> ; Flow R
0b68 0b68 <halt> ; Flow R
0b69 0b69 <halt> ; Flow R
0b6a 0b6a <halt> ; Flow R
0b6b 0b6b <halt> ; Flow R
0b6c 0b6c <halt> ; Flow R
0b6d 0b6d <halt> ; Flow R
0b6e 0b6e <halt> ; Flow R
0b6f 0b6f <halt> ; Flow R
0b70 0b70 <halt> ; Flow R
0b71 0b71 <halt> ; Flow R
0b72 0b72 <halt> ; Flow R
0b73 0b73 <halt> ; Flow R
0b74 0b74 <halt> ; Flow R
0b75 0b75 <halt> ; Flow R
0b76 0b76 <halt> ; Flow R
0b77 0b77 <halt> ; Flow R
0b78 0b78 <halt> ; Flow R
0b79 0b79 <halt> ; Flow R
0b7a 0b7a <halt> ; Flow R
0b7b 0b7b <halt> ; Flow R
0b7c 0b7c <halt> ; Flow R
0b7d 0b7d <halt> ; Flow R
0b7e 0b7e <halt> ; Flow R
0b7f 0b7f <halt> ; Flow R
0b80 0b80 <halt> ; Flow R
0b81 0b81 <halt> ; Flow R
0b82 0b82 <halt> ; Flow R
0b83 0b83 <halt> ; Flow R
0b84 0b84 <halt> ; Flow R
0b85 0b85 <halt> ; Flow R
0b86 0b86 <halt> ; Flow R
0b87 0b87 <halt> ; Flow R
0b88 0b88 <halt> ; Flow R
0b89 0b89 <halt> ; Flow R
0b8a 0b8a <halt> ; Flow R
0b8b 0b8b <halt> ; Flow R
0b8c 0b8c <halt> ; Flow R
0b8d 0b8d <halt> ; Flow R
0b8e 0b8e <halt> ; Flow R
0b8f 0b8f <halt> ; Flow R
0b90 0b90 <halt> ; Flow R
0b91 0b91 <halt> ; Flow R
0b92 0b92 <halt> ; Flow R
0b93 0b93 <halt> ; Flow R
0b94 0b94 <halt> ; Flow R
0b95 0b95 <halt> ; Flow R
0b96 0b96 <halt> ; Flow R
0b97 0b97 <halt> ; Flow R
0b98 0b98 <halt> ; Flow R
0b99 0b99 <halt> ; Flow R
0b9a 0b9a <halt> ; Flow R
0b9b 0b9b <halt> ; Flow R
0b9c 0b9c <halt> ; Flow R
0b9d 0b9d <halt> ; Flow R
0b9e 0b9e <halt> ; Flow R
0b9f 0b9f <halt> ; Flow R
0ba0 0ba0 <halt> ; Flow R
0ba1 0ba1 <halt> ; Flow R
0ba2 0ba2 <halt> ; Flow R
0ba3 0ba3 <halt> ; Flow R
0ba4 0ba4 <halt> ; Flow R
0ba5 0ba5 <halt> ; Flow R
0ba6 0ba6 <halt> ; Flow R
0ba7 0ba7 <halt> ; Flow R
0ba8 0ba8 <halt> ; Flow R
0ba9 0ba9 <halt> ; Flow R
0baa 0baa <halt> ; Flow R
0bab 0bab <halt> ; Flow R
0bac 0bac <halt> ; Flow R
0bad 0bad <halt> ; Flow R
0bae 0bae <halt> ; Flow R
0baf 0baf <halt> ; Flow R
0bb0 0bb0 <halt> ; Flow R
0bb1 0bb1 <halt> ; Flow R
0bb2 0bb2 <halt> ; Flow R
0bb3 0bb3 <halt> ; Flow R
0bb4 0bb4 <halt> ; Flow R
0bb5 0bb5 <halt> ; Flow R
0bb6 0bb6 <halt> ; Flow R
0bb7 0bb7 <halt> ; Flow R
0bb8 0bb8 <halt> ; Flow R
0bb9 0bb9 <halt> ; Flow R
0bba 0bba <halt> ; Flow R
0bbb 0bbb <halt> ; Flow R
0bbc 0bbc <halt> ; Flow R
0bbd 0bbd <halt> ; Flow R
0bbe 0bbe <halt> ; Flow R
0bbf 0bbf <halt> ; Flow R
0bc0 0bc0 <halt> ; Flow R
0bc1 0bc1 <halt> ; Flow R
0bc2 0bc2 <halt> ; Flow R
0bc3 0bc3 <halt> ; Flow R
0bc4 0bc4 <halt> ; Flow R
0bc5 0bc5 <halt> ; Flow R
0bc6 0bc6 <halt> ; Flow R
0bc7 0bc7 <halt> ; Flow R
0bc8 0bc8 <halt> ; Flow R
0bc9 0bc9 <halt> ; Flow R
0bca 0bca <halt> ; Flow R
0bcb 0bcb <halt> ; Flow R
0bcc 0bcc <halt> ; Flow R
0bcd 0bcd <halt> ; Flow R
0bce 0bce <halt> ; Flow R
0bcf 0bcf <halt> ; Flow R
0bd0 0bd0 <halt> ; Flow R
0bd1 0bd1 <halt> ; Flow R
0bd2 0bd2 <halt> ; Flow R
0bd3 0bd3 <halt> ; Flow R
0bd4 0bd4 <halt> ; Flow R
0bd5 0bd5 <halt> ; Flow R
0bd6 0bd6 <halt> ; Flow R
0bd7 0bd7 <halt> ; Flow R
0bd8 0bd8 <halt> ; Flow R
0bd9 0bd9 <halt> ; Flow R
0bda 0bda <halt> ; Flow R
0bdb 0bdb <halt> ; Flow R
0bdc 0bdc <halt> ; Flow R
0bdd 0bdd <halt> ; Flow R
0bde 0bde <halt> ; Flow R
0bdf 0bdf <halt> ; Flow R
0be0 0be0 <halt> ; Flow R
0be1 0be1 <halt> ; Flow R
0be2 0be2 <halt> ; Flow R
0be3 0be3 <halt> ; Flow R
0be4 0be4 <halt> ; Flow R
0be5 0be5 <halt> ; Flow R
0be6 0be6 <halt> ; Flow R
0be7 0be7 <halt> ; Flow R
0be8 0be8 <halt> ; Flow R
0be9 0be9 <halt> ; Flow R
0bea 0bea <halt> ; Flow R
0beb 0beb <halt> ; Flow R
0bec 0bec <halt> ; Flow R
0bed 0bed <halt> ; Flow R
0bee 0bee <halt> ; Flow R
0bef 0bef <halt> ; Flow R
0bf0 0bf0 <halt> ; Flow R
0bf1 0bf1 <halt> ; Flow R
0bf2 0bf2 <halt> ; Flow R
0bf3 0bf3 <halt> ; Flow R
0bf4 0bf4 <halt> ; Flow R
0bf5 0bf5 <halt> ; Flow R
0bf6 0bf6 <halt> ; Flow R
0bf7 0bf7 <halt> ; Flow R
0bf8 0bf8 <halt> ; Flow R
0bf9 0bf9 <halt> ; Flow R
0bfa 0bfa <halt> ; Flow R
0bfb 0bfb <halt> ; Flow R
0bfc 0bfc <halt> ; Flow R
0bfd 0bfd <halt> ; Flow R
0bfe 0bfe <halt> ; Flow R
0bff 0bff <halt> ; Flow R
0c00 ; --------------------------------------------------------------------------------------
0c00 ; 0C00 - 1190 TYP_TEST
0c00 ; Comes from:
0c00 ; 030f C from color DIAGNOSTIC_START
0c00 ; --------------------------------------------------------------------------------------
0c00 0c00 seq_b_timing 0 Early Condition; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 25 TYP.FALSE (early)
0c01 0c01 seq_b_timing 0 Early Condition; Flow J cc=False 0xc03
seq_br_type 0 Branch False
seq_branch_adr 0c03 0x0c03
seq_cond_sel 25 TYP.FALSE (early)
0c02 0c02 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c03 0c03 seq_b_timing 0 Early Condition; Flow J cc=True 0xc05
seq_br_type 1 Branch True
seq_branch_adr 0c05 0x0c05
seq_cond_sel 26 TYP.TRUE (early)
0c04 0c04 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c05 0c05 seq_b_timing 0 Early Condition; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 26 TYP.TRUE (early)
0c06 0c06 seq_cond_sel 25 TYP.FALSE (early)
0c07 0c07 seq_b_timing 0 Early Condition; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
0c08 0c08 seq_cond_sel 25 TYP.FALSE (early)
0c09 0c09 seq_b_timing 0 Early Condition; Flow J cc=False 0xc0b
seq_br_type 0 Branch False
seq_branch_adr 0c0b 0x0c0b
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
0c0a 0c0a seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c0b 0c0b seq_cond_sel 26 TYP.TRUE (early)
0c0c 0c0c seq_b_timing 0 Early Condition; Flow J cc=True 0xc0e
seq_br_type 1 Branch True
seq_branch_adr 0c0e 0x0c0e
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
0c0d 0c0d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c0e 0c0e seq_cond_sel 26 TYP.TRUE (early)
0c0f 0c0f seq_b_timing 0 Early Condition; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
0c10 0c10 typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c11 0c11 seq_b_timing 0 Early Condition; Flow J cc=True 0xc13
seq_br_type 1 Branch True
seq_branch_adr 0c13 0x0c13
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
0c12 0c12 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c13 0c13 seq_b_timing 0 Early Condition; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
0c14 0c14 typ_alu_func 13 ONES
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c15 0c15 seq_b_timing 0 Early Condition; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
0c16 0c16 seq_b_timing 0 Early Condition; Flow J cc=False 0xc18
seq_br_type 0 Branch False
seq_branch_adr 0c18 0x0c18
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
0c17 0c17 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c18 0c18 seq_b_timing 0 Early Condition; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c19 0c19 seq_b_timing 0 Early Condition; Flow J cc=True 0xc1b
seq_br_type 1 Branch True
seq_branch_adr 0c1b 0x0c1b
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_alu_func 13 ONES
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c1a 0c1a seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c1b 0c1b seq_b_timing 0 Early Condition; Flow J cc=False 0xc1d
seq_br_type 0 Branch False
seq_branch_adr 0c1d 0x0c1d
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c1c 0c1c seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c1d 0c1d seq_b_timing 0 Early Condition; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_alu_func 13 ONES
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
0c1e 0c1e seq_br_type 1 Branch True; Flow J cc=True 0xc20
seq_branch_adr 0c20 0x0c20
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c1f 0c1f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c20 0c20 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c21 0c21 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc23
seq_br_type 1 Branch True
seq_branch_adr 0c23 0x0c23
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c22 0c22 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c23 0c23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c24 0c24 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c25 0c25 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc27
seq_br_type 0 Branch False
seq_branch_adr 0c27 0x0c27
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c26 0c26 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c27 0c27 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c28 0c28 seq_br_type 0 Branch False; Flow J cc=False 0xc2a
seq_branch_adr 0c2a 0x0c2a
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c29 0c29 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c2a 0c2a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c2b 0c2b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc2d
seq_br_type 0 Branch False
seq_branch_adr 0c2d 0x0c2d
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c2c 0c2c seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c2d 0c2d seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c2e 0c2e seq_br_type 0 Branch False; Flow J cc=False 0xc30
seq_branch_adr 0c30 0x0c30
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c2f 0c2f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c30 0c30 seq_br_type 1 Branch True; Flow J cc=True 0xc32
seq_branch_adr 0c32 0x0c32
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c31 0c31 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c32 0c32 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c33 0c33 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc35
seq_br_type 1 Branch True
seq_branch_adr 0c35 0x0c35
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c34 0c34 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c35 0c35 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 24 TYP.SIGN_BITS_EQUAL(med_late)
typ_a_adr 22 TR10:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0c36 0c36 seq_br_type 1 Branch True; Flow J cc=True 0xc38
seq_branch_adr 0c38 0x0c38
seq_cond_sel 18 TYP.ALU_ZERO(late)
0c37 0c37 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c38 0c38 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
0c39 0c39 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_alu_func 13 ONES
0c3a 0c3a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc3c
seq_br_type 0 Branch False
seq_branch_adr 0c3c 0x0c3c
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_alu_func 13 ONES
0c3b 0c3b seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c3c 0c3c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc3e
seq_br_type 1 Branch True
seq_branch_adr 0c3e 0x0c3e
seq_cond_sel 18 TYP.ALU_ZERO(late)
0c3d 0c3d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c3e 0c3e seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
0c3f 0c3f seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_alu_func 13 ONES
0c40 0c40 seq_br_type 0 Branch False; Flow J cc=False 0xc42
seq_branch_adr 0c42 0x0c42
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_alu_func 13 ONES
0c41 0c41 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c42 0c42 seq_br_type 1 Branch True; Flow J cc=True 0xc44
seq_branch_adr 0c44 0x0c44
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c43 0c43 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c44 0c44 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c45 0c45 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c46 0c46 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc48
seq_br_type 0 Branch False
seq_branch_adr 0c48 0x0c48
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c47 0c47 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c48 0c48 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc4a
seq_br_type 1 Branch True
seq_branch_adr 0c4a 0x0c4a
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c49 0c49 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c4a 0c4a seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c4b 0c4b seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c4c 0c4c seq_br_type 0 Branch False; Flow J cc=False 0xc4e
seq_branch_adr 0c4e 0x0c4e
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c4d 0c4d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c4e 0c4e seq_br_type 1 Branch True; Flow J cc=True 0xc50
seq_branch_adr 0c50 0x0c50
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 13 ONES
0c4f 0c4f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c50 0c50 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 13 ONES
0c51 0c51 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
0c52 0c52 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc54
seq_br_type 0 Branch False
seq_branch_adr 0c54 0x0c54
seq_cond_sel 19 TYP.ALU_NONZERO(late)
0c53 0c53 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c54 0c54 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc56
seq_br_type 1 Branch True
seq_branch_adr 0c56 0x0c56
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 13 ONES
0c55 0c55 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c56 0c56 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 13 ONES
0c57 0c57 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
0c58 0c58 seq_br_type 0 Branch False; Flow J cc=False 0xc5a
seq_branch_adr 0c5a 0x0c5a
seq_cond_sel 19 TYP.ALU_NONZERO(late)
0c59 0c59 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c5a 0c5a seq_br_type 1 Branch True; Flow J cc=True 0xc5c
seq_branch_adr 0c5c 0x0c5c
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c5b 0c5b seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c5c 0c5c seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c5d 0c5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c5e 0c5e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc60
seq_br_type 0 Branch False
seq_branch_adr 0c60 0x0c60
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c5f 0c5f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c60 0c60 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc62
seq_br_type 1 Branch True
seq_branch_adr 0c62 0x0c62
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c61 0c61 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c62 0c62 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c63 0c63 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c64 0c64 seq_br_type 0 Branch False; Flow J cc=False 0xc66
seq_branch_adr 0c66 0x0c66
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c65 0c65 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c66 0c66 seq_br_type 1 Branch True; Flow J cc=True 0xc68
seq_branch_adr 0c68 0x0c68
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_alu_func 13 ONES
0c67 0c67 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c68 0c68 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_alu_func 13 ONES
0c69 0c69 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
0c6a 0c6a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc6c
seq_br_type 0 Branch False
seq_branch_adr 0c6c 0x0c6c
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
0c6b 0c6b seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c6c 0c6c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc6e
seq_br_type 1 Branch True
seq_branch_adr 0c6e 0x0c6e
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_alu_func 13 ONES
0c6d 0c6d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c6e 0c6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_alu_func 13 ONES
0c6f 0c6f seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
0c70 0c70 seq_br_type 0 Branch False; Flow J cc=False 0xc72
seq_branch_adr 0c72 0x0c72
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
0c71 0c71 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c72 0c72 seq_br_type 1 Branch True; Flow J cc=True 0xc74
seq_branch_adr 0c74 0x0c74
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c73 0c73 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c74 0c74 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c75 0c75 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c76 0c76 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc78
seq_br_type 0 Branch False
seq_branch_adr 0c78 0x0c78
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c77 0c77 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c78 0c78 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc7a
seq_br_type 1 Branch True
seq_branch_adr 0c7a 0x0c7a
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c79 0c79 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c7a 0c7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c7b 0c7b seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c7c 0c7c seq_br_type 0 Branch False; Flow J cc=False 0xc7e
seq_branch_adr 0c7e 0x0c7e
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c7d 0c7d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c7e 0c7e seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc80
seq_br_type 0 Branch False
seq_branch_adr 0c80 0x0c80
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_alu_func 13 ONES
0c7f 0c7f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c80 0c80 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_alu_func 13 ONES
0c81 0c81 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc83
seq_br_type 0 Branch False
seq_branch_adr 0c83 0x0c83
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
0c82 0c82 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c83 0c83 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
0c84 0c84 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
0c85 0c85 seq_br_type 1 Branch True; Flow J cc=True 0xc87
seq_branch_adr 0c87 0x0c87
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
0c86 0c86 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c87 0c87 seq_br_type 0 Branch False; Flow J cc=False 0xc89
seq_branch_adr 0c89 0x0c89
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_alu_func 13 ONES
0c88 0c88 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c89 0c89 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_alu_func 13 ONES
0c8a 0c8a seq_br_type 0 Branch False; Flow J cc=False 0xc8c
seq_branch_adr 0c8c 0x0c8c
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
0c8b 0c8b seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c8c 0c8c seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
0c8d 0c8d seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
0c8e 0c8e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xc90
seq_br_type 1 Branch True
seq_branch_adr 0c90 0x0c90
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
0c8f 0c8f seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c90 0c90 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc92
seq_br_type 0 Branch False
seq_branch_adr 0c92 0x0c92
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c91 0c91 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c92 0c92 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c93 0c93 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xc95
seq_br_type 0 Branch False
seq_branch_adr 0c95 0x0c95
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c94 0c94 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c95 0c95 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c96 0c96 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 21 TR10:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c97 0c97 seq_br_type 1 Branch True; Flow J cc=True 0xc99
seq_branch_adr 0c99 0x0c99
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 21 TR10:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c98 0c98 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c99 0c99 seq_br_type 0 Branch False; Flow J cc=False 0xc9b
seq_branch_adr 0c9b 0x0c9b
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c9a 0c9a seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c9b 0c9b seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_frame 10
0c9c 0c9c seq_br_type 0 Branch False; Flow J cc=False 0xc9e
seq_branch_adr 0c9e 0x0c9e
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c9d 0c9d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0c9e 0c9e seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0c9f 0c9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 21 TR10:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca0 0ca0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xca2
seq_br_type 1 Branch True
seq_branch_adr 0ca2 0x0ca2
seq_cond_sel 23 TYP.ALU_LE_ZERO(late)
typ_a_adr 21 TR10:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca1 0ca1 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ca2 0ca2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca3 0ca3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xca5
seq_br_type 0 Branch False
seq_branch_adr 0ca5 0x0ca5
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca4 0ca4 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ca5 0ca5 seq_br_type 1 Branch True; Flow J cc=True 0xca7
seq_branch_adr 0ca7 0x0ca7
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca6 0ca6 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ca7 0ca7 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca8 0ca8 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ca9 0ca9 seq_br_type 0 Branch False; Flow J cc=False 0xcab
seq_branch_adr 0cab 0x0cab
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0caa 0caa seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cab 0cab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcad
seq_br_type 1 Branch True
seq_branch_adr 0cad 0x0cad
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cac 0cac seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cad 0cad seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cae 0cae seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0caf 0caf seq_br_type 1 Branch True; Flow J cc=True 0xcb1
seq_branch_adr 0cb1 0x0cb1
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb0 0cb0 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cb1 0cb1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xcb3
seq_br_type 0 Branch False
seq_branch_adr 0cb3 0x0cb3
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb2 0cb2 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cb3 0cb3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb4 0cb4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb5 0cb5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcb7
seq_br_type 1 Branch True
seq_branch_adr 0cb7 0x0cb7
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb6 0cb6 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cb7 0cb7 seq_br_type 0 Branch False; Flow J cc=False 0xcb9
seq_branch_adr 0cb9 0x0cb9
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cb8 0cb8 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cb9 0cb9 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cba 0cba seq_br_type 0 Branch False; Flow J cc=False 0xcbc
seq_branch_adr 0cbc 0x0cbc
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 25 TR13:05
typ_alu_func 7 INC_A
typ_frame 13
0cbb 0cbb seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cbc 0cbc seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late)
typ_a_adr 24 TR16:04
typ_alu_func 7 INC_A
typ_frame 16
0cbd 0cbd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cbe 0cbe seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xcc0
seq_br_type 0 Branch False
seq_branch_adr 0cc0 0x0cc0
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cbf 0cbf seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cc0 0cc0 seq_br_type 1 Branch True; Flow J cc=True 0xcc2
seq_branch_adr 0cc2 0x0cc2
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc1 0cc1 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cc2 0cc2 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc3 0cc3 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc4 0cc4 seq_br_type 0 Branch False; Flow J cc=False 0xcc6
seq_branch_adr 0cc6 0x0cc6
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc5 0cc5 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cc6 0cc6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcc8
seq_br_type 1 Branch True
seq_branch_adr 0cc8 0x0cc8
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc7 0cc7 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cc8 0cc8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cc9 0cc9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xccb
seq_br_type 0 Branch False
seq_branch_adr 0ccb 0x0ccb
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cca 0cca seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ccb 0ccb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0ccc 0ccc seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0ccd 0ccd seq_br_type 1 Branch True; Flow J cc=True 0xccf
seq_branch_adr 0ccf 0x0ccf
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cce 0cce seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ccf 0ccf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xcd1
seq_br_type 0 Branch False
seq_branch_adr 0cd1 0x0cd1
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cd0 0cd0 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cd1 0cd1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cd2 0cd2 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cd3 0cd3 seq_br_type 1 Branch True; Flow J cc=True 0xcd5
seq_branch_adr 0cd5 0x0cd5
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cd4 0cd4 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cd5 0cd5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xcd7
seq_br_type 0 Branch False
seq_branch_adr 0cd7 0x0cd7
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cd6 0cd6 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cd7 0cd7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cd8 0cd8 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0cd9 0cd9 seq_br_type 1 Branch True; Flow J cc=True 0xcdb
seq_branch_adr 0cdb 0x0cdb
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0cda 0cda seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cdb 0cdb seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xcdd
seq_br_type 0 Branch False
seq_branch_adr 0cdd 0x0cdd
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cdc 0cdc seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cdd 0cdd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cde 0cde seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cdf 0cdf seq_br_type 1 Branch True; Flow J cc=True 0xce1
seq_branch_adr 0ce1 0x0ce1
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0ce0 0ce0 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ce1 0ce1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xce3
seq_br_type 0 Branch False
seq_branch_adr 0ce3 0x0ce3
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0ce2 0ce2 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ce3 0ce3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0ce4 0ce4 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0ce5 0ce5 seq_br_type 1 Branch True; Flow J cc=True 0xce7
seq_branch_adr 0ce7 0x0ce7
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0ce6 0ce6 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ce7 0ce7 seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0ce8 0ce8 seq_br_type 1 Branch True; Flow J cc=True 0xcea
seq_branch_adr 0cea 0x0cea
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0ce9 0ce9 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cea 0cea seq_br_type 4 Call False; Flow C cc=False 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 3f TR05:1f
typ_alu_func 6 A_MINUS_B
typ_b_adr 3f TR05:1f
typ_frame 5
0ceb 0ceb seq_br_type 1 Branch True; Flow J cc=True 0xced
seq_branch_adr 0ced 0x0ced
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 3f TR05:1f
typ_alu_func 6 A_MINUS_B
typ_b_adr 3f TR05:1f
typ_frame 5
0cec 0cec seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0ced 0ced seq_br_type 0 Branch False; Flow J cc=False 0xcef
seq_branch_adr 0cef 0x0cef
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cee 0cee seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cef 0cef seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cf0 0cf0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cf1 0cf1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcf3
seq_br_type 1 Branch True
seq_branch_adr 0cf3 0x0cf3
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cf2 0cf2 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cf3 0cf3 seq_br_type 0 Branch False; Flow J cc=False 0xcf5
seq_branch_adr 0cf5 0x0cf5
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cf4 0cf4 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cf5 0cf5 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0cf6 0cf6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cf7 0cf7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcf9
seq_br_type 1 Branch True
seq_branch_adr 0cf9 0x0cf9
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0cf8 0cf8 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cf9 0cf9 seq_br_type 0 Branch False; Flow J cc=False 0xcfb
seq_branch_adr 0cfb 0x0cfb
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cfa 0cfa seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cfb 0cfb seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0cfc 0cfc seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0cfd 0cfd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xcff
seq_br_type 1 Branch True
seq_branch_adr 0cff 0x0cff
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0cfe 0cfe seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0cff 0cff seq_br_type 0 Branch False; Flow J cc=False 0xd01
seq_branch_adr 0d01 0x0d01
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0d00 0d00 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d01 0d01 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
0d02 0d02 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0d03 0d03 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd05
seq_br_type 1 Branch True
seq_branch_adr 0d05 0x0d05
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0d04 0d04 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d05 0d05 seq_br_type 0 Branch False; Flow J cc=False 0xd07
seq_branch_adr 0d07 0x0d07
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0d06 0d06 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d07 0d07 seq_br_type 5 Call True; Flow C cc=True 0x1165
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 27 TR10:07
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR10:02
typ_frame 10
0d08 0d08 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0d09 0d09 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd0b
seq_br_type 1 Branch True
seq_branch_adr 0d0b 0x0d0b
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 22 TR10:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 27 TR10:07
typ_frame 10
0d0a 0d0a seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d0b 0d0b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0d0c 0d0c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd0e
seq_br_type 1 Branch True
seq_branch_adr 0d0e 0x0d0e
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 23 TR10:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR10:03
typ_frame 10
0d0d 0d0d seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d0e 0d0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1165
seq_br_type 4 Call False
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 3f TR05:1f
typ_alu_func 6 A_MINUS_B
typ_b_adr 3f TR05:1f
typ_frame 5
0d0f 0d0f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd11
seq_br_type 1 Branch True
seq_branch_adr 0d11 0x0d11
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 3f TR05:1f
typ_alu_func 6 A_MINUS_B
typ_b_adr 3f TR05:1f
typ_frame 5
0d10 0d10 seq_br_type 7 Unconditional Call; Flow C 0x1165
seq_branch_adr 1165 COND_ERROR
0d11 0d11 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
0d12 0d12 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
0d13 0d13 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_rand d SET_PASS_PRIVACY_BIT
0d14 0d14 typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d15 0d15 seq_br_type 4 Call False; Flow C cc=False 0x1167
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
0d16 0d16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d17 0d17 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d18 0d18 typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d19 0d19 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d1a 0d1a typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
0d1b 0d1b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
0d1c 0d1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 1c DEC_A
0d1d 0d1d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
0d1e 0d1e typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
0d1f 0d1f typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d20 0d20 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
0d21 0d21 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 04 GP04
0d22 0d22 seq_b_timing 0 Early Condition; Flow J cc=False 0xd1d
seq_br_type 0 Branch False
seq_branch_adr 0d1d 0x0d1d
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
0d23 0d23 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
0d24 0d24 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
0d25 0d25 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_rand d SET_PASS_PRIVACY_BIT
0d26 0d26 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
0d27 0d27 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
0d28 0d28 typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 04 GP04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
0d29 0d29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
0d2a 0d2a typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
0d2b 0d2b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1167
seq_br_type 5 Call True
seq_branch_adr 1167 REG_FILE_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
0d2c 0d2c seq_b_timing 0 Early Condition; Flow J cc=False 0xd26
seq_br_type 0 Branch False
seq_branch_adr 0d26 0x0d26
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
0d2d 0d2d typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
0d2e 0d2e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0d2f 0d2f typ_alu_func 13 ONES
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
0d30 0d30 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0d31 0d31 typ_a_adr 20 TR11:00
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d32 0d32 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d33 0d33 typ_a_adr 21 TR11:01
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d34 0d34 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d35 0d35 typ_a_adr 22 TR11:02
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d36 0d36 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d37 0d37 typ_a_adr 23 TR11:03
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d38 0d38 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d39 0d39 typ_a_adr 24 TR11:04
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d3a 0d3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d3b 0d3b typ_a_adr 25 TR11:05
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d3c 0d3c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d3d 0d3d typ_alu_func 1a PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d3e 0d3e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d3f 0d3f typ_alu_func 1a PASS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d40 0d40 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d41 0d41 typ_alu_func 1a PASS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d42 0d42 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d43 0d43 typ_alu_func 1a PASS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d44 0d44 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d45 0d45 typ_alu_func 1a PASS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d46 0d46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d47 0d47 typ_alu_func 1a PASS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d48 0d48 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d49 0d49 typ_a_adr 20 TR11:00
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d4a 0d4a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d4b 0d4b typ_a_adr 21 TR11:01
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d4c 0d4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d4d 0d4d typ_a_adr 22 TR11:02
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d4e 0d4e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d4f 0d4f typ_a_adr 23 TR11:03
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d50 0d50 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d51 0d51 typ_a_adr 24 TR11:04
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d52 0d52 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d53 0d53 typ_a_adr 25 TR11:05
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d54 0d54 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d55 0d55 typ_alu_func 15 NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d56 0d56 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d57 0d57 typ_alu_func 15 NOT_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d58 0d58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d59 0d59 typ_alu_func 15 NOT_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d5a 0d5a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d5b 0d5b typ_alu_func 15 NOT_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d5c 0d5c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d5d 0d5d typ_alu_func 15 NOT_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d5e 0d5e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d5f 0d5f typ_alu_func 15 NOT_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d60 0d60 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d61 0d61 typ_a_adr 22 TR11:02
typ_alu_func 1e A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d62 0d62 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d63 0d63 typ_a_adr 20 TR11:00
typ_alu_func 1e A_AND_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d64 0d64 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d65 0d65 typ_a_adr 23 TR11:03
typ_alu_func 1e A_AND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d66 0d66 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d67 0d67 typ_a_adr 21 TR11:01
typ_alu_func 1e A_AND_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d68 0d68 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d69 0d69 typ_a_adr 24 TR11:04
typ_alu_func 1e A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d6a 0d6a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d6b 0d6b typ_a_adr 20 TR11:00
typ_alu_func 1e A_AND_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d6c 0d6c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d6d 0d6d typ_a_adr 25 TR11:05
typ_alu_func 1e A_AND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d6e 0d6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d6f 0d6f typ_a_adr 21 TR11:01
typ_alu_func 1e A_AND_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d70 0d70 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d71 0d71 typ_a_adr 22 TR11:02
typ_alu_func 1b A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d72 0d72 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d73 0d73 typ_a_adr 20 TR11:00
typ_alu_func 1b A_OR_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d74 0d74 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d75 0d75 typ_a_adr 23 TR11:03
typ_alu_func 1b A_OR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d76 0d76 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d77 0d77 typ_a_adr 21 TR11:01
typ_alu_func 1b A_OR_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d78 0d78 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d79 0d79 typ_a_adr 24 TR11:04
typ_alu_func 1b A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d7a 0d7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d7b 0d7b typ_a_adr 20 TR11:00
typ_alu_func 1b A_OR_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d7c 0d7c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d7d 0d7d typ_a_adr 25 TR11:05
typ_alu_func 1b A_OR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d7e 0d7e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d7f 0d7f typ_a_adr 21 TR11:01
typ_alu_func 1b A_OR_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d80 0d80 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d81 0d81 typ_a_adr 22 TR11:02
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d82 0d82 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d83 0d83 typ_a_adr 20 TR11:00
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d84 0d84 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d85 0d85 typ_a_adr 23 TR11:03
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d86 0d86 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d87 0d87 typ_a_adr 21 TR11:01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d88 0d88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d89 0d89 typ_a_adr 24 TR11:04
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d8a 0d8a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d8b 0d8b typ_a_adr 20 TR11:00
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d8c 0d8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d8d 0d8d typ_a_adr 25 TR11:05
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d8e 0d8e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d8f 0d8f typ_a_adr 21 TR11:01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d90 0d90 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d91 0d91 typ_a_adr 22 TR11:02
typ_alu_func 11 A_NAND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d92 0d92 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d93 0d93 typ_a_adr 20 TR11:00
typ_alu_func 11 A_NAND_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d94 0d94 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d95 0d95 typ_a_adr 23 TR11:03
typ_alu_func 11 A_NAND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d96 0d96 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d97 0d97 typ_a_adr 21 TR11:01
typ_alu_func 11 A_NAND_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d98 0d98 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d99 0d99 typ_a_adr 24 TR11:04
typ_alu_func 11 A_NAND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d9a 0d9a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d9b 0d9b typ_a_adr 20 TR11:00
typ_alu_func 11 A_NAND_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d9c 0d9c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d9d 0d9d typ_a_adr 25 TR11:05
typ_alu_func 11 A_NAND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0d9e 0d9e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0d9f 0d9f typ_a_adr 21 TR11:01
typ_alu_func 11 A_NAND_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0da0 0da0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0da1 0da1 typ_a_adr 22 TR11:02
typ_alu_func 14 A_NOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0da2 0da2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0da3 0da3 typ_a_adr 20 TR11:00
typ_alu_func 14 A_NOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0da4 0da4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0da5 0da5 typ_a_adr 23 TR11:03
typ_alu_func 14 A_NOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0da6 0da6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0da7 0da7 typ_a_adr 21 TR11:01
typ_alu_func 14 A_NOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0da8 0da8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0da9 0da9 typ_a_adr 24 TR11:04
typ_alu_func 14 A_NOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0daa 0daa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dab 0dab typ_a_adr 20 TR11:00
typ_alu_func 14 A_NOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dac 0dac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dad 0dad typ_a_adr 25 TR11:05
typ_alu_func 14 A_NOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dae 0dae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0daf 0daf typ_a_adr 21 TR11:01
typ_alu_func 14 A_NOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0db0 0db0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0db1 0db1 typ_a_adr 22 TR11:02
typ_alu_func 16 A_XNOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0db2 0db2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0db3 0db3 typ_a_adr 20 TR11:00
typ_alu_func 16 A_XNOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0db4 0db4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0db5 0db5 typ_a_adr 23 TR11:03
typ_alu_func 16 A_XNOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0db6 0db6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0db7 0db7 typ_a_adr 21 TR11:01
typ_alu_func 16 A_XNOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0db8 0db8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0db9 0db9 typ_a_adr 24 TR11:04
typ_alu_func 16 A_XNOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dba 0dba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dbb 0dbb typ_a_adr 20 TR11:00
typ_alu_func 16 A_XNOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dbc 0dbc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dbd 0dbd typ_a_adr 25 TR11:05
typ_alu_func 16 A_XNOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dbe 0dbe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dbf 0dbf typ_a_adr 21 TR11:01
typ_alu_func 16 A_XNOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dc0 0dc0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dc1 0dc1 typ_a_adr 22 TR11:02
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dc2 0dc2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dc3 0dc3 typ_a_adr 20 TR11:00
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dc4 0dc4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dc5 0dc5 typ_a_adr 23 TR11:03
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dc6 0dc6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dc7 0dc7 typ_a_adr 21 TR11:01
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dc8 0dc8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dc9 0dc9 typ_a_adr 24 TR11:04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dca 0dca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dcb 0dcb typ_a_adr 20 TR11:00
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dcc 0dcc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dcd 0dcd typ_a_adr 25 TR11:05
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dce 0dce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dcf 0dcf typ_a_adr 21 TR11:01
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dd0 0dd0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dd1 0dd1 typ_a_adr 22 TR11:02
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dd2 0dd2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dd3 0dd3 typ_a_adr 20 TR11:00
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dd4 0dd4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dd5 0dd5 typ_a_adr 23 TR11:03
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dd6 0dd6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR11:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dd7 0dd7 typ_a_adr 21 TR11:01
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dd8 0dd8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dd9 0dd9 typ_a_adr 24 TR11:04
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dda 0dda seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR11:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ddb 0ddb typ_a_adr 20 TR11:00
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ddc 0ddc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ddd 0ddd typ_a_adr 25 TR11:05
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dde 0dde seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR11:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ddf 0ddf typ_a_adr 21 TR11:01
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0de0 0de0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR11:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0de1 0de1 typ_a_adr 22 TR11:02
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0de2 0de2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0de3 0de3 typ_a_adr 20 TR11:00
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0de4 0de4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0de5 0de5 typ_a_adr 23 TR11:03
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0de6 0de6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0de7 0de7 typ_a_adr 21 TR11:01
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0de8 0de8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0de9 0de9 typ_a_adr 24 TR11:04
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dea 0dea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0deb 0deb typ_a_adr 20 TR11:00
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dec 0dec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ded 0ded typ_a_adr 25 TR11:05
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dee 0dee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0def 0def typ_a_adr 21 TR11:01
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0df0 0df0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0df1 0df1 typ_a_adr 22 TR11:02
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0df2 0df2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0df3 0df3 typ_a_adr 20 TR11:00
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0df4 0df4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0df5 0df5 typ_a_adr 23 TR11:03
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0df6 0df6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0df7 0df7 typ_a_adr 21 TR11:01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0df8 0df8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR11:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0df9 0df9 typ_a_adr 24 TR11:04
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dfa 0dfa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dfb 0dfb typ_a_adr 20 TR11:00
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dfc 0dfc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR11:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dfd 0dfd typ_a_adr 25 TR11:05
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0dfe 0dfe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR11:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0dff 0dff typ_a_adr 21 TR11:01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e00 0e00 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1169
seq_br_type 5 Call True
seq_branch_adr 1169 LOGICAL_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR11:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e01 0e01 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e02 0e02 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e03 0e03 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
0e04 0e04 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e05 0e05 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e06 0e06 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0e07 0e07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR10:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e08 0e08 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e09 0e09 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR05:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 5
0e0a 0e0a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e0b 0e0b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e0c 0e0c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR11:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e0d 0e0d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e0e 0e0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e0f 0e0f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TR11:0f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e10 0e10 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e11 0e11 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e12 0e12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR11:10
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e13 0e13 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e14 0e14 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e15 0e15 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 31 TR11:11
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e16 0e16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e17 0e17 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e18 0e18 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR11:12
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e19 0e19 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e1a 0e1a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e1b 0e1b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR11:13
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e1c 0e1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e1d 0e1d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0e1e 0e1e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0e1f 0e1f seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR04:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
0e20 0e20 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR04:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
0e21 0e21 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0e22 0e22 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 3f TR05:1f
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 5
0e23 0e23 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 3f TR05:1f
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 5
0e24 0e24 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR10:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0e25 0e25 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e26 0e26 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e27 0e27 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR11:14
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e28 0e28 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e29 0e29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e2a 0e2a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR11:15
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e2b 0e2b seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e2c 0e2c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e2d 0e2d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR11:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e2e 0e2e seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e2f 0e2f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e30 0e30 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 37 TR11:17
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e31 0e31 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e32 0e32 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e33 0e33 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR11:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e34 0e34 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e35 0e35 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e36 0e36 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 39 TR11:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e37 0e37 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e38 0e38 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR12:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e39 0e39 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e3a 0e3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR12:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e3b 0e3b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e3c 0e3c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR12:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e3d 0e3d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e3e 0e3e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR12:10
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e3f 0e3f seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e40 0e40 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR12:12
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e41 0e41 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e42 0e42 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR12:14
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e43 0e43 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e44 0e44 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR12:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e45 0e45 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e46 0e46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR12:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e47 0e47 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e48 0e48 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TR12:0f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e49 0e49 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e4a 0e4a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 31 TR12:11
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e4b 0e4b seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e4c 0e4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR12:13
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e4d 0e4d seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e4e 0e4e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR12:15
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e4f 0e4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e50 0e50 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e51 0e51 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e52 0e52 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e53 0e53 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e54 0e54 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e55 0e55 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e56 0e56 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e57 0e57 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR12:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e58 0e58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e59 0e59 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e5a 0e5a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR12:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e5b 0e5b seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e5c 0e5c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e5d 0e5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR11:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e5e 0e5e seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e5f 0e5f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e60 0e60 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR11:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e61 0e61 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e62 0e62 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e63 0e63 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR12:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e64 0e64 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e65 0e65 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e66 0e66 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR12:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e67 0e67 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e68 0e68 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e69 0e69 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR12:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e6a 0e6a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e6b 0e6b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e6c 0e6c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR12:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e6d 0e6d seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e6e 0e6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e6f 0e6f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR11:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e70 0e70 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e71 0e71 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e72 0e72 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR11:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e73 0e73 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e74 0e74 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e75 0e75 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR12:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e76 0e76 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e77 0e77 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e78 0e78 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR12:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e79 0e79 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e7a 0e7a seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 1 A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e7b 0e7b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR12:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e7c 0e7c seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e7d 0e7d seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 1 A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e7e 0e7e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR12:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e7f 0e7f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e80 0e80 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e81 0e81 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR12:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e82 0e82 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e83 0e83 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e84 0e84 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR12:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e85 0e85 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e86 0e86 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e87 0e87 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR12:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e88 0e88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e89 0e89 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e8a 0e8a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR12:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e8b 0e8b seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e8c 0e8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e8d 0e8d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR11:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e8e 0e8e seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e8f 0e8f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e90 0e90 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR11:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0e91 0e91 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e92 0e92 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e93 0e93 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR12:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e94 0e94 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e95 0e95 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e96 0e96 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR12:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e97 0e97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e98 0e98 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e99 0e99 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e9a 0e9a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e9b 0e9b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e9c 0e9c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0e9d 0e9d seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e9e 0e9e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0e9f 0e9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR11:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ea0 0ea0 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea1 0ea1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea2 0ea2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR11:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ea3 0ea3 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea4 0ea4 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea5 0ea5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR12:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ea6 0ea6 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea7 0ea7 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ea8 0ea8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR12:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ea9 0ea9 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eaa 0eaa seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eab 0eab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR11:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0eac 0eac seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ead 0ead seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eae 0eae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR11:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0eaf 0eaf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb0 0eb0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb1 0eb1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0eb2 0eb2 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb3 0eb3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb4 0eb4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR11:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0eb5 0eb5 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb6 0eb6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb7 0eb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR11:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0eb8 0eb8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eb9 0eb9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eba 0eba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR12:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ebb 0ebb seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ebc 0ebc seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ebd 0ebd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR12:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ebe 0ebe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ebf 0ebf seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec0 0ec0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR12:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ec1 0ec1 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec2 0ec2 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec3 0ec3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR11:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ec4 0ec4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec5 0ec5 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec6 0ec6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR12:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ec7 0ec7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec8 0ec8 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ec9 0ec9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR12:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0eca 0eca seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ecb 0ecb seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ecc 0ecc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR12:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ecd 0ecd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ece 0ece seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ecf 0ecf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR12:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ed0 0ed0 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed1 0ed1 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed2 0ed2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR11:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ed3 0ed3 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed4 0ed4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed5 0ed5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR11:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ed6 0ed6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed7 0ed7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ed8 0ed8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ed9 0ed9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eda 0eda seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 6 A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0edb 0edb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR12:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0edc 0edc seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0edd 0edd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ede 0ede seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR11:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0edf 0edf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee0 0ee0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee1 0ee1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR12:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ee2 0ee2 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee3 0ee3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee4 0ee4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR11:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ee5 0ee5 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee6 0ee6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee7 0ee7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR11:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ee8 0ee8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ee9 0ee9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eea 0eea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR12:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0eeb 0eeb seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eec 0eec seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eed 0eed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR12:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0eee 0eee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eef 0eef seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef0 0ef0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ef1 0ef1 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef2 0ef2 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef3 0ef3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR12:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ef4 0ef4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef5 0ef5 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR11:00
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef6 0ef6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR12:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0ef7 0ef7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef8 0ef8 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0ef9 0ef9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0efa 0efa seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0efb 0efb seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0efc 0efc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR12:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0efd 0efd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR11:03
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0efe 0efe seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR11:03
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0eff 0eff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR12:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f00 0f00 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f01 0f01 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f02 0f02 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR12:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f03 0f03 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 24 TR11:04
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f04 0f04 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 24 TR11:04
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f05 0f05 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR11:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f06 0f06 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f07 0f07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f08 0f08 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR12:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f09 0f09 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 25 TR11:05
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f0a 0f0a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 25 TR11:05
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f0b 0f0b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR12:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f0c 0f0c seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f0d 0f0d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 21 TR11:01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f0e 0f0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR11:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f0f 0f0f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f10 0f10 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f11 0f11 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR04:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
0f12 0f12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 27 TR04:07
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand 0 NO_OP
0f13 0f13 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 27 TR04:07
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand 0 NO_OP
0f14 0f14 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR04:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
0f15 0f15 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f16 0f16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f17 0f17 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR10:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f18 0f18 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 23 TR10:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f19 0f19 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 23 TR10:03
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f1a 0f1a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR10:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f1b 0f1b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 2e TR10:0e
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f1c 0f1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 2e TR10:0e
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f1d 0f1d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f1e 0f1e seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 2f TR10:0f
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f1f 0f1f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 2f TR10:0f
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f20 0f20 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f21 0f21 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f22 0f22 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f23 0f23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TR10:0f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f24 0f24 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 22 TR10:02
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f25 0f25 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 22 TR10:02
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f26 0f26 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR10:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f27 0f27 seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 27 TR04:07
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand 0 NO_OP
0f28 0f28 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 27 TR04:07
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand 0 NO_OP
0f29 0f29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f2a 0f2a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 2c TR10:0c
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f2b 0f2b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 2c TR10:0c
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f2c 0f2c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f2d 0f2d seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 2d TR10:0d
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f2e 0f2e seq_br_type 4 Call False; Flow C cc=False 0x116b
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 21 TYP.ALU_OVERFLOW(late)
typ_a_adr 2d TR10:0d
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 0 NO_OP
0f2f 0f2f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116b
seq_br_type 5 Call True
seq_branch_adr 116b ARITH_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR10:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f30 0f30 seq_cond_sel 26 TYP.TRUE (early)
0f31 0f31 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f32 0f32 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f33 0f33 seq_cond_sel 26 TYP.TRUE (early)
0f34 0f34 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f35 0f35 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f36 0f36 seq_cond_sel 25 TYP.FALSE (early)
0f37 0f37 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f38 0f38 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f39 0f39 seq_cond_sel 25 TYP.FALSE (early)
0f3a 0f3a seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f3b 0f3b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f3c 0f3c seq_cond_sel 26 TYP.TRUE (early)
0f3d 0f3d seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f3e 0f3e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f3f 0f3f seq_cond_sel 26 TYP.TRUE (early)
0f40 0f40 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f41 0f41 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f42 0f42 seq_cond_sel 25 TYP.FALSE (early)
0f43 0f43 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f44 0f44 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f45 0f45 seq_cond_sel 25 TYP.FALSE (early)
0f46 0f46 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f47 0f47 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f48 0f48 seq_cond_sel 26 TYP.TRUE (early)
0f49 0f49 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f4a 0f4a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f4b 0f4b seq_cond_sel 26 TYP.TRUE (early)
0f4c 0f4c seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f4d 0f4d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f4e 0f4e seq_cond_sel 25 TYP.FALSE (early)
0f4f 0f4f seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f50 0f50 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f51 0f51 seq_cond_sel 25 TYP.FALSE (early)
0f52 0f52 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f53 0f53 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f54 0f54 seq_cond_sel 26 TYP.TRUE (early)
0f55 0f55 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f56 0f56 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f57 0f57 seq_cond_sel 26 TYP.TRUE (early)
0f58 0f58 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f59 0f59 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f5a 0f5a seq_cond_sel 25 TYP.FALSE (early)
0f5b 0f5b seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f5c 0f5c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f5d 0f5d seq_cond_sel 25 TYP.FALSE (early)
0f5e 0f5e seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR10:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f5f 0f5f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f60 0f60 seq_cond_sel 26 TYP.TRUE (early)
0f61 0f61 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f62 0f62 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f63 0f63 seq_cond_sel 26 TYP.TRUE (early)
0f64 0f64 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f65 0f65 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f66 0f66 seq_cond_sel 25 TYP.FALSE (early)
0f67 0f67 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f68 0f68 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f69 0f69 seq_cond_sel 25 TYP.FALSE (early)
0f6a 0f6a seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f6b 0f6b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f6c 0f6c seq_cond_sel 26 TYP.TRUE (early)
0f6d 0f6d seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f6e 0f6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f6f 0f6f seq_cond_sel 26 TYP.TRUE (early)
0f70 0f70 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f71 0f71 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f72 0f72 seq_cond_sel 25 TYP.FALSE (early)
0f73 0f73 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f74 0f74 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f75 0f75 seq_cond_sel 25 TYP.FALSE (early)
0f76 0f76 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
0f77 0f77 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0f78 0f78 seq_cond_sel 26 TYP.TRUE (early)
0f79 0f79 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f7a 0f7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f7b 0f7b seq_cond_sel 26 TYP.TRUE (early)
0f7c 0f7c seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f7d 0f7d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f7e 0f7e seq_cond_sel 25 TYP.FALSE (early)
0f7f 0f7f seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f80 0f80 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f81 0f81 seq_cond_sel 25 TYP.FALSE (early)
0f82 0f82 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f83 0f83 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f84 0f84 seq_cond_sel 26 TYP.TRUE (early)
0f85 0f85 seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f86 0f86 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f87 0f87 seq_cond_sel 26 TYP.TRUE (early)
0f88 0f88 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f89 0f89 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR12:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f8a 0f8a seq_cond_sel 25 TYP.FALSE (early)
0f8b 0f8b seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f8c 0f8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f8d 0f8d seq_cond_sel 25 TYP.FALSE (early)
0f8e 0f8e seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
0f8f 0f8f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116d
seq_br_type 5 Call True
seq_branch_adr 116d COND_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR11:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f90 0f90 typ_a_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f91 0f91 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR12:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f92 0f92 typ_a_adr 22 TR11:02
typ_alu_func 13 ONES
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f93 0f93 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 37 TR12:17
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f94 0f94 typ_a_adr 22 TR11:02
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f95 0f95 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0f96 0f96 typ_a_adr 22 TR11:02
typ_alu_func 1a PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f97 0f97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR12:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f98 0f98 typ_a_adr 22 TR11:02
typ_alu_func 10 NOT_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f99 0f99 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 39 TR12:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f9a 0f9a typ_a_adr 22 TR11:02
typ_alu_func 15 NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f9b 0f9b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR12:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f9c 0f9c typ_a_adr 22 TR11:02
typ_alu_func 1e A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f9d 0f9d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR12:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0f9e 0f9e typ_a_adr 22 TR11:02
typ_alu_func 1b A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0f9f 0f9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR12:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fa0 0fa0 typ_a_adr 22 TR11:02
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fa1 0fa1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR12:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fa2 0fa2 typ_a_adr 22 TR11:02
typ_alu_func 11 A_NAND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fa3 0fa3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR12:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fa4 0fa4 typ_a_adr 22 TR11:02
typ_alu_func 14 A_NOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fa5 0fa5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR12:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fa6 0fa6 typ_a_adr 22 TR11:02
typ_alu_func 16 A_XNOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fa7 0fa7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR13:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fa8 0fa8 typ_a_adr 22 TR11:02
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fa9 0fa9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR13:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0faa 0faa typ_a_adr 22 TR11:02
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fab 0fab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR13:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fac 0fac typ_a_adr 22 TR11:02
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fad 0fad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR13:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fae 0fae typ_a_adr 22 TR11:02
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0faf 0faf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR13:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fb0 0fb0 typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 6 CHECK_CLASS_A_??_B
0fb1 0fb1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
0fb2 0fb2 typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 6 CHECK_CLASS_A_??_B
0fb3 0fb3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR13:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fb4 0fb4 typ_a_adr 22 TR11:02
typ_alu_func 3 LEFT_I_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fb5 0fb5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR13:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fb6 0fb6 typ_a_adr 22 TR11:02
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fb7 0fb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR13:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fb8 0fb8 typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fb9 0fb9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR13:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fba 0fba typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fbb 0fbb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR13:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fbc 0fbc typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fbd 0fbd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR13:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fbe 0fbe typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fbf 0fbf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR13:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fc0 0fc0 seq_cond_sel 26 TYP.TRUE (early)
0fc1 0fc1 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fc2 0fc2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fc3 0fc3 seq_cond_sel 25 TYP.FALSE (early)
0fc4 0fc4 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fc5 0fc5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR12:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fc6 0fc6 seq_cond_sel 26 TYP.TRUE (early)
0fc7 0fc7 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fc8 0fc8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR12:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
0fc9 0fc9 seq_cond_sel 25 TYP.FALSE (early)
0fca 0fca seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fcb 0fcb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fcc 0fcc seq_cond_sel 26 TYP.TRUE (early); SELECT_CONDITION(TYP(TRUE)),
0fcd 0fcd seq_en_micro 0 ; DISABLE(MICRO_EVENTS),
; TYP { RESULT := PASS_HIGH_A (16#36C936C936C936C9#) },
; TYP { RESULT := PASS_A (16#36C936C936C936C9#) ELSE
; INC_A (16#36C936C936C936C9#) },
typ_a_adr 22 TR11:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
; TYP { BAD_BITS := RESULT XOR 16#36C936C936C936C9# },
; IF TYP ( RESULT /= 16#36C936C936C936C9#) THEN
; RARELY CALL_SPLIT_ALU_ERROR,
0fce 0fce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fcf 0fcf seq_cond_sel 25 TYP.FALSE (early); SELECT_CONDITION(TYP(FALSE)),
0fd0 0fd0 seq_en_micro 0 ; DISABLE(MICRO_EVENTS),
; TYP { RESULT := PASS_HIGH_A (16#36C936C936C936C9#) },
; TYP { RESULT := PASS_A (16#36C936C936C936C9#) ELSE
; INC_A (16#36C936C936C936C9#) },
typ_a_adr 22 TR11:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
; TYP { BAD_BITS := RESULT XOR 16#36C936C936C936CA# },
; IF TYP ( RESULT /= 16#36C936C936C936CA#) THEN
; RARELY CALL_SPLIT_ALU_ERROR,
0fd1 0fd1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR11:10
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fd2 0fd2 seq_cond_sel 26 TYP.TRUE (early); SELECT_CONDITION(TYP(TRUE)),
0fd3 0fd3 seq_en_micro 0 ; DISABLE(MICRO_EVENTS),
; TYP { RESULT := PASS_HIGH_A (16#36C936C936C936C9#) },
; TYP { RESULT := INC_A (16#36C936C936C936C9#) ELSE
; PASS_A (16#36C936C936C936C9#) },
typ_a_adr 22 TR11:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
; TYP { BAD_BITS := RESULT XOR 16#36C936C936C936CA# },
; IF TYP ( RESULT /= 16#36C936C936C936CA#) THEN
; RARELY CALL_SPLIT_ALU_ERROR,
0fd4 0fd4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR11:10
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fd5 0fd5 seq_cond_sel 25 TYP.FALSE (early)
0fd6 0fd6 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fd7 0fd7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fd8 0fd8 seq_cond_sel 26 TYP.TRUE (early)
0fd9 0fd9 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fda 0fda seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fdb 0fdb seq_cond_sel 25 TYP.FALSE (early)
0fdc 0fdc seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func e PASS_A_ELSE_DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fdd 0fdd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR11:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fde 0fde seq_cond_sel 26 TYP.TRUE (early)
0fdf 0fdf seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fe0 0fe0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR11:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fe1 0fe1 seq_cond_sel 25 TYP.FALSE (early)
0fe2 0fe2 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func f DEC_A_ELSE__PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fe3 0fe3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0fe4 0fe4 seq_cond_sel 26 TYP.TRUE (early)
0fe5 0fe5 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fe6 0fe6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR13:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fe7 0fe7 seq_cond_sel 25 TYP.FALSE (early)
0fe8 0fe8 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fe9 0fe9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR13:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fea 0fea seq_cond_sel 26 TYP.TRUE (early)
0feb 0feb seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fec 0fec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR13:0a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0fed 0fed seq_cond_sel 25 TYP.FALSE (early)
0fee 0fee seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 6 CHECK_CLASS_A_??_B
0fef 0fef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR13:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ff0 0ff0 typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ff1 0ff1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2c TR13:0c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ff2 0ff2 typ_alu_func 13 ONES
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ff3 0ff3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2d TR13:0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ff4 0ff4 typ_a_adr 22 TR11:02
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ff5 0ff5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ff6 0ff6 typ_alu_func 1a PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ff7 0ff7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
0ff8 0ff8 typ_a_adr 22 TR11:02
typ_alu_func 10 NOT_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ff9 0ff9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TR13:0f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ffa 0ffa typ_alu_func 15 NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ffb 0ffb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR13:10
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ffc 0ffc typ_a_adr 22 TR11:02
typ_alu_func 1e A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0ffd 0ffd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 31 TR13:11
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
0ffe 0ffe typ_a_adr 22 TR11:02
typ_alu_func 1b A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
0fff 0fff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR13:12
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1000 1000 typ_a_adr 22 TR11:02
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1001 1001 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR13:13
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1002 1002 typ_a_adr 22 TR11:02
typ_alu_func 11 A_NAND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1003 1003 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR13:14
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1004 1004 typ_a_adr 22 TR11:02
typ_alu_func 14 A_NOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1005 1005 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR13:15
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1006 1006 typ_a_adr 22 TR11:02
typ_alu_func 16 A_XNOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1007 1007 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR13:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1008 1008 typ_a_adr 22 TR11:02
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1009 1009 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 37 TR13:17
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
100a 100a typ_a_adr 22 TR11:02
typ_alu_func 1d A_AND_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
100b 100b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR13:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
100c 100c typ_a_adr 22 TR11:02
typ_alu_func 12 NOT_A_OR_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
100d 100d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 39 TR13:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
100e 100e typ_a_adr 22 TR11:02
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
100f 100f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR13:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1010 1010 typ_a_adr 22 TR10:02
typ_alu_func 7 INC_A
typ_b_adr 22 TR10:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 5 CHECK_CLASS_B_LIT
1011 1011 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1012 1012 typ_a_adr 20 TR10:00
typ_alu_func 1c DEC_A
typ_b_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 5 CHECK_CLASS_B_LIT
1013 1013 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR13:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1014 1014 typ_a_adr 22 TR11:02
typ_alu_func 3 LEFT_I_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1015 1015 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR13:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1016 1016 typ_a_adr 22 TR11:02
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1017 1017 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR13:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1018 1018 typ_a_adr 22 TR11:02
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1019 1019 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR13:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
101a 101a typ_a_adr 22 TR11:02
typ_alu_func 2 INC_A_PLUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
101b 101b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR13:1e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
101c 101c typ_a_adr 22 TR11:02
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
101d 101d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR13:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
101e 101e typ_a_adr 22 TR11:02
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
101f 101f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR14:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1020 1020 seq_cond_sel 26 TYP.TRUE (early)
1021 1021 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1022 1022 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1023 1023 seq_cond_sel 25 TYP.FALSE (early)
1024 1024 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func a PASS_A_ELSE_PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1025 1025 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1026 1026 seq_cond_sel 26 TYP.TRUE (early)
1027 1027 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1028 1028 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1029 1029 seq_cond_sel 25 TYP.FALSE (early)
102a 102a seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func b PASS_B_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
102b 102b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
102c 102c seq_cond_sel 26 TYP.TRUE (early)
102d 102d seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
102e 102e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
102f 102f seq_cond_sel 25 TYP.FALSE (early)
1030 1030 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func c PASS_A_ELSE_INC_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1031 1031 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR14:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1032 1032 seq_cond_sel 26 TYP.TRUE (early)
1033 1033 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1034 1034 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR14:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1035 1035 seq_cond_sel 25 TYP.FALSE (early)
1036 1036 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func d INC_A_ELSE_PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1037 1037 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1038 1038 seq_cond_sel 26 TYP.TRUE (early)
1039 1039 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func e PASS_A_ELSE_DEC_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
103a 103a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
103b 103b seq_cond_sel 25 TYP.FALSE (early)
103c 103c seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func e PASS_A_ELSE_DEC_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
103d 103d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR14:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
103e 103e seq_cond_sel 26 TYP.TRUE (early)
103f 103f seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func f DEC_A_ELSE__PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1040 1040 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR14:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1041 1041 seq_cond_sel 25 TYP.FALSE (early)
1042 1042 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func f DEC_A_ELSE__PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1043 1043 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1044 1044 seq_cond_sel 26 TYP.TRUE (early)
1045 1045 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1046 1046 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR13:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1047 1047 seq_cond_sel 25 TYP.FALSE (early)
1048 1048 seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 8 PLUS_ELSE_MINUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
1049 1049 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR13:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
104a 104a seq_cond_sel 26 TYP.TRUE (early)
104b 104b seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
104c 104c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR13:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
104d 104d seq_cond_sel 25 TYP.FALSE (early)
104e 104e seq_en_micro 0
typ_a_adr 22 TR11:02
typ_alu_func 9 MINUS_ELSE_PLUS
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
104f 104f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x116f
seq_br_type 5 Call True
seq_branch_adr 116f SPLIT_ALU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR13:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1050 1050 typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
1051 1051 seq_b_timing 0 Early Condition; Flow C cc=False 0x1171
seq_br_type 4 Call False
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1052 1052 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1053 1053 typ_a_adr 25 TR10:05
typ_alu_func 10 NOT_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 10
1054 1054 seq_b_timing 0 Early Condition; Flow C cc=False 0x1171
seq_br_type 4 Call False
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1055 1055 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
1056 1056 typ_a_adr 25 TR10:05
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 10
1057 1057 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1058 1058 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR10:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1059 1059 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
105a 105a seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
105b 105b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
105c 105c typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
105d 105d seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
105e 105e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR04:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
105f 105f typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1060 1060 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1061 1061 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1062 1062 typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1063 1063 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1064 1064 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1065 1065 typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1066 1066 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1067 1067 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR04:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1068 1068 typ_a_adr 25 TR04:05
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1069 1069 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
106a 106a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
106b 106b typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
106c 106c seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
106d 106d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR04:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
106e 106e typ_a_adr 27 TR04:07
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
106f 106f seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1070 1070 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 27 TR04:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1071 1071 typ_a_adr 28 TR04:08
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1072 1072 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1073 1073 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR04:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1074 1074 typ_a_adr 29 TR04:09
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1075 1075 seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
1076 1076 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR04:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1077 1077 typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
1078 1078 typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
1079 1079 seq_b_timing 0 Early Condition; Flow C cc=False 0x1171
seq_br_type 4 Call False
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_rand e CHECK_CLASS_SYSTEM_B
107a 107a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
107b 107b seq_b_timing 0 Early Condition; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 01 GP01
typ_alu_func 7 INC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_rand e CHECK_CLASS_SYSTEM_B
107c 107c seq_br_type 1 Branch True; Flow J cc=True 0x107b
seq_branch_adr 107b 0x107b
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
107d 107d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 02 GP02
typ_alu_func 19 X_XOR_B
typ_b_adr 2a TR04:0a
typ_frame 4
107e 107e seq_b_timing 0 Early Condition; Flow C cc=False 0x1171
seq_br_type 4 Call False
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
107f 107f typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
1080 1080 seq_b_timing 0 Early Condition; Flow C cc=False 0x1171
seq_br_type 4 Call False
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
1081 1081 typ_a_adr 25 TR10:05
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1082 1082 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1083 1083 seq_b_timing 0 Early Condition; Flow J cc=False 0x1082
seq_br_type 0 Branch False
seq_branch_adr 1082 0x1082
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 01 GP01
typ_alu_func 1c DEC_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1084 1084 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1085 1085 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1086 1086 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1171
seq_br_type 5 Call True
seq_branch_adr 1171 LOOP_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 02 GP02
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR10:06
typ_frame 10
1087 1087 seq_br_type 1 Branch True; Flow J cc=True 0x1089
seq_branch_adr 1089 0x1089
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 2a TR05:0a
typ_frame 5
1088 1088 seq_br_type 7 Unconditional Call; Flow C 0x117b
seq_branch_adr 117b BIT_21_ERROR
1089 1089 seq_br_type 4 Call False; Flow C cc=False 0x117b
seq_branch_adr 117b BIT_21_ERROR
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 2a TR05:0a
typ_frame 5
108a 108a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x117b
seq_br_type 5 Call True
seq_branch_adr 117b BIT_21_ERROR
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 3d TR16:1d
typ_frame 16
108b 108b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x108d
seq_br_type 0 Branch False
seq_branch_adr 108d 0x108d
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 3d TR16:1d
typ_frame 16
108c 108c seq_br_type 7 Unconditional Call; Flow C 0x117b
seq_branch_adr 117b BIT_21_ERROR
108d 108d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x108f
seq_br_type 1 Branch True
seq_branch_adr 108f 0x108f
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 2a TR05:0a
typ_frame 5
108e 108e seq_br_type 7 Unconditional Call; Flow C 0x117b
seq_branch_adr 117b BIT_21_ERROR
108f 108f seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x117b
seq_br_type 4 Call False
seq_branch_adr 117b BIT_21_ERROR
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 2a TR05:0a
typ_frame 5
1090 1090 seq_br_type 5 Call True; Flow C cc=True 0x117b
seq_branch_adr 117b BIT_21_ERROR
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 3d TR16:1d
typ_frame 16
1091 1091 seq_br_type 0 Branch False; Flow J cc=False 0x1093
seq_branch_adr 1093 0x1093
seq_cond_sel 3f TYP.D_BUS_BIT_21 (med_late)
typ_b_adr 3d TR16:1d
typ_frame 16
1092 1092 seq_br_type 7 Unconditional Call; Flow C 0x117b
seq_branch_adr 117b BIT_21_ERROR
1093 1093 seq_br_type 1 Branch True; Flow J cc=True 0x1095
seq_branch_adr 1095 0x1095
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 3f TR04:1f
typ_frame 4
1094 1094 seq_br_type 7 Unconditional Call; Flow C 0x117d
seq_branch_adr 117d BIT_32_ERROR
1095 1095 seq_br_type 4 Call False; Flow C cc=False 0x117d
seq_branch_adr 117d BIT_32_ERROR
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 3f TR04:1f
typ_frame 4
1096 1096 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x117d
seq_br_type 5 Call True
seq_branch_adr 117d BIT_32_ERROR
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 21 TR16:01
typ_frame 16
1097 1097 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1099
seq_br_type 0 Branch False
seq_branch_adr 1099 0x1099
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 21 TR16:01
typ_frame 16
1098 1098 seq_br_type 7 Unconditional Call; Flow C 0x117d
seq_branch_adr 117d BIT_32_ERROR
1099 1099 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x109b
seq_br_type 1 Branch True
seq_branch_adr 109b 0x109b
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 3f TR04:1f
typ_frame 4
109a 109a seq_br_type 7 Unconditional Call; Flow C 0x117d
seq_branch_adr 117d BIT_32_ERROR
109b 109b seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x117d
seq_br_type 4 Call False
seq_branch_adr 117d BIT_32_ERROR
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 3f TR04:1f
typ_frame 4
109c 109c seq_br_type 5 Call True; Flow C cc=True 0x117d
seq_branch_adr 117d BIT_32_ERROR
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 21 TR16:01
typ_frame 16
109d 109d seq_br_type 0 Branch False; Flow J cc=False 0x109f
seq_branch_adr 109f 0x109f
seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late)
typ_b_adr 21 TR16:01
typ_frame 16
109e 109e seq_br_type 7 Unconditional Call; Flow C 0x117d
seq_branch_adr 117d BIT_32_ERROR
109f 109f seq_br_type 1 Branch True; Flow J cc=True 0x10a1
seq_branch_adr 10a1 0x10a1
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10a0 10a0 seq_br_type 7 Unconditional Call; Flow C 0x117f
seq_branch_adr 117f BIT_33_ERROR
10a1 10a1 seq_br_type 4 Call False; Flow C cc=False 0x117f
seq_branch_adr 117f BIT_33_ERROR
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10a2 10a2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x117f
seq_br_type 5 Call True
seq_branch_adr 117f BIT_33_ERROR
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 22 TR16:02
typ_frame 16
10a3 10a3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10a5
seq_br_type 0 Branch False
seq_branch_adr 10a5 0x10a5
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 22 TR16:02
typ_frame 16
10a4 10a4 seq_br_type 7 Unconditional Call; Flow C 0x117f
seq_branch_adr 117f BIT_33_ERROR
10a5 10a5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x10a7
seq_br_type 1 Branch True
seq_branch_adr 10a7 0x10a7
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10a6 10a6 seq_br_type 7 Unconditional Call; Flow C 0x117f
seq_branch_adr 117f BIT_33_ERROR
10a7 10a7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x117f
seq_br_type 4 Call False
seq_branch_adr 117f BIT_33_ERROR
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10a8 10a8 seq_br_type 5 Call True; Flow C cc=True 0x117f
seq_branch_adr 117f BIT_33_ERROR
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 22 TR16:02
typ_frame 16
10a9 10a9 seq_br_type 0 Branch False; Flow J cc=False 0x10ab
seq_branch_adr 10ab 0x10ab
seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late)
typ_b_adr 22 TR16:02
typ_frame 16
10aa 10aa seq_br_type 7 Unconditional Call; Flow C 0x117f
seq_branch_adr 117f BIT_33_ERROR
10ab 10ab seq_br_type 1 Branch True; Flow J cc=True 0x10ad
seq_branch_adr 10ad 0x10ad
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10ac 10ac seq_br_type 7 Unconditional Call; Flow C 0x1181
seq_branch_adr 1181 BIT_34_ERROR
10ad 10ad seq_br_type 4 Call False; Flow C cc=False 0x1181
seq_branch_adr 1181 BIT_34_ERROR
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10ae 10ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1181
seq_br_type 5 Call True
seq_branch_adr 1181 BIT_34_ERROR
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 23 TR16:03
typ_frame 16
10af 10af seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10b1
seq_br_type 0 Branch False
seq_branch_adr 10b1 0x10b1
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 23 TR16:03
typ_frame 16
10b0 10b0 seq_br_type 7 Unconditional Call; Flow C 0x1181
seq_branch_adr 1181 BIT_34_ERROR
10b1 10b1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x10b3
seq_br_type 1 Branch True
seq_branch_adr 10b3 0x10b3
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10b2 10b2 seq_br_type 7 Unconditional Call; Flow C 0x1181
seq_branch_adr 1181 BIT_34_ERROR
10b3 10b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1181
seq_br_type 4 Call False
seq_branch_adr 1181 BIT_34_ERROR
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10b4 10b4 seq_br_type 5 Call True; Flow C cc=True 0x1181
seq_branch_adr 1181 BIT_34_ERROR
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 23 TR16:03
typ_frame 16
10b5 10b5 seq_br_type 0 Branch False; Flow J cc=False 0x10b7
seq_branch_adr 10b7 0x10b7
seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late)
typ_b_adr 23 TR16:03
typ_frame 16
10b6 10b6 seq_br_type 7 Unconditional Call; Flow C 0x1181
seq_branch_adr 1181 BIT_34_ERROR
10b7 10b7 seq_br_type 1 Branch True; Flow J cc=True 0x10b9
seq_branch_adr 10b9 0x10b9
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 3c TR04:1c
typ_frame 4
10b8 10b8 seq_br_type 7 Unconditional Call; Flow C 0x1183
seq_branch_adr 1183 BIT_35_ERROR
10b9 10b9 seq_br_type 4 Call False; Flow C cc=False 0x1183
seq_branch_adr 1183 BIT_35_ERROR
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 3c TR04:1c
typ_frame 4
10ba 10ba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1183
seq_br_type 5 Call True
seq_branch_adr 1183 BIT_35_ERROR
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 24 TR16:04
typ_frame 16
10bb 10bb seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10bd
seq_br_type 0 Branch False
seq_branch_adr 10bd 0x10bd
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 24 TR16:04
typ_frame 16
10bc 10bc seq_br_type 7 Unconditional Call; Flow C 0x1183
seq_branch_adr 1183 BIT_35_ERROR
10bd 10bd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x10bf
seq_br_type 1 Branch True
seq_branch_adr 10bf 0x10bf
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 3c TR04:1c
typ_frame 4
10be 10be seq_br_type 7 Unconditional Call; Flow C 0x1183
seq_branch_adr 1183 BIT_35_ERROR
10bf 10bf seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1183
seq_br_type 4 Call False
seq_branch_adr 1183 BIT_35_ERROR
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 3c TR04:1c
typ_frame 4
10c0 10c0 seq_br_type 5 Call True; Flow C cc=True 0x1183
seq_branch_adr 1183 BIT_35_ERROR
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 24 TR16:04
typ_frame 16
10c1 10c1 seq_br_type 0 Branch False; Flow J cc=False 0x10c3
seq_branch_adr 10c3 0x10c3
seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late)
typ_b_adr 24 TR16:04
typ_frame 16
10c2 10c2 seq_br_type 7 Unconditional Call; Flow C 0x1183
seq_branch_adr 1183 BIT_35_ERROR
10c3 10c3 seq_br_type 1 Branch True; Flow J cc=True 0x10c5
seq_branch_adr 10c5 0x10c5
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10c4 10c4 seq_br_type 7 Unconditional Call; Flow C 0x1185
seq_branch_adr 1185 BIT_36_ERROR
10c5 10c5 seq_br_type 4 Call False; Flow C cc=False 0x1185
seq_branch_adr 1185 BIT_36_ERROR
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10c6 10c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1185
seq_br_type 5 Call True
seq_branch_adr 1185 BIT_36_ERROR
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 25 TR16:05
typ_frame 16
10c7 10c7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10c9
seq_br_type 0 Branch False
seq_branch_adr 10c9 0x10c9
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 25 TR16:05
typ_frame 16
10c8 10c8 seq_br_type 7 Unconditional Call; Flow C 0x1185
seq_branch_adr 1185 BIT_36_ERROR
10c9 10c9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x10cb
seq_br_type 1 Branch True
seq_branch_adr 10cb 0x10cb
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10ca 10ca seq_br_type 7 Unconditional Call; Flow C 0x1185
seq_branch_adr 1185 BIT_36_ERROR
10cb 10cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1185
seq_br_type 4 Call False
seq_branch_adr 1185 BIT_36_ERROR
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10cc 10cc seq_br_type 5 Call True; Flow C cc=True 0x1185
seq_branch_adr 1185 BIT_36_ERROR
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 25 TR16:05
typ_frame 16
10cd 10cd seq_br_type 0 Branch False; Flow J cc=False 0x10cf
seq_branch_adr 10cf 0x10cf
seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late)
typ_b_adr 25 TR16:05
typ_frame 16
10ce 10ce seq_br_type 7 Unconditional Call; Flow C 0x1185
seq_branch_adr 1185 BIT_36_ERROR
10cf 10cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10d1
seq_br_type 0 Branch False
seq_branch_adr 10d1 0x10d1
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10d0 10d0 seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10d1 10d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1187
seq_br_type 5 Call True
seq_branch_adr 1187 BIT_33_34_36_ERROR
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3e TR04:1e
typ_frame 4
10d2 10d2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10d4
seq_br_type 0 Branch False
seq_branch_adr 10d4 0x10d4
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10d3 10d3 seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10d4 10d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1187
seq_br_type 5 Call True
seq_branch_adr 1187 BIT_33_34_36_ERROR
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3d TR04:1d
typ_frame 4
10d5 10d5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10d7
seq_br_type 0 Branch False
seq_branch_adr 10d7 0x10d7
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10d6 10d6 seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10d7 10d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1187
seq_br_type 5 Call True
seq_branch_adr 1187 BIT_33_34_36_ERROR
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 3b TR04:1b
typ_frame 4
10d8 10d8 seq_br_type 4 Call False; Flow C cc=False 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 20 TR10:00
typ_frame 10
10d9 10d9 seq_br_type 1 Branch True; Flow J cc=True 0x10db
seq_branch_adr 10db 0x10db
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 20 TR10:00
typ_frame 10
10da 10da seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10db 10db seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10dd
seq_br_type 0 Branch False
seq_branch_adr 10dd 0x10dd
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 22 TR10:02
typ_frame 10
10dc 10dc seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10dd 10dd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1187
seq_br_type 5 Call True
seq_branch_adr 1187 BIT_33_34_36_ERROR
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 22 TR10:02
typ_frame 10
10de 10de seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10e0
seq_br_type 0 Branch False
seq_branch_adr 10e0 0x10e0
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 26 TR16:06
typ_frame 16
10df 10df seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10e0 10e0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10e2
seq_br_type 0 Branch False
seq_branch_adr 10e2 0x10e2
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 27 TR16:07
typ_frame 16
10e1 10e1 seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10e2 10e2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x10e4
seq_br_type 0 Branch False
seq_branch_adr 10e4 0x10e4
seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late)
typ_b_adr 28 TR16:08
typ_frame 16
10e3 10e3 seq_br_type 7 Unconditional Call; Flow C 0x1187
seq_branch_adr 1187 BIT_33_34_36_ERROR
10e4 10e4 val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
10e5 10e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 4 CHECK_CLASS_A_LIT
10e6 10e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1189
seq_br_type 5 Call True
seq_branch_adr 1189 CARRY_IN_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 22 VR10:02
val_alu_func 7 INC_A
val_frame 10
10e7 10e7 seq_br_type 1 Branch True; Flow J cc=True 0x10e9
seq_branch_adr 10e9 0x10e9
seq_cond_sel 20 TYP.ALU_CARRY(late)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 22 TR10:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 4 CHECK_CLASS_A_LIT
10e8 10e8 seq_br_type 7 Unconditional Call; Flow C 0x1189
seq_branch_adr 1189 CARRY_IN_ERROR
10e9 10e9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x10eb
seq_br_type 1 Branch True
seq_branch_adr 10eb 0x10eb
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
10ea 10ea seq_br_type 7 Unconditional Call; Flow C 0x1189
seq_branch_adr 1189 CARRY_IN_ERROR
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
10eb 10eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1165
seq_br_type 5 Call True
seq_branch_adr 1165 COND_ERROR
seq_cond_sel 20 TYP.ALU_CARRY(late)
seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand 4 CHECK_CLASS_A_LIT
10ec 10ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1189
seq_br_type 5 Call True
seq_branch_adr 1189 CARRY_IN_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
10ed 10ed typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
10ee 10ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
10ef 10ef typ_a_adr 22 TR10:02
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
10f0 10f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
10f1 10f1 typ_a_adr 20 TR11:00
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10f2 10f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10f3 10f3 typ_a_adr 21 TR11:01
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10f4 10f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10f5 10f5 typ_a_adr 22 TR11:02
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10f6 10f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10f7 10f7 typ_a_adr 23 TR11:03
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10f8 10f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10f9 10f9 typ_a_adr 24 TR11:04
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10fa 10fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10fb 10fb typ_a_adr 25 TR11:05
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
10fc 10fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
10fd 10fd typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
10fe 10fe typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
10ff 10ff typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
1100 1100 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1173
seq_br_type 5 Call True
seq_branch_adr 1173 CMUX_PASS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1101 1101 seq_b_timing 0 Early Condition; Flow J cc=False 0x10ff
seq_br_type 0 Branch False
seq_branch_adr 10ff 0x10ff
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1102 1102 seq_br_type 3 Unconditional Branch; Flow J 0x1103
seq_branch_adr 1103 0x1103
1103 1103 ioc_load_wdr 0
typ_b_adr 20 TR10:00
typ_frame 10
1104 1104 typ_c_adr 3e GP01
1105 1105 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1106 1106 ioc_load_wdr 0
typ_b_adr 22 TR10:02
typ_frame 10
1107 1107 typ_c_adr 3e GP01
1108 1108 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1109 1109 ioc_load_wdr 0
typ_b_adr 20 TR11:00
typ_frame 11
110a 110a typ_c_adr 3e GP01
110b 110b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
110c 110c ioc_load_wdr 0
typ_b_adr 21 TR11:01
typ_frame 11
110d 110d typ_c_adr 3e GP01
110e 110e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
110f 110f ioc_load_wdr 0
typ_b_adr 22 TR11:02
typ_frame 11
1110 1110 typ_c_adr 3e GP01
1111 1111 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1112 1112 ioc_load_wdr 0
typ_b_adr 23 TR11:03
typ_frame 11
1113 1113 typ_c_adr 3e GP01
1114 1114 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1115 1115 ioc_load_wdr 0
typ_b_adr 24 TR11:04
typ_frame 11
1116 1116 typ_c_adr 3e GP01
1117 1117 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1118 1118 ioc_load_wdr 0
typ_b_adr 25 TR11:05
typ_frame 11
1119 1119 typ_c_adr 3e GP01
111a 111a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
111b 111b typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
111c 111c typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
111d 111d ioc_load_wdr 0
typ_b_adr 05 GP05
111e 111e typ_c_adr 3e GP01
111f 111f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1175
seq_br_type 5 Call True
seq_branch_adr 1175 CMUX_WDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1120 1120 seq_b_timing 0 Early Condition; Flow J cc=False 0x111d
seq_br_type 0 Branch False
seq_branch_adr 111d 0x111d
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1121 1121 <default>
1122 1122 seq_br_type 3 Unconditional Branch; Flow J 0x1123
seq_branch_adr 1123 0x1123
1123 1123 ioc_fiubs 2 typ
typ_a_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 10
1124 1124 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1125 1125 ioc_fiubs 2 typ
typ_a_adr 22 TR10:02
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 10
1126 1126 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR10:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1127 1127 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
1128 1128 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR11:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1129 1129 ioc_fiubs 2 typ
typ_a_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
112a 112a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR11:01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
112b 112b ioc_fiubs 2 typ
typ_a_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
112c 112c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR11:02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
112d 112d ioc_fiubs 2 typ
typ_a_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
112e 112e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR11:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
112f 112f ioc_fiubs 2 typ
typ_a_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
1130 1130 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR11:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1131 1131 ioc_fiubs 2 typ
typ_a_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
typ_frame 11
1132 1132 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR11:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
1133 1133 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
1134 1134 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1135 1135 ioc_fiubs 2 typ
typ_a_adr 05 GP05
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
1136 1136 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1177
seq_br_type 5 Call True
seq_branch_adr 1177 CMUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1137 1137 seq_b_timing 0 Early Condition; Flow J cc=False 0x1135
seq_br_type 0 Branch False
seq_branch_adr 1135 0x1135
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1138 1138 ioc_fiubs 2 typ
typ_a_adr 22 TR10:02
typ_alu_func 1a PASS_B
typ_b_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 10
typ_rand c WRITE_OUTER_FRAME
1139 1139 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
113a 113a ioc_fiubs 2 typ
typ_a_adr 20 TR10:00
typ_alu_func 1a PASS_B
typ_b_adr 22 TR10:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 10
typ_rand c WRITE_OUTER_FRAME
113b 113b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR13:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
113c 113c ioc_fiubs 2 typ
typ_a_adr 22 TR11:02
typ_alu_func 1a PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
113d 113d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR12:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
113e 113e ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
113f 113f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1140 1140 ioc_fiubs 2 typ
typ_a_adr 22 TR11:02
typ_alu_func 1a PASS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1141 1141 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3a TR12:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
1142 1142 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1143 1143 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR13:13
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1144 1144 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1145 1145 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TR13:0f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1146 1146 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1147 1147 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR13:16
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1148 1148 ioc_fiubs 2 typ
typ_a_adr 2c TR17:0c
typ_alu_func 1a PASS_B
typ_b_adr 27 TR17:07
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 17
typ_rand c WRITE_OUTER_FRAME
1149 1149 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR17:08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
114a 114a ioc_fiubs 2 typ
typ_a_adr 29 TR17:09
typ_alu_func 1a PASS_B
typ_b_adr 26 TR17:06
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_c_source 0 FIU_BUS
typ_frame 17
typ_rand c WRITE_OUTER_FRAME
114b 114b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR17:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
114c 114c ioc_fiubs 2 typ
typ_a_adr 22 TR10:02
typ_alu_func 1a PASS_B
typ_b_adr 20 TR10:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand c WRITE_OUTER_FRAME
114d 114d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR13:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
114e 114e ioc_fiubs 2 typ
typ_a_adr 20 TR10:00
typ_alu_func 1a PASS_B
typ_b_adr 22 TR10:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
typ_rand c WRITE_OUTER_FRAME
114f 114f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
1150 1150 ioc_fiubs 2 typ
typ_a_adr 22 TR11:02
typ_alu_func 1a PASS_B
typ_b_adr 20 TR11:00
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1151 1151 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2e TR13:0e
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 13
1152 1152 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 22 TR11:02
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1153 1153 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR12:18
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 12
1154 1154 ioc_fiubs 2 typ
typ_a_adr 22 TR11:02
typ_alu_func 1a PASS_B
typ_b_adr 21 TR11:01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1155 1155 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR14:03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1156 1156 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 23 TR11:03
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1157 1157 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR14:04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1158 1158 ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 24 TR11:04
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
1159 1159 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR14:05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
115a 115a ioc_fiubs 2 typ
typ_a_adr 20 TR11:00
typ_alu_func 1a PASS_B
typ_b_adr 25 TR11:05
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand c WRITE_OUTER_FRAME
115b 115b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118d
seq_br_type 5 Call True
seq_branch_adr 118d FIU_LOW_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR14:06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
115c 115c ioc_fiubs 2 typ
typ_a_adr 2c TR17:0c
typ_alu_func 1a PASS_B
typ_b_adr 2a TR17:0a
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 17
typ_rand c WRITE_OUTER_FRAME
115d 115d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR17:0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
115e 115e ioc_fiubs 2 typ
typ_a_adr 29 TR17:09
typ_alu_func 1a PASS_B
typ_b_adr 2d TR17:0d
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 17
typ_rand c WRITE_OUTER_FRAME
115f 115f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118b
seq_br_type 5 Call True
seq_branch_adr 118b FIU_HIGH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
1160 1160 <default>
1161 1161 typ_a_adr 25 TR10:05
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 10
1162 1162 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x118f
seq_br_type 5 Call True
seq_branch_adr 118f REG_A_B_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1163 1163 seq_b_timing 0 Early Condition; Flow J cc=False 0x1162
seq_br_type 0 Branch False
seq_branch_adr 1162 0x1162
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
1164 1164 seq_br_type a Unconditional Return; Flow R
1165 ; --------------------------------------------------------------------------------------
1165 ; Comes from:
1165 ; 0c00 C True from color 0x0c00
1165 ; 0c02 C from color 0x0c00
1165 ; 0c04 C from color 0x0c00
1165 ; 0c05 C False from color 0x0c00
1165 ; 0c07 C True from color 0x0c00
1165 ; 0c0a C from color 0x0c00
1165 ; 0c0d C from color 0x0c00
1165 ; 0c0f C False from color 0x0c00
1165 ; 0c12 C from color 0x0c00
1165 ; 0c13 C False from color 0x0c00
1165 ; 0c15 C True from color 0x0c00
1165 ; 0c17 C from color 0x0c00
1165 ; 0c18 C True from color 0x0c00
1165 ; 0c1a C from color 0x0c00
1165 ; 0c1c C from color 0x0c00
1165 ; 0c1d C False from color 0x0c00
1165 ; 0c1f C from color 0x0c00
1165 ; 0c20 C False from color 0x0c00
1165 ; 0c22 C from color 0x0c00
1165 ; 0c23 C False from color 0x0c00
1165 ; 0c24 C True from color 0x0c00
1165 ; 0c26 C from color 0x0c00
1165 ; 0c27 C True from color 0x0c00
1165 ; 0c29 C from color 0x0c00
1165 ; 0c2a C True from color 0x0c00
1165 ; 0c2c C from color 0x0c00
1165 ; 0c2d C True from color 0x0c00
1165 ; 0c2f C from color 0x0c00
1165 ; 0c31 C from color 0x0c00
1165 ; 0c32 C False from color 0x0c00
1165 ; 0c34 C from color 0x0c00
1165 ; 0c35 C False from color 0x0c00
1165 ; 0c37 C from color 0x0c00
1165 ; 0c38 C False from color 0x0c00
1165 ; 0c39 C True from color 0x0c00
1165 ; 0c3b C from color 0x0c00
1165 ; 0c3d C from color 0x0c00
1165 ; 0c3e C False from color 0x0c00
1165 ; 0c3f C True from color 0x0c00
1165 ; 0c41 C from color 0x0c00
1165 ; 0c43 C from color 0x0c00
1165 ; 0c44 C False from color 0x0c00
1165 ; 0c45 C True from color 0x0c00
1165 ; 0c47 C from color 0x0c00
1165 ; 0c49 C from color 0x0c00
1165 ; 0c4a C False from color 0x0c00
1165 ; 0c4b C True from color 0x0c00
1165 ; 0c4d C from color 0x0c00
1165 ; 0c4f C from color 0x0c00
1165 ; 0c50 C False from color 0x0c00
1165 ; 0c51 C True from color 0x0c00
1165 ; 0c53 C from color 0x0c00
1165 ; 0c55 C from color 0x0c00
1165 ; 0c56 C False from color 0x0c00
1165 ; 0c57 C True from color 0x0c00
1165 ; 0c59 C from color 0x0c00
1165 ; 0c5b C from color 0x0c00
1165 ; 0c5c C False from color 0x0c00
1165 ; 0c5d C True from color 0x0c00
1165 ; 0c5f C from color 0x0c00
1165 ; 0c61 C from color 0x0c00
1165 ; 0c62 C False from color 0x0c00
1165 ; 0c63 C True from color 0x0c00
1165 ; 0c65 C from color 0x0c00
1165 ; 0c67 C from color 0x0c00
1165 ; 0c68 C False from color 0x0c00
1165 ; 0c69 C True from color 0x0c00
1165 ; 0c6b C from color 0x0c00
1165 ; 0c6d C from color 0x0c00
1165 ; 0c6e C False from color 0x0c00
1165 ; 0c6f C True from color 0x0c00
1165 ; 0c71 C from color 0x0c00
1165 ; 0c73 C from color 0x0c00
1165 ; 0c74 C False from color 0x0c00
1165 ; 0c75 C True from color 0x0c00
1165 ; 0c77 C from color 0x0c00
1165 ; 0c79 C from color 0x0c00
1165 ; 0c7a C False from color 0x0c00
1165 ; 0c7b C True from color 0x0c00
1165 ; 0c7d C from color 0x0c00
1165 ; 0c7f C from color 0x0c00
1165 ; 0c80 C True from color 0x0c00
1165 ; 0c82 C from color 0x0c00
1165 ; 0c83 C True from color 0x0c00
1165 ; 0c84 C False from color 0x0c00
1165 ; 0c86 C from color 0x0c00
1165 ; 0c88 C from color 0x0c00
1165 ; 0c89 C True from color 0x0c00
1165 ; 0c8b C from color 0x0c00
1165 ; 0c8c C True from color 0x0c00
1165 ; 0c8d C False from color 0x0c00
1165 ; 0c8f C from color 0x0c00
1165 ; 0c91 C from color 0x0c00
1165 ; 0c92 C True from color 0x0c00
1165 ; 0c94 C from color 0x0c00
1165 ; 0c95 C True from color 0x0c00
1165 ; 0c96 C False from color 0x0c00
1165 ; 0c98 C from color 0x0c00
1165 ; 0c9a C from color 0x0c00
1165 ; 0c9b C True from color 0x0c00
1165 ; 0c9d C from color 0x0c00
1165 ; 0c9e C True from color 0x0c00
1165 ; 0c9f C False from color 0x0c00
1165 ; 0ca1 C from color 0x0c00
1165 ; 0ca2 C True from color 0x0c00
1165 ; 0ca4 C from color 0x0c00
1165 ; 0ca6 C from color 0x0c00
1165 ; 0ca7 C False from color 0x0c00
1165 ; 0ca8 C True from color 0x0c00
1165 ; 0caa C from color 0x0c00
1165 ; 0cac C from color 0x0c00
1165 ; 0cad C False from color 0x0c00
1165 ; 0cae C False from color 0x0c00
1165 ; 0cb0 C from color 0x0c00
1165 ; 0cb2 C from color 0x0c00
1165 ; 0cb3 C True from color 0x0c00
1165 ; 0cb4 C False from color 0x0c00
1165 ; 0cb6 C from color 0x0c00
1165 ; 0cb8 C from color 0x0c00
1165 ; 0cb9 C True from color 0x0c00
1165 ; 0cbb C from color 0x0c00
1165 ; 0cbc C False from color 0x0c00
1165 ; 0cbd C True from color 0x0c00
1165 ; 0cbf C from color 0x0c00
1165 ; 0cc1 C from color 0x0c00
1165 ; 0cc2 C False from color 0x0c00
1165 ; 0cc3 C True from color 0x0c00
1165 ; 0cc5 C from color 0x0c00
1165 ; 0cc7 C from color 0x0c00
1165 ; 0cc8 C False from color 0x0c00
1165 ; 0cca C from color 0x0c00
1165 ; 0ccb C True from color 0x0c00
1165 ; 0ccc C False from color 0x0c00
1165 ; 0cce C from color 0x0c00
1165 ; 0cd0 C from color 0x0c00
1165 ; 0cd1 C True from color 0x0c00
1165 ; 0cd2 C False from color 0x0c00
1165 ; 0cd4 C from color 0x0c00
1165 ; 0cd6 C from color 0x0c00
1165 ; 0cd7 C True from color 0x0c00
1165 ; 0cd8 C False from color 0x0c00
1165 ; 0cda C from color 0x0c00
1165 ; 0cdc C from color 0x0c00
1165 ; 0cdd C True from color 0x0c00
1165 ; 0cde C False from color 0x0c00
1165 ; 0ce0 C from color 0x0c00
1165 ; 0ce2 C from color 0x0c00
1165 ; 0ce3 C True from color 0x0c00
1165 ; 0ce4 C False from color 0x0c00
1165 ; 0ce6 C from color 0x0c00
1165 ; 0ce7 C False from color 0x0c00
1165 ; 0ce9 C from color 0x0c00
1165 ; 0cea C False from color 0x0c00
1165 ; 0cec C from color 0x0c00
1165 ; 0cee C from color 0x0c00
1165 ; 0cef C True from color 0x0c00
1165 ; 0cf0 C False from color 0x0c00
1165 ; 0cf2 C from color 0x0c00
1165 ; 0cf4 C from color 0x0c00
1165 ; 0cf5 C True from color 0x0c00
1165 ; 0cf6 C False from color 0x0c00
1165 ; 0cf8 C from color 0x0c00
1165 ; 0cfa C from color 0x0c00
1165 ; 0cfb C True from color 0x0c00
1165 ; 0cfc C False from color 0x0c00
1165 ; 0cfe C from color 0x0c00
1165 ; 0d00 C from color 0x0c00
1165 ; 0d01 C True from color 0x0c00
1165 ; 0d02 C False from color 0x0c00
1165 ; 0d04 C from color 0x0c00
1165 ; 0d06 C from color 0x0c00
1165 ; 0d07 C True from color 0x0c00
1165 ; 0d08 C False from color 0x0c00
1165 ; 0d0a C from color 0x0c00
1165 ; 0d0b C False from color 0x0c00
1165 ; 0d0d C from color 0x0c00
1165 ; 0d0e C False from color 0x0c00
1165 ; 0d10 C from color 0x0c00
1165 ; 10e5 C True from color 0x0c00
1165 ; 10eb C True from color 0x0c00
1165 ; --------------------------------------------------------------------------------------
1165 COND_ERROR:
1165 1165 <halt> ; Flow R
1166 1166 seq_br_type a Unconditional Return; Flow R
1167 ; --------------------------------------------------------------------------------------
1167 ; Comes from:
1167 ; 0d13 C True from color 0x0c00
1167 ; 0d15 C False from color 0x0c00
1167 ; 0d16 C True from color 0x0c00
1167 ; 0d17 C True from color 0x0c00
1167 ; 0d19 C True from color 0x0c00
1167 ; 0d1b C True from color 0x0c00
1167 ; 0d1c C True from color 0x0c00
1167 ; 0d1d C True from color 0x0c00
1167 ; 0d20 C True from color 0x0c00
1167 ; 0d21 C True from color 0x0c00
1167 ; 0d25 C True from color 0x0c00
1167 ; 0d27 C True from color 0x0c00
1167 ; 0d29 C True from color 0x0c00
1167 ; 0d2b C True from color 0x0c00
1167 ; --------------------------------------------------------------------------------------
1167 REG_FILE_ERROR:
1167 1167 <halt> ; Flow R
1168 1168 seq_br_type a Unconditional Return; Flow R
1169 ; --------------------------------------------------------------------------------------
1169 ; Comes from:
1169 ; 0d2e C True from color 0x0c00
1169 ; 0d30 C True from color 0x0c00
1169 ; 0d32 C True from color 0x0c00
1169 ; 0d34 C True from color 0x0c00
1169 ; 0d36 C True from color 0x0c00
1169 ; 0d38 C True from color 0x0c00
1169 ; 0d3a C True from color 0x0c00
1169 ; 0d3c C True from color 0x0c00
1169 ; 0d3e C True from color 0x0c00
1169 ; 0d40 C True from color 0x0c00
1169 ; 0d42 C True from color 0x0c00
1169 ; 0d44 C True from color 0x0c00
1169 ; 0d46 C True from color 0x0c00
1169 ; 0d48 C True from color 0x0c00
1169 ; 0d4a C True from color 0x0c00
1169 ; 0d4c C True from color 0x0c00
1169 ; 0d4e C True from color 0x0c00
1169 ; 0d50 C True from color 0x0c00
1169 ; 0d52 C True from color 0x0c00
1169 ; 0d54 C True from color 0x0c00
1169 ; 0d56 C True from color 0x0c00
1169 ; 0d58 C True from color 0x0c00
1169 ; 0d5a C True from color 0x0c00
1169 ; 0d5c C True from color 0x0c00
1169 ; 0d5e C True from color 0x0c00
1169 ; 0d60 C True from color 0x0c00
1169 ; 0d62 C True from color 0x0c00
1169 ; 0d64 C True from color 0x0c00
1169 ; 0d66 C True from color 0x0c00
1169 ; 0d68 C True from color 0x0c00
1169 ; 0d6a C True from color 0x0c00
1169 ; 0d6c C True from color 0x0c00
1169 ; 0d6e C True from color 0x0c00
1169 ; 0d70 C True from color 0x0c00
1169 ; 0d72 C True from color 0x0c00
1169 ; 0d74 C True from color 0x0c00
1169 ; 0d76 C True from color 0x0c00
1169 ; 0d78 C True from color 0x0c00
1169 ; 0d7a C True from color 0x0c00
1169 ; 0d7c C True from color 0x0c00
1169 ; 0d7e C True from color 0x0c00
1169 ; 0d80 C True from color 0x0c00
1169 ; 0d82 C True from color 0x0c00
1169 ; 0d84 C True from color 0x0c00
1169 ; 0d86 C True from color 0x0c00
1169 ; 0d88 C True from color 0x0c00
1169 ; 0d8a C True from color 0x0c00
1169 ; 0d8c C True from color 0x0c00
1169 ; 0d8e C True from color 0x0c00
1169 ; 0d90 C True from color 0x0c00
1169 ; 0d92 C True from color 0x0c00
1169 ; 0d94 C True from color 0x0c00
1169 ; 0d96 C True from color 0x0c00
1169 ; 0d98 C True from color 0x0c00
1169 ; 0d9a C True from color 0x0c00
1169 ; 0d9c C True from color 0x0c00
1169 ; 0d9e C True from color 0x0c00
1169 ; 0da0 C True from color 0x0c00
1169 ; 0da2 C True from color 0x0c00
1169 ; 0da4 C True from color 0x0c00
1169 ; 0da6 C True from color 0x0c00
1169 ; 0da8 C True from color 0x0c00
1169 ; 0daa C True from color 0x0c00
1169 ; 0dac C True from color 0x0c00
1169 ; 0dae C True from color 0x0c00
1169 ; 0db0 C True from color 0x0c00
1169 ; 0db2 C True from color 0x0c00
1169 ; 0db4 C True from color 0x0c00
1169 ; 0db6 C True from color 0x0c00
1169 ; 0db8 C True from color 0x0c00
1169 ; 0dba C True from color 0x0c00
1169 ; 0dbc C True from color 0x0c00
1169 ; 0dbe C True from color 0x0c00
1169 ; 0dc0 C True from color 0x0c00
1169 ; 0dc2 C True from color 0x0c00
1169 ; 0dc4 C True from color 0x0c00
1169 ; 0dc6 C True from color 0x0c00
1169 ; 0dc8 C True from color 0x0c00
1169 ; 0dca C True from color 0x0c00
1169 ; 0dcc C True from color 0x0c00
1169 ; 0dce C True from color 0x0c00
1169 ; 0dd0 C True from color 0x0c00
1169 ; 0dd2 C True from color 0x0c00
1169 ; 0dd4 C True from color 0x0c00
1169 ; 0dd6 C True from color 0x0c00
1169 ; 0dd8 C True from color 0x0c00
1169 ; 0dda C True from color 0x0c00
1169 ; 0ddc C True from color 0x0c00
1169 ; 0dde C True from color 0x0c00
1169 ; 0de0 C True from color 0x0c00
1169 ; 0de2 C True from color 0x0c00
1169 ; 0de4 C True from color 0x0c00
1169 ; 0de6 C True from color 0x0c00
1169 ; 0de8 C True from color 0x0c00
1169 ; 0dea C True from color 0x0c00
1169 ; 0dec C True from color 0x0c00
1169 ; 0dee C True from color 0x0c00
1169 ; 0df0 C True from color 0x0c00
1169 ; 0df2 C True from color 0x0c00
1169 ; 0df4 C True from color 0x0c00
1169 ; 0df6 C True from color 0x0c00
1169 ; 0df8 C True from color 0x0c00
1169 ; 0dfa C True from color 0x0c00
1169 ; 0dfc C True from color 0x0c00
1169 ; 0dfe C True from color 0x0c00
1169 ; 0e00 C True from color 0x0c00
1169 ; --------------------------------------------------------------------------------------
1169 LOGICAL_ALU_ERROR:
1169 1169 <halt> ; Flow R
116a 116a seq_br_type a Unconditional Return; Flow R
116b ; --------------------------------------------------------------------------------------
116b ; Comes from:
116b ; 0e01 C True from color 0x0c00
116b ; 0e02 C True from color 0x0c00
116b ; 0e03 C True from color 0x0c00
116b ; 0e04 C False from color 0x0c00
116b ; 0e05 C True from color 0x0c00
116b ; 0e06 C True from color 0x0c00
116b ; 0e07 C True from color 0x0c00
116b ; 0e08 C False from color 0x0c00
116b ; 0e09 C True from color 0x0c00
116b ; 0e0a C True from color 0x0c00
116b ; 0e0b C True from color 0x0c00
116b ; 0e0c C True from color 0x0c00
116b ; 0e0d C True from color 0x0c00
116b ; 0e0e C True from color 0x0c00
116b ; 0e0f C True from color 0x0c00
116b ; 0e10 C True from color 0x0c00
116b ; 0e11 C True from color 0x0c00
116b ; 0e12 C True from color 0x0c00
116b ; 0e13 C True from color 0x0c00
116b ; 0e14 C True from color 0x0c00
116b ; 0e15 C True from color 0x0c00
116b ; 0e16 C True from color 0x0c00
116b ; 0e17 C True from color 0x0c00
116b ; 0e18 C True from color 0x0c00
116b ; 0e19 C True from color 0x0c00
116b ; 0e1a C True from color 0x0c00
116b ; 0e1b C True from color 0x0c00
116b ; 0e1c C True from color 0x0c00
116b ; 0e1d C True from color 0x0c00
116b ; 0e1e C True from color 0x0c00
116b ; 0e1f C False from color 0x0c00
116b ; 0e20 C True from color 0x0c00
116b ; 0e21 C True from color 0x0c00
116b ; 0e22 C False from color 0x0c00
116b ; 0e23 C False from color 0x0c00
116b ; 0e24 C True from color 0x0c00
116b ; 0e25 C False from color 0x0c00
116b ; 0e26 C True from color 0x0c00
116b ; 0e27 C True from color 0x0c00
116b ; 0e28 C False from color 0x0c00
116b ; 0e29 C True from color 0x0c00
116b ; 0e2a C True from color 0x0c00
116b ; 0e2b C False from color 0x0c00
116b ; 0e2c C True from color 0x0c00
116b ; 0e2d C True from color 0x0c00
116b ; 0e2e C False from color 0x0c00
116b ; 0e2f C True from color 0x0c00
116b ; 0e30 C True from color 0x0c00
116b ; 0e31 C False from color 0x0c00
116b ; 0e32 C True from color 0x0c00
116b ; 0e33 C True from color 0x0c00
116b ; 0e34 C False from color 0x0c00
116b ; 0e35 C True from color 0x0c00
116b ; 0e36 C True from color 0x0c00
116b ; 0e37 C True from color 0x0c00
116b ; 0e38 C True from color 0x0c00
116b ; 0e39 C False from color 0x0c00
116b ; 0e3a C True from color 0x0c00
116b ; 0e3b C True from color 0x0c00
116b ; 0e3c C True from color 0x0c00
116b ; 0e3d C True from color 0x0c00
116b ; 0e3e C True from color 0x0c00
116b ; 0e3f C False from color 0x0c00
116b ; 0e40 C True from color 0x0c00
116b ; 0e41 C False from color 0x0c00
116b ; 0e42 C True from color 0x0c00
116b ; 0e43 C True from color 0x0c00
116b ; 0e44 C True from color 0x0c00
116b ; 0e45 C False from color 0x0c00
116b ; 0e46 C True from color 0x0c00
116b ; 0e47 C True from color 0x0c00
116b ; 0e48 C True from color 0x0c00
116b ; 0e49 C True from color 0x0c00
116b ; 0e4a C True from color 0x0c00
116b ; 0e4b C False from color 0x0c00
116b ; 0e4c C True from color 0x0c00
116b ; 0e4d C False from color 0x0c00
116b ; 0e4e C True from color 0x0c00
116b ; 0e4f C True from color 0x0c00
116b ; 0e50 C False from color 0x0c00
116b ; 0e51 C True from color 0x0c00
116b ; 0e52 C True from color 0x0c00
116b ; 0e53 C False from color 0x0c00
116b ; 0e54 C True from color 0x0c00
116b ; 0e55 C True from color 0x0c00
116b ; 0e56 C False from color 0x0c00
116b ; 0e57 C True from color 0x0c00
116b ; 0e58 C True from color 0x0c00
116b ; 0e59 C False from color 0x0c00
116b ; 0e5a C True from color 0x0c00
116b ; 0e5b C False from color 0x0c00
116b ; 0e5c C True from color 0x0c00
116b ; 0e5d C True from color 0x0c00
116b ; 0e5e C False from color 0x0c00
116b ; 0e5f C True from color 0x0c00
116b ; 0e60 C True from color 0x0c00
116b ; 0e61 C True from color 0x0c00
116b ; 0e62 C True from color 0x0c00
116b ; 0e63 C True from color 0x0c00
116b ; 0e64 C True from color 0x0c00
116b ; 0e65 C True from color 0x0c00
116b ; 0e66 C True from color 0x0c00
116b ; 0e67 C True from color 0x0c00
116b ; 0e68 C True from color 0x0c00
116b ; 0e69 C True from color 0x0c00
116b ; 0e6a C True from color 0x0c00
116b ; 0e6b C True from color 0x0c00
116b ; 0e6c C True from color 0x0c00
116b ; 0e6d C False from color 0x0c00
116b ; 0e6e C True from color 0x0c00
116b ; 0e6f C True from color 0x0c00
116b ; 0e70 C False from color 0x0c00
116b ; 0e71 C True from color 0x0c00
116b ; 0e72 C True from color 0x0c00
116b ; 0e73 C False from color 0x0c00
116b ; 0e74 C False from color 0x0c00
116b ; 0e75 C True from color 0x0c00
116b ; 0e76 C False from color 0x0c00
116b ; 0e77 C False from color 0x0c00
116b ; 0e78 C True from color 0x0c00
116b ; 0e79 C False from color 0x0c00
116b ; 0e7a C False from color 0x0c00
116b ; 0e7b C True from color 0x0c00
116b ; 0e7c C False from color 0x0c00
116b ; 0e7d C False from color 0x0c00
116b ; 0e7e C True from color 0x0c00
116b ; 0e7f C True from color 0x0c00
116b ; 0e80 C False from color 0x0c00
116b ; 0e81 C True from color 0x0c00
116b ; 0e82 C True from color 0x0c00
116b ; 0e83 C False from color 0x0c00
116b ; 0e84 C True from color 0x0c00
116b ; 0e85 C True from color 0x0c00
116b ; 0e86 C False from color 0x0c00
116b ; 0e87 C True from color 0x0c00
116b ; 0e88 C True from color 0x0c00
116b ; 0e89 C False from color 0x0c00
116b ; 0e8a C True from color 0x0c00
116b ; 0e8b C False from color 0x0c00
116b ; 0e8c C True from color 0x0c00
116b ; 0e8d C True from color 0x0c00
116b ; 0e8e C False from color 0x0c00
116b ; 0e8f C True from color 0x0c00
116b ; 0e90 C True from color 0x0c00
116b ; 0e91 C True from color 0x0c00
116b ; 0e92 C True from color 0x0c00
116b ; 0e93 C True from color 0x0c00
116b ; 0e94 C True from color 0x0c00
116b ; 0e95 C True from color 0x0c00
116b ; 0e96 C True from color 0x0c00
116b ; 0e97 C True from color 0x0c00
116b ; 0e98 C True from color 0x0c00
116b ; 0e99 C True from color 0x0c00
116b ; 0e9a C True from color 0x0c00
116b ; 0e9b C True from color 0x0c00
116b ; 0e9c C True from color 0x0c00
116b ; 0e9d C False from color 0x0c00
116b ; 0e9e C True from color 0x0c00
116b ; 0e9f C True from color 0x0c00
116b ; 0ea0 C False from color 0x0c00
116b ; 0ea1 C True from color 0x0c00
116b ; 0ea2 C True from color 0x0c00
116b ; 0ea3 C False from color 0x0c00
116b ; 0ea4 C False from color 0x0c00
116b ; 0ea5 C True from color 0x0c00
116b ; 0ea6 C False from color 0x0c00
116b ; 0ea7 C False from color 0x0c00
116b ; 0ea8 C True from color 0x0c00
116b ; 0ea9 C False from color 0x0c00
116b ; 0eaa C False from color 0x0c00
116b ; 0eab C True from color 0x0c00
116b ; 0eac C False from color 0x0c00
116b ; 0ead C False from color 0x0c00
116b ; 0eae C True from color 0x0c00
116b ; 0eaf C True from color 0x0c00
116b ; 0eb0 C True from color 0x0c00
116b ; 0eb1 C True from color 0x0c00
116b ; 0eb2 C False from color 0x0c00
116b ; 0eb3 C True from color 0x0c00
116b ; 0eb4 C True from color 0x0c00
116b ; 0eb5 C False from color 0x0c00
116b ; 0eb6 C True from color 0x0c00
116b ; 0eb7 C True from color 0x0c00
116b ; 0eb8 C True from color 0x0c00
116b ; 0eb9 C True from color 0x0c00
116b ; 0eba C True from color 0x0c00
116b ; 0ebb C False from color 0x0c00
116b ; 0ebc C False from color 0x0c00
116b ; 0ebd C True from color 0x0c00
116b ; 0ebe C True from color 0x0c00
116b ; 0ebf C False from color 0x0c00
116b ; 0ec0 C True from color 0x0c00
116b ; 0ec1 C False from color 0x0c00
116b ; 0ec2 C False from color 0x0c00
116b ; 0ec3 C True from color 0x0c00
116b ; 0ec4 C True from color 0x0c00
116b ; 0ec5 C False from color 0x0c00
116b ; 0ec6 C True from color 0x0c00
116b ; 0ec7 C True from color 0x0c00
116b ; 0ec8 C False from color 0x0c00
116b ; 0ec9 C True from color 0x0c00
116b ; 0eca C False from color 0x0c00
116b ; 0ecb C False from color 0x0c00
116b ; 0ecc C True from color 0x0c00
116b ; 0ecd C True from color 0x0c00
116b ; 0ece C False from color 0x0c00
116b ; 0ecf C True from color 0x0c00
116b ; 0ed0 C False from color 0x0c00
116b ; 0ed1 C False from color 0x0c00
116b ; 0ed2 C True from color 0x0c00
116b ; 0ed3 C False from color 0x0c00
116b ; 0ed4 C True from color 0x0c00
116b ; 0ed5 C True from color 0x0c00
116b ; 0ed6 C True from color 0x0c00
116b ; 0ed7 C True from color 0x0c00
116b ; 0ed8 C True from color 0x0c00
116b ; 0ed9 C True from color 0x0c00
116b ; 0eda C True from color 0x0c00
116b ; 0edb C True from color 0x0c00
116b ; 0edc C False from color 0x0c00
116b ; 0edd C True from color 0x0c00
116b ; 0ede C True from color 0x0c00
116b ; 0edf C True from color 0x0c00
116b ; 0ee0 C True from color 0x0c00
116b ; 0ee1 C True from color 0x0c00
116b ; 0ee2 C False from color 0x0c00
116b ; 0ee3 C True from color 0x0c00
116b ; 0ee4 C True from color 0x0c00
116b ; 0ee5 C False from color 0x0c00
116b ; 0ee6 C True from color 0x0c00
116b ; 0ee7 C True from color 0x0c00
116b ; 0ee8 C True from color 0x0c00
116b ; 0ee9 C True from color 0x0c00
116b ; 0eea C True from color 0x0c00
116b ; 0eeb C False from color 0x0c00
116b ; 0eec C False from color 0x0c00
116b ; 0eed C True from color 0x0c00
116b ; 0eee C True from color 0x0c00
116b ; 0eef C False from color 0x0c00
116b ; 0ef0 C True from color 0x0c00
116b ; 0ef1 C False from color 0x0c00
116b ; 0ef2 C False from color 0x0c00
116b ; 0ef3 C True from color 0x0c00
116b ; 0ef4 C True from color 0x0c00
116b ; 0ef5 C False from color 0x0c00
116b ; 0ef6 C True from color 0x0c00
116b ; 0ef7 C True from color 0x0c00
116b ; 0ef8 C False from color 0x0c00
116b ; 0ef9 C True from color 0x0c00
116b ; 0efa C False from color 0x0c00
116b ; 0efb C False from color 0x0c00
116b ; 0efc C True from color 0x0c00
116b ; 0efd C True from color 0x0c00
116b ; 0efe C False from color 0x0c00
116b ; 0eff C True from color 0x0c00
116b ; 0f00 C False from color 0x0c00
116b ; 0f01 C False from color 0x0c00
116b ; 0f02 C True from color 0x0c00
116b ; 0f03 C False from color 0x0c00
116b ; 0f04 C True from color 0x0c00
116b ; 0f05 C True from color 0x0c00
116b ; 0f06 C True from color 0x0c00
116b ; 0f07 C True from color 0x0c00
116b ; 0f08 C True from color 0x0c00
116b ; 0f09 C True from color 0x0c00
116b ; 0f0a C True from color 0x0c00
116b ; 0f0b C True from color 0x0c00
116b ; 0f0c C False from color 0x0c00
116b ; 0f0d C True from color 0x0c00
116b ; 0f0e C True from color 0x0c00
116b ; 0f0f C True from color 0x0c00
116b ; 0f10 C True from color 0x0c00
116b ; 0f11 C True from color 0x0c00
116b ; 0f12 C True from color 0x0c00
116b ; 0f13 C True from color 0x0c00
116b ; 0f14 C True from color 0x0c00
116b ; 0f15 C False from color 0x0c00
116b ; 0f16 C True from color 0x0c00
116b ; 0f17 C True from color 0x0c00
116b ; 0f18 C True from color 0x0c00
116b ; 0f19 C False from color 0x0c00
116b ; 0f1a C True from color 0x0c00
116b ; 0f1b C True from color 0x0c00
116b ; 0f1c C True from color 0x0c00
116b ; 0f1d C True from color 0x0c00
116b ; 0f1e C False from color 0x0c00
116b ; 0f1f C True from color 0x0c00
116b ; 0f20 C True from color 0x0c00
116b ; 0f21 C True from color 0x0c00
116b ; 0f22 C True from color 0x0c00
116b ; 0f23 C True from color 0x0c00
116b ; 0f24 C False from color 0x0c00
116b ; 0f25 C True from color 0x0c00
116b ; 0f26 C True from color 0x0c00
116b ; 0f27 C False from color 0x0c00
116b ; 0f28 C True from color 0x0c00
116b ; 0f29 C True from color 0x0c00
116b ; 0f2a C True from color 0x0c00
116b ; 0f2b C True from color 0x0c00
116b ; 0f2c C True from color 0x0c00
116b ; 0f2d C False from color 0x0c00
116b ; 0f2e C False from color 0x0c00
116b ; 0f2f C True from color 0x0c00
116b ; --------------------------------------------------------------------------------------
116b ARITH_ALU_ERROR:
116b 116b <halt> ; Flow R
116c 116c seq_br_type a Unconditional Return; Flow R
116d ; --------------------------------------------------------------------------------------
116d ; Comes from:
116d ; 0f32 C True from color 0x0c00
116d ; 0f35 C True from color 0x0c00
116d ; 0f38 C True from color 0x0c00
116d ; 0f3b C True from color 0x0c00
116d ; 0f3e C True from color 0x0c00
116d ; 0f41 C True from color 0x0c00
116d ; 0f44 C True from color 0x0c00
116d ; 0f47 C True from color 0x0c00
116d ; 0f4a C True from color 0x0c00
116d ; 0f4d C True from color 0x0c00
116d ; 0f50 C True from color 0x0c00
116d ; 0f53 C True from color 0x0c00
116d ; 0f56 C True from color 0x0c00
116d ; 0f59 C True from color 0x0c00
116d ; 0f5c C True from color 0x0c00
116d ; 0f5f C True from color 0x0c00
116d ; 0f62 C True from color 0x0c00
116d ; 0f65 C True from color 0x0c00
116d ; 0f68 C True from color 0x0c00
116d ; 0f6b C True from color 0x0c00
116d ; 0f6e C True from color 0x0c00
116d ; 0f71 C True from color 0x0c00
116d ; 0f74 C True from color 0x0c00
116d ; 0f77 C True from color 0x0c00
116d ; 0f7a C True from color 0x0c00
116d ; 0f7d C True from color 0x0c00
116d ; 0f80 C True from color 0x0c00
116d ; 0f83 C True from color 0x0c00
116d ; 0f86 C True from color 0x0c00
116d ; 0f89 C True from color 0x0c00
116d ; 0f8c C True from color 0x0c00
116d ; 0f8f C True from color 0x0c00
116d ; --------------------------------------------------------------------------------------
116d COND_ALU_ERROR:
116d 116d <halt> ; Flow R
116e 116e seq_br_type a Unconditional Return; Flow R
116f ; --------------------------------------------------------------------------------------
116f ; Comes from:
116f ; 0f91 C True from color 0x0c00
116f ; 0f93 C True from color 0x0c00
116f ; 0f95 C True from color 0x0c00
116f ; 0f97 C True from color 0x0c00
116f ; 0f99 C True from color 0x0c00
116f ; 0f9b C True from color 0x0c00
116f ; 0f9d C True from color 0x0c00
116f ; 0f9f C True from color 0x0c00
116f ; 0fa1 C True from color 0x0c00
116f ; 0fa3 C True from color 0x0c00
116f ; 0fa5 C True from color 0x0c00
116f ; 0fa7 C True from color 0x0c00
116f ; 0fa9 C True from color 0x0c00
116f ; 0fab C True from color 0x0c00
116f ; 0fad C True from color 0x0c00
116f ; 0faf C True from color 0x0c00
116f ; 0fb1 C True from color 0x0c00
116f ; 0fb3 C True from color 0x0c00
116f ; 0fb5 C True from color 0x0c00
116f ; 0fb7 C True from color 0x0c00
116f ; 0fb9 C True from color 0x0c00
116f ; 0fbb C True from color 0x0c00
116f ; 0fbd C True from color 0x0c00
116f ; 0fbf C True from color 0x0c00
116f ; 0fc2 C True from color 0x0c00
116f ; 0fc5 C True from color 0x0c00
116f ; 0fc8 C True from color 0x0c00
116f ; 0fcb C True from color 0x0c00
116f ; 0fce C True from color 0x0c00
116f ; 0fd1 C True from color 0x0c00
116f ; 0fd4 C True from color 0x0c00
116f ; 0fd7 C True from color 0x0c00
116f ; 0fda C True from color 0x0c00
116f ; 0fdd C True from color 0x0c00
116f ; 0fe0 C True from color 0x0c00
116f ; 0fe3 C True from color 0x0c00
116f ; 0fe6 C True from color 0x0c00
116f ; 0fe9 C True from color 0x0c00
116f ; 0fec C True from color 0x0c00
116f ; 0fef C True from color 0x0c00
116f ; 0ff1 C True from color 0x0c00
116f ; 0ff3 C True from color 0x0c00
116f ; 0ff5 C True from color 0x0c00
116f ; 0ff7 C True from color 0x0c00
116f ; 0ff9 C True from color 0x0c00
116f ; 0ffb C True from color 0x0c00
116f ; 0ffd C True from color 0x0c00
116f ; 0fff C True from color 0x0c00
116f ; 1001 C True from color 0x0c00
116f ; 1003 C True from color 0x0c00
116f ; 1005 C True from color 0x0c00
116f ; 1007 C True from color 0x0c00
116f ; 1009 C True from color 0x0c00
116f ; 100b C True from color 0x0c00
116f ; 100d C True from color 0x0c00
116f ; 100f C True from color 0x0c00
116f ; 1011 C True from color 0x0c00
116f ; 1013 C True from color 0x0c00
116f ; 1015 C True from color 0x0c00
116f ; 1017 C True from color 0x0c00
116f ; 1019 C True from color 0x0c00
116f ; 101b C True from color 0x0c00
116f ; 101d C True from color 0x0c00
116f ; 101f C True from color 0x0c00
116f ; 1022 C True from color 0x0c00
116f ; 1025 C True from color 0x0c00
116f ; 1028 C True from color 0x0c00
116f ; 102b C True from color 0x0c00
116f ; 102e C True from color 0x0c00
116f ; 1031 C True from color 0x0c00
116f ; 1034 C True from color 0x0c00
116f ; 1037 C True from color 0x0c00
116f ; 103a C True from color 0x0c00
116f ; 103d C True from color 0x0c00
116f ; 1040 C True from color 0x0c00
116f ; 1043 C True from color 0x0c00
116f ; 1046 C True from color 0x0c00
116f ; 1049 C True from color 0x0c00
116f ; 104c C True from color 0x0c00
116f ; 104f C True from color 0x0c00
116f ; --------------------------------------------------------------------------------------
116f SPLIT_ALU_ERROR:
; DISABLE(MICRO_EVENTS),
; HALT,
116f 116f <halt> ; Flow R
; RETURN,
1170 1170 seq_br_type a Unconditional Return; Flow R
1171 ; --------------------------------------------------------------------------------------
1171 ; Comes from:
1171 ; 1051 C False from color 0x0c00
1171 ; 1052 C True from color 0x0c00
1171 ; 1054 C False from color 0x0c00
1171 ; 1055 C True from color 0x0c00
1171 ; 1057 C True from color 0x0c00
1171 ; 1058 C True from color 0x0c00
1171 ; 105a C True from color 0x0c00
1171 ; 105b C True from color 0x0c00
1171 ; 105d C True from color 0x0c00
1171 ; 105e C True from color 0x0c00
1171 ; 1060 C True from color 0x0c00
1171 ; 1061 C True from color 0x0c00
1171 ; 1063 C True from color 0x0c00
1171 ; 1064 C True from color 0x0c00
1171 ; 1066 C True from color 0x0c00
1171 ; 1067 C True from color 0x0c00
1171 ; 1069 C True from color 0x0c00
1171 ; 106a C True from color 0x0c00
1171 ; 106c C True from color 0x0c00
1171 ; 106d C True from color 0x0c00
1171 ; 106f C True from color 0x0c00
1171 ; 1070 C True from color 0x0c00
1171 ; 1072 C True from color 0x0c00
1171 ; 1073 C True from color 0x0c00
1171 ; 1075 C True from color 0x0c00
1171 ; 1076 C True from color 0x0c00
1171 ; 1079 C False from color 0x0c00
1171 ; 107a C True from color 0x0c00
1171 ; 107b C True from color 0x0c00
1171 ; 107d C True from color 0x0c00
1171 ; 107e C False from color 0x0c00
1171 ; 1080 C False from color 0x0c00
1171 ; 1082 C True from color 0x0c00
1171 ; 1084 C True from color 0x0c00
1171 ; 1085 C True from color 0x0c00
1171 ; 1086 C True from color 0x0c00
1171 ; --------------------------------------------------------------------------------------
1171 LOOP_ERROR:
1171 1171 <halt> ; Flow R
1172 1172 seq_br_type a Unconditional Return; Flow R
1173 ; --------------------------------------------------------------------------------------
1173 ; Comes from:
1173 ; 10ee C True from color 0x0c00
1173 ; 10f0 C True from color 0x0c00
1173 ; 10f2 C True from color 0x0c00
1173 ; 10f4 C True from color 0x0c00
1173 ; 10f6 C True from color 0x0c00
1173 ; 10f8 C True from color 0x0c00
1173 ; 10fa C True from color 0x0c00
1173 ; 10fc C True from color 0x0c00
1173 ; 1100 C True from color 0x0c00
1173 ; --------------------------------------------------------------------------------------
1173 CMUX_PASS_ERROR:
1173 1173 <halt> ; Flow R
1174 1174 seq_br_type a Unconditional Return; Flow R
1175 ; --------------------------------------------------------------------------------------
1175 ; Comes from:
1175 ; 1105 C True from color 0x0c00
1175 ; 1108 C True from color 0x0c00
1175 ; 110b C True from color 0x0c00
1175 ; 110e C True from color 0x0c00
1175 ; 1111 C True from color 0x0c00
1175 ; 1114 C True from color 0x0c00
1175 ; 1117 C True from color 0x0c00
1175 ; 111a C True from color 0x0c00
1175 ; 111f C True from color 0x0c00
1175 ; --------------------------------------------------------------------------------------
1175 CMUX_WDR_ERROR:
1175 1175 <halt> ; Flow R
1176 1176 seq_br_type a Unconditional Return; Flow R
1177 ; --------------------------------------------------------------------------------------
1177 ; Comes from:
1177 ; 1124 C True from color 0x0c00
1177 ; 1126 C True from color 0x0c00
1177 ; 1128 C True from color 0x0c00
1177 ; 112a C True from color 0x0c00
1177 ; 112c C True from color 0x0c00
1177 ; 112e C True from color 0x0c00
1177 ; 1130 C True from color 0x0c00
1177 ; 1132 C True from color 0x0c00
1177 ; 1136 C True from color 0x0c00
1177 ; --------------------------------------------------------------------------------------
1177 CMUX_FIU_ERROR:
1177 1177 <halt> ; Flow R
1178 1178 seq_br_type a Unconditional Return; Flow R
1179 ZERO_COND_ERROR:
1179 1179 <halt> ; Flow R
117a 117a seq_br_type a Unconditional Return; Flow R
117b ; --------------------------------------------------------------------------------------
117b ; Comes from:
117b ; 1088 C from color 0x0c00
117b ; 1089 C False from color 0x0c00
117b ; 108a C True from color 0x0c00
117b ; 108c C from color 0x0c00
117b ; 108e C from color 0x0c00
117b ; 108f C False from color 0x0c00
117b ; 1090 C True from color 0x0c00
117b ; 1092 C from color 0x0c00
117b ; --------------------------------------------------------------------------------------
117b BIT_21_ERROR:
117b 117b <halt> ; Flow R
117c 117c seq_br_type a Unconditional Return; Flow R
117d ; --------------------------------------------------------------------------------------
117d ; Comes from:
117d ; 1094 C from color 0x0c00
117d ; 1095 C False from color 0x0c00
117d ; 1096 C True from color 0x0c00
117d ; 1098 C from color 0x0c00
117d ; 109a C from color 0x0c00
117d ; 109b C False from color 0x0c00
117d ; 109c C True from color 0x0c00
117d ; 109e C from color 0x0c00
117d ; --------------------------------------------------------------------------------------
117d BIT_32_ERROR:
117d 117d <halt> ; Flow R
117e 117e seq_br_type a Unconditional Return; Flow R
117f ; --------------------------------------------------------------------------------------
117f ; Comes from:
117f ; 10a0 C from color 0x0c00
117f ; 10a1 C False from color 0x0c00
117f ; 10a2 C True from color 0x0c00
117f ; 10a4 C from color 0x0c00
117f ; 10a6 C from color 0x0c00
117f ; 10a7 C False from color 0x0c00
117f ; 10a8 C True from color 0x0c00
117f ; 10aa C from color 0x0c00
117f ; --------------------------------------------------------------------------------------
117f BIT_33_ERROR:
117f 117f <halt> ; Flow R
1180 1180 seq_br_type a Unconditional Return; Flow R
1181 ; --------------------------------------------------------------------------------------
1181 ; Comes from:
1181 ; 10ac C from color 0x0c00
1181 ; 10ad C False from color 0x0c00
1181 ; 10ae C True from color 0x0c00
1181 ; 10b0 C from color 0x0c00
1181 ; 10b2 C from color 0x0c00
1181 ; 10b3 C False from color 0x0c00
1181 ; 10b4 C True from color 0x0c00
1181 ; 10b6 C from color 0x0c00
1181 ; --------------------------------------------------------------------------------------
1181 BIT_34_ERROR:
1181 1181 <halt> ; Flow R
1182 1182 seq_br_type a Unconditional Return; Flow R
1183 ; --------------------------------------------------------------------------------------
1183 ; Comes from:
1183 ; 10b8 C from color 0x0c00
1183 ; 10b9 C False from color 0x0c00
1183 ; 10ba C True from color 0x0c00
1183 ; 10bc C from color 0x0c00
1183 ; 10be C from color 0x0c00
1183 ; 10bf C False from color 0x0c00
1183 ; 10c0 C True from color 0x0c00
1183 ; 10c2 C from color 0x0c00
1183 ; --------------------------------------------------------------------------------------
1183 BIT_35_ERROR:
1183 1183 <halt> ; Flow R
1184 1184 seq_br_type a Unconditional Return; Flow R
1185 ; --------------------------------------------------------------------------------------
1185 ; Comes from:
1185 ; 10c4 C from color 0x0c00
1185 ; 10c5 C False from color 0x0c00
1185 ; 10c6 C True from color 0x0c00
1185 ; 10c8 C from color 0x0c00
1185 ; 10ca C from color 0x0c00
1185 ; 10cb C False from color 0x0c00
1185 ; 10cc C True from color 0x0c00
1185 ; 10ce C from color 0x0c00
1185 ; --------------------------------------------------------------------------------------
1185 BIT_36_ERROR:
1185 1185 <halt> ; Flow R
1186 1186 seq_br_type a Unconditional Return; Flow R
1187 ; --------------------------------------------------------------------------------------
1187 ; Comes from:
1187 ; 10d0 C from color 0x0c00
1187 ; 10d1 C True from color 0x0c00
1187 ; 10d3 C from color 0x0c00
1187 ; 10d4 C True from color 0x0c00
1187 ; 10d6 C from color 0x0c00
1187 ; 10d7 C True from color 0x0c00
1187 ; 10d8 C False from color 0x0c00
1187 ; 10da C from color 0x0c00
1187 ; 10dc C from color 0x0c00
1187 ; 10dd C True from color 0x0c00
1187 ; 10df C from color 0x0c00
1187 ; 10e1 C from color 0x0c00
1187 ; 10e3 C from color 0x0c00
1187 ; --------------------------------------------------------------------------------------
1187 BIT_33_34_36_ERROR:
1187 1187 <halt> ; Flow R
1188 1188 seq_br_type a Unconditional Return; Flow R
1189 ; --------------------------------------------------------------------------------------
1189 ; Comes from:
1189 ; 10e6 C True from color 0x0c00
1189 ; 10e8 C from color 0x0c00
1189 ; 10ea C from color 0x0c00
1189 ; 10ec C True from color 0x0c00
1189 ; --------------------------------------------------------------------------------------
1189 CARRY_IN_ERROR:
1189 1189 <halt> ; Flow R
118a 118a seq_br_type a Unconditional Return; Flow R
118b ; --------------------------------------------------------------------------------------
118b ; Comes from:
118b ; 1139 C True from color 0x0c00
118b ; 113b C True from color 0x0c00
118b ; 113d C True from color 0x0c00
118b ; 113f C True from color 0x0c00
118b ; 1141 C True from color 0x0c00
118b ; 1143 C True from color 0x0c00
118b ; 1145 C True from color 0x0c00
118b ; 1147 C True from color 0x0c00
118b ; 1149 C True from color 0x0c00
118b ; 114b C True from color 0x0c00
118b ; 115d C True from color 0x0c00
118b ; 115f C True from color 0x0c00
118b ; --------------------------------------------------------------------------------------
118b FIU_HIGH_ERROR:
118b 118b <halt> ; Flow R
118c 118c seq_br_type a Unconditional Return; Flow R
118d ; --------------------------------------------------------------------------------------
118d ; Comes from:
118d ; 114d C True from color 0x0c00
118d ; 114f C True from color 0x0c00
118d ; 1151 C True from color 0x0c00
118d ; 1153 C True from color 0x0c00
118d ; 1155 C True from color 0x0c00
118d ; 1157 C True from color 0x0c00
118d ; 1159 C True from color 0x0c00
118d ; 115b C True from color 0x0c00
118d ; --------------------------------------------------------------------------------------
118d FIU_LOW_ERROR:
118d 118d <halt> ; Flow R
118e 118e seq_br_type a Unconditional Return; Flow R
118f ; --------------------------------------------------------------------------------------
118f ; Comes from:
118f ; 1162 C True from color 0x0c00
118f ; --------------------------------------------------------------------------------------
118f REG_A_B_ERROR:
118f 118f <halt> ; Flow R
1190 1190 seq_br_type a Unconditional Return; Flow R
1191 1191 <halt> ; Flow R
1192 1192 <halt> ; Flow R
1193 1193 <halt> ; Flow R
1194 1194 <halt> ; Flow R
1195 1195 <halt> ; Flow R
1196 1196 <halt> ; Flow R
1197 1197 <halt> ; Flow R
1198 1198 <halt> ; Flow R
1199 1199 <halt> ; Flow R
119a 119a <halt> ; Flow R
119b 119b <halt> ; Flow R
119c 119c <halt> ; Flow R
119d 119d <halt> ; Flow R
119e 119e <halt> ; Flow R
119f 119f <halt> ; Flow R
11a0 11a0 <halt> ; Flow R
11a1 11a1 <halt> ; Flow R
11a2 11a2 <halt> ; Flow R
11a3 11a3 <halt> ; Flow R
11a4 11a4 <halt> ; Flow R
11a5 11a5 <halt> ; Flow R
11a6 11a6 <halt> ; Flow R
11a7 11a7 <halt> ; Flow R
11a8 11a8 <halt> ; Flow R
11a9 11a9 <halt> ; Flow R
11aa 11aa <halt> ; Flow R
11ab 11ab <halt> ; Flow R
11ac 11ac <halt> ; Flow R
11ad 11ad <halt> ; Flow R
11ae 11ae <halt> ; Flow R
11af 11af <halt> ; Flow R
11b0 11b0 <halt> ; Flow R
11b1 11b1 <halt> ; Flow R
11b2 11b2 <halt> ; Flow R
11b3 11b3 <halt> ; Flow R
11b4 11b4 <halt> ; Flow R
11b5 11b5 <halt> ; Flow R
11b6 11b6 <halt> ; Flow R
11b7 11b7 <halt> ; Flow R
11b8 11b8 <halt> ; Flow R
11b9 11b9 <halt> ; Flow R
11ba 11ba <halt> ; Flow R
11bb 11bb <halt> ; Flow R
11bc 11bc <halt> ; Flow R
11bd 11bd <halt> ; Flow R
11be 11be <halt> ; Flow R
11bf 11bf <halt> ; Flow R
11c0 11c0 <halt> ; Flow R
11c1 11c1 <halt> ; Flow R
11c2 11c2 <halt> ; Flow R
11c3 11c3 <halt> ; Flow R
11c4 11c4 <halt> ; Flow R
11c5 11c5 <halt> ; Flow R
11c6 11c6 <halt> ; Flow R
11c7 11c7 <halt> ; Flow R
11c8 11c8 <halt> ; Flow R
11c9 11c9 <halt> ; Flow R
11ca 11ca <halt> ; Flow R
11cb 11cb <halt> ; Flow R
11cc 11cc <halt> ; Flow R
11cd 11cd <halt> ; Flow R
11ce 11ce <halt> ; Flow R
11cf 11cf <halt> ; Flow R
11d0 11d0 <halt> ; Flow R
11d1 11d1 <halt> ; Flow R
11d2 11d2 <halt> ; Flow R
11d3 11d3 <halt> ; Flow R
11d4 11d4 <halt> ; Flow R
11d5 11d5 <halt> ; Flow R
11d6 11d6 <halt> ; Flow R
11d7 11d7 <halt> ; Flow R
11d8 11d8 <halt> ; Flow R
11d9 11d9 <halt> ; Flow R
11da 11da <halt> ; Flow R
11db 11db <halt> ; Flow R
11dc 11dc <halt> ; Flow R
11dd 11dd <halt> ; Flow R
11de 11de <halt> ; Flow R
11df 11df <halt> ; Flow R
11e0 11e0 <halt> ; Flow R
11e1 11e1 <halt> ; Flow R
11e2 11e2 <halt> ; Flow R
11e3 11e3 <halt> ; Flow R
11e4 11e4 <halt> ; Flow R
11e5 11e5 <halt> ; Flow R
11e6 11e6 <halt> ; Flow R
11e7 11e7 <halt> ; Flow R
11e8 11e8 <halt> ; Flow R
11e9 11e9 <halt> ; Flow R
11ea 11ea <halt> ; Flow R
11eb 11eb <halt> ; Flow R
11ec 11ec <halt> ; Flow R
11ed 11ed <halt> ; Flow R
11ee 11ee <halt> ; Flow R
11ef 11ef <halt> ; Flow R
11f0 11f0 <halt> ; Flow R
11f1 11f1 <halt> ; Flow R
11f2 11f2 <halt> ; Flow R
11f3 11f3 <halt> ; Flow R
11f4 11f4 <halt> ; Flow R
11f5 11f5 <halt> ; Flow R
11f6 11f6 <halt> ; Flow R
11f7 11f7 <halt> ; Flow R
11f8 11f8 <halt> ; Flow R
11f9 11f9 <halt> ; Flow R
11fa 11fa <halt> ; Flow R
11fb 11fb <halt> ; Flow R
11fc 11fc <halt> ; Flow R
11fd 11fd <halt> ; Flow R
11fe 11fe <halt> ; Flow R
11ff 11ff <halt> ; Flow R
1200 1200 <halt> ; Flow R
1201 1201 <halt> ; Flow R
1202 1202 <halt> ; Flow R
1203 1203 <halt> ; Flow R
1204 1204 <halt> ; Flow R
1205 1205 <halt> ; Flow R
1206 1206 <halt> ; Flow R
1207 1207 <halt> ; Flow R
1208 1208 <halt> ; Flow R
1209 1209 <halt> ; Flow R
120a 120a <halt> ; Flow R
120b 120b <halt> ; Flow R
120c 120c <halt> ; Flow R
120d 120d <halt> ; Flow R
120e 120e <halt> ; Flow R
120f 120f <halt> ; Flow R
1210 1210 <halt> ; Flow R
1211 1211 <halt> ; Flow R
1212 1212 <halt> ; Flow R
1213 1213 <halt> ; Flow R
1214 1214 <halt> ; Flow R
1215 1215 <halt> ; Flow R
1216 1216 <halt> ; Flow R
1217 1217 <halt> ; Flow R
1218 1218 <halt> ; Flow R
1219 1219 <halt> ; Flow R
121a 121a <halt> ; Flow R
121b 121b <halt> ; Flow R
121c 121c <halt> ; Flow R
121d 121d <halt> ; Flow R
121e 121e <halt> ; Flow R
121f 121f <halt> ; Flow R
1220 1220 <halt> ; Flow R
1221 1221 <halt> ; Flow R
1222 1222 <halt> ; Flow R
1223 1223 <halt> ; Flow R
1224 1224 <halt> ; Flow R
1225 1225 <halt> ; Flow R
1226 1226 <halt> ; Flow R
1227 1227 <halt> ; Flow R
1228 1228 <halt> ; Flow R
1229 1229 <halt> ; Flow R
122a 122a <halt> ; Flow R
122b 122b <halt> ; Flow R
122c 122c <halt> ; Flow R
122d 122d <halt> ; Flow R
122e 122e <halt> ; Flow R
122f 122f <halt> ; Flow R
1230 1230 <halt> ; Flow R
1231 1231 <halt> ; Flow R
1232 1232 <halt> ; Flow R
1233 1233 <halt> ; Flow R
1234 1234 <halt> ; Flow R
1235 1235 <halt> ; Flow R
1236 1236 <halt> ; Flow R
1237 1237 <halt> ; Flow R
1238 1238 <halt> ; Flow R
1239 1239 <halt> ; Flow R
123a 123a <halt> ; Flow R
123b 123b <halt> ; Flow R
123c 123c <halt> ; Flow R
123d 123d <halt> ; Flow R
123e 123e <halt> ; Flow R
123f 123f <halt> ; Flow R
1240 1240 <halt> ; Flow R
1241 1241 <halt> ; Flow R
1242 1242 <halt> ; Flow R
1243 1243 <halt> ; Flow R
1244 1244 <halt> ; Flow R
1245 1245 <halt> ; Flow R
1246 1246 <halt> ; Flow R
1247 1247 <halt> ; Flow R
1248 1248 <halt> ; Flow R
1249 1249 <halt> ; Flow R
124a 124a <halt> ; Flow R
124b 124b <halt> ; Flow R
124c 124c <halt> ; Flow R
124d 124d <halt> ; Flow R
124e 124e <halt> ; Flow R
124f 124f <halt> ; Flow R
1250 1250 <halt> ; Flow R
1251 1251 <halt> ; Flow R
1252 1252 <halt> ; Flow R
1253 1253 <halt> ; Flow R
1254 1254 <halt> ; Flow R
1255 1255 <halt> ; Flow R
1256 1256 <halt> ; Flow R
1257 1257 <halt> ; Flow R
1258 1258 <halt> ; Flow R
1259 1259 <halt> ; Flow R
125a 125a <halt> ; Flow R
125b 125b <halt> ; Flow R
125c 125c <halt> ; Flow R
125d 125d <halt> ; Flow R
125e 125e <halt> ; Flow R
125f 125f <halt> ; Flow R
1260 1260 <halt> ; Flow R
1261 1261 <halt> ; Flow R
1262 1262 <halt> ; Flow R
1263 1263 <halt> ; Flow R
1264 1264 <halt> ; Flow R
1265 1265 <halt> ; Flow R
1266 1266 <halt> ; Flow R
1267 1267 <halt> ; Flow R
1268 1268 <halt> ; Flow R
1269 1269 <halt> ; Flow R
126a 126a <halt> ; Flow R
126b 126b <halt> ; Flow R
126c 126c <halt> ; Flow R
126d 126d <halt> ; Flow R
126e 126e <halt> ; Flow R
126f 126f <halt> ; Flow R
1270 1270 <halt> ; Flow R
1271 1271 <halt> ; Flow R
1272 1272 <halt> ; Flow R
1273 1273 <halt> ; Flow R
1274 1274 <halt> ; Flow R
1275 1275 <halt> ; Flow R
1276 1276 <halt> ; Flow R
1277 1277 <halt> ; Flow R
1278 1278 <halt> ; Flow R
1279 1279 <halt> ; Flow R
127a 127a <halt> ; Flow R
127b 127b <halt> ; Flow R
127c 127c <halt> ; Flow R
127d 127d <halt> ; Flow R
127e 127e <halt> ; Flow R
127f 127f <halt> ; Flow R
1280 1280 <halt> ; Flow R
1281 1281 <halt> ; Flow R
1282 1282 <halt> ; Flow R
1283 1283 <halt> ; Flow R
1284 1284 <halt> ; Flow R
1285 1285 <halt> ; Flow R
1286 1286 <halt> ; Flow R
1287 1287 <halt> ; Flow R
1288 1288 <halt> ; Flow R
1289 1289 <halt> ; Flow R
128a 128a <halt> ; Flow R
128b 128b <halt> ; Flow R
128c 128c <halt> ; Flow R
128d 128d <halt> ; Flow R
128e 128e <halt> ; Flow R
128f 128f <halt> ; Flow R
1290 1290 <halt> ; Flow R
1291 1291 <halt> ; Flow R
1292 1292 <halt> ; Flow R
1293 1293 <halt> ; Flow R
1294 1294 <halt> ; Flow R
1295 1295 <halt> ; Flow R
1296 1296 <halt> ; Flow R
1297 1297 <halt> ; Flow R
1298 1298 <halt> ; Flow R
1299 1299 <halt> ; Flow R
129a 129a <halt> ; Flow R
129b 129b <halt> ; Flow R
129c 129c <halt> ; Flow R
129d 129d <halt> ; Flow R
129e 129e <halt> ; Flow R
129f 129f <halt> ; Flow R
12a0 12a0 <halt> ; Flow R
12a1 12a1 <halt> ; Flow R
12a2 12a2 <halt> ; Flow R
12a3 12a3 <halt> ; Flow R
12a4 12a4 <halt> ; Flow R
12a5 12a5 <halt> ; Flow R
12a6 12a6 <halt> ; Flow R
12a7 12a7 <halt> ; Flow R
12a8 12a8 <halt> ; Flow R
12a9 12a9 <halt> ; Flow R
12aa 12aa <halt> ; Flow R
12ab 12ab <halt> ; Flow R
12ac 12ac <halt> ; Flow R
12ad 12ad <halt> ; Flow R
12ae 12ae <halt> ; Flow R
12af 12af <halt> ; Flow R
12b0 12b0 <halt> ; Flow R
12b1 12b1 <halt> ; Flow R
12b2 12b2 <halt> ; Flow R
12b3 12b3 <halt> ; Flow R
12b4 12b4 <halt> ; Flow R
12b5 12b5 <halt> ; Flow R
12b6 12b6 <halt> ; Flow R
12b7 12b7 <halt> ; Flow R
12b8 12b8 <halt> ; Flow R
12b9 12b9 <halt> ; Flow R
12ba 12ba <halt> ; Flow R
12bb 12bb <halt> ; Flow R
12bc 12bc <halt> ; Flow R
12bd 12bd <halt> ; Flow R
12be 12be <halt> ; Flow R
12bf 12bf <halt> ; Flow R
12c0 12c0 <halt> ; Flow R
12c1 12c1 <halt> ; Flow R
12c2 12c2 <halt> ; Flow R
12c3 12c3 <halt> ; Flow R
12c4 12c4 <halt> ; Flow R
12c5 12c5 <halt> ; Flow R
12c6 12c6 <halt> ; Flow R
12c7 12c7 <halt> ; Flow R
12c8 12c8 <halt> ; Flow R
12c9 12c9 <halt> ; Flow R
12ca 12ca <halt> ; Flow R
12cb 12cb <halt> ; Flow R
12cc 12cc <halt> ; Flow R
12cd 12cd <halt> ; Flow R
12ce 12ce <halt> ; Flow R
12cf 12cf <halt> ; Flow R
12d0 12d0 <halt> ; Flow R
12d1 12d1 <halt> ; Flow R
12d2 12d2 <halt> ; Flow R
12d3 12d3 <halt> ; Flow R
12d4 12d4 <halt> ; Flow R
12d5 12d5 <halt> ; Flow R
12d6 12d6 <halt> ; Flow R
12d7 12d7 <halt> ; Flow R
12d8 12d8 <halt> ; Flow R
12d9 12d9 <halt> ; Flow R
12da 12da <halt> ; Flow R
12db 12db <halt> ; Flow R
12dc 12dc <halt> ; Flow R
12dd 12dd <halt> ; Flow R
12de 12de <halt> ; Flow R
12df 12df <halt> ; Flow R
12e0 12e0 <halt> ; Flow R
12e1 12e1 <halt> ; Flow R
12e2 12e2 <halt> ; Flow R
12e3 12e3 <halt> ; Flow R
12e4 12e4 <halt> ; Flow R
12e5 12e5 <halt> ; Flow R
12e6 12e6 <halt> ; Flow R
12e7 12e7 <halt> ; Flow R
12e8 12e8 <halt> ; Flow R
12e9 12e9 <halt> ; Flow R
12ea 12ea <halt> ; Flow R
12eb 12eb <halt> ; Flow R
12ec 12ec <halt> ; Flow R
12ed 12ed <halt> ; Flow R
12ee 12ee <halt> ; Flow R
12ef 12ef <halt> ; Flow R
12f0 12f0 <halt> ; Flow R
12f1 12f1 <halt> ; Flow R
12f2 12f2 <halt> ; Flow R
12f3 12f3 <halt> ; Flow R
12f4 12f4 <halt> ; Flow R
12f5 12f5 <halt> ; Flow R
12f6 12f6 <halt> ; Flow R
12f7 12f7 <halt> ; Flow R
12f8 12f8 <halt> ; Flow R
12f9 12f9 <halt> ; Flow R
12fa 12fa <halt> ; Flow R
12fb 12fb <halt> ; Flow R
12fc 12fc <halt> ; Flow R
12fd 12fd <halt> ; Flow R
12fe 12fe <halt> ; Flow R
12ff 12ff <halt> ; Flow R
1300 ; --------------------------------------------------------------------------------------
1300 ; 1300 - 169F CLASS_TEST
1300 ; Comes from:
1300 ; 0311 C from color DIAGNOSTIC_START
1300 ; --------------------------------------------------------------------------------------
1300 1300 seq_br_type 7 Unconditional Call; Flow C 0x1691
seq_branch_adr 1691 0x1691
1301 1301 typ_a_adr 2f TR10:0f
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1302 1302 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 1
1303 1303 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 2
1304 1304 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 4
1305 1305 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 8
1306 1306 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 10
1307 1307 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 2
1308 1308 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 1
1309 1309 seq_br_type 1 Branch True; Flow J cc=True 0x130b
seq_branch_adr 130b 0x130b
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
130a 130a seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
130b 130b typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
130c 130c seq_br_type 1 Branch True; Flow J cc=True 0x130e
seq_branch_adr 130e 0x130e
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 1
130d 130d seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
130e 130e typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
130f 130f seq_br_type 1 Branch True; Flow J cc=True 0x1311
seq_branch_adr 1311 0x1311
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 2
1310 1310 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1311 1311 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1312 1312 seq_br_type 1 Branch True; Flow J cc=True 0x1314
seq_branch_adr 1314 0x1314
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 4
1313 1313 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1314 1314 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1315 1315 seq_br_type 1 Branch True; Flow J cc=True 0x1317
seq_branch_adr 1317 0x1317
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 8
1316 1316 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1317 1317 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1318 1318 seq_br_type 1 Branch True; Flow J cc=True 0x131a
seq_branch_adr 131a 0x131a
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_frame 10
1319 1319 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
131a 131a typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
131b 131b seq_br_type 1 Branch True; Flow J cc=True 0x131d
seq_branch_adr 131d 0x131d
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 2
131c 131c seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
131d 131d typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
131e 131e seq_br_type 1 Branch True; Flow J cc=True 0x1320
seq_branch_adr 1320 0x1320
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 1
131f 131f seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1320 1320 typ_a_adr 27 TR04:07
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1321 1321 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 1
1322 1322 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 2
1323 1323 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 4
1324 1324 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 8
1325 1325 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 10
1326 1326 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 2
1327 1327 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 1
1328 1328 seq_br_type 1 Branch True; Flow J cc=True 0x132a
seq_branch_adr 132a 0x132a
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
1329 1329 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
132a 132a typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
132b 132b seq_br_type 1 Branch True; Flow J cc=True 0x132d
seq_branch_adr 132d 0x132d
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 1
132c 132c seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
132d 132d typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
132e 132e seq_br_type 1 Branch True; Flow J cc=True 0x1330
seq_branch_adr 1330 0x1330
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 2
132f 132f seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1330 1330 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1331 1331 seq_br_type 1 Branch True; Flow J cc=True 0x1333
seq_branch_adr 1333 0x1333
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 4
1332 1332 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1333 1333 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1334 1334 seq_br_type 1 Branch True; Flow J cc=True 0x1336
seq_branch_adr 1336 0x1336
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 8
1335 1335 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1336 1336 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1337 1337 seq_br_type 1 Branch True; Flow J cc=True 0x1339
seq_branch_adr 1339 0x1339
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_frame 10
1338 1338 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1339 1339 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
133a 133a seq_br_type 1 Branch True; Flow J cc=True 0x133c
seq_branch_adr 133c 0x133c
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 2
133b 133b seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
133c 133c typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
133d 133d seq_br_type 1 Branch True; Flow J cc=True 0x133f
seq_branch_adr 133f 0x133f
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 1
133e 133e seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
133f 133f typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1340 1340 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1e
1341 1341 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1d
1342 1342 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1b
1343 1343 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 1
typ_frame d
1344 1344 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame f
1345 1345 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 1
typ_frame 1f
1346 1346 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1696
seq_br_type 5 Call True
seq_branch_adr 1696 A_EQ_L_FAILED
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1347 1347 seq_br_type 1 Branch True; Flow J cc=True 0x1349
seq_branch_adr 1349 0x1349
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1f
1348 1348 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1349 1349 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
134a 134a seq_br_type 1 Branch True; Flow J cc=True 0x134c
seq_branch_adr 134c 0x134c
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1e
134b 134b seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
134c 134c typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
134d 134d seq_br_type 1 Branch True; Flow J cc=True 0x134f
seq_branch_adr 134f 0x134f
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1d
134e 134e seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
134f 134f typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1350 1350 seq_br_type 1 Branch True; Flow J cc=True 0x1352
seq_branch_adr 1352 0x1352
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 1b
1351 1351 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1352 1352 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1353 1353 seq_br_type 1 Branch True; Flow J cc=True 0x1355
seq_branch_adr 1355 0x1355
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame 17
1354 1354 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1355 1355 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1356 1356 seq_br_type 1 Branch True; Flow J cc=True 0x1358
seq_branch_adr 1358 0x1358
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 0
typ_frame f
1357 1357 seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
1358 1358 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1359 1359 seq_br_type 1 Branch True; Flow J cc=True 0x135b
seq_branch_adr 135b 0x135b
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 1
typ_frame 1f
135a 135a seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
135b 135b typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
135c 135c seq_br_type 1 Branch True; Flow J cc=True 0x135e
seq_branch_adr 135e 0x135e
seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late)
typ_a_adr 03 GP03
typ_c_lit 2
typ_frame 1f
135d 135d seq_br_type 7 Unconditional Call; Flow C 0x1696
seq_branch_adr 1696 A_EQ_L_FAILED
135e 135e typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
135f 135f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1e
1360 1360 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1d
1361 1361 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1b
1362 1362 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 17
1363 1363 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame f
1364 1364 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1f
1365 1365 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1698
seq_br_type 5 Call True
seq_branch_adr 1698 B_EQ_L_FAILED
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1366 1366 seq_br_type 1 Branch True; Flow J cc=True 0x1368
seq_branch_adr 1368 0x1368
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1f
1367 1367 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1368 1368 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1369 1369 seq_br_type 1 Branch True; Flow J cc=True 0x136b
seq_branch_adr 136b 0x136b
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1e
136a 136a seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
136b 136b typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
136c 136c seq_br_type 1 Branch True; Flow J cc=True 0x136e
seq_branch_adr 136e 0x136e
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1d
136d 136d seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
136e 136e typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
136f 136f seq_br_type 1 Branch True; Flow J cc=True 0x1371
seq_branch_adr 1371 0x1371
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 1b
1370 1370 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1371 1371 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1372 1372 seq_br_type 1 Branch True; Flow J cc=True 0x1374
seq_branch_adr 1374 0x1374
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 17
1373 1373 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1374 1374 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1375 1375 seq_br_type 1 Branch True; Flow J cc=True 0x1377
seq_branch_adr 1377 0x1377
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame f
1376 1376 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
1377 1377 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1378 1378 seq_br_type 1 Branch True; Flow J cc=True 0x137a
seq_branch_adr 137a 0x137a
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1f
1379 1379 seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
137a 137a typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
137b 137b seq_br_type 1 Branch True; Flow J cc=True 0x137d
seq_branch_adr 137d 0x137d
seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late)
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
137c 137c seq_br_type 7 Unconditional Call; Flow C 0x1698
seq_branch_adr 1698 B_EQ_L_FAILED
137d 137d typ_a_adr 2f TR10:0f
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
137e 137e typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
137f 137f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1380 1380 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1381 1381 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1382 1382 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1383 1383 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1384 1384 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1385 1385 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1386 1386 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
1387 1387 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1388 1388 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1389 1389 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138a 138a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138b 138b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138c 138c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138d 138d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138e 138e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
138f 138f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169a
seq_br_type 5 Call True
seq_branch_adr 169a A_EQ_B_FAILED
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1390 1390 seq_br_type 1 Branch True; Flow J cc=True 0x1392
seq_branch_adr 1392 0x1392
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1391 1391 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
1392 1392 typ_a_adr 04 GP04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1393 1393 seq_br_type 1 Branch True; Flow J cc=True 0x1395
seq_branch_adr 1395 0x1395
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1394 1394 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
1395 1395 typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1396 1396 seq_br_type 1 Branch True; Flow J cc=True 0x1398
seq_branch_adr 1398 0x1398
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1397 1397 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
1398 1398 typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1399 1399 seq_br_type 1 Branch True; Flow J cc=True 0x139b
seq_branch_adr 139b 0x139b
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
139a 139a seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
139b 139b typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
139c 139c seq_br_type 1 Branch True; Flow J cc=True 0x139e
seq_branch_adr 139e 0x139e
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
139d 139d seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
139e 139e typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
139f 139f seq_br_type 1 Branch True; Flow J cc=True 0x13a1
seq_branch_adr 13a1 0x13a1
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
13a0 13a0 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
13a1 13a1 typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
13a2 13a2 seq_br_type 1 Branch True; Flow J cc=True 0x13a4
seq_branch_adr 13a4 0x13a4
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
13a3 13a3 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
13a4 13a4 typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
13a5 13a5 seq_br_type 1 Branch True; Flow J cc=True 0x13a7
seq_branch_adr 13a7 0x13a7
seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
13a6 13a6 seq_br_type 7 Unconditional Call; Flow C 0x169a
seq_branch_adr 169a A_EQ_B_FAILED
13a7 13a7 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13a8 13a8 seq_br_type 7 Unconditional Call; Flow C 0x1690
seq_branch_adr 1690 0x1690
13a9 13a9 typ_a_adr 03 GP03
typ_c_lit 2
typ_frame 1b
typ_rand b CARRY IN = Q BIT FROM VAL
13aa 13aa seq_br_type 7 Unconditional Call; Flow C 0x1692
seq_branch_adr 1692 0x1692
13ab 13ab typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13ac 13ac seq_br_type 7 Unconditional Call; Flow C 0x1691
seq_branch_adr 1691 0x1691
13ad 13ad typ_a_adr 03 GP03
typ_c_lit 2
typ_frame 1b
typ_rand b CARRY IN = Q BIT FROM VAL
13ae 13ae seq_br_type 7 Unconditional Call; Flow C 0x1694
seq_branch_adr 1694 0x1694
13af 13af typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13b0 13b0 seq_br_type 7 Unconditional Call; Flow C 0x1690
seq_branch_adr 1690 0x1690
13b1 13b1 typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1b
typ_rand a PASS_B_HIGH
13b2 13b2 seq_br_type 7 Unconditional Call; Flow C 0x1692
seq_branch_adr 1692 0x1692
13b3 13b3 typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13b4 13b4 seq_br_type 7 Unconditional Call; Flow C 0x1691
seq_branch_adr 1691 0x1691
13b5 13b5 typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1b
typ_rand a PASS_B_HIGH
13b6 13b6 seq_br_type 7 Unconditional Call; Flow C 0x1694
seq_branch_adr 1694 0x1694
13b7 13b7 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13b8 13b8 typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
13b9 13b9 seq_br_type 7 Unconditional Call; Flow C 0x1690
seq_branch_adr 1690 0x1690
13ba 13ba typ_a_adr 03 GP03
typ_b_adr 04 GP04
typ_rand 9 PASS_A_HIGH
13bb 13bb seq_br_type 7 Unconditional Call; Flow C 0x1692
seq_branch_adr 1692 0x1692
13bc 13bc typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13bd 13bd typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
13be 13be seq_br_type 7 Unconditional Call; Flow C 0x1691
seq_branch_adr 1691 0x1691
13bf 13bf typ_a_adr 03 GP03
typ_b_adr 04 GP04
typ_rand 9 PASS_A_HIGH
13c0 13c0 seq_br_type 7 Unconditional Call; Flow C 0x1694
seq_branch_adr 1694 0x1694
13c1 13c1 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13c2 13c2 typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
13c3 13c3 seq_br_type 7 Unconditional Call; Flow C 0x1690
seq_branch_adr 1690 0x1690
13c4 13c4 typ_a_adr 03 GP03
typ_b_adr 04 GP04
typ_c_lit 2
typ_frame 1b
typ_rand 8 SPARE_0x08
13c5 13c5 seq_br_type 7 Unconditional Call; Flow C 0x1692
seq_branch_adr 1692 0x1692
13c6 13c6 typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13c7 13c7 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
13c8 13c8 seq_br_type 7 Unconditional Call; Flow C 0x1690
seq_branch_adr 1690 0x1690
13c9 13c9 typ_a_adr 03 GP03
typ_b_adr 04 GP04
typ_c_lit 2
typ_frame 1b
typ_rand 8 SPARE_0x08
13ca 13ca seq_br_type 7 Unconditional Call; Flow C 0x1692
seq_branch_adr 1692 0x1692
13cb 13cb typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13cc 13cc typ_a_adr 31 TR14:11
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
13cd 13cd seq_br_type 7 Unconditional Call; Flow C 0x1691
seq_branch_adr 1691 0x1691
13ce 13ce typ_a_adr 03 GP03
typ_b_adr 04 GP04
typ_c_lit 2
typ_frame 1b
typ_rand 8 SPARE_0x08
13cf 13cf seq_br_type 7 Unconditional Call; Flow C 0x1694
seq_branch_adr 1694 0x1694
13d0 13d0 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13d1 13d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13d2 13d2 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
13d3 13d3 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13d4 13d4 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13d5 13d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13d6 13d6 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13d7 13d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13d8 13d8 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13d9 13d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13da 13da typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13db 13db seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13dc 13dc typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13dd 13dd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13de 13de typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13df 13df seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00)
Discrete_Var
Subprogram_Ref_For_Call
Discrete_Ref
Subprogram_For_Call
Float_Var
Variable_Ref
Float_Ref
Entry_Var
Access_Var
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Subprogram_For_Call_Elaborated
Task_Var
Task_Ref
Select_Var
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
typ_b_adr 03 GP03
13e0 13e0 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
13e1 13e1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13e2 13e2 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
13e3 13e3 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13e4 13e4 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13e5 13e5 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13e6 13e6 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13e7 13e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13e8 13e8 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13e9 13e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13ea 13ea typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13eb 13eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13ec 13ec typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13ed 13ed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13ee 13ee typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13ef 13ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01)
Discrete_Var
Discrete_Ref
Float_Var
Float_Ref
Access_Var
Access_Ref
Task_Var
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Package_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 1
13f0 13f0 typ_a_adr 2b TR16:0b
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
13f1 13f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13f2 13f2 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
13f3 13f3 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13f4 13f4 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13f5 13f5 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13f6 13f6 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13f7 13f7 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13f8 13f8 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13f9 13f9 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13fa 13fa typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13fb 13fb seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13fc 13fc typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13fd 13fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
13fe 13fe typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
13ff 13ff seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02)
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 2
1400 1400 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1401 1401 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
1402 1402 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1403 1403 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
1404 1404 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1405 1405 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
1406 1406 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1407 1407 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
1408 1408 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1409 1409 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
140a 140a typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
140b 140b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
140c 140c typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
140d 140d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
140e 140e typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
140f 140f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03)
Discrete_Var
Float_Var
Access_Var
Task_Var
Heap_Access_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 3
1410 1410 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1411 1411 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
1412 1412 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1413 1413 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
1414 1414 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1415 1415 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
1416 1416 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1417 1417 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
1418 1418 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1419 1419 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
141a 141a typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
141b 141b seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
141c 141c typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
141d 141d seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
141e 141e typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
141f 141f seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04)
Discrete_Var
Float_Var
typ_b_adr 03 GP03
typ_frame 4
1420 1420 typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1421 1421 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
1422 1422 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1423 1423 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
1424 1424 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1425 1425 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
1426 1426 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1427 1427 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
1428 1428 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1429 1429 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
142a 142a typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
142b 142b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
142c 142c typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
142d 142d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
142e 142e typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
142f 142f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 5
1430 1430 typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1431 1431 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1432 1432 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1433 1433 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1434 1434 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1435 1435 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1436 1436 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1437 1437 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1438 1438 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1439 1439 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
143a 143a typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
143b 143b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
143c 143c typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
143d 143d seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
143e 143e typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
143f 143f seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1440 1440 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1441 1441 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1442 1442 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1443 1443 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1444 1444 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06)
Heap_Access_Ref
typ_b_adr 03 GP03
typ_frame 6
1445 1445 typ_a_adr 37 TR14:17
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1446 1446 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
1447 1447 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1448 1448 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
1449 1449 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
144a 144a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
144b 144b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
144c 144c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
144d 144d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
144e 144e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
144f 144f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1450 1450 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
1451 1451 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1452 1452 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
1453 1453 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1454 1454 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 7
1455 1455 typ_a_adr 2c TR16:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1456 1456 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
1457 1457 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1458 1458 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
1459 1459 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
145a 145a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
145b 145b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
145c 145c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
145d 145d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
145e 145e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
145f 145f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1460 1460 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
1461 1461 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1462 1462 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
1463 1463 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1464 1464 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08)
Subvector_Var
Subarray_Var
typ_b_adr 03 GP03
typ_frame 8
1465 1465 typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1466 1466 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
1467 1467 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1468 1468 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
1469 1469 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
146a 146a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
146b 146b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
146c 146c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
146d 146d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
146e 146e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
146f 146f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1470 1470 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
1471 1471 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1472 1472 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
1473 1473 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1474 1474 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 9
1475 1475 typ_a_adr 33 TR14:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1476 1476 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
1477 1477 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1478 1478 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
1479 1479 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
147a 147a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
147b 147b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
147c 147c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
147d 147d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
147e 147e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
147f 147f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1480 1480 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
1481 1481 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1482 1482 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
1483 1483 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1484 1484 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0a)
Subprogram_For_Call
Entry_Var
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_For_Call_Visible
Family_Var
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram
Delay_Alternative
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_frame a
1485 1485 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1486 1486 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
1487 1487 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1488 1488 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
1489 1489 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
148a 148a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
148b 148b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
148c 148c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
148d 148d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
148e 148e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
148f 148f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1490 1490 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
1491 1491 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1492 1492 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
1493 1493 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1494 1494 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame b
1495 1495 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1496 1496 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
1497 1497 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1498 1498 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
1499 1499 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
149a 149a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
149b 149b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
149c 149c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
149d 149d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
149e 149e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
149f 149f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14a0 14a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
14a1 14a1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14a2 14a2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
14a3 14a3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14a4 14a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0c)
Control_State
Slice_Stuff
Static_Connection
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_frame c
14a5 14a5 typ_a_adr 2a TR16:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
14a6 14a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14a7 14a7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14a8 14a8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14a9 14a9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14aa 14aa seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14ab 14ab typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ac 14ac seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14ad 14ad typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ae 14ae seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14af 14af typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14b0 14b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14b1 14b1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14b2 14b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14b3 14b3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14b4 14b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0d)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_frame d
14b5 14b5 typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14b6 14b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14b7 14b7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14b8 14b8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14b9 14b9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ba 14ba seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14bb 14bb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14bc 14bc seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14bd 14bd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14be 14be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14bf 14bf typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14c0 14c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14c1 14c1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14c2 14c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14c3 14c3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14c4 14c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0e)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_frame e
14c5 14c5 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
14c6 14c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14c7 14c7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14c8 14c8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14c9 14c9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ca 14ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14cb 14cb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14cc 14cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14cd 14cd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ce 14ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14cf 14cf typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14d0 14d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14d1 14d1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14d2 14d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14d3 14d3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14d4 14d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f)
Discrete_Ref
Float_Ref
Access_Ref
Task_Ref
Subvector_Var
Subarray_Var
Heap_Access_Ref
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame f
14d5 14d5 typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14d6 14d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14d7 14d7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14d8 14d8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14d9 14d9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14da 14da seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14db 14db typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14dc 14dc seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14dd 14dd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14de 14de seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14df 14df typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14e0 14e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14e1 14e1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14e2 14e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14e3 14e3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14e4 14e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10)
Subprogram_Ref_For_Call
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_frame 10
14e5 14e5 typ_a_adr 33 TR14:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14e6 14e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14e7 14e7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14e8 14e8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14e9 14e9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ea 14ea seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14eb 14eb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ec 14ec seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14ed 14ed typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14ee 14ee seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14ef 14ef typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14f0 14f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14f1 14f1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14f2 14f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14f3 14f3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14f4 14f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 11
14f5 14f5 typ_a_adr 2e TR16:0e
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
14f6 14f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
14f7 14f7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
14f8 14f8 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
14f9 14f9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14fa 14fa seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
14fb 14fb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14fc 14fc seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
14fd 14fd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
14fe 14fe seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
14ff 14ff typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1500 1500 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
1501 1501 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1502 1502 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
1503 1503 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1504 1504 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x12)
Entry_Var
Family_Var
Delay_Alternative
Familiy_Alternative
typ_b_adr 03 GP03
typ_frame 12
1505 1505 typ_a_adr 2a TR16:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1506 1506 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
1507 1507 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1508 1508 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
1509 1509 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
150a 150a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
150b 150b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
150c 150c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
150d 150d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
150e 150e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
150f 150f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1510 1510 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
1511 1511 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1512 1512 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
1513 1513 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1514 1514 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x13)
Module_Key
typ_b_adr 03 GP03
typ_frame 13
1515 1515 typ_a_adr 2d TR16:0d
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1516 1516 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
1517 1517 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1518 1518 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
1519 1519 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
151a 151a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
151b 151b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
151c 151c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
151d 151d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
151e 151e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
151f 151f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1520 1520 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
1521 1521 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1522 1522 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
1523 1523 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1524 1524 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14)
Deletion_Key
typ_b_adr 03 GP03
typ_frame 14
1525 1525 typ_a_adr 2f TR16:0f
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1526 1526 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
1527 1527 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1528 1528 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
1529 1529 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
152a 152a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
152b 152b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
152c 152c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
152d 152d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
152e 152e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
152f 152f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1530 1530 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
1531 1531 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1532 1532 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
1533 1533 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1534 1534 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15)
Interface_Key
typ_b_adr 03 GP03
typ_frame 15
1535 1535 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1536 1536 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
1537 1537 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1538 1538 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
1539 1539 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
153a 153a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
153b 153b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
153c 153c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
153d 153d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
153e 153e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
153f 153f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1540 1540 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
1541 1541 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1542 1542 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
1543 1543 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1544 1544 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16)
Record_Var
Variant_Record_Var
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_frame 16
1545 1545 typ_a_adr 2a TR16:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1546 1546 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
1547 1547 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1548 1548 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
1549 1549 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
154a 154a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
154b 154b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
154c 154c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
154d 154d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
154e 154e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
154f 154f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1550 1550 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
1551 1551 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1552 1552 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
1553 1553 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1554 1554 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17)
Module_Key
Deletion_Key
typ_b_adr 03 GP03
typ_frame 17
1555 1555 typ_a_adr 37 TR16:17
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1556 1556 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18)
Select_Var
Default_Var
Exception_Var
typ_b_adr 03 GP03
typ_frame 18
1557 1557 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1558 1558 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18)
Select_Var
Default_Var
Exception_Var
typ_b_adr 03 GP03
typ_frame 18
1559 1559 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
155a 155a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18)
Select_Var
Default_Var
Exception_Var
typ_b_adr 03 GP03
typ_frame 18
155b 155b typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
155c 155c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18)
Select_Var
Default_Var
Exception_Var
typ_b_adr 03 GP03
typ_frame 18
155d 155d typ_a_adr 33 TR14:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
155e 155e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
155f 155f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1560 1560 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
1561 1561 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1562 1562 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
1563 1563 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1564 1564 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
1565 1565 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1566 1566 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
1567 1567 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1568 1568 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
1569 1569 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
156a 156a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
156b 156b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
156c 156c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b)
Subprogram_For_Call
Subprogram_For_Call_Elaborated
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
typ_b_adr 03 GP03
typ_frame 1b
156d 156d typ_a_adr 33 TR14:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
156e 156e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
156f 156f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1570 1570 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
1571 1571 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1572 1572 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
1573 1573 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1574 1574 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
1575 1575 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1576 1576 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
1577 1577 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1578 1578 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
1579 1579 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
157a 157a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
157b 157b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
157c 157c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
157d 157d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
157e 157e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c)
Null_Subprogram
typ_b_adr 03 GP03
typ_frame 1c
157f 157f typ_a_adr 35 TR14:15
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1580 1580 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
1581 1581 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1582 1582 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
1583 1583 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1584 1584 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
1585 1585 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1586 1586 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
1587 1587 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1588 1588 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
1589 1589 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
158a 158a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
158b 158b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
158c 158c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
158d 158d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
158e 158e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d)
Task_Var
Package_Var
typ_b_adr 03 GP03
typ_frame 1d
158f 158f typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1590 1590 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e)
Control_Allocation
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1e
1591 1591 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1592 1592 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e)
Control_Allocation
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1e
1593 1593 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR04:06
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1594 1594 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e)
Control_Allocation
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1e
1595 1595 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1596 1596 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e)
Control_Allocation
Accept_Subprogram_Ref
Record_Var
Accept_Subprogram
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1e
1597 1597 typ_a_adr 25 TR04:05
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1598 1598 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1f
1599 1599 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
159a 159a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1f
159b 159b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
159c 159c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1f
159d 159d typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
159e 159e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1f)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_frame 1f
159f 159f typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15a0 15a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
15a1 15a1 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15a2 15a2 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
15a3 15a3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR04:04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15a4 15a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
15a5 15a5 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15a6 15a6 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x20)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
15a7 15a7 typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15a8 15a8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21)
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_state2
Subarray_Var
Family_Var
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Package_Var
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1
15a9 15a9 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15aa 15aa seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21)
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_state2
Subarray_Var
Family_Var
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Package_Var
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1
15ab 15ab typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15ac 15ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21)
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_state2
Subarray_Var
Family_Var
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Package_Var
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1
15ad 15ad typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15ae 15ae seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x21)
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_state2
Subarray_Var
Family_Var
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Scheduling_Allocation
Variant_Record_Var
Delay_Alternative
Package_Var
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1
15af 15af typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15b0 15b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Ref
Deletion_Key
Entry_Var
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Ref
Select_Var
Auxiliary_Mark
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Ref
Default_Var
Activation_Link
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 2
15b1 15b1 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15b2 15b2 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Ref
Deletion_Key
Entry_Var
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Ref
Select_Var
Auxiliary_Mark
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Ref
Default_Var
Activation_Link
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 2
15b3 15b3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15b4 15b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Ref
Deletion_Key
Entry_Var
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Ref
Select_Var
Auxiliary_Mark
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Ref
Default_Var
Activation_Link
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 2
15b5 15b5 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15b6 15b6 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x22)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Ref
Deletion_Key
Entry_Var
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Ref
Select_Var
Auxiliary_Mark
Subvector_Var
Subprogram_For_Call_Visible
Subarray_Var
Family_Var
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Ref
Default_Var
Activation_Link
Record_Var
Accept_Subprogram
Variant_Record_Var
Delay_Alternative
Interface_Subprogram
Accept_Link
Utility_Subprogram
Vector_Var
Familiy_Alternative
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 2
15b7 15b7 typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15b8 15b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23)
Subprogram_Ref_For_Call
Word3_Flag
Subprogram_For_Call
Mark_Word_Flag
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Activation_Link
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Accept_Link
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 3
15b9 15b9 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15ba 15ba seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23)
Subprogram_Ref_For_Call
Word3_Flag
Subprogram_For_Call
Mark_Word_Flag
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Activation_Link
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Accept_Link
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 3
15bb 15bb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR04:01
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15bc 15bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23)
Subprogram_Ref_For_Call
Word3_Flag
Subprogram_For_Call
Mark_Word_Flag
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Activation_Link
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Accept_Link
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 3
15bd 15bd typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15be 15be seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x23)
Subprogram_Ref_For_Call
Word3_Flag
Subprogram_For_Call
Mark_Word_Flag
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Auxiliary_Mark
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Activation_Link
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Accept_Link
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 3
15bf 15bf typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15c0 15c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 4
15c1 15c1 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15c2 15c2 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 4
15c3 15c3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15c4 15c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 4
15c5 15c5 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15c6 15c6 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x24)
Control_State
Word3_Flag
Module_Key
Mark_Word_Flag
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Auxiliary_Mark
Micro_State1
Micro_state2
Activation_Link
Control_Allocation
Scheduling_Allocation
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 4
15c7 15c7 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
15c8 15c8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25)
Discrete_Var
Control_State
Subprogram_Ref_For_Call
Word3_Flag
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 5
15c9 15c9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR04:06
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15ca 15ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25)
Discrete_Var
Control_State
Subprogram_Ref_For_Call
Word3_Flag
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 5
15cb 15cb typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
15cc 15cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25)
Discrete_Var
Control_State
Subprogram_Ref_For_Call
Word3_Flag
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 5
15cd 15cd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR04:06
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15ce 15ce seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x25)
Discrete_Var
Control_State
Subprogram_Ref_For_Call
Word3_Flag
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Float_Var
Slice_Stuff
Variable_Ref
Float_Ref
Deletion_Key
Entry_Var
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 5
15cf 15cf typ_a_adr 39 TR14:19
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15d0 15d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15d1 15d1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15d2 15d2 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15d3 15d3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15d4 15d4 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15d5 15d5 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15d6 15d6 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15d7 15d7 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15d8 15d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15d9 15d9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15da 15da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15db 15db typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15dc 15dc seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15dd 15dd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15de 15de seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a)
Vector_Var
Matrix_Var
Array_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame a
15df 15df typ_a_adr 35 TR14:15
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15e0 15e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f)
Task_Ref
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame f
15e1 15e1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15e2 15e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f)
Task_Ref
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame f
15e3 15e3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 26 TR04:06
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15e4 15e4 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f)
Task_Ref
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame f
15e5 15e5 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15e6 15e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f)
Task_Ref
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame f
15e7 15e7 typ_a_adr 2a TR16:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
15e8 15e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15e9 15e9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15ea 15ea seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15eb 15eb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15ec 15ec seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15ed 15ed typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15ee 15ee seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15ef 15ef typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15f0 15f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15f1 15f1 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15f2 15f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15f3 15f3 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15f4 15f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15f5 15f5 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15f6 15f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32)
Module_Key
Deletion_Key
Interface_Key
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 12
15f7 15f7 typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15f8 15f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
15f9 15f9 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
15fa 15fa seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
15fb 15fb typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15fc 15fc seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
15fd 15fd typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
15fe 15fe seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
15ff 15ff typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1600 1600 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
1601 1601 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1602 1602 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
1603 1603 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1604 1604 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
1605 1605 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1606 1606 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33)
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 13
1607 1607 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1608 1608 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e)
Control_State
Module_Key
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1e
1609 1609 typ_a_adr 35 TR16:15
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
160a 160a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e)
Control_State
Module_Key
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1e
160b 160b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
160c 160c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e)
Control_State
Module_Key
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1e
160d 160d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
160e 160e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e)
Control_State
Module_Key
Slice_Stuff
Deletion_Key
Static_Connection
Interface_Key
Dependence_Link
Micro_State1
Micro_state2
Control_Allocation
Scheduling_Allocation
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1e
160f 160f typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1610 1610 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f)
Subprogram_Ref_For_Call
Subprogram_For_Call
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1611 1611 typ_a_adr 36 TR16:16
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1612 1612 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f)
Subprogram_Ref_For_Call
Subprogram_For_Call
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1613 1613 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1614 1614 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f)
Subprogram_Ref_For_Call
Subprogram_For_Call
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1615 1615 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1616 1616 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3f)
Subprogram_Ref_For_Call
Subprogram_For_Call
Variable_Ref
Entry_Var
Subprogram_Ref_For_Call_Elaborated
Subprogram_For_Call_Elaborated
Select_Var
Subprogram_Ref_For_Call_Visible
Subprogram_For_Call_Visible
Family_Var
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Default_Var
Accept_Subprogram_Ref
Accept_Subprogram
Delay_Alternative
Interface_Subprogram_Ref
Interface_Subprogram
Utility_Subprogram
Familiy_Alternative
Null_Subprogram
Exception_Var
typ_b_adr 03 GP03
typ_c_lit 2
typ_frame 1f
1617 1617 typ_a_adr 32 TR14:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1618 1618 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40)
Word3_Flag
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
1619 1619 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
161a 161a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40)
Word3_Flag
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
161b 161b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
161c 161c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40)
Word3_Flag
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
161d 161d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
161e 161e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x40)
Word3_Flag
Mark_Word_Flag
Auxiliary_Mark
Activation_Link
Accept_Link
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
161f 161f typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1620 1620 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Subvector_Var
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Record_Var
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Matrix_Var
Null_Subprogram
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1
1621 1621 typ_a_adr 32 TR16:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1622 1622 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Subvector_Var
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Record_Var
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Matrix_Var
Null_Subprogram
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1
1623 1623 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1624 1624 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Subvector_Var
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Record_Var
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Matrix_Var
Null_Subprogram
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1
1625 1625 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1626 1626 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41)
Discrete_Ref
Module_Key
Subprogram_For_Call
Mark_Word_Flag
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Subvector_Var
Subprogram_For_Call_Visible
Subprogram_For_Call_Visible_Elaborated
Record_Var
Accept_Subprogram
Interface_Subprogram
Utility_Subprogram
Matrix_Var
Null_Subprogram
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 1
1627 1627 typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1628 1628 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42)
Float_Var
Slice_Stuff
Variable_Ref
Task_Var
Dependence_Link
Micro_state2
Heap_Access_Var
Scheduling_Allocation
Package_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 2
1629 1629 typ_a_adr 34 TR16:14
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
162a 162a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42)
Float_Var
Slice_Stuff
Variable_Ref
Task_Var
Dependence_Link
Micro_state2
Heap_Access_Var
Scheduling_Allocation
Package_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 2
162b 162b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
162c 162c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42)
Float_Var
Slice_Stuff
Variable_Ref
Task_Var
Dependence_Link
Micro_state2
Heap_Access_Var
Scheduling_Allocation
Package_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 2
162d 162d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
162e 162e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x42)
Float_Var
Slice_Stuff
Variable_Ref
Task_Var
Dependence_Link
Micro_state2
Heap_Access_Var
Scheduling_Allocation
Package_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 2
162f 162f typ_a_adr 34 TR14:14
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1630 1630 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43)
Float_Ref
Deletion_Key
Entry_Var
Task_Ref
Select_Var
Auxiliary_Mark
Subarray_Var
Family_Var
Heap_Access_Ref
Default_Var
Activation_Link
Variant_Record_Var
Delay_Alternative
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 3
1631 1631 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1632 1632 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43)
Float_Ref
Deletion_Key
Entry_Var
Task_Ref
Select_Var
Auxiliary_Mark
Subarray_Var
Family_Var
Heap_Access_Ref
Default_Var
Activation_Link
Variant_Record_Var
Delay_Alternative
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 3
1633 1633 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR04:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1634 1634 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43)
Float_Ref
Deletion_Key
Entry_Var
Task_Ref
Select_Var
Auxiliary_Mark
Subarray_Var
Family_Var
Heap_Access_Ref
Default_Var
Activation_Link
Variant_Record_Var
Delay_Alternative
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 3
1635 1635 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1636 1636 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x43)
Float_Ref
Deletion_Key
Entry_Var
Task_Ref
Select_Var
Auxiliary_Mark
Subarray_Var
Family_Var
Heap_Access_Ref
Default_Var
Activation_Link
Variant_Record_Var
Delay_Alternative
Accept_Link
Vector_Var
Familiy_Alternative
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 3
1637 1637 typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1638 1638 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 4
1639 1639 typ_a_adr 30 TR16:10
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
163a 163a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 4
163b 163b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR04:04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
163c 163c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 4
163d 163d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
163e 163e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44)
Access_Var
Static_Connection
Subprogram_Ref_For_Call_Elaborated
Access_Ref
Interface_Key
Subprogram_For_Call_Elaborated
Task_Var
Dependence_Link
Task_Ref
Select_Var
Auxiliary_Mark
Interface_Subprogram_Ref
Interface_Subprogram
Package_Var
Accept_Link
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 4
163f 163f typ_a_adr 25 TR04:05
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1640 1640 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 5
1641 1641 typ_a_adr 31 TR16:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1642 1642 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 5
1643 1643 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR04:04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1644 1644 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 5
1645 1645 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1646 1646 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x45)
Micro_State1
Subprogram_Ref_For_Call_Visible
Subvector_Var
Subprogram_For_Call_Visible
Micro_state2
Subarray_Var
Family_Var
Utility_Subprogram
Vector_Var
Familiy_Alternative
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 5
1647 1647 typ_a_adr 36 TR14:16
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1648 1648 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46)
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 6
1649 1649 typ_a_adr 2c TR10:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
164a 164a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46)
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 6
164b 164b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR04:04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
164c 164c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46)
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 6
164d 164d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
164e 164e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x46)
Subprogram_Ref_For_Call_Visible_Elaborated
Subprogram_For_Call_Visible_Elaborated
Heap_Access_Var
Heap_Access_Ref
Default_Var
Activation_Link
Matrix_Var
Null_Subprogram
Array_Var
Exception_Var
Activation_State
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 6
164f 164f typ_a_adr 3b TR10:1b
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1650 1650 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47)
Matrix_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 7
1651 1651 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1652 1652 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47)
Matrix_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 7
1653 1653 typ_a_adr 3c TR10:1c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1654 1654 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47)
Matrix_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 7
1655 1655 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1656 1656 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x47)
Matrix_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 7
1657 1657 typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1658 1658 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49)
Float_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 9
1659 1659 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
165a 165a seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49)
Float_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 9
165b 165b typ_a_adr 3f TR10:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TR10:1e
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
165c 165c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49)
Float_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 9
165d 165d typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
165e 165e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49)
Float_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 9
165f 165f typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1660 1660 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49)
Float_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame 9
1661 1661 typ_a_adr 3d TR10:1d
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1662 1662 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a)
Heap_Access_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame a
1663 1663 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1664 1664 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a)
Heap_Access_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame a
1665 1665 typ_a_adr 37 TR14:17
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1666 1666 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a)
Heap_Access_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame a
1667 1667 typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1668 1668 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a)
Heap_Access_Var
typ_b_adr 03 GP03
typ_c_lit 1
typ_frame a
1669 1669 typ_a_adr 3a TR16:1a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
166a 166a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
166b 166b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
166c 166c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
166d 166d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
166e 166e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
166f 166f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1670 1670 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
1671 1671 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1672 1672 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
1673 1673 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 35 TR14:15
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1674 1674 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
1675 1675 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 36 TR14:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1676 1676 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
1677 1677 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR14:18
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1678 1678 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62)
Auxiliary_Mark
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 2
1679 1679 typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
167a 167a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
167b 167b typ_a_adr 33 TR16:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
167c 167c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
167d 167d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 32 TR14:12
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
167e 167e seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
167f 167f typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 33 TR14:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1680 1680 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
1681 1681 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1682 1682 seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
1683 1683 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 34 TR14:14
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1684 1684 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64)
Subprogram_Ref_For_Call
Variable_Ref
Subprogram_Ref_For_Call_Elaborated
Subprogram_Ref_For_Call_Visible
Subprogram_Ref_For_Call_Visible_Elaborated
Accept_Subprogram_Ref
Interface_Subprogram_Ref
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 4
1685 1685 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1686 1686 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65)
Entry_Var
Family_Var
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 5
1687 1687 typ_a_adr 38 TR16:18
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
1688 1688 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65)
Entry_Var
Family_Var
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 5
1689 1689 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
168a 168a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65)
Entry_Var
Family_Var
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 5
168b 168b typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
168c 168c seq_br_type 4 Call False; Flow C cc=False 0x169e
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65)
Entry_Var
Family_Var
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 5
168d 168d typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
168e 168e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169e
seq_br_type 5 Call True
seq_branch_adr 169e OF_KIND_ERROR
seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65)
Entry_Var
Family_Var
typ_b_adr 03 GP03
typ_c_lit 0
typ_frame 5
168f 168f seq_br_type a Unconditional Return; Flow R
1690 ; --------------------------------------------------------------------------------------
1690 ; Comes from:
1690 ; 13a8 C from color 0x1300
1690 ; 13b0 C from color 0x1300
1690 ; 13b9 C from color 0x1300
1690 ; 13c3 C from color 0x1300
1690 ; 13c8 C from color 0x1300
1690 ; --------------------------------------------------------------------------------------
1690 1690 seq_br_type a Unconditional Return; Flow R
typ_alu_func 13 ONES
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1691 ; --------------------------------------------------------------------------------------
1691 ; Comes from:
1691 ; 1300 C from color 0x1300
1691 ; 13ac C from color 0x1300
1691 ; 13b4 C from color 0x1300
1691 ; 13be C from color 0x1300
1691 ; 13cd C from color 0x1300
1691 ; --------------------------------------------------------------------------------------
1691 1691 seq_br_type a Unconditional Return; Flow R
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1692 ; --------------------------------------------------------------------------------------
1692 ; Comes from:
1692 ; 13aa C from color 0x1300
1692 ; 13b2 C from color 0x1300
1692 ; 13bb C from color 0x1300
1692 ; 13c5 C from color 0x1300
1692 ; 13ca C from color 0x1300
1692 ; --------------------------------------------------------------------------------------
1692 1692 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169c
seq_br_type 5 Call True
seq_branch_adr 169c CLASS_EVENT_FAILED
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 10 NOT_A
1693 1693 seq_br_type a Unconditional Return; Flow R
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1694 ; --------------------------------------------------------------------------------------
1694 ; Comes from:
1694 ; 13ae C from color 0x1300
1694 ; 13b6 C from color 0x1300
1694 ; 13c0 C from color 0x1300
1694 ; 13cf C from color 0x1300
1694 ; --------------------------------------------------------------------------------------
1694 1694 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x169c
seq_br_type 5 Call True
seq_branch_adr 169c CLASS_EVENT_FAILED
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 0 PASS_A
1695 1695 seq_br_type a Unconditional Return; Flow R
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1696 ; --------------------------------------------------------------------------------------
1696 ; Comes from:
1696 ; 1302 C True from color 0x1300
1696 ; 1303 C True from color 0x1300
1696 ; 1304 C True from color 0x1300
1696 ; 1305 C True from color 0x1300
1696 ; 1306 C True from color 0x1300
1696 ; 1307 C True from color 0x1300
1696 ; 1308 C True from color 0x1300
1696 ; 130a C from color 0x1300
1696 ; 130d C from color 0x1300
1696 ; 1310 C from color 0x1300
1696 ; 1313 C from color 0x1300
1696 ; 1316 C from color 0x1300
1696 ; 1319 C from color 0x1300
1696 ; 131c C from color 0x1300
1696 ; 131f C from color 0x1300
1696 ; 1340 C True from color 0x1300
1696 ; 1341 C True from color 0x1300
1696 ; 1342 C True from color 0x1300
1696 ; 1343 C True from color 0x1300
1696 ; 1344 C True from color 0x1300
1696 ; 1345 C True from color 0x1300
1696 ; 1346 C True from color 0x1300
1696 ; 1348 C from color 0x1300
1696 ; 134b C from color 0x1300
1696 ; 134e C from color 0x1300
1696 ; 1351 C from color 0x1300
1696 ; 1354 C from color 0x1300
1696 ; 1357 C from color 0x1300
1696 ; 135a C from color 0x1300
1696 ; 135d C from color 0x1300
1696 ; --------------------------------------------------------------------------------------
1696 A_EQ_L_FAILED:
1696 1696 <halt> ; Flow R
1697 1697 seq_br_type a Unconditional Return; Flow R
1698 ; --------------------------------------------------------------------------------------
1698 ; Comes from:
1698 ; 1321 C True from color 0x1300
1698 ; 1322 C True from color 0x1300
1698 ; 1323 C True from color 0x1300
1698 ; 1324 C True from color 0x1300
1698 ; 1325 C True from color 0x1300
1698 ; 1326 C True from color 0x1300
1698 ; 1327 C True from color 0x1300
1698 ; 1329 C from color 0x1300
1698 ; 132c C from color 0x1300
1698 ; 132f C from color 0x1300
1698 ; 1332 C from color 0x1300
1698 ; 1335 C from color 0x1300
1698 ; 1338 C from color 0x1300
1698 ; 133b C from color 0x1300
1698 ; 133e C from color 0x1300
1698 ; 135f C True from color 0x1300
1698 ; 1360 C True from color 0x1300
1698 ; 1361 C True from color 0x1300
1698 ; 1362 C True from color 0x1300
1698 ; 1363 C True from color 0x1300
1698 ; 1364 C True from color 0x1300
1698 ; 1365 C True from color 0x1300
1698 ; 1367 C from color 0x1300
1698 ; 136a C from color 0x1300
1698 ; 136d C from color 0x1300
1698 ; 1370 C from color 0x1300
1698 ; 1373 C from color 0x1300
1698 ; 1376 C from color 0x1300
1698 ; 1379 C from color 0x1300
1698 ; 137c C from color 0x1300
1698 ; --------------------------------------------------------------------------------------
1698 B_EQ_L_FAILED:
1698 1698 <halt> ; Flow R
1699 1699 seq_br_type a Unconditional Return; Flow R
169a ; --------------------------------------------------------------------------------------
169a ; Comes from:
169a ; 137f C True from color 0x1300
169a ; 1380 C True from color 0x1300
169a ; 1381 C True from color 0x1300
169a ; 1382 C True from color 0x1300
169a ; 1383 C True from color 0x1300
169a ; 1384 C True from color 0x1300
169a ; 1385 C True from color 0x1300
169a ; 1389 C True from color 0x1300
169a ; 138a C True from color 0x1300
169a ; 138b C True from color 0x1300
169a ; 138c C True from color 0x1300
169a ; 138d C True from color 0x1300
169a ; 138e C True from color 0x1300
169a ; 138f C True from color 0x1300
169a ; 1391 C from color 0x1300
169a ; 1394 C from color 0x1300
169a ; 1397 C from color 0x1300
169a ; 139a C from color 0x1300
169a ; 139d C from color 0x1300
169a ; 13a0 C from color 0x1300
169a ; 13a3 C from color 0x1300
169a ; 13a6 C from color 0x1300
169a ; --------------------------------------------------------------------------------------
169a A_EQ_B_FAILED:
169a 169a <halt> ; Flow R
169b 169b seq_br_type a Unconditional Return; Flow R
169c ; --------------------------------------------------------------------------------------
169c ; Comes from:
169c ; 01a8 C True from color UE_CLASS
169c ; 1692 C True from color 0x1692
169c ; 1694 C True from color 0x1694
169c ; --------------------------------------------------------------------------------------
169c CLASS_EVENT_FAILED:
169c 169c <halt> ; Flow R
169d 169d seq_br_type a Unconditional Return; Flow R
169e ; --------------------------------------------------------------------------------------
169e ; Comes from:
169e ; 13d1 C True from color 0x1300
169e ; 13d3 C False from color 0x1300
169e ; 13d5 C True from color 0x1300
169e ; 13d7 C True from color 0x1300
169e ; 13d9 C True from color 0x1300
169e ; 13db C True from color 0x1300
169e ; 13dd C True from color 0x1300
169e ; 13df C True from color 0x1300
169e ; 13e1 C True from color 0x1300
169e ; 13e3 C False from color 0x1300
169e ; 13e5 C False from color 0x1300
169e ; 13e7 C True from color 0x1300
169e ; 13e9 C True from color 0x1300
169e ; 13eb C True from color 0x1300
169e ; 13ed C True from color 0x1300
169e ; 13ef C True from color 0x1300
169e ; 13f1 C True from color 0x1300
169e ; 13f3 C False from color 0x1300
169e ; 13f5 C False from color 0x1300
169e ; 13f7 C False from color 0x1300
169e ; 13f9 C False from color 0x1300
169e ; 13fb C False from color 0x1300
169e ; 13fd C True from color 0x1300
169e ; 13ff C False from color 0x1300
169e ; 1401 C True from color 0x1300
169e ; 1403 C False from color 0x1300
169e ; 1405 C False from color 0x1300
169e ; 1407 C False from color 0x1300
169e ; 1409 C True from color 0x1300
169e ; 140b C True from color 0x1300
169e ; 140d C True from color 0x1300
169e ; 140f C True from color 0x1300
169e ; 1411 C True from color 0x1300
169e ; 1413 C False from color 0x1300
169e ; 1415 C False from color 0x1300
169e ; 1417 C False from color 0x1300
169e ; 1419 C True from color 0x1300
169e ; 141b C False from color 0x1300
169e ; 141d C False from color 0x1300
169e ; 141f C False from color 0x1300
169e ; 1421 C True from color 0x1300
169e ; 1423 C False from color 0x1300
169e ; 1425 C False from color 0x1300
169e ; 1427 C False from color 0x1300
169e ; 1429 C True from color 0x1300
169e ; 142b C True from color 0x1300
169e ; 142d C True from color 0x1300
169e ; 142f C True from color 0x1300
169e ; 1431 C True from color 0x1300
169e ; 1433 C False from color 0x1300
169e ; 1435 C False from color 0x1300
169e ; 1437 C False from color 0x1300
169e ; 1439 C True from color 0x1300
169e ; 143b C True from color 0x1300
169e ; 143d C False from color 0x1300
169e ; 143f C False from color 0x1300
169e ; 1442 C True from color 0x1300
169e ; 1444 C True from color 0x1300
169e ; 1446 C True from color 0x1300
169e ; 1448 C False from color 0x1300
169e ; 144a C False from color 0x1300
169e ; 144c C False from color 0x1300
169e ; 144e C True from color 0x1300
169e ; 1450 C True from color 0x1300
169e ; 1452 C True from color 0x1300
169e ; 1454 C False from color 0x1300
169e ; 1456 C True from color 0x1300
169e ; 1458 C False from color 0x1300
169e ; 145a C False from color 0x1300
169e ; 145c C False from color 0x1300
169e ; 145e C True from color 0x1300
169e ; 1460 C False from color 0x1300
169e ; 1462 C False from color 0x1300
169e ; 1464 C False from color 0x1300
169e ; 1466 C True from color 0x1300
169e ; 1468 C False from color 0x1300
169e ; 146a C False from color 0x1300
169e ; 146c C False from color 0x1300
169e ; 146e C True from color 0x1300
169e ; 1470 C True from color 0x1300
169e ; 1472 C True from color 0x1300
169e ; 1474 C True from color 0x1300
169e ; 1476 C True from color 0x1300
169e ; 1478 C False from color 0x1300
169e ; 147a C False from color 0x1300
169e ; 147c C False from color 0x1300
169e ; 147e C True from color 0x1300
169e ; 1480 C True from color 0x1300
169e ; 1482 C True from color 0x1300
169e ; 1484 C True from color 0x1300
169e ; 1486 C True from color 0x1300
169e ; 1488 C False from color 0x1300
169e ; 148a C True from color 0x1300
169e ; 148c C True from color 0x1300
169e ; 148e C True from color 0x1300
169e ; 1490 C True from color 0x1300
169e ; 1492 C True from color 0x1300
169e ; 1494 C True from color 0x1300
169e ; 1496 C True from color 0x1300
169e ; 1498 C False from color 0x1300
169e ; 149a C False from color 0x1300
169e ; 149c C False from color 0x1300
169e ; 149e C True from color 0x1300
169e ; 14a0 C True from color 0x1300
169e ; 14a2 C True from color 0x1300
169e ; 14a4 C True from color 0x1300
169e ; 14a6 C True from color 0x1300
169e ; 14a8 C False from color 0x1300
169e ; 14aa C False from color 0x1300
169e ; 14ac C False from color 0x1300
169e ; 14ae C True from color 0x1300
169e ; 14b0 C True from color 0x1300
169e ; 14b2 C True from color 0x1300
169e ; 14b4 C True from color 0x1300
169e ; 14b6 C True from color 0x1300
169e ; 14b8 C False from color 0x1300
169e ; 14ba C False from color 0x1300
169e ; 14bc C False from color 0x1300
169e ; 14be C True from color 0x1300
169e ; 14c0 C True from color 0x1300
169e ; 14c2 C True from color 0x1300
169e ; 14c4 C True from color 0x1300
169e ; 14c6 C True from color 0x1300
169e ; 14c8 C False from color 0x1300
169e ; 14ca C True from color 0x1300
169e ; 14cc C True from color 0x1300
169e ; 14ce C True from color 0x1300
169e ; 14d0 C True from color 0x1300
169e ; 14d2 C True from color 0x1300
169e ; 14d4 C True from color 0x1300
169e ; 14d6 C True from color 0x1300
169e ; 14d8 C False from color 0x1300
169e ; 14da C False from color 0x1300
169e ; 14dc C False from color 0x1300
169e ; 14de C False from color 0x1300
169e ; 14e0 C True from color 0x1300
169e ; 14e2 C True from color 0x1300
169e ; 14e4 C True from color 0x1300
169e ; 14e6 C True from color 0x1300
169e ; 14e8 C False from color 0x1300
169e ; 14ea C False from color 0x1300
169e ; 14ec C False from color 0x1300
169e ; 14ee C False from color 0x1300
169e ; 14f0 C True from color 0x1300
169e ; 14f2 C True from color 0x1300
169e ; 14f4 C True from color 0x1300
169e ; 14f6 C True from color 0x1300
169e ; 14f8 C False from color 0x1300
169e ; 14fa C False from color 0x1300
169e ; 14fc C False from color 0x1300
169e ; 14fe C False from color 0x1300
169e ; 1500 C False from color 0x1300
169e ; 1502 C True from color 0x1300
169e ; 1504 C True from color 0x1300
169e ; 1506 C True from color 0x1300
169e ; 1508 C False from color 0x1300
169e ; 150a C False from color 0x1300
169e ; 150c C False from color 0x1300
169e ; 150e C False from color 0x1300
169e ; 1510 C False from color 0x1300
169e ; 1512 C True from color 0x1300
169e ; 1514 C True from color 0x1300
169e ; 1516 C True from color 0x1300
169e ; 1518 C False from color 0x1300
169e ; 151a C False from color 0x1300
169e ; 151c C False from color 0x1300
169e ; 151e C False from color 0x1300
169e ; 1520 C False from color 0x1300
169e ; 1522 C True from color 0x1300
169e ; 1524 C True from color 0x1300
169e ; 1526 C True from color 0x1300
169e ; 1528 C False from color 0x1300
169e ; 152a C False from color 0x1300
169e ; 152c C False from color 0x1300
169e ; 152e C False from color 0x1300
169e ; 1530 C False from color 0x1300
169e ; 1532 C True from color 0x1300
169e ; 1534 C True from color 0x1300
169e ; 1536 C True from color 0x1300
169e ; 1538 C False from color 0x1300
169e ; 153a C False from color 0x1300
169e ; 153c C False from color 0x1300
169e ; 153e C True from color 0x1300
169e ; 1540 C True from color 0x1300
169e ; 1542 C True from color 0x1300
169e ; 1544 C True from color 0x1300
169e ; 1546 C True from color 0x1300
169e ; 1548 C False from color 0x1300
169e ; 154a C False from color 0x1300
169e ; 154c C False from color 0x1300
169e ; 154e C True from color 0x1300
169e ; 1550 C False from color 0x1300
169e ; 1552 C True from color 0x1300
169e ; 1554 C True from color 0x1300
169e ; 1556 C True from color 0x1300
169e ; 1558 C False from color 0x1300
169e ; 155a C False from color 0x1300
169e ; 155c C True from color 0x1300
169e ; 155e C True from color 0x1300
169e ; 1560 C False from color 0x1300
169e ; 1562 C False from color 0x1300
169e ; 1564 C False from color 0x1300
169e ; 1566 C False from color 0x1300
169e ; 1568 C True from color 0x1300
169e ; 156a C True from color 0x1300
169e ; 156c C False from color 0x1300
169e ; 156e C True from color 0x1300
169e ; 1570 C False from color 0x1300
169e ; 1572 C False from color 0x1300
169e ; 1574 C False from color 0x1300
169e ; 1576 C False from color 0x1300
169e ; 1578 C True from color 0x1300
169e ; 157a C True from color 0x1300
169e ; 157c C False from color 0x1300
169e ; 157e C True from color 0x1300
169e ; 1580 C True from color 0x1300
169e ; 1582 C False from color 0x1300
169e ; 1584 C False from color 0x1300
169e ; 1586 C False from color 0x1300
169e ; 1588 C False from color 0x1300
169e ; 158a C False from color 0x1300
169e ; 158c C False from color 0x1300
169e ; 158e C True from color 0x1300
169e ; 1590 C True from color 0x1300
169e ; 1592 C False from color 0x1300
169e ; 1594 C True from color 0x1300
169e ; 1596 C False from color 0x1300
169e ; 1598 C True from color 0x1300
169e ; 159a C False from color 0x1300
169e ; 159c C True from color 0x1300
169e ; 159e C False from color 0x1300
169e ; 15a0 C True from color 0x1300
169e ; 15a2 C False from color 0x1300
169e ; 15a4 C True from color 0x1300
169e ; 15a6 C False from color 0x1300
169e ; 15a8 C True from color 0x1300
169e ; 15aa C False from color 0x1300
169e ; 15ac C True from color 0x1300
169e ; 15ae C False from color 0x1300
169e ; 15b0 C True from color 0x1300
169e ; 15b2 C False from color 0x1300
169e ; 15b4 C True from color 0x1300
169e ; 15b6 C False from color 0x1300
169e ; 15b8 C True from color 0x1300
169e ; 15ba C False from color 0x1300
169e ; 15bc C True from color 0x1300
169e ; 15be C False from color 0x1300
169e ; 15c0 C True from color 0x1300
169e ; 15c2 C False from color 0x1300
169e ; 15c4 C True from color 0x1300
169e ; 15c6 C False from color 0x1300
169e ; 15c8 C True from color 0x1300
169e ; 15ca C True from color 0x1300
169e ; 15cc C True from color 0x1300
169e ; 15ce C False from color 0x1300
169e ; 15d0 C True from color 0x1300
169e ; 15d2 C False from color 0x1300
169e ; 15d4 C False from color 0x1300
169e ; 15d6 C False from color 0x1300
169e ; 15d8 C True from color 0x1300
169e ; 15da C True from color 0x1300
169e ; 15dc C False from color 0x1300
169e ; 15de C False from color 0x1300
169e ; 15e0 C True from color 0x1300
169e ; 15e2 C True from color 0x1300
169e ; 15e4 C False from color 0x1300
169e ; 15e6 C True from color 0x1300
169e ; 15e8 C True from color 0x1300
169e ; 15ea C False from color 0x1300
169e ; 15ec C False from color 0x1300
169e ; 15ee C False from color 0x1300
169e ; 15f0 C True from color 0x1300
169e ; 15f2 C True from color 0x1300
169e ; 15f4 C True from color 0x1300
169e ; 15f6 C True from color 0x1300
169e ; 15f8 C True from color 0x1300
169e ; 15fa C False from color 0x1300
169e ; 15fc C False from color 0x1300
169e ; 15fe C False from color 0x1300
169e ; 1600 C True from color 0x1300
169e ; 1602 C True from color 0x1300
169e ; 1604 C True from color 0x1300
169e ; 1606 C True from color 0x1300
169e ; 1608 C True from color 0x1300
169e ; 160a C True from color 0x1300
169e ; 160c C False from color 0x1300
169e ; 160e C False from color 0x1300
169e ; 1610 C True from color 0x1300
169e ; 1612 C True from color 0x1300
169e ; 1614 C False from color 0x1300
169e ; 1616 C False from color 0x1300
169e ; 1618 C True from color 0x1300
169e ; 161a C True from color 0x1300
169e ; 161c C False from color 0x1300
169e ; 161e C False from color 0x1300
169e ; 1620 C True from color 0x1300
169e ; 1622 C True from color 0x1300
169e ; 1624 C False from color 0x1300
169e ; 1626 C False from color 0x1300
169e ; 1628 C True from color 0x1300
169e ; 162a C True from color 0x1300
169e ; 162c C False from color 0x1300
169e ; 162e C False from color 0x1300
169e ; 1630 C True from color 0x1300
169e ; 1632 C True from color 0x1300
169e ; 1634 C False from color 0x1300
169e ; 1636 C False from color 0x1300
169e ; 1638 C True from color 0x1300
169e ; 163a C True from color 0x1300
169e ; 163c C False from color 0x1300
169e ; 163e C False from color 0x1300
169e ; 1640 C True from color 0x1300
169e ; 1642 C True from color 0x1300
169e ; 1644 C False from color 0x1300
169e ; 1646 C False from color 0x1300
169e ; 1648 C True from color 0x1300
169e ; 164a C True from color 0x1300
169e ; 164c C False from color 0x1300
169e ; 164e C False from color 0x1300
169e ; 1650 C True from color 0x1300
169e ; 1652 C False from color 0x1300
169e ; 1654 C True from color 0x1300
169e ; 1656 C False from color 0x1300
169e ; 1658 C True from color 0x1300
169e ; 165a C False from color 0x1300
169e ; 165c C True from color 0x1300
169e ; 165e C True from color 0x1300
169e ; 1660 C False from color 0x1300
169e ; 1662 C True from color 0x1300
169e ; 1664 C False from color 0x1300
169e ; 1666 C True from color 0x1300
169e ; 1668 C False from color 0x1300
169e ; 166a C True from color 0x1300
169e ; 166c C False from color 0x1300
169e ; 166e C False from color 0x1300
169e ; 1670 C False from color 0x1300
169e ; 1672 C False from color 0x1300
169e ; 1674 C False from color 0x1300
169e ; 1676 C False from color 0x1300
169e ; 1678 C False from color 0x1300
169e ; 167a C True from color 0x1300
169e ; 167c C True from color 0x1300
169e ; 167e C False from color 0x1300
169e ; 1680 C False from color 0x1300
169e ; 1682 C False from color 0x1300
169e ; 1684 C True from color 0x1300
169e ; 1686 C True from color 0x1300
169e ; 1688 C True from color 0x1300
169e ; 168a C True from color 0x1300
169e ; 168c C False from color 0x1300
169e ; 168e C True from color 0x1300
169e ; --------------------------------------------------------------------------------------
169e OF_KIND_ERROR:
169e 169e <halt> ; Flow R
169f 169f seq_br_type a Unconditional Return; Flow R
16a0 16a0 <halt> ; Flow R
16a1 16a1 <halt> ; Flow R
16a2 16a2 <halt> ; Flow R
16a3 16a3 <halt> ; Flow R
16a4 16a4 <halt> ; Flow R
16a5 16a5 <halt> ; Flow R
16a6 16a6 <halt> ; Flow R
16a7 16a7 <halt> ; Flow R
16a8 16a8 <halt> ; Flow R
16a9 16a9 <halt> ; Flow R
16aa 16aa <halt> ; Flow R
16ab 16ab <halt> ; Flow R
16ac 16ac <halt> ; Flow R
16ad 16ad <halt> ; Flow R
16ae 16ae <halt> ; Flow R
16af 16af <halt> ; Flow R
16b0 16b0 <halt> ; Flow R
16b1 16b1 <halt> ; Flow R
16b2 16b2 <halt> ; Flow R
16b3 16b3 <halt> ; Flow R
16b4 16b4 <halt> ; Flow R
16b5 16b5 <halt> ; Flow R
16b6 16b6 <halt> ; Flow R
16b7 16b7 <halt> ; Flow R
16b8 16b8 <halt> ; Flow R
16b9 16b9 <halt> ; Flow R
16ba 16ba <halt> ; Flow R
16bb 16bb <halt> ; Flow R
16bc 16bc <halt> ; Flow R
16bd 16bd <halt> ; Flow R
16be 16be <halt> ; Flow R
16bf 16bf <halt> ; Flow R
16c0 16c0 <halt> ; Flow R
16c1 16c1 <halt> ; Flow R
16c2 16c2 <halt> ; Flow R
16c3 16c3 <halt> ; Flow R
16c4 16c4 <halt> ; Flow R
16c5 16c5 <halt> ; Flow R
16c6 16c6 <halt> ; Flow R
16c7 16c7 <halt> ; Flow R
16c8 16c8 <halt> ; Flow R
16c9 16c9 <halt> ; Flow R
16ca 16ca <halt> ; Flow R
16cb 16cb <halt> ; Flow R
16cc 16cc <halt> ; Flow R
16cd 16cd <halt> ; Flow R
16ce 16ce <halt> ; Flow R
16cf 16cf <halt> ; Flow R
16d0 16d0 <halt> ; Flow R
16d1 16d1 <halt> ; Flow R
16d2 16d2 <halt> ; Flow R
16d3 16d3 <halt> ; Flow R
16d4 16d4 <halt> ; Flow R
16d5 16d5 <halt> ; Flow R
16d6 16d6 <halt> ; Flow R
16d7 16d7 <halt> ; Flow R
16d8 16d8 <halt> ; Flow R
16d9 16d9 <halt> ; Flow R
16da 16da <halt> ; Flow R
16db 16db <halt> ; Flow R
16dc 16dc <halt> ; Flow R
16dd 16dd <halt> ; Flow R
16de 16de <halt> ; Flow R
16df 16df <halt> ; Flow R
16e0 16e0 <halt> ; Flow R
16e1 16e1 <halt> ; Flow R
16e2 16e2 <halt> ; Flow R
16e3 16e3 <halt> ; Flow R
16e4 16e4 <halt> ; Flow R
16e5 16e5 <halt> ; Flow R
16e6 16e6 <halt> ; Flow R
16e7 16e7 <halt> ; Flow R
16e8 16e8 <halt> ; Flow R
16e9 16e9 <halt> ; Flow R
16ea 16ea <halt> ; Flow R
16eb 16eb <halt> ; Flow R
16ec 16ec <halt> ; Flow R
16ed 16ed <halt> ; Flow R
16ee 16ee <halt> ; Flow R
16ef 16ef <halt> ; Flow R
16f0 16f0 <halt> ; Flow R
16f1 16f1 <halt> ; Flow R
16f2 16f2 <halt> ; Flow R
16f3 16f3 <halt> ; Flow R
16f4 16f4 <halt> ; Flow R
16f5 16f5 <halt> ; Flow R
16f6 16f6 <halt> ; Flow R
16f7 16f7 <halt> ; Flow R
16f8 16f8 <halt> ; Flow R
16f9 16f9 <halt> ; Flow R
16fa 16fa <halt> ; Flow R
16fb 16fb <halt> ; Flow R
16fc 16fc <halt> ; Flow R
16fd 16fd <halt> ; Flow R
16fe 16fe <halt> ; Flow R
16ff 16ff <halt> ; Flow R
1700 1700 <halt> ; Flow R
1701 1701 <halt> ; Flow R
1702 1702 <halt> ; Flow R
1703 1703 <halt> ; Flow R
1704 1704 <halt> ; Flow R
1705 1705 <halt> ; Flow R
1706 1706 <halt> ; Flow R
1707 1707 <halt> ; Flow R
1708 1708 <halt> ; Flow R
1709 1709 <halt> ; Flow R
170a 170a <halt> ; Flow R
170b 170b <halt> ; Flow R
170c 170c <halt> ; Flow R
170d 170d <halt> ; Flow R
170e 170e <halt> ; Flow R
170f 170f <halt> ; Flow R
1710 1710 <halt> ; Flow R
1711 1711 <halt> ; Flow R
1712 1712 <halt> ; Flow R
1713 1713 <halt> ; Flow R
1714 1714 <halt> ; Flow R
1715 1715 <halt> ; Flow R
1716 1716 <halt> ; Flow R
1717 1717 <halt> ; Flow R
1718 1718 <halt> ; Flow R
1719 1719 <halt> ; Flow R
171a 171a <halt> ; Flow R
171b 171b <halt> ; Flow R
171c 171c <halt> ; Flow R
171d 171d <halt> ; Flow R
171e 171e <halt> ; Flow R
171f 171f <halt> ; Flow R
1720 1720 <halt> ; Flow R
1721 1721 <halt> ; Flow R
1722 1722 <halt> ; Flow R
1723 1723 <halt> ; Flow R
1724 1724 <halt> ; Flow R
1725 1725 <halt> ; Flow R
1726 1726 <halt> ; Flow R
1727 1727 <halt> ; Flow R
1728 1728 <halt> ; Flow R
1729 1729 <halt> ; Flow R
172a 172a <halt> ; Flow R
172b 172b <halt> ; Flow R
172c 172c <halt> ; Flow R
172d 172d <halt> ; Flow R
172e 172e <halt> ; Flow R
172f 172f <halt> ; Flow R
1730 1730 <halt> ; Flow R
1731 1731 <halt> ; Flow R
1732 1732 <halt> ; Flow R
1733 1733 <halt> ; Flow R
1734 1734 <halt> ; Flow R
1735 1735 <halt> ; Flow R
1736 1736 <halt> ; Flow R
1737 1737 <halt> ; Flow R
1738 1738 <halt> ; Flow R
1739 1739 <halt> ; Flow R
173a 173a <halt> ; Flow R
173b 173b <halt> ; Flow R
173c 173c <halt> ; Flow R
173d 173d <halt> ; Flow R
173e 173e <halt> ; Flow R
173f 173f <halt> ; Flow R
1740 1740 <halt> ; Flow R
1741 1741 <halt> ; Flow R
1742 1742 <halt> ; Flow R
1743 1743 <halt> ; Flow R
1744 1744 <halt> ; Flow R
1745 1745 <halt> ; Flow R
1746 1746 <halt> ; Flow R
1747 1747 <halt> ; Flow R
1748 1748 <halt> ; Flow R
1749 1749 <halt> ; Flow R
174a 174a <halt> ; Flow R
174b 174b <halt> ; Flow R
174c 174c <halt> ; Flow R
174d 174d <halt> ; Flow R
174e 174e <halt> ; Flow R
174f 174f <halt> ; Flow R
1750 1750 <halt> ; Flow R
1751 1751 <halt> ; Flow R
1752 1752 <halt> ; Flow R
1753 1753 <halt> ; Flow R
1754 1754 <halt> ; Flow R
1755 1755 <halt> ; Flow R
1756 1756 <halt> ; Flow R
1757 1757 <halt> ; Flow R
1758 1758 <halt> ; Flow R
1759 1759 <halt> ; Flow R
175a 175a <halt> ; Flow R
175b 175b <halt> ; Flow R
175c 175c <halt> ; Flow R
175d 175d <halt> ; Flow R
175e 175e <halt> ; Flow R
175f 175f <halt> ; Flow R
1760 1760 <halt> ; Flow R
1761 1761 <halt> ; Flow R
1762 1762 <halt> ; Flow R
1763 1763 <halt> ; Flow R
1764 1764 <halt> ; Flow R
1765 1765 <halt> ; Flow R
1766 1766 <halt> ; Flow R
1767 1767 <halt> ; Flow R
1768 1768 <halt> ; Flow R
1769 1769 <halt> ; Flow R
176a 176a <halt> ; Flow R
176b 176b <halt> ; Flow R
176c 176c <halt> ; Flow R
176d 176d <halt> ; Flow R
176e 176e <halt> ; Flow R
176f 176f <halt> ; Flow R
1770 1770 <halt> ; Flow R
1771 1771 <halt> ; Flow R
1772 1772 <halt> ; Flow R
1773 1773 <halt> ; Flow R
1774 1774 <halt> ; Flow R
1775 1775 <halt> ; Flow R
1776 1776 <halt> ; Flow R
1777 1777 <halt> ; Flow R
1778 1778 <halt> ; Flow R
1779 1779 <halt> ; Flow R
177a 177a <halt> ; Flow R
177b 177b <halt> ; Flow R
177c 177c <halt> ; Flow R
177d 177d <halt> ; Flow R
177e 177e <halt> ; Flow R
177f 177f <halt> ; Flow R
1780 1780 <halt> ; Flow R
1781 1781 <halt> ; Flow R
1782 1782 <halt> ; Flow R
1783 1783 <halt> ; Flow R
1784 1784 <halt> ; Flow R
1785 1785 <halt> ; Flow R
1786 1786 <halt> ; Flow R
1787 1787 <halt> ; Flow R
1788 1788 <halt> ; Flow R
1789 1789 <halt> ; Flow R
178a 178a <halt> ; Flow R
178b 178b <halt> ; Flow R
178c 178c <halt> ; Flow R
178d 178d <halt> ; Flow R
178e 178e <halt> ; Flow R
178f 178f <halt> ; Flow R
1790 1790 <halt> ; Flow R
1791 1791 <halt> ; Flow R
1792 1792 <halt> ; Flow R
1793 1793 <halt> ; Flow R
1794 1794 <halt> ; Flow R
1795 1795 <halt> ; Flow R
1796 1796 <halt> ; Flow R
1797 1797 <halt> ; Flow R
1798 1798 <halt> ; Flow R
1799 1799 <halt> ; Flow R
179a 179a <halt> ; Flow R
179b 179b <halt> ; Flow R
179c 179c <halt> ; Flow R
179d 179d <halt> ; Flow R
179e 179e <halt> ; Flow R
179f 179f <halt> ; Flow R
17a0 17a0 <halt> ; Flow R
17a1 17a1 <halt> ; Flow R
17a2 17a2 <halt> ; Flow R
17a3 17a3 <halt> ; Flow R
17a4 17a4 <halt> ; Flow R
17a5 17a5 <halt> ; Flow R
17a6 17a6 <halt> ; Flow R
17a7 17a7 <halt> ; Flow R
17a8 17a8 <halt> ; Flow R
17a9 17a9 <halt> ; Flow R
17aa 17aa <halt> ; Flow R
17ab 17ab <halt> ; Flow R
17ac 17ac <halt> ; Flow R
17ad 17ad <halt> ; Flow R
17ae 17ae <halt> ; Flow R
17af 17af <halt> ; Flow R
17b0 17b0 <halt> ; Flow R
17b1 17b1 <halt> ; Flow R
17b2 17b2 <halt> ; Flow R
17b3 17b3 <halt> ; Flow R
17b4 17b4 <halt> ; Flow R
17b5 17b5 <halt> ; Flow R
17b6 17b6 <halt> ; Flow R
17b7 17b7 <halt> ; Flow R
17b8 17b8 <halt> ; Flow R
17b9 17b9 <halt> ; Flow R
17ba 17ba <halt> ; Flow R
17bb 17bb <halt> ; Flow R
17bc 17bc <halt> ; Flow R
17bd 17bd <halt> ; Flow R
17be 17be <halt> ; Flow R
17bf 17bf <halt> ; Flow R
17c0 17c0 <halt> ; Flow R
17c1 17c1 <halt> ; Flow R
17c2 17c2 <halt> ; Flow R
17c3 17c3 <halt> ; Flow R
17c4 17c4 <halt> ; Flow R
17c5 17c5 <halt> ; Flow R
17c6 17c6 <halt> ; Flow R
17c7 17c7 <halt> ; Flow R
17c8 17c8 <halt> ; Flow R
17c9 17c9 <halt> ; Flow R
17ca 17ca <halt> ; Flow R
17cb 17cb <halt> ; Flow R
17cc 17cc <halt> ; Flow R
17cd 17cd <halt> ; Flow R
17ce 17ce <halt> ; Flow R
17cf 17cf <halt> ; Flow R
17d0 17d0 <halt> ; Flow R
17d1 17d1 <halt> ; Flow R
17d2 17d2 <halt> ; Flow R
17d3 17d3 <halt> ; Flow R
17d4 17d4 <halt> ; Flow R
17d5 17d5 <halt> ; Flow R
17d6 17d6 <halt> ; Flow R
17d7 17d7 <halt> ; Flow R
17d8 17d8 <halt> ; Flow R
17d9 17d9 <halt> ; Flow R
17da 17da <halt> ; Flow R
17db 17db <halt> ; Flow R
17dc 17dc <halt> ; Flow R
17dd 17dd <halt> ; Flow R
17de 17de <halt> ; Flow R
17df 17df <halt> ; Flow R
17e0 17e0 <halt> ; Flow R
17e1 17e1 <halt> ; Flow R
17e2 17e2 <halt> ; Flow R
17e3 17e3 <halt> ; Flow R
17e4 17e4 <halt> ; Flow R
17e5 17e5 <halt> ; Flow R
17e6 17e6 <halt> ; Flow R
17e7 17e7 <halt> ; Flow R
17e8 17e8 <halt> ; Flow R
17e9 17e9 <halt> ; Flow R
17ea 17ea <halt> ; Flow R
17eb 17eb <halt> ; Flow R
17ec 17ec <halt> ; Flow R
17ed 17ed <halt> ; Flow R
17ee 17ee <halt> ; Flow R
17ef 17ef <halt> ; Flow R
17f0 17f0 <halt> ; Flow R
17f1 17f1 <halt> ; Flow R
17f2 17f2 <halt> ; Flow R
17f3 17f3 <halt> ; Flow R
17f4 17f4 <halt> ; Flow R
17f5 17f5 <halt> ; Flow R
17f6 17f6 <halt> ; Flow R
17f7 17f7 <halt> ; Flow R
17f8 17f8 <halt> ; Flow R
17f9 17f9 <halt> ; Flow R
17fa 17fa <halt> ; Flow R
17fb 17fb <halt> ; Flow R
17fc 17fc <halt> ; Flow R
17fd 17fd <halt> ; Flow R
17fe 17fe <halt> ; Flow R
17ff 17ff <halt> ; Flow R
1800 ; --------------------------------------------------------------------------------------
1800 ; 1800 - 1900 PRIVACY_TEST
1800 ; Comes from:
1800 ; 0313 C from color DIAGNOSTIC_START
1800 ; --------------------------------------------------------------------------------------
1800 1800 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
1801 1801 typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
1802 1802 typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1803 1803 seq_br_type 4 Call False; Flow C cc=False 0x18f1
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1804 1804 seq_br_type 4 Call False; Flow C cc=False 0x18f3
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1805 1805 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1806 1806 seq_br_type 4 Call False; Flow C cc=False 0x18f1
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1807 1807 seq_br_type 4 Call False; Flow C cc=False 0x18f3
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1808 1808 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1809 1809 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
180a 180a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
180b 180b typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
180c 180c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
180d 180d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
180e 180e typ_a_adr 25 TR04:05
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
180f 180f typ_a_adr 24 TR10:04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
1810 1810 typ_a_adr 04 GP04
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1811 1811 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1812 1812 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1813 1813 typ_a_adr 04 GP04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1814 1814 typ_a_adr 04 GP04
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR05:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1815 1815 seq_b_timing 0 Early Condition; Flow J cc=False 0x1811
seq_br_type 0 Branch False
seq_branch_adr 1811 0x1811
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 04 GP04
typ_alu_func 1 A_PLUS_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
1816 1816 typ_b_adr 20 TR10:00
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
1817 1817 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1818 1818 seq_br_type 4 Call False; Flow C cc=False 0x18f1
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1819 1819 seq_br_type 4 Call False; Flow C cc=False 0x18f3
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
181a 181a typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
181b 181b seq_br_type 4 Call False; Flow C cc=False 0x18f1
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
181c 181c seq_br_type 4 Call False; Flow C cc=False 0x18f3
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
181d 181d typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
181e 181e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
181f 181f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1820 1820 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1821 1821 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1822 1822 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1823 1823 typ_a_adr 25 TR04:05
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1824 1824 typ_a_adr 20 TR05:00
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1825 1825 typ_a_adr 04 GP04
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1826 1826 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f1
seq_br_type 5 Call True
seq_branch_adr 18f1 PRIVACY_A_FAILED
seq_cond_sel 2d TYP.PRIVACY_A_OP_PASS (med_late)
typ_a_adr 03 GP03
1827 1827 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f3
seq_br_type 5 Call True
seq_branch_adr 18f3 PRIVACY_B_FAILED
seq_cond_sel 2e TYP.PRIVACY_B_OP_PASS (med_late)
typ_b_adr 03 GP03
1828 1828 typ_a_adr 04 GP04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1829 1829 seq_b_timing 0 Early Condition; Flow J cc=False 0x1826
seq_br_type 0 Branch False
seq_branch_adr 1826 0x1826
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 04 GP04
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
182a 182a typ_a_adr 3a TR14:1a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
182b 182b typ_a_adr 22 TR10:02
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
182c 182c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
182d 182d typ_a_adr 23 TR04:03
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
182e 182e typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
182f 182f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1830 1830 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1831 1831 seq_b_timing 0 Early Condition; Flow J cc=False 0x182f
seq_br_type 0 Branch False
seq_branch_adr 182f 0x182f
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 33 TR04:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
1832 1832 typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1833 1833 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1834 1834 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1835 1835 seq_b_timing 0 Early Condition; Flow J cc=False 0x1833
seq_br_type 0 Branch False
seq_branch_adr 1833 0x1833
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 33 TR04:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
1836 1836 typ_a_adr 25 TR04:05
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1837 1837 seq_br_type 4 Call False; Flow C cc=False 0x18f5
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1838 1838 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1839 1839 seq_b_timing 0 Early Condition; Flow J cc=False 0x1837
seq_br_type 0 Branch False
seq_branch_adr 1837 0x1837
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 33 TR04:13
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
183a 183a typ_a_adr 32 TR04:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
183b 183b typ_a_adr 29 TR16:09
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 16
183c 183c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
183d 183d typ_a_adr 23 TR04:03
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
183e 183e typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
183f 183f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1840 1840 seq_b_timing 0 Early Condition; Flow J cc=False 0x183f
seq_br_type 0 Branch False
seq_branch_adr 183f 0x183f
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1841 1841 typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1842 1842 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f5
seq_br_type 5 Call True
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1843 1843 seq_b_timing 0 Early Condition; Flow J cc=False 0x1842
seq_br_type 0 Branch False
seq_branch_adr 1842 0x1842
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1844 1844 typ_a_adr 25 TR04:05
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
1845 1845 seq_br_type 4 Call False; Flow C cc=False 0x18f5
seq_branch_adr 18f5 PRIVACY_NAMES_EQ_FAILED
seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1846 1846 seq_b_timing 0 Early Condition; Flow J cc=False 0x1845
seq_br_type 0 Branch False
seq_branch_adr 1845 0x1845
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1847 1847 typ_a_adr 27 TR14:07
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
1848 1848 typ_a_adr 27 TR14:07
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 14
1849 1849 seq_br_type 4 Call False; Flow C cc=False 0x18fd
seq_branch_adr 18fd PRIVACY_PATHS_EQ_FAILED
seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
184a 184a typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
184b 184b typ_a_adr 3b TR14:1b
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
184c 184c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18fd
seq_br_type 5 Call True
seq_branch_adr 18fd PRIVACY_PATHS_EQ_FAILED
seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
184d 184d typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
184e 184e typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
184f 184f seq_b_timing 0 Early Condition; Flow J cc=False 0x184c
seq_br_type 0 Branch False
seq_branch_adr 184c 0x184c
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR04:07
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
1850 1850 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1851 1851 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
1852 1852 seq_br_type 4 Call False; Flow C cc=False 0x18fd
seq_branch_adr 18fd PRIVACY_PATHS_EQ_FAILED
seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1853 1853 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1854 1854 typ_a_adr 3b TR14:1b
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
1855 1855 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18fd
seq_br_type 5 Call True
seq_branch_adr 18fd PRIVACY_PATHS_EQ_FAILED
seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1856 1856 seq_b_timing 0 Early Condition; Flow J cc=False 0x1855
seq_br_type 0 Branch False
seq_branch_adr 1855 0x1855
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1857 1857 typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
1858 1858 typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1859 1859 typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
185a 185a typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
185b 185b typ_a_adr 04 GP04
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
185c 185c typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
185d 185d seq_br_type 4 Call False; Flow C cc=False 0x18f7
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
185e 185e typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR05:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
185f 185f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1860 1860 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
1861 1861 typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR05:08
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1862 1862 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1863 1863 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
1864 1864 typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR05:10
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1865 1865 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1866 1866 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
1867 1867 typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 38 TR05:18
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1868 1868 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1869 1869 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
186a 186a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 04 GP04
186b 186b typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
186c 186c seq_br_type 4 Call False; Flow C cc=False 0x18f7
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
186d 186d seq_br_type 4 Call False; Flow C cc=False 0x18f7
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
186e 186e typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR05:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
186f 186f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
1870 1870 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1871 1871 typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1872 1872 typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
1873 1873 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR05:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
1874 1874 typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR05:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1875 1875 seq_br_type 4 Call False; Flow C cc=False 0x18f7
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1876 1876 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1877 1877 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1878 1878 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
1879 1879 typ_a_adr 04 GP04
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
187a 187a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
187b 187b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f7
seq_br_type 5 Call True
seq_branch_adr 18f7 PRIVACY_A_B_FAILED
seq_cond_sel 30 TYP.PRIVACY_BIN_OP_PASS (med_late)
typ_a_adr 04 GP04
typ_b_adr 03 GP03
187c 187c typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
187d 187d typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
187e 187e typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
187f 187f seq_br_type 4 Call False; Flow C cc=False 0x18f9
seq_branch_adr 18f9 PRIVACY_EQ_FAILED
seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1880 1880 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18fb
seq_br_type 5 Call True
seq_branch_adr 18fb PRIVACY_STRUCTURE_FAILED
seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1881 1881 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1882 1882 seq_br_type 4 Call False; Flow C cc=False 0x18f9
seq_branch_adr 18f9 PRIVACY_EQ_FAILED
seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1883 1883 seq_br_type 4 Call False; Flow C cc=False 0x18fb
seq_branch_adr 18fb PRIVACY_STRUCTURE_FAILED
seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1884 1884 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 29 TR10:09
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1885 1885 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18f9
seq_br_type 5 Call True
seq_branch_adr 18f9 PRIVACY_EQ_FAILED
seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1886 1886 seq_br_type 4 Call False; Flow C cc=False 0x18fb
seq_branch_adr 18fb PRIVACY_STRUCTURE_FAILED
seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1887 1887 typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR04:1c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1888 1888 seq_br_type 4 Call False; Flow C cc=False 0x18f9
seq_branch_adr 18f9 PRIVACY_EQ_FAILED
seq_cond_sel 2f TYP.PRIVACY_BIN_EQ_PASS (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
1889 1889 seq_br_type 4 Call False; Flow C cc=False 0x18fb
seq_branch_adr 18fb PRIVACY_STRUCTURE_FAILED
seq_cond_sel 33 TYP.PRIVACY_STRUCTURE (med_late)
typ_a_adr 03 GP03
typ_b_adr 04 GP04
188a 188a typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
188b 188b seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
188c 188c typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
188d 188d seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
188e 188e typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
188f 188f seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
1890 1890 typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
1891 1891 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
1892 1892 typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
1893 1893 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
typ_a_adr 10 TOP
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 4
1894 1894 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
1895 1895 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
1896 1896 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
1897 1897 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 10 TOP
typ_alu_func 1b A_OR_B
typ_b_adr 24 TR10:04
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
1898 1898 typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
1899 1899 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
189a 189a typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
189b 189b seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
typ_a_adr 10 TOP
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 4
189c 189c seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
189d 189d seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
189e 189e seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
189f 189f seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
typ_a_adr 10 TOP
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
18a0 18a0 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
18a1 18a1 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
18a2 18a2 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
18a3 18a3 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
typ_a_adr 10 TOP
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 4
18a4 18a4 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
18a5 18a5 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
18a6 18a6 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
18a7 18a7 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
typ_a_adr 10 TOP
typ_alu_func 1b A_OR_B
typ_b_adr 24 TR10:04
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
18a8 18a8 seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_a_adr 10 TOP
typ_priv_check 2 CHECK_A_(TOP)_UNARY_OP
18a9 18a9 seq_br_type 7 Unconditional Call; Flow C 0x18e6
seq_branch_adr 18e6 0x18e6
18aa 18aa seq_br_type 7 Unconditional Call; Flow C 0x18ed
seq_branch_adr 18ed 0x18ed
typ_b_adr 10 TOP
typ_priv_check 4 CHECK_B_(TOP)_UNARY_OP
18ab 18ab typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
18ac 18ac seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 10
18ad 18ad typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18ae 18ae seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
18af 18af typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18b0 18b0 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 10
18b1 18b1 typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18b2 18b2 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
18b3 18b3 typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18b4 18b4 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
typ_a_adr 1f TOP - 1
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 4
18b5 18b5 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18b6 18b6 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
18b7 18b7 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18b8 18b8 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 1f TOP - 1
typ_alu_func 1b A_OR_B
typ_b_adr 24 TR10:04
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 10
18b9 18b9 typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18ba 18ba seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
18bb 18bb typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18bc 18bc seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
typ_a_adr 1f TOP - 1
typ_alu_func 1b A_OR_B
typ_b_adr 3c TR04:1c
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 4
18bd 18bd seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18be 18be seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
18bf 18bf seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18c0 18c0 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
typ_a_adr 1f TOP - 1
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR10:04
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 10
18c1 18c1 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18c2 18c2 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
18c3 18c3 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18c4 18c4 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
typ_a_adr 1f TOP - 1
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 4
18c5 18c5 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18c6 18c6 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
18c7 18c7 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18c8 18c8 seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
typ_a_adr 1f TOP - 1
typ_alu_func 1b A_OR_B
typ_b_adr 24 TR10:04
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 10
18c9 18c9 seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_a_adr 1f TOP - 1
typ_priv_check 3 CHECK_A_(TOP-1)_UNARY_OP
18ca 18ca seq_br_type 7 Unconditional Call; Flow C 0x18e7
seq_branch_adr 18e7 0x18e7
18cb 18cb seq_br_type 7 Unconditional Call; Flow C 0x18ef
seq_branch_adr 18ef 0x18ef
typ_b_adr 1f TOP - 1
typ_priv_check 5 CHECK_B_(TOP-1)_UNARY_OP
18cc 18cc seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
18cd 18cd seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 24 TR10:04
typ_b_adr 24 TR10:04
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18ce 18ce seq_br_type 7 Unconditional Call; Flow C 0x18e5
seq_branch_adr 18e5 0x18e5
typ_a_adr 3d TR04:1d
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
18cf 18cf seq_br_type 7 Unconditional Call; Flow C 0x18eb
seq_branch_adr 18eb 0x18eb
typ_a_adr 03 GP03
typ_b_adr 24 TR10:04
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18d0 18d0 typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
18d1 18d1 typ_a_adr 3d TR04:1d
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
18d2 18d2 seq_br_type 7 Unconditional Call; Flow C 0x18e4
seq_branch_adr 18e4 0x18e4
typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
18d3 18d3 seq_br_type 7 Unconditional Call; Flow C 0x18e9
seq_branch_adr 18e9 0x18e9
typ_a_adr 04 GP04
typ_b_adr 22 TR10:02
typ_frame 10
typ_priv_check 0 CHECK_BINARY_EQ
18d4 18d4 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
18d5 18d5 seq_br_type 7 Unconditional Call; Flow C 0x18e4
seq_branch_adr 18e4 0x18e4
typ_a_adr 3d TR04:1d
typ_b_adr 3c TR04:1c
typ_frame 4
typ_priv_check 0 CHECK_BINARY_EQ
18d6 18d6 typ_a_adr 03 GP03
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
18d7 18d7 seq_br_type 7 Unconditional Call; Flow C 0x18e9
seq_branch_adr 18e9 0x18e9
typ_a_adr 3c TR04:1c
typ_b_adr 03 GP03
typ_frame 4
typ_priv_check 0 CHECK_BINARY_EQ
18d8 18d8 seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_b_adr 24 TR10:04
typ_frame 10
typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
18d9 18d9 seq_br_type 7 Unconditional Call; Flow C 0x18e5
seq_branch_adr 18e5 0x18e5
typ_a_adr 24 TR10:04
typ_b_adr 24 TR10:04
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18da 18da seq_br_type 7 Unconditional Call; Flow C 0x18eb
seq_branch_adr 18eb 0x18eb
typ_a_adr 22 TR10:02
typ_b_adr 22 TR10:02
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18db 18db seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_a_adr 24 TR10:04
typ_alu_func 0 PASS_A
typ_c_adr 2f TOP
typ_c_mux_sel 0 ALU
typ_frame 10
18dc 18dc typ_a_adr 10 TOP
typ_alu_func 1b A_OR_B
typ_b_adr 3d TR04:1d
typ_c_adr 20 TOP - 0x1
typ_c_mux_sel 0 ALU
typ_frame 4
18dd 18dd typ_a_adr 10 TOP
typ_b_adr 1f TOP - 1
typ_priv_check 1 CHECK_BINARY_OP
18de 18de seq_br_type 7 Unconditional Call; Flow C 0x18e8
seq_branch_adr 18e8 0x18e8
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
18df 18df typ_a_adr 22 TR10:02
typ_b_adr 22 TR10:02
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18e0 18e0 typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
typ_rand 2 DEC_LOOP_COUNTER
18e1 18e1 seq_br_type 7 Unconditional Call; Flow C 0x18e5
seq_branch_adr 18e5 0x18e5
typ_priv_check 6 CLEAR_PASS_PRIVACY_BIT
18e2 18e2 typ_a_adr 22 TR10:02
typ_b_adr 22 TR10:02
typ_frame 10
typ_priv_check 1 CHECK_BINARY_OP
18e3 18e3 seq_br_type a Unconditional Return; Flow R
18e4 ; --------------------------------------------------------------------------------------
18e4 ; Comes from:
18e4 ; 18d2 C from color 0x1800
18e4 ; 18d5 C from color 0x1800
18e4 ; --------------------------------------------------------------------------------------
18e4 18e4 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18e5 ; --------------------------------------------------------------------------------------
18e5 ; Comes from:
18e5 ; 18ce C from color 0x1800
18e5 ; 18d9 C from color 0x1800
18e5 ; 18e1 C from color 0x1800
18e5 ; --------------------------------------------------------------------------------------
18e5 18e5 seq_br_type a Unconditional Return; Flow R
typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18e6 ; --------------------------------------------------------------------------------------
18e6 ; Comes from:
18e6 ; 1893 C from color 0x1800
18e6 ; 1895 C from color 0x1800
18e6 ; 189b C from color 0x1800
18e6 ; 189d C from color 0x1800
18e6 ; 189f C from color 0x1800
18e6 ; 18a1 C from color 0x1800
18e6 ; 18a3 C from color 0x1800
18e6 ; 18a5 C from color 0x1800
18e6 ; 18a7 C from color 0x1800
18e6 ; 18a9 C from color 0x1800
18e6 ; --------------------------------------------------------------------------------------
18e6 18e6 seq_br_type a Unconditional Return; Flow R
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18e7 ; --------------------------------------------------------------------------------------
18e7 ; Comes from:
18e7 ; 18b4 C from color 0x1800
18e7 ; 18b6 C from color 0x1800
18e7 ; 18bc C from color 0x1800
18e7 ; 18be C from color 0x1800
18e7 ; 18c0 C from color 0x1800
18e7 ; 18c2 C from color 0x1800
18e7 ; 18c4 C from color 0x1800
18e7 ; 18c6 C from color 0x1800
18e7 ; 18c8 C from color 0x1800
18e7 ; 18ca C from color 0x1800
18e7 ; --------------------------------------------------------------------------------------
18e7 18e7 seq_br_type a Unconditional Return; Flow R
typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18e8 ; --------------------------------------------------------------------------------------
18e8 ; Comes from:
18e8 ; 1800 C from color 0x1800
18e8 ; 188b C from color 0x1800
18e8 ; 188d C from color 0x1800
18e8 ; 188f C from color 0x1800
18e8 ; 1891 C from color 0x1800
18e8 ; 1897 C from color 0x1800
18e8 ; 1899 C from color 0x1800
18e8 ; 18ac C from color 0x1800
18e8 ; 18ae C from color 0x1800
18e8 ; 18b0 C from color 0x1800
18e8 ; 18b2 C from color 0x1800
18e8 ; 18b8 C from color 0x1800
18e8 ; 18ba C from color 0x1800
18e8 ; 18cc C from color 0x1800
18e8 ; 18cd C from color 0x1800
18e8 ; 18d4 C from color 0x1800
18e8 ; 18d8 C from color 0x1800
18e8 ; 18db C from color 0x1800
18e8 ; 18de C from color 0x1800
18e8 ; --------------------------------------------------------------------------------------
18e8 18e8 seq_br_type a Unconditional Return; Flow R
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18e9 ; --------------------------------------------------------------------------------------
18e9 ; Comes from:
18e9 ; 18d3 C from color 0x1800
18e9 ; 18d7 C from color 0x1800
18e9 ; --------------------------------------------------------------------------------------
18e9 18e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18ff
seq_br_type 5 Call True
seq_branch_adr 18ff PRIVACY_CHECKER_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_frame 4
18ea 18ea seq_br_type a Unconditional Return; Flow R
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18eb ; --------------------------------------------------------------------------------------
18eb ; Comes from:
18eb ; 18cf C from color 0x1800
18eb ; 18da C from color 0x1800
18eb ; --------------------------------------------------------------------------------------
18eb 18eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18ff
seq_br_type 5 Call True
seq_branch_adr 18ff PRIVACY_CHECKER_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_frame 4
18ec 18ec seq_br_type a Unconditional Return; Flow R
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18ed ; --------------------------------------------------------------------------------------
18ed ; Comes from:
18ed ; 1894 C from color 0x1800
18ed ; 1896 C from color 0x1800
18ed ; 189c C from color 0x1800
18ed ; 189e C from color 0x1800
18ed ; 18a0 C from color 0x1800
18ed ; 18a2 C from color 0x1800
18ed ; 18a4 C from color 0x1800
18ed ; 18a6 C from color 0x1800
18ed ; 18a8 C from color 0x1800
18ed ; 18aa C from color 0x1800
18ed ; --------------------------------------------------------------------------------------
18ed 18ed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18ff
seq_br_type 5 Call True
seq_branch_adr 18ff PRIVACY_CHECKER_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 23 VR04:03
val_frame 4
18ee 18ee seq_br_type a Unconditional Return; Flow R
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18ef ; --------------------------------------------------------------------------------------
18ef ; Comes from:
18ef ; 18b5 C from color 0x1800
18ef ; 18b7 C from color 0x1800
18ef ; 18bd C from color 0x1800
18ef ; 18bf C from color 0x1800
18ef ; 18c1 C from color 0x1800
18ef ; 18c3 C from color 0x1800
18ef ; 18c5 C from color 0x1800
18ef ; 18c7 C from color 0x1800
18ef ; 18c9 C from color 0x1800
18ef ; 18cb C from color 0x1800
18ef ; --------------------------------------------------------------------------------------
18ef 18ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x18ff
seq_br_type 5 Call True
seq_branch_adr 18ff PRIVACY_CHECKER_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 22 VR04:02
val_frame 4
18f0 18f0 seq_br_type a Unconditional Return; Flow R
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
18f1 ; --------------------------------------------------------------------------------------
18f1 ; Comes from:
18f1 ; 1803 C False from color 0x1800
18f1 ; 1806 C False from color 0x1800
18f1 ; 1809 C True from color 0x1800
18f1 ; 180c C True from color 0x1800
18f1 ; 1811 C True from color 0x1800
18f1 ; 1818 C False from color 0x1800
18f1 ; 181b C False from color 0x1800
18f1 ; 181e C True from color 0x1800
18f1 ; 1821 C True from color 0x1800
18f1 ; 1826 C True from color 0x1800
18f1 ; --------------------------------------------------------------------------------------
18f1 PRIVACY_A_FAILED:
18f1 18f1 <halt> ; Flow R
18f2 18f2 seq_br_type a Unconditional Return; Flow R
18f3 ; --------------------------------------------------------------------------------------
18f3 ; Comes from:
18f3 ; 1804 C False from color 0x1800
18f3 ; 1807 C False from color 0x1800
18f3 ; 180a C True from color 0x1800
18f3 ; 180d C True from color 0x1800
18f3 ; 1812 C True from color 0x1800
18f3 ; 1819 C False from color 0x1800
18f3 ; 181c C False from color 0x1800
18f3 ; 181f C True from color 0x1800
18f3 ; 1822 C True from color 0x1800
18f3 ; 1827 C True from color 0x1800
18f3 ; --------------------------------------------------------------------------------------
18f3 PRIVACY_B_FAILED:
18f3 18f3 <halt> ; Flow R
18f4 18f4 seq_br_type a Unconditional Return; Flow R
18f5 ; --------------------------------------------------------------------------------------
18f5 ; Comes from:
18f5 ; 182c C True from color 0x1800
18f5 ; 182f C True from color 0x1800
18f5 ; 1833 C True from color 0x1800
18f5 ; 1837 C False from color 0x1800
18f5 ; 183c C True from color 0x1800
18f5 ; 183f C True from color 0x1800
18f5 ; 1842 C True from color 0x1800
18f5 ; 1845 C False from color 0x1800
18f5 ; --------------------------------------------------------------------------------------
18f5 PRIVACY_NAMES_EQ_FAILED:
18f5 18f5 <halt> ; Flow R
18f6 18f6 seq_br_type a Unconditional Return; Flow R
18f7 ; --------------------------------------------------------------------------------------
18f7 ; Comes from:
18f7 ; 185d C False from color 0x1800
18f7 ; 185f C True from color 0x1800
18f7 ; 1860 C True from color 0x1800
18f7 ; 1862 C True from color 0x1800
18f7 ; 1863 C True from color 0x1800
18f7 ; 1865 C True from color 0x1800
18f7 ; 1866 C True from color 0x1800
18f7 ; 1868 C True from color 0x1800
18f7 ; 1869 C True from color 0x1800
18f7 ; 186a C True from color 0x1800
18f7 ; 186c C False from color 0x1800
18f7 ; 186d C False from color 0x1800
18f7 ; 186f C True from color 0x1800
18f7 ; 1870 C True from color 0x1800
18f7 ; 1875 C False from color 0x1800
18f7 ; 1877 C True from color 0x1800
18f7 ; 1878 C True from color 0x1800
18f7 ; 187a C True from color 0x1800
18f7 ; 187b C True from color 0x1800
18f7 ; --------------------------------------------------------------------------------------
18f7 PRIVACY_A_B_FAILED:
18f7 18f7 <halt> ; Flow R
18f8 18f8 seq_br_type a Unconditional Return; Flow R
18f9 ; --------------------------------------------------------------------------------------
18f9 ; Comes from:
18f9 ; 187f C False from color 0x1800
18f9 ; 1882 C False from color 0x1800
18f9 ; 1885 C True from color 0x1800
18f9 ; 1888 C False from color 0x1800
18f9 ; --------------------------------------------------------------------------------------
18f9 PRIVACY_EQ_FAILED:
18f9 18f9 <halt> ; Flow R
18fa 18fa seq_br_type a Unconditional Return; Flow R
18fb ; --------------------------------------------------------------------------------------
18fb ; Comes from:
18fb ; 1880 C True from color 0x1800
18fb ; 1883 C False from color 0x1800
18fb ; 1886 C False from color 0x1800
18fb ; 1889 C False from color 0x1800
18fb ; --------------------------------------------------------------------------------------
18fb PRIVACY_STRUCTURE_FAILED:
18fb 18fb <halt> ; Flow R
18fc 18fc seq_br_type a Unconditional Return; Flow R
18fd ; --------------------------------------------------------------------------------------
18fd ; Comes from:
18fd ; 1849 C False from color 0x1800
18fd ; 184c C True from color 0x1800
18fd ; 1852 C False from color 0x1800
18fd ; 1855 C True from color 0x1800
18fd ; --------------------------------------------------------------------------------------
18fd PRIVACY_PATHS_EQ_FAILED:
18fd 18fd <halt> ; Flow R
18fe 18fe seq_br_type a Unconditional Return; Flow R
18ff ; --------------------------------------------------------------------------------------
18ff ; Comes from:
18ff ; 18e9 C True from color 0x18e9
18ff ; 18eb C True from color 0x18eb
18ff ; 18ed C True from color 0x18ed
18ff ; 18ef C True from color 0x18ef
18ff ; --------------------------------------------------------------------------------------
18ff PRIVACY_CHECKER_ERROR:
18ff 18ff <halt> ; Flow R
1900 1900 seq_br_type a Unconditional Return; Flow R
1901 1901 <halt> ; Flow R
1902 1902 <halt> ; Flow R
1903 1903 <halt> ; Flow R
1904 1904 <halt> ; Flow R
1905 1905 <halt> ; Flow R
1906 1906 <halt> ; Flow R
1907 1907 <halt> ; Flow R
1908 1908 <halt> ; Flow R
1909 1909 <halt> ; Flow R
190a 190a <halt> ; Flow R
190b 190b <halt> ; Flow R
190c 190c <halt> ; Flow R
190d 190d <halt> ; Flow R
190e 190e <halt> ; Flow R
190f 190f <halt> ; Flow R
1910 1910 <halt> ; Flow R
1911 1911 <halt> ; Flow R
1912 1912 <halt> ; Flow R
1913 1913 <halt> ; Flow R
1914 1914 <halt> ; Flow R
1915 1915 <halt> ; Flow R
1916 1916 <halt> ; Flow R
1917 1917 <halt> ; Flow R
1918 1918 <halt> ; Flow R
1919 1919 <halt> ; Flow R
191a 191a <halt> ; Flow R
191b 191b <halt> ; Flow R
191c 191c <halt> ; Flow R
191d 191d <halt> ; Flow R
191e 191e <halt> ; Flow R
191f 191f <halt> ; Flow R
1920 1920 <halt> ; Flow R
1921 1921 <halt> ; Flow R
1922 1922 <halt> ; Flow R
1923 1923 <halt> ; Flow R
1924 1924 <halt> ; Flow R
1925 1925 <halt> ; Flow R
1926 1926 <halt> ; Flow R
1927 1927 <halt> ; Flow R
1928 1928 <halt> ; Flow R
1929 1929 <halt> ; Flow R
192a 192a <halt> ; Flow R
192b 192b <halt> ; Flow R
192c 192c <halt> ; Flow R
192d 192d <halt> ; Flow R
192e 192e <halt> ; Flow R
192f 192f <halt> ; Flow R
1930 1930 <halt> ; Flow R
1931 1931 <halt> ; Flow R
1932 1932 <halt> ; Flow R
1933 1933 <halt> ; Flow R
1934 1934 <halt> ; Flow R
1935 1935 <halt> ; Flow R
1936 1936 <halt> ; Flow R
1937 1937 <halt> ; Flow R
1938 1938 <halt> ; Flow R
1939 1939 <halt> ; Flow R
193a 193a <halt> ; Flow R
193b 193b <halt> ; Flow R
193c 193c <halt> ; Flow R
193d 193d <halt> ; Flow R
193e 193e <halt> ; Flow R
193f 193f <halt> ; Flow R
1940 1940 <halt> ; Flow R
1941 1941 <halt> ; Flow R
1942 1942 <halt> ; Flow R
1943 1943 <halt> ; Flow R
1944 1944 <halt> ; Flow R
1945 1945 <halt> ; Flow R
1946 1946 <halt> ; Flow R
1947 1947 <halt> ; Flow R
1948 1948 <halt> ; Flow R
1949 1949 <halt> ; Flow R
194a 194a <halt> ; Flow R
194b 194b <halt> ; Flow R
194c 194c <halt> ; Flow R
194d 194d <halt> ; Flow R
194e 194e <halt> ; Flow R
194f 194f <halt> ; Flow R
1950 1950 <halt> ; Flow R
1951 1951 <halt> ; Flow R
1952 1952 <halt> ; Flow R
1953 1953 <halt> ; Flow R
1954 1954 <halt> ; Flow R
1955 1955 <halt> ; Flow R
1956 1956 <halt> ; Flow R
1957 1957 <halt> ; Flow R
1958 1958 <halt> ; Flow R
1959 1959 <halt> ; Flow R
195a 195a <halt> ; Flow R
195b 195b <halt> ; Flow R
195c 195c <halt> ; Flow R
195d 195d <halt> ; Flow R
195e 195e <halt> ; Flow R
195f 195f <halt> ; Flow R
1960 1960 <halt> ; Flow R
1961 1961 <halt> ; Flow R
1962 1962 <halt> ; Flow R
1963 1963 <halt> ; Flow R
1964 1964 <halt> ; Flow R
1965 1965 <halt> ; Flow R
1966 1966 <halt> ; Flow R
1967 1967 <halt> ; Flow R
1968 1968 <halt> ; Flow R
1969 1969 <halt> ; Flow R
196a 196a <halt> ; Flow R
196b 196b <halt> ; Flow R
196c 196c <halt> ; Flow R
196d 196d <halt> ; Flow R
196e 196e <halt> ; Flow R
196f 196f <halt> ; Flow R
1970 1970 <halt> ; Flow R
1971 1971 <halt> ; Flow R
1972 1972 <halt> ; Flow R
1973 1973 <halt> ; Flow R
1974 1974 <halt> ; Flow R
1975 1975 <halt> ; Flow R
1976 1976 <halt> ; Flow R
1977 1977 <halt> ; Flow R
1978 1978 <halt> ; Flow R
1979 1979 <halt> ; Flow R
197a 197a <halt> ; Flow R
197b 197b <halt> ; Flow R
197c 197c <halt> ; Flow R
197d 197d <halt> ; Flow R
197e 197e <halt> ; Flow R
197f 197f <halt> ; Flow R
1980 1980 <halt> ; Flow R
1981 1981 <halt> ; Flow R
1982 1982 <halt> ; Flow R
1983 1983 <halt> ; Flow R
1984 1984 <halt> ; Flow R
1985 1985 <halt> ; Flow R
1986 1986 <halt> ; Flow R
1987 1987 <halt> ; Flow R
1988 1988 <halt> ; Flow R
1989 1989 <halt> ; Flow R
198a 198a <halt> ; Flow R
198b 198b <halt> ; Flow R
198c 198c <halt> ; Flow R
198d 198d <halt> ; Flow R
198e 198e <halt> ; Flow R
198f 198f <halt> ; Flow R
1990 1990 <halt> ; Flow R
1991 1991 <halt> ; Flow R
1992 1992 <halt> ; Flow R
1993 1993 <halt> ; Flow R
1994 1994 <halt> ; Flow R
1995 1995 <halt> ; Flow R
1996 1996 <halt> ; Flow R
1997 1997 <halt> ; Flow R
1998 1998 <halt> ; Flow R
1999 1999 <halt> ; Flow R
199a 199a <halt> ; Flow R
199b 199b <halt> ; Flow R
199c 199c <halt> ; Flow R
199d 199d <halt> ; Flow R
199e 199e <halt> ; Flow R
199f 199f <halt> ; Flow R
19a0 19a0 <halt> ; Flow R
19a1 19a1 <halt> ; Flow R
19a2 19a2 <halt> ; Flow R
19a3 19a3 <halt> ; Flow R
19a4 19a4 <halt> ; Flow R
19a5 19a5 <halt> ; Flow R
19a6 19a6 <halt> ; Flow R
19a7 19a7 <halt> ; Flow R
19a8 19a8 <halt> ; Flow R
19a9 19a9 <halt> ; Flow R
19aa 19aa <halt> ; Flow R
19ab 19ab <halt> ; Flow R
19ac 19ac <halt> ; Flow R
19ad 19ad <halt> ; Flow R
19ae 19ae <halt> ; Flow R
19af 19af <halt> ; Flow R
19b0 19b0 <halt> ; Flow R
19b1 19b1 <halt> ; Flow R
19b2 19b2 <halt> ; Flow R
19b3 19b3 <halt> ; Flow R
19b4 19b4 <halt> ; Flow R
19b5 19b5 <halt> ; Flow R
19b6 19b6 <halt> ; Flow R
19b7 19b7 <halt> ; Flow R
19b8 19b8 <halt> ; Flow R
19b9 19b9 <halt> ; Flow R
19ba 19ba <halt> ; Flow R
19bb 19bb <halt> ; Flow R
19bc 19bc <halt> ; Flow R
19bd 19bd <halt> ; Flow R
19be 19be <halt> ; Flow R
19bf 19bf <halt> ; Flow R
19c0 19c0 <halt> ; Flow R
19c1 19c1 <halt> ; Flow R
19c2 19c2 <halt> ; Flow R
19c3 19c3 <halt> ; Flow R
19c4 19c4 <halt> ; Flow R
19c5 19c5 <halt> ; Flow R
19c6 19c6 <halt> ; Flow R
19c7 19c7 <halt> ; Flow R
19c8 19c8 <halt> ; Flow R
19c9 19c9 <halt> ; Flow R
19ca 19ca <halt> ; Flow R
19cb 19cb <halt> ; Flow R
19cc 19cc <halt> ; Flow R
19cd 19cd <halt> ; Flow R
19ce 19ce <halt> ; Flow R
19cf 19cf <halt> ; Flow R
19d0 19d0 <halt> ; Flow R
19d1 19d1 <halt> ; Flow R
19d2 19d2 <halt> ; Flow R
19d3 19d3 <halt> ; Flow R
19d4 19d4 <halt> ; Flow R
19d5 19d5 <halt> ; Flow R
19d6 19d6 <halt> ; Flow R
19d7 19d7 <halt> ; Flow R
19d8 19d8 <halt> ; Flow R
19d9 19d9 <halt> ; Flow R
19da 19da <halt> ; Flow R
19db 19db <halt> ; Flow R
19dc 19dc <halt> ; Flow R
19dd 19dd <halt> ; Flow R
19de 19de <halt> ; Flow R
19df 19df <halt> ; Flow R
19e0 19e0 <halt> ; Flow R
19e1 19e1 <halt> ; Flow R
19e2 19e2 <halt> ; Flow R
19e3 19e3 <halt> ; Flow R
19e4 19e4 <halt> ; Flow R
19e5 19e5 <halt> ; Flow R
19e6 19e6 <halt> ; Flow R
19e7 19e7 <halt> ; Flow R
19e8 19e8 <halt> ; Flow R
19e9 19e9 <halt> ; Flow R
19ea 19ea <halt> ; Flow R
19eb 19eb <halt> ; Flow R
19ec 19ec <halt> ; Flow R
19ed 19ed <halt> ; Flow R
19ee 19ee <halt> ; Flow R
19ef 19ef <halt> ; Flow R
19f0 19f0 <halt> ; Flow R
19f1 19f1 <halt> ; Flow R
19f2 19f2 <halt> ; Flow R
19f3 19f3 <halt> ; Flow R
19f4 19f4 <halt> ; Flow R
19f5 19f5 <halt> ; Flow R
19f6 19f6 <halt> ; Flow R
19f7 19f7 <halt> ; Flow R
19f8 19f8 <halt> ; Flow R
19f9 19f9 <halt> ; Flow R
19fa 19fa <halt> ; Flow R
19fb 19fb <halt> ; Flow R
19fc 19fc <halt> ; Flow R
19fd 19fd <halt> ; Flow R
19fe 19fe <halt> ; Flow R
19ff 19ff <halt> ; Flow R
1a00 ; --------------------------------------------------------------------------------------
1a00 ; 1A00 - 1C23 FIU_TEST
1a00 ; Comes from:
1a00 ; 0315 C from color DIAGNOSTIC_START
1a00 ; --------------------------------------------------------------------------------------
1a00 1a00 val_a_adr 27 VR04:07
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1a01 1a01 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
1a02 1a02 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a03 1a03 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a04 1a04 seq_b_timing 0 Early Condition; Flow J cc=False 0x1a01
seq_br_type 0 Branch False
seq_branch_adr 1a01 0x1a01
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1a05 1a05 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
1a06 1a06 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a07 1a07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1a08 1a08 fiu_load_oreg 1 hold_oreg
1a09 1a09 fiu_tivi_src c mar_0xc; Flow C cc=True 0x1bfe
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1a0a 1a0a fiu_load_oreg 1 hold_oreg
fiu_offs_lit 01
val_a_adr 14 ZEROS
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a0b 1a0b fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a0c 1a0c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a0d 1a0d fiu_load_oreg 1 hold_oreg
fiu_offs_lit 02
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a0e 1a0e fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a0f 1a0f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a10 1a10 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 04
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a11 1a11 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a12 1a12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a13 1a13 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 08
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a14 1a14 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a15 1a15 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a16 1a16 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 10
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a17 1a17 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a18 1a18 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a19 1a19 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 20
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a1a 1a1a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a1b 1a1b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a1c 1a1c fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1a1d 1a1d fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
val_a_adr 2d VR10:0d
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1a1e 1a1e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1bfe
seq_br_type 5 Call True
seq_branch_adr 1bfe OFFSET_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1a1f 1a1f val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1a20 1a20 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 20 VR05:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
1a21 1a21 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36)
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 03 GP03
val_rand 2 DEC_LOOP_COUNTER
1a22 1a22 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a23 1a23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a24 1a24 seq_b_timing 0 Early Condition; Flow J cc=False 0x1a21
seq_br_type 0 Branch False
seq_branch_adr 1a21 0x1a21
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 03 GP03
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR05:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
1a25 1a25 val_a_adr 26 VR04:06
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1a26 1a26 typ_a_adr 3b TR04:1b
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR05:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
1a27 1a27 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36)
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 9 type_val
typ_b_adr 3b TR04:1b
typ_frame 4
val_b_adr 03 GP03
val_rand 2 DEC_LOOP_COUNTER
1a28 1a28 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a29 1a29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a2a 1a2a seq_b_timing 0 Early Condition; Flow J cc=False 0x1a27
seq_br_type 0 Branch False
seq_branch_adr 1a27 0x1a27
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 03 GP03
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR05:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
1a2b 1a2b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36)
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 9 type_val
typ_b_adr 3b TR04:1b
typ_frame 4
val_b_adr 20 VR10:00
val_frame 10
1a2c 1a2c fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a2d 1a2d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a2e 1a2e typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1a2f 1a2f fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
typ_b_adr 03 GP03
val_rand 2 DEC_LOOP_COUNTER
1a30 1a30 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a31 1a31 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a32 1a32 seq_b_timing 0 Early Condition; Flow J cc=False 0x1a2f
seq_br_type 0 Branch False
seq_branch_adr 1a2f 0x1a2f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a33 1a33 typ_a_adr 3b TR04:1b
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1a34 1a34 fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
typ_b_adr 03 GP03
val_rand 2 DEC_LOOP_COUNTER
1a35 1a35 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a36 1a36 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a37 1a37 seq_b_timing 0 Early Condition; Flow J cc=False 0x1a34
seq_br_type 0 Branch False
seq_branch_adr 1a34 0x1a34
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a38 1a38 fiu_len_fill_lit 00 sign-fill 0x0
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a39 1a39 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a3a 1a3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a3b 1a3b fiu_len_fill_lit 40 zero-fill 0x0
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a3c 1a3c fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a3d 1a3d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a3e 1a3e fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a3f 1a3f fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a40 1a40 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a41 1a41 fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a42 1a42 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a43 1a43 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a44 1a44 fiu_len_fill_lit 01 sign-fill 0x1
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 2f TR04:0f
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a45 1a45 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a46 1a46 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a47 1a47 fiu_len_fill_lit 41 zero-fill 0x1
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a48 1a48 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a49 1a49 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a4a 1a4a fiu_len_fill_lit 3e sign-fill 0x3e
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a4b 1a4b fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a4c 1a4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a4d 1a4d fiu_len_fill_lit 7e zero-fill 0x3e
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a4e 1a4e fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a4f 1a4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a50 1a50 fiu_len_fill_lit 02 sign-fill 0x2
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 30 TR04:10
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a51 1a51 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a52 1a52 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a53 1a53 fiu_len_fill_lit 42 zero-fill 0x2
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a54 1a54 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a55 1a55 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a56 1a56 fiu_len_fill_lit 3d sign-fill 0x3d
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a57 1a57 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a58 1a58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a59 1a59 fiu_len_fill_lit 7d zero-fill 0x3d
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a5a 1a5a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a5b 1a5b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a5c 1a5c fiu_len_fill_lit 04 sign-fill 0x4
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 31 TR04:11
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a5d 1a5d fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a5e 1a5e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a5f 1a5f fiu_len_fill_lit 44 zero-fill 0x4
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a60 1a60 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a61 1a61 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a62 1a62 fiu_len_fill_lit 3b sign-fill 0x3b
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a63 1a63 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a64 1a64 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a65 1a65 fiu_len_fill_lit 7b zero-fill 0x3b
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a66 1a66 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a67 1a67 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a68 1a68 fiu_len_fill_lit 08 sign-fill 0x8
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 32 TR04:12
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a69 1a69 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a6a 1a6a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a6b 1a6b fiu_len_fill_lit 48 zero-fill 0x8
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a6c 1a6c fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a6d 1a6d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a6e 1a6e fiu_len_fill_lit 37 sign-fill 0x37
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a6f 1a6f fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a70 1a70 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a71 1a71 fiu_len_fill_lit 77 zero-fill 0x37
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a72 1a72 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a73 1a73 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a74 1a74 fiu_len_fill_lit 10 sign-fill 0x10
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 33 TR04:13
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a75 1a75 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a76 1a76 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a77 1a77 fiu_len_fill_lit 50 zero-fill 0x10
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a78 1a78 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a79 1a79 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a7a 1a7a fiu_len_fill_lit 2f sign-fill 0x2f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a7b 1a7b fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a7c 1a7c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a7d 1a7d fiu_len_fill_lit 6f zero-fill 0x2f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a7e 1a7e fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a7f 1a7f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a80 1a80 fiu_len_fill_lit 20 sign-fill 0x20
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 34 TR04:14
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a81 1a81 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a82 1a82 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a83 1a83 fiu_len_fill_lit 60 zero-fill 0x20
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a84 1a84 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a85 1a85 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a86 1a86 fiu_len_fill_lit 1f sign-fill 0x1f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR10:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1a87 1a87 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a88 1a88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a89 1a89 fiu_len_fill_lit 5f zero-fill 0x1f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR04:1b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1a8a 1a8a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_a_adr 2b TR10:0b
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1a8b 1a8b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c00
seq_br_type 5 Call True
seq_branch_adr 1c00 LENGTH_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1a8c 1a8c fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
1a8d 1a8d fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a8e 1a8e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a8f 1a8f fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a90 1a90 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a91 1a91 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a92 1a92 seq_b_timing 0 Early Condition; Flow C cc=False 0x1c02
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a93 1a93 fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
1a94 1a94 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a95 1a95 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a96 1a96 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a97 1a97 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a98 1a98 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 3f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a99 1a99 seq_b_timing 0 Early Condition; Flow C cc=False 0x1c02
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a9a 1a9a fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
1a9b 1a9b fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a9c 1a9c fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a9d 1a9d fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a9e 1a9e fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1a9f 1a9f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa0 1aa0 seq_b_timing 0 Early Condition; Flow C cc=False 0x1c02
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa1 1aa1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
1aa2 1aa2 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa3 1aa3 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa4 1aa4 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa5 1aa5 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa6 1aa6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 41
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa7 1aa7 seq_b_timing 0 Early Condition; Flow C cc=True 0x1c02
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aa8 1aa8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
1aa9 1aa9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aaa 1aaa fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aab 1aab fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aac 1aac fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aad 1aad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 42
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aae 1aae seq_b_timing 0 Early Condition; Flow C cc=True 0x1c02
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aaf 1aaf fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
1ab0 1ab0 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab1 1ab1 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab2 1ab2 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab3 1ab3 fiu_len_fill_lit 01 sign-fill 0x1; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab4 1ab4 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab5 1ab5 fiu_len_fill_lit 02 sign-fill 0x2; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab6 1ab6 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab7 1ab7 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab8 1ab8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7e
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ab9 1ab9 seq_b_timing 0 Early Condition; Flow C cc=True 0x1c02
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1aba 1aba fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
1abb 1abb fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1abc 1abc fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1abd 1abd fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1abe 1abe fiu_len_fill_lit 01 sign-fill 0x1; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1abf 1abf fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ac0 1ac0 fiu_len_fill_lit 3e sign-fill 0x3e; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ac1 1ac1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c02
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ac2 1ac2 seq_b_timing 0 Early Condition; Flow C cc=True 0x1c02
seq_br_type 5 Call True
seq_branch_adr 1c02 XWORD_ERROR
seq_cond_sel 65 CROSS_WORD_FIELD~
1ac3 1ac3 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 23 VR17:03
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
1ac4 1ac4 typ_a_adr 3d TR17:1d
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 17
1ac5 1ac5 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
1ac6 1ac6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1ac8
seq_br_type 0 Branch False
seq_branch_adr 1ac8 0x1ac8
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
1ac7 1ac7 seq_br_type 7 Unconditional Call; Flow C 0x1c04
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
1ac8 1ac8 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
1ac9 1ac9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1acb
seq_br_type 0 Branch False
seq_branch_adr 1acb 0x1acb
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
1aca 1aca seq_br_type 7 Unconditional Call; Flow C 0x1c04
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
1acb 1acb typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR04:07
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1acc 1acc typ_a_adr 04 GP04
typ_alu_func 1 A_PLUS_B
typ_b_adr 27 TR04:07
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
1acd 1acd fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
1ace 1ace seq_br_type 4 Call False; Flow C cc=False 0x1c04
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
1acf 1acf fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
1ad0 1ad0 seq_br_type 4 Call False; Flow C cc=False 0x1c04
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
1ad1 1ad1 seq_b_timing 0 Early Condition; Flow J cc=False 0x1acb
seq_br_type 0 Branch False
seq_branch_adr 1acb 0x1acb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1ad2 1ad2 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_mar_cntl b LOAD_MAR_DATA
1ad3 1ad3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c04
seq_br_type 5 Call True
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
typ_mar_cntl 6 INCREMENT_MAR
1ad4 1ad4 seq_br_type 4 Call False; Flow C cc=False 0x1c04
seq_branch_adr 1c04 MAR_WORD_EQ_ZERO_ERROR
seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~
1ad5 1ad5 val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1ad6 1ad6 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_alu_func 13 ONES
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1ad7 1ad7 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c06
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c06 VAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1ad8 1ad8 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_b_adr 04 GP04
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1ad9 1ad9 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c06
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c06 VAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1ada 1ada fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1adb 1adb ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c06
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c06 VAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1adc 1adc fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_b_adr 04 GP04
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1add 1add ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c06
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c06 VAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1ade 1ade fiu_load_var 1 hold_var; Flow J cc=True 0x1adb
fiu_tivi_src 1 tar_val
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1adb 0x1adb
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1adf 1adf typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1ae0 1ae0 fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1ae1 1ae1 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c08
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c08 TAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ae2 1ae2 fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1ae3 1ae3 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c08
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c08 TAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ae4 1ae4 fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1ae5 1ae5 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c08
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c08 TAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ae6 1ae6 fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_latch 1
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1ae7 1ae7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c08
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c08 TAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ae8 1ae8 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1ae5
fiu_tivi_src 8 type_var
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1ae5 0x1ae5
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1ae9 1ae9 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1aea 1aea fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
typ_alu_func 13 ONES
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1aeb 1aeb fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1aec 1aec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c0a
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1aed 1aed ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c0a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1aee 1aee fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_b_adr 04 GP04
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1aef 1aef fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1af0 1af0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c0a
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1af1 1af1 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c0a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1af2 1af2 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1af3 1af3 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1af4 1af4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c0a
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1af5 1af5 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c0a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1af6 1af6 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_b_adr 04 GP04
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1af7 1af7 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1af8 1af8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1c0a
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1af9 1af9 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c0a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0a MDR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1afa 1afa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1af3
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1af3 0x1af3
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1afb 1afb val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1afc 1afc fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 03 GP03
val_alu_func 13 ONES
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1afd 1afd ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0c VI_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1afe 1afe fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 04 GP04
1aff 1aff val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b00 1b00 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0c VI_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b01 1b01 fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b02 1b02 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0c VI_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b03 1b03 fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 04 GP04
1b04 1b04 seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b05 1b05 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0c VI_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b06 1b06 fiu_load_var 1 hold_var; Flow J cc=True 0x1b02
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1b02 0x1b02
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b07 1b07 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b08 1b08 fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
fiu_vmux_sel 3 FIU BUS
ioc_fiubs 1 val
val_a_adr 03 GP03
val_alu_func 13 ONES
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b09 1b09 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b0a 1b0a fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
fiu_vmux_sel 3 FIU BUS
ioc_fiubs 1 val
val_a_adr 04 GP04
1b0b 1b0b val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b0c 1b0c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b0d 1b0d fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
fiu_vmux_sel 3 FIU BUS
ioc_fiubs 1 val
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b0e 1b0e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b0f 1b0f fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
fiu_vmux_sel 3 FIU BUS
ioc_fiubs 1 val
val_a_adr 04 GP04
1b10 1b10 seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b11 1b11 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b12 1b12 fiu_load_var 1 hold_var; Flow J cc=True 0x1b0e
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
fiu_vmux_sel 3 FIU BUS
ioc_fiubs 1 val
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1b0e 0x1b0e
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b13 1b13 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 7f
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
fiu_vmux_sel 1 fill value
val_b_adr 20 VR10:00
val_frame 10
1b14 1b14 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b15 1b15 fiu_len_fill_lit 00 sign-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 7f
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
fiu_vmux_sel 1 fill value
val_b_adr 20 VR10:00
val_frame 10
1b16 1b16 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b17 1b17 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 7f
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
fiu_vmux_sel 1 fill value
val_b_adr 20 VR04:00
val_frame 4
1b18 1b18 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR04:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
1b19 1b19 fiu_len_fill_lit 00 sign-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 7f
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
fiu_vmux_sel 1 fill value
val_b_adr 20 VR04:00
val_frame 4
1b1a 1b1a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c0e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c0e MERGE_V_MUX_FIU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b1b 1b1b typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1b1c 1b1c fiu_load_tar 1 hold_tar
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 2 typ
typ_a_adr 03 GP03
typ_alu_func 13 ONES
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1b1d 1b1d ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c10
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c10 TI_MUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1b1e 1b1e fiu_load_tar 1 hold_tar
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 2 typ
typ_a_adr 04 GP04
1b1f 1b1f typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1b20 1b20 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c10
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c10 TI_MUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1b21 1b21 fiu_load_tar 1 hold_tar
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 2 typ
typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1b22 1b22 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c10
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c10 TI_MUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1b23 1b23 fiu_load_tar 1 hold_tar
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 2 typ
typ_a_adr 04 GP04
1b24 1b24 seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_latch 1
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1b25 1b25 ioc_tvbs 2 fiu+val; Flow C cc=True 0x1c10
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c10 TI_MUX_FIU_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1b26 1b26 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1b22
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 2 typ
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 1b22 0x1b22
typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1b27 1b27 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 2d VR10:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b28 1b28 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
1b29 1b29 fiu_len_fill_lit 40 zero-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 10 NOT_A
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b2a 1b2a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR04:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
1b2b 1b2b fiu_len_fill_lit 00 sign-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 03 GP03
val_b_adr 03 GP03
1b2c 1b2c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b2d 1b2d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x1b2f
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
seq_b_timing 3 Late Condition, Hint False
seq_br_type 0 Branch False
seq_branch_adr 1b2f 0x1b2f
seq_cond_sel 08 VAL.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_b_adr 04 GP04
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_b_adr 04 GP04
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b2e 1b2e typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1b2f 1b2f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b30 1b30 fiu_len_fill_lit 00 sign-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 04 GP04
val_b_adr 04 GP04
1b31 1b31 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b32 1b32 fiu_len_fill_lit 40 zero-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b33 1b33 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b34 1b34 fiu_len_fill_lit 00 sign-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b35 1b35 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b36 1b36 fiu_len_fill_lit 40 zero-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b37 1b37 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR04:00
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
1b38 1b38 fiu_len_fill_lit 00 sign-fill 0x0
fiu_length_src 0 length_register
fiu_load_var 1 hold_var
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b39 1b39 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c12
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c12 FILL_BIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b3a 1b3a fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1b29
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 1b29 0x1b29
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 17 LOOP_COUNTER
val_alu_func 1c DEC_A
val_rand 2 DEC_LOOP_COUNTER
1b3b 1b3b fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
typ_a_adr 24 TR17:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 22 VR16:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
1b3c 1b3c fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
typ_alu_func 1a PASS_B
typ_b_adr 2a TR10:0a
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1b3d 1b3d fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_frame 10
1b3e 1b3e fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b3f 1b3f ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c14
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c14 MERGER_EXTRACT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b40 1b40 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
typ_a_adr 03 GP03
typ_alu_func 6 A_MINUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_frame 10
1b41 1b41 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_tivi_src 9 type_val
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b42 1b42 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c14
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c14 MERGER_EXTRACT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 16 A_XNOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b43 1b43 fiu_len_fill_reg_ctl 2
fiu_tivi_src 8 type_var
typ_b_adr 03 GP03
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
1b44 1b44 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1b3d
seq_br_type 0 Branch False
seq_branch_adr 1b3d 0x1b3d
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR16:01
val_frame 16
1b45 1b45 fiu_len_fill_lit 00 sign-fill 0x0
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
typ_a_adr 25 TR17:05
typ_alu_func 1c DEC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b46 1b46 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 22 VR10:02
val_frame 10
1b47 1b47 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 1 insert last
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b48 1b48 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c18
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c18 MERGER_INSERT_T_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 16 A_XNOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 22 VR10:02
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b49 1b49 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_frame 10
1b4a 1b4a fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 1 insert last
fiu_tivi_src 9 type_val
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b4b 1b4b ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c18
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c18 MERGER_INSERT_T_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b4c 1b4c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1b47
fiu_load_mdr 1 hold_mdr
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
fiu_oreg_src 0 rotator output
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_adrbs 2 typ
ioc_fiubs 1 val
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 1b47 0x1b47
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 22 VR10:02
val_frame 10
val_rand 2 DEC_LOOP_COUNTER
1b4d 1b4d typ_a_adr 24 TR17:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 22 VR16:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
1b4e 1b4e fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1b4f 1b4f fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_frame 10
1b50 1b50 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 2 insert first
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b51 1b51 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c16
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c16 MERGER_INSERT_V_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b52 1b52 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_frame 10
1b53 1b53 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 2 insert first
fiu_tivi_src 9 type_val
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b54 1b54 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c16
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c16 MERGER_INSERT_V_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 16 A_XNOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b55 1b55 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
fiu_oreg_src 0 rotator output
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_adrbs 2 typ
ioc_fiubs 1 val
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 22 VR10:02
val_frame 10
val_rand 2 DEC_LOOP_COUNTER
1b56 1b56 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1b50
seq_br_type 0 Branch False
seq_branch_adr 1b50 0x1b50
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR16:01
val_frame 16
1b57 1b57 typ_a_adr 24 TR17:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 22 VR16:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
1b58 1b58 typ_a_adr 2a TR10:0a
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
1b59 1b59 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 2
fiu_load_mdr 1 hold_mdr
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
fiu_oreg_src 0 rotator output
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
ioc_adrbs 1 val
typ_b_adr 06 GP06
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_b_adr 22 VR10:02
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
1b5a 1b5a typ_a_adr 13 LOOP_REG
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b5b 1b5b fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1b5c 1b5c fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1c DEC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
1b5d 1b5d ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c1a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c1a MERGER_INSERT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b5e 1b5e fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_tivi_src 9 type_val
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
1b5f 1b5f fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1b5d
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_b_timing 3 Late Condition, Hint False
seq_br_type 0 Branch False
seq_branch_adr 1b5d 0x1b5d
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_a_adr 07 GP07
val_alu_func 1c DEC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
1b60 1b60 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c1a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c1a MERGER_INSERT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b61 1b61 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_mdr 1 hold_mdr
fiu_load_oreg 1 hold_oreg
fiu_offs_lit 40
fiu_oreg_src 0 rotator output
fiu_rdata_src 0 rotator
fiu_tivi_src 1 tar_val
ioc_adrbs 1 val
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_b_adr 20 VR10:00
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
1b62 1b62 typ_a_adr 13 LOOP_REG
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
1b63 1b63 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_tivi_src 9 type_val
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1b64 1b64 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1c DEC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
1b65 1b65 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c1a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c1a MERGER_INSERT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 16 A_XNOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b66 1b66 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_tivi_src 9 type_val
typ_b_adr 22 TR10:02
typ_frame 10
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_b_adr 22 VR10:02
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
1b67 1b67 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1b65
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_b_timing 3 Late Condition, Hint False
seq_br_type 0 Branch False
seq_branch_adr 1b65 0x1b65
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_a_adr 07 GP07
val_alu_func 1c DEC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
1b68 1b68 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x1c1a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c1a MERGER_INSERT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 16 A_XNOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b69 1b69 typ_a_adr 06 GP06
typ_alu_func 6 A_MINUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1b6a 1b6a fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x1b59
fiu_tivi_src c mar_0xc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 0 Branch False
seq_branch_adr 1b59 0x1b59
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 6 A_MINUS_B
val_b_adr 21 VR16:01
val_frame 16
1b6b 1b6b val_c_adr 39 GP06
val_c_mux_sel 2 ALU
1b6c 1b6c val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b6d 1b6d fiu_load_tar 1 hold_tar
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 20 VR04:00
val_alu_func 1a PASS_B
val_b_adr 20 VR04:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
1b6e 1b6e fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 06 GP06
val_alu_func 0 PASS_A
1b6f 1b6f fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_frame 10
1b70 1b70 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1b71 1b71 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1c
seq_br_type 5 Call True
seq_branch_adr 1c1c ROTATE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b72 1b72 val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1b73 1b73 seq_b_timing 0 Early Condition; Flow J cc=False 0x1b6e
seq_br_type 0 Branch False
seq_branch_adr 1b6e 0x1b6e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
val_rand 2 DEC_LOOP_COUNTER
1b74 1b74 fiu_load_tar 1 hold_tar
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 20 VR10:00
val_frame 10
1b75 1b75 val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b76 1b76 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
1b77 1b77 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 06 GP06
val_alu_func 0 PASS_A
1b78 1b78 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 20 VR04:00
val_frame 4
1b79 1b79 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1b7a 1b7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1c
seq_br_type 5 Call True
seq_branch_adr 1c1c ROTATE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b7b 1b7b val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1b7c 1b7c seq_b_timing 0 Early Condition; Flow J cc=False 0x1b77
seq_br_type 0 Branch False
seq_branch_adr 1b77 0x1b77
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
val_rand 2 DEC_LOOP_COUNTER
1b7d 1b7d val_c_adr 39 GP06
val_c_mux_sel 2 ALU
1b7e 1b7e val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b7f 1b7f fiu_load_tar 1 hold_tar
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 24 VR10:04
val_alu_func 1a PASS_B
val_b_adr 24 VR10:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
1b80 1b80 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 06 GP06
val_alu_func 0 PASS_A
1b81 1b81 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_frame 10
1b82 1b82 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1b83 1b83 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1c
seq_br_type 5 Call True
seq_branch_adr 1c1c ROTATE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b84 1b84 val_a_adr 05 GP05
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1b85 1b85 seq_b_timing 0 Early Condition; Flow J cc=False 0x1b80
seq_br_type 0 Branch False
seq_branch_adr 1b80 0x1b80
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
val_rand 2 DEC_LOOP_COUNTER
1b86 1b86 fiu_load_tar 1 hold_tar
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 22 VR10:02
val_frame 10
1b87 1b87 val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b88 1b88 val_a_adr 24 VR10:04
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
1b89 1b89 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_len_fill_reg_ctl 1 len=literal, fill=literal
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
val_a_adr 06 GP06
val_alu_func 0 PASS_A
1b8a 1b8a fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 24 VR10:04
val_frame 10
1b8b 1b8b fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1b8c 1b8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1c
seq_br_type 5 Call True
seq_branch_adr 1c1c ROTATE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b8d 1b8d val_a_adr 05 GP05
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1b8e 1b8e seq_b_timing 0 Early Condition; Flow J cc=False 0x1b89
seq_br_type 0 Branch False
seq_branch_adr 1b89 0x1b89
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
val_rand 2 DEC_LOOP_COUNTER
1b8f 1b8f typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
1b90 1b90 val_a_adr 2b VR10:0b
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1b91 1b91 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 27 VR04:07
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 4
1b92 1b92 typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
1b93 1b93 typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b94 1b94 typ_a_adr 08 GP08
typ_alu_func 1c DEC_A
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_a_adr 08 GP08
val_alu_func 1c DEC_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
1b95 1b95 typ_a_adr 08 GP08
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
1b96 1b96 val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
1b97 1b97 fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
typ_b_adr 06 GP06
val_a_adr 06 GP06
val_alu_func 0 PASS_A
1b98 1b98 fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 04 GP04
val_b_adr 04 GP04
1b99 1b99 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c20
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c20 EXTRACT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1b9a 1b9a fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_load_var 1 hold_var
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
typ_b_adr 04 GP04
val_b_adr 04 GP04
1b9b 1b9b ioc_tvbs 1 typ+fiu; Flow C cc=True 0x1c20
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 1c20 EXTRACT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 22 VR10:02
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1b9c 1b9c val_a_adr 06 GP06
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
1b9d 1b9d seq_b_timing 0 Early Condition; Flow J cc=False 0x1b97
seq_br_type 0 Branch False
seq_branch_adr 1b97 0x1b97
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1b9e 1b9e fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x1b93
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 1b93 0x1b93
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 06 GP06
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR04:0f
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 03 GP03
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1b9f 1b9f val_a_adr 2d VR10:0d
val_alu_func 0 PASS_A
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
val_frame 10
1ba0 1ba0 fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 8 type_var
fiu_vmux_sel 1 fill value
typ_a_adr 21 TR10:01
typ_alu_func 0 PASS_A
typ_b_adr 20 TR10:00
typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 21 VR04:01
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
1ba1 1ba1 typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 26 VR05:06
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1ba2 1ba2 typ_a_adr 0a GP0a
typ_alu_func 0 PASS_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
val_a_adr 0a GP0a
val_alu_func 0 PASS_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1ba3 1ba3 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36)
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
fiu_tivi_src 9 type_val
ioc_adrbs 1 val
typ_b_adr 22 TR10:02
typ_frame 10
val_a_adr 0b GP0b
val_alu_func 0 PASS_A
val_b_adr 0d GP0d
1ba4 1ba4 typ_a_adr 0c GP0c
typ_alu_func 0 PASS_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 09 GP09
val_alu_func 0 PASS_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
1ba5 1ba5 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
1ba6 1ba6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bbe
seq_br_type 1 Branch True
seq_branch_adr 1bbe 0x1bbe
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 09 GP09
typ_alu_func 0 PASS_A
val_a_adr 2b VR10:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
1ba7 1ba7 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1ba8 1ba8 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1ba9 1ba9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1baa 1baa fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bab 1bab fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bac 1bac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bad 1bad seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bb2
seq_br_type 1 Branch True
seq_branch_adr 1bb2 0x1bb2
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 0b GP0b
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1bae 1bae seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bb0
seq_br_type 0 Branch False
seq_branch_adr 1bb0 0x1bb0
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
1baf 1baf seq_br_type 3 Unconditional Branch; Flow J 0x1bc7
seq_branch_adr 1bc7 0x1bc7
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 10
1bb0 1bb0 seq_b_timing 0 Early Condition; Flow J cc=False 0x1ba7
seq_br_type 0 Branch False
seq_branch_adr 1ba7 0x1ba7
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1bb1 1bb1 seq_br_type 3 Unconditional Branch; Flow J 0x1bd4
seq_branch_adr 1bd4 0x1bd4
1bb2 1bb2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bc5
seq_br_type 1 Branch True
seq_branch_adr 1bc5 0x1bc5
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 1e A_AND_B
val_b_adr 3c VR15:1c
val_frame 15
1bb3 1bb3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bb5
seq_br_type 0 Branch False
seq_branch_adr 1bb5 0x1bb5
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
1bb4 1bb4 seq_br_type 3 Unconditional Branch; Flow J 0x1bcc
seq_branch_adr 1bcc 0x1bcc
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 10
1bb5 1bb5 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bb6 1bb6 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bb7 1bb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bb8 1bb8 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bb9 1bb9 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bba 1bba seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bbb 1bbb typ_a_adr 0b GP0b
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1bbc 1bbc seq_b_timing 0 Early Condition; Flow J cc=False 0x1bb2
seq_br_type 0 Branch False
seq_branch_adr 1bb2 0x1bb2
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1bbd 1bbd seq_br_type 3 Unconditional Branch; Flow J 0x1bd4
seq_branch_adr 1bd4 0x1bd4
1bbe 1bbe fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bbf 1bbf fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bc0 1bc0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bc1 1bc1 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bc2 1bc2 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bc3 1bc3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bc4 1bc4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bc9
seq_br_type 1 Branch True
seq_branch_adr 1bc9 0x1bc9
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 0b GP0b
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1bc5 1bc5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bc7
seq_br_type 0 Branch False
seq_branch_adr 1bc7 0x1bc7
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
1bc6 1bc6 seq_br_type 3 Unconditional Branch; Flow J 0x1bb0
seq_branch_adr 1bb0 0x1bb0
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 10
1bc7 1bc7 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bbe
seq_br_type 0 Branch False
seq_branch_adr 1bbe 0x1bbe
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1bc8 1bc8 seq_br_type 3 Unconditional Branch; Flow J 0x1bd4
seq_branch_adr 1bd4 0x1bd4
1bc9 1bc9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bae
seq_br_type 1 Branch True
seq_branch_adr 1bae 0x1bae
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 1e A_AND_B
val_b_adr 3c VR15:1c
val_frame 15
1bca 1bca seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bcc
seq_br_type 0 Branch False
seq_branch_adr 1bcc 0x1bcc
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
1bcb 1bcb seq_br_type 3 Unconditional Branch; Flow J 0x1bb5
seq_branch_adr 1bb5 0x1bb5
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 10
1bcc 1bcc fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bcd 1bcd fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bce 1bce seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bcf 1bcf fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bd0 1bd0 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
1bd1 1bd1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1bd2 1bd2 typ_a_adr 0b GP0b
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 3 LEFT_I_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
1bd3 1bd3 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bc9
seq_br_type 0 Branch False
seq_branch_adr 1bc9 0x1bc9
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
1bd4 1bd4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bd6
seq_br_type 0 Branch False
seq_branch_adr 1bd6 0x1bd6
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 09 GP09
val_alu_func 3 LEFT_I_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1bd5 1bd5 typ_a_adr 09 GP09
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 4
1bd6 1bd6 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x1ba3
fiu_tivi_src c mar_0xc
seq_br_type 1 Branch True
seq_branch_adr 1ba3 0x1ba3
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 0c GP0c
typ_alu_func 1c DEC_A
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 0d GP0d
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR05:00
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1bd7 1bd7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bd9
seq_br_type 0 Branch False
seq_branch_adr 1bd9 0x1bd9
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 0a GP0a
val_alu_func 3 LEFT_I_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
1bd8 1bd8 typ_a_adr 0a GP0a
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
1bd9 1bd9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x1ba1
fiu_tivi_src c mar_0xc
seq_br_type 1 Branch True
seq_branch_adr 1ba1 0x1ba1
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0b GP0b
val_alu_func 1c DEC_A
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
1bda 1bda fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 8 type_var
fiu_vmux_sel 1 fill value
typ_b_adr 20 TR10:00
typ_frame 10
1bdb 1bdb typ_a_adr 27 TR04:07
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 4
1bdc 1bdc typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
1bdd 1bdd typ_a_adr 28 TR10:08
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 0a GP0a
val_alu_func 0 PASS_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1bde 1bde typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 26 VR05:06
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1bdf 1bdf typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_frame 4
1be0 1be0 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
1be1 1be1 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36)
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
fiu_tivi_src 9 type_val
ioc_adrbs 2 typ
typ_a_adr 0b GP0b
typ_alu_func 0 PASS_A
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 0d GP0d
1be2 1be2 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1be3 1be3 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
1be4 1be4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1be5 1be5 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1be6 1be6 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
1be7 1be7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 1a PASS_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1be8 1be8 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bea
seq_br_type 0 Branch False
seq_branch_adr 1bea 0x1bea
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1be9 1be9 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
1bea 1bea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bf5
seq_br_type 1 Branch True
seq_branch_adr 1bf5 0x1bf5
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 09 GP09
1beb 1beb seq_b_timing 0 Early Condition; Flow J cc=False 0x1be2
seq_br_type 0 Branch False
seq_branch_adr 1be2 0x1be2
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
1bec 1bec seq_br_type 3 Unconditional Branch; Flow J 0x1bf6
seq_branch_adr 1bf6 0x1bf6
1bed 1bed fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bee 1bee fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
1bef 1bef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 1a PASS_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1bf0 1bf0 fiu_fill_mode_src 0
fiu_length_src 0 length_register
fiu_load_mdr 1 hold_mdr
fiu_offset_src 0 offset_register
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
val_a_adr 0c GP0c
1bf1 1bf1 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 40
fiu_op_sel 3 insert
ioc_fiubs 0 fiu
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
1bf2 1bf2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1c1e
seq_br_type 5 Call True
seq_branch_adr 1c1e 0x1c1e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1bf3 1bf3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bf5
seq_br_type 0 Branch False
seq_branch_adr 1bf5 0x1bf5
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 0c GP0c
val_alu_func 3 LEFT_I_A
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1bf4 1bf4 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
1bf5 1bf5 seq_b_timing 0 Early Condition; Flow J cc=False 0x1bed
seq_br_type 0 Branch False
seq_branch_adr 1bed 0x1bed
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
1bf6 1bf6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bf8
seq_br_type 0 Branch False
seq_branch_adr 1bf8 0x1bf8
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 04 GP04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1bf7 1bf7 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
1bf8 1bf8 val_a_adr 0d GP0d
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR05:00
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1bf9 1bf9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x1bdf
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 1bdf 0x1bdf
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 09 GP09
val_alu_func 1e A_AND_B
val_b_adr 3c VR15:1c
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 15
1bfa 1bfa seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1bfc
seq_br_type 0 Branch False
seq_branch_adr 1bfc 0x1bfc
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 0a GP0a
val_alu_func 7 INC_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
1bfb 1bfb typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1bfc 1bfc fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x1bdd
fiu_tivi_src c mar_0xc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 0 Branch False
seq_branch_adr 1bdd 0x1bdd
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 0b GP0b
typ_alu_func 1c DEC_A
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_a_adr 0a GP0a
val_alu_func 1e A_AND_B
val_b_adr 3c VR15:1c
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
1bfd 1bfd seq_br_type a Unconditional Return; Flow R
1bfe ; --------------------------------------------------------------------------------------
1bfe ; Comes from:
1bfe ; 1a03 C True from color 0x1a00
1bfe ; 1a07 C True from color 0x1a00
1bfe ; 1a09 C True from color 0x1a00
1bfe ; 1a0c C True from color 0x1a00
1bfe ; 1a0f C True from color 0x1a00
1bfe ; 1a12 C True from color 0x1a00
1bfe ; 1a15 C True from color 0x1a00
1bfe ; 1a18 C True from color 0x1a00
1bfe ; 1a1b C True from color 0x1a00
1bfe ; 1a1e C True from color 0x1a00
1bfe ; --------------------------------------------------------------------------------------
1bfe OFFSET_ERROR:
1bfe 1bfe <halt> ; Flow R
1bff 1bff seq_br_type a Unconditional Return; Flow R
1c00 ; --------------------------------------------------------------------------------------
1c00 ; Comes from:
1c00 ; 1a23 C True from color 0x1a00
1c00 ; 1a29 C True from color 0x1a00
1c00 ; 1a2d C True from color 0x1a00
1c00 ; 1a31 C True from color 0x1a00
1c00 ; 1a36 C True from color 0x1a00
1c00 ; 1a3a C True from color 0x1a00
1c00 ; 1a3d C True from color 0x1a00
1c00 ; 1a40 C True from color 0x1a00
1c00 ; 1a43 C True from color 0x1a00
1c00 ; 1a46 C True from color 0x1a00
1c00 ; 1a49 C True from color 0x1a00
1c00 ; 1a4c C True from color 0x1a00
1c00 ; 1a4f C True from color 0x1a00
1c00 ; 1a52 C True from color 0x1a00
1c00 ; 1a55 C True from color 0x1a00
1c00 ; 1a58 C True from color 0x1a00
1c00 ; 1a5b C True from color 0x1a00
1c00 ; 1a5e C True from color 0x1a00
1c00 ; 1a61 C True from color 0x1a00
1c00 ; 1a64 C True from color 0x1a00
1c00 ; 1a67 C True from color 0x1a00
1c00 ; 1a6a C True from color 0x1a00
1c00 ; 1a6d C True from color 0x1a00
1c00 ; 1a70 C True from color 0x1a00
1c00 ; 1a73 C True from color 0x1a00
1c00 ; 1a76 C True from color 0x1a00
1c00 ; 1a79 C True from color 0x1a00
1c00 ; 1a7c C True from color 0x1a00
1c00 ; 1a7f C True from color 0x1a00
1c00 ; 1a82 C True from color 0x1a00
1c00 ; 1a85 C True from color 0x1a00
1c00 ; 1a88 C True from color 0x1a00
1c00 ; 1a8b C True from color 0x1a00
1c00 ; --------------------------------------------------------------------------------------
1c00 LENGTH_ERROR:
1c00 1c00 <halt> ; Flow R
1c01 1c01 seq_br_type a Unconditional Return; Flow R
1c02 ; --------------------------------------------------------------------------------------
1c02 ; Comes from:
1c02 ; 1a8d C False from color 0x1a00
1c02 ; 1a8e C False from color 0x1a00
1c02 ; 1a8f C False from color 0x1a00
1c02 ; 1a90 C False from color 0x1a00
1c02 ; 1a91 C False from color 0x1a00
1c02 ; 1a92 C False from color 0x1a00
1c02 ; 1a94 C False from color 0x1a00
1c02 ; 1a95 C False from color 0x1a00
1c02 ; 1a96 C False from color 0x1a00
1c02 ; 1a97 C False from color 0x1a00
1c02 ; 1a98 C False from color 0x1a00
1c02 ; 1a99 C False from color 0x1a00
1c02 ; 1a9b C False from color 0x1a00
1c02 ; 1a9c C False from color 0x1a00
1c02 ; 1a9d C False from color 0x1a00
1c02 ; 1a9e C False from color 0x1a00
1c02 ; 1a9f C False from color 0x1a00
1c02 ; 1aa0 C False from color 0x1a00
1c02 ; 1aa2 C False from color 0x1a00
1c02 ; 1aa3 C False from color 0x1a00
1c02 ; 1aa4 C False from color 0x1a00
1c02 ; 1aa5 C False from color 0x1a00
1c02 ; 1aa6 C False from color 0x1a00
1c02 ; 1aa7 C True from color 0x1a00
1c02 ; 1aa9 C False from color 0x1a00
1c02 ; 1aaa C False from color 0x1a00
1c02 ; 1aab C False from color 0x1a00
1c02 ; 1aac C True from color 0x1a00
1c02 ; 1aad C True from color 0x1a00
1c02 ; 1aae C True from color 0x1a00
1c02 ; 1ab0 C False from color 0x1a00
1c02 ; 1ab1 C False from color 0x1a00
1c02 ; 1ab2 C False from color 0x1a00
1c02 ; 1ab3 C False from color 0x1a00
1c02 ; 1ab4 C False from color 0x1a00
1c02 ; 1ab5 C True from color 0x1a00
1c02 ; 1ab6 C True from color 0x1a00
1c02 ; 1ab7 C True from color 0x1a00
1c02 ; 1ab8 C True from color 0x1a00
1c02 ; 1ab9 C True from color 0x1a00
1c02 ; 1abb C False from color 0x1a00
1c02 ; 1abc C False from color 0x1a00
1c02 ; 1abd C False from color 0x1a00
1c02 ; 1abe C True from color 0x1a00
1c02 ; 1abf C True from color 0x1a00
1c02 ; 1ac0 C True from color 0x1a00
1c02 ; 1ac1 C True from color 0x1a00
1c02 ; 1ac2 C True from color 0x1a00
1c02 ; --------------------------------------------------------------------------------------
1c02 XWORD_ERROR:
1c02 1c02 <halt> ; Flow R
1c03 1c03 seq_br_type a Unconditional Return; Flow R
1c04 ; --------------------------------------------------------------------------------------
1c04 ; Comes from:
1c04 ; 1ac7 C from color 0x1a00
1c04 ; 1aca C from color 0x1a00
1c04 ; 1ace C False from color 0x1a00
1c04 ; 1ad0 C False from color 0x1a00
1c04 ; 1ad3 C True from color 0x1a00
1c04 ; 1ad4 C False from color 0x1a00
1c04 ; --------------------------------------------------------------------------------------
1c04 MAR_WORD_EQ_ZERO_ERROR:
1c04 1c04 <halt> ; Flow R
1c05 1c05 seq_br_type a Unconditional Return; Flow R
1c06 ; --------------------------------------------------------------------------------------
1c06 ; Comes from:
1c06 ; 1ad7 C True from color 0x1a00
1c06 ; 1ad9 C True from color 0x1a00
1c06 ; 1adb C True from color 0x1a00
1c06 ; 1add C True from color 0x1a00
1c06 ; --------------------------------------------------------------------------------------
1c06 VAR_ERROR:
1c06 1c06 <halt> ; Flow R
1c07 1c07 seq_br_type a Unconditional Return; Flow R
1c08 ; --------------------------------------------------------------------------------------
1c08 ; Comes from:
1c08 ; 1ae1 C True from color 0x1a00
1c08 ; 1ae3 C True from color 0x1a00
1c08 ; 1ae5 C True from color 0x1a00
1c08 ; 1ae7 C True from color 0x1a00
1c08 ; --------------------------------------------------------------------------------------
1c08 TAR_ERROR:
1c08 1c08 <halt> ; Flow R
1c09 1c09 seq_br_type a Unconditional Return; Flow R
1c0a ; --------------------------------------------------------------------------------------
1c0a ; Comes from:
1c0a ; 1aec C True from color 0x1a00
1c0a ; 1aed C True from color 0x1a00
1c0a ; 1af0 C True from color 0x1a00
1c0a ; 1af1 C True from color 0x1a00
1c0a ; 1af4 C True from color 0x1a00
1c0a ; 1af5 C True from color 0x1a00
1c0a ; 1af8 C True from color 0x1a00
1c0a ; 1af9 C True from color 0x1a00
1c0a ; --------------------------------------------------------------------------------------
1c0a MDR_ERROR:
1c0a 1c0a <halt> ; Flow R
1c0b 1c0b seq_br_type a Unconditional Return; Flow R
1c0c ; --------------------------------------------------------------------------------------
1c0c ; Comes from:
1c0c ; 1afd C True from color 0x1a00
1c0c ; 1b00 C True from color 0x1a00
1c0c ; 1b02 C True from color 0x1a00
1c0c ; 1b05 C True from color 0x1a00
1c0c ; --------------------------------------------------------------------------------------
1c0c VI_MUX_FIU_ERROR:
1c0c 1c0c <halt> ; Flow R
1c0d 1c0d seq_br_type a Unconditional Return; Flow R
1c0e ; --------------------------------------------------------------------------------------
1c0e ; Comes from:
1c0e ; 1b09 C True from color 0x1a00
1c0e ; 1b0c C True from color 0x1a00
1c0e ; 1b0e C True from color 0x1a00
1c0e ; 1b11 C True from color 0x1a00
1c0e ; 1b14 C True from color 0x1a00
1c0e ; 1b16 C True from color 0x1a00
1c0e ; 1b18 C True from color 0x1a00
1c0e ; 1b1a C True from color 0x1a00
1c0e ; --------------------------------------------------------------------------------------
1c0e MERGE_V_MUX_FIU_ERROR:
1c0e 1c0e <halt> ; Flow R
1c0f 1c0f seq_br_type a Unconditional Return; Flow R
1c10 ; --------------------------------------------------------------------------------------
1c10 ; Comes from:
1c10 ; 1b1d C True from color 0x1a00
1c10 ; 1b20 C True from color 0x1a00
1c10 ; 1b22 C True from color 0x1a00
1c10 ; 1b25 C True from color 0x1a00
1c10 ; --------------------------------------------------------------------------------------
1c10 TI_MUX_FIU_ERROR:
1c10 1c10 <halt> ; Flow R
1c11 1c11 seq_br_type a Unconditional Return; Flow R
1c12 ; --------------------------------------------------------------------------------------
1c12 ; Comes from:
1c12 ; 1b2a C True from color 0x1a00
1c12 ; 1b2c C True from color 0x1a00
1c12 ; 1b2f C True from color 0x1a00
1c12 ; 1b31 C True from color 0x1a00
1c12 ; 1b33 C True from color 0x1a00
1c12 ; 1b35 C True from color 0x1a00
1c12 ; 1b37 C True from color 0x1a00
1c12 ; 1b39 C True from color 0x1a00
1c12 ; --------------------------------------------------------------------------------------
1c12 FILL_BIT_ERROR:
1c12 1c12 <halt> ; Flow R
1c13 1c13 seq_br_type a Unconditional Return; Flow R
1c14 ; --------------------------------------------------------------------------------------
1c14 ; Comes from:
1c14 ; 1b3f C True from color 0x1a00
1c14 ; 1b42 C True from color 0x1a00
1c14 ; --------------------------------------------------------------------------------------
1c14 MERGER_EXTRACT_ERROR:
1c14 1c14 <halt> ; Flow R
1c15 1c15 seq_br_type a Unconditional Return; Flow R
1c16 ; --------------------------------------------------------------------------------------
1c16 ; Comes from:
1c16 ; 1b51 C True from color 0x1a00
1c16 ; 1b54 C True from color 0x1a00
1c16 ; --------------------------------------------------------------------------------------
1c16 MERGER_INSERT_V_ERROR:
1c16 1c16 <halt> ; Flow R
1c17 1c17 seq_br_type a Unconditional Return; Flow R
1c18 ; --------------------------------------------------------------------------------------
1c18 ; Comes from:
1c18 ; 1b48 C True from color 0x1a00
1c18 ; 1b4b C True from color 0x1a00
1c18 ; --------------------------------------------------------------------------------------
1c18 MERGER_INSERT_T_ERROR:
1c18 1c18 <halt> ; Flow R
1c19 1c19 seq_br_type a Unconditional Return; Flow R
1c1a ; --------------------------------------------------------------------------------------
1c1a ; Comes from:
1c1a ; 1b5d C True from color 0x1a00
1c1a ; 1b60 C True from color 0x1a00
1c1a ; 1b65 C True from color 0x1a00
1c1a ; 1b68 C True from color 0x1a00
1c1a ; --------------------------------------------------------------------------------------
1c1a MERGER_INSERT_ERROR:
1c1a 1c1a <halt> ; Flow R
1c1b 1c1b seq_br_type a Unconditional Return; Flow R
1c1c ; --------------------------------------------------------------------------------------
1c1c ; Comes from:
1c1c ; 1b71 C True from color 0x1a00
1c1c ; 1b7a C True from color 0x1a00
1c1c ; 1b83 C True from color 0x1a00
1c1c ; 1b8c C True from color 0x1a00
1c1c ; --------------------------------------------------------------------------------------
1c1c ROTATE_ERROR:
1c1c 1c1c <halt> ; Flow R
1c1d 1c1d seq_br_type a Unconditional Return; Flow R
1c1e ; --------------------------------------------------------------------------------------
1c1e ; Comes from:
1c1e ; 1ba9 C True from color 0x1a00
1c1e ; 1bac C True from color 0x1a00
1c1e ; 1bb7 C True from color 0x1a00
1c1e ; 1bba C True from color 0x1a00
1c1e ; 1bc0 C True from color 0x1a00
1c1e ; 1bc3 C True from color 0x1a00
1c1e ; 1bce C True from color 0x1a00
1c1e ; 1bd1 C True from color 0x1a00
1c1e ; 1be4 C True from color 0x1a00
1c1e ; 1be7 C True from color 0x1a00
1c1e ; 1bef C True from color 0x1a00
1c1e ; 1bf2 C True from color 0x1a00
1c1e ; --------------------------------------------------------------------------------------
1c1e 1c1e <halt> ; Flow R
1c1f 1c1f seq_br_type a Unconditional Return; Flow R
1c20 ; --------------------------------------------------------------------------------------
1c20 ; Comes from:
1c20 ; 1b99 C True from color 0x1a00
1c20 ; 1b9b C True from color 0x1a00
1c20 ; --------------------------------------------------------------------------------------
1c20 EXTRACT_ERROR:
1c20 1c20 <halt> ; Flow R
1c21 1c21 seq_br_type a Unconditional Return; Flow R
1c22 INSERT_ERROR:
1c22 1c22 <halt> ; Flow R
1c23 1c23 seq_br_type a Unconditional Return; Flow R
1c24 1c24 <halt> ; Flow R
1c25 1c25 <halt> ; Flow R
1c26 1c26 <halt> ; Flow R
1c27 1c27 <halt> ; Flow R
1c28 1c28 <halt> ; Flow R
1c29 1c29 <halt> ; Flow R
1c2a 1c2a <halt> ; Flow R
1c2b 1c2b <halt> ; Flow R
1c2c 1c2c <halt> ; Flow R
1c2d 1c2d <halt> ; Flow R
1c2e 1c2e <halt> ; Flow R
1c2f 1c2f <halt> ; Flow R
1c30 1c30 <halt> ; Flow R
1c31 1c31 <halt> ; Flow R
1c32 1c32 <halt> ; Flow R
1c33 1c33 <halt> ; Flow R
1c34 1c34 <halt> ; Flow R
1c35 1c35 <halt> ; Flow R
1c36 1c36 <halt> ; Flow R
1c37 1c37 <halt> ; Flow R
1c38 1c38 <halt> ; Flow R
1c39 1c39 <halt> ; Flow R
1c3a 1c3a <halt> ; Flow R
1c3b 1c3b <halt> ; Flow R
1c3c 1c3c <halt> ; Flow R
1c3d 1c3d <halt> ; Flow R
1c3e 1c3e <halt> ; Flow R
1c3f 1c3f <halt> ; Flow R
1c40 1c40 <halt> ; Flow R
1c41 1c41 <halt> ; Flow R
1c42 1c42 <halt> ; Flow R
1c43 1c43 <halt> ; Flow R
1c44 1c44 <halt> ; Flow R
1c45 1c45 <halt> ; Flow R
1c46 1c46 <halt> ; Flow R
1c47 1c47 <halt> ; Flow R
1c48 1c48 <halt> ; Flow R
1c49 1c49 <halt> ; Flow R
1c4a 1c4a <halt> ; Flow R
1c4b 1c4b <halt> ; Flow R
1c4c 1c4c <halt> ; Flow R
1c4d 1c4d <halt> ; Flow R
1c4e 1c4e <halt> ; Flow R
1c4f 1c4f <halt> ; Flow R
1c50 1c50 <halt> ; Flow R
1c51 1c51 <halt> ; Flow R
1c52 1c52 <halt> ; Flow R
1c53 1c53 <halt> ; Flow R
1c54 1c54 <halt> ; Flow R
1c55 1c55 <halt> ; Flow R
1c56 1c56 <halt> ; Flow R
1c57 1c57 <halt> ; Flow R
1c58 1c58 <halt> ; Flow R
1c59 1c59 <halt> ; Flow R
1c5a 1c5a <halt> ; Flow R
1c5b 1c5b <halt> ; Flow R
1c5c 1c5c <halt> ; Flow R
1c5d 1c5d <halt> ; Flow R
1c5e 1c5e <halt> ; Flow R
1c5f 1c5f <halt> ; Flow R
1c60 1c60 <halt> ; Flow R
1c61 1c61 <halt> ; Flow R
1c62 1c62 <halt> ; Flow R
1c63 1c63 <halt> ; Flow R
1c64 1c64 <halt> ; Flow R
1c65 1c65 <halt> ; Flow R
1c66 1c66 <halt> ; Flow R
1c67 1c67 <halt> ; Flow R
1c68 1c68 <halt> ; Flow R
1c69 1c69 <halt> ; Flow R
1c6a 1c6a <halt> ; Flow R
1c6b 1c6b <halt> ; Flow R
1c6c 1c6c <halt> ; Flow R
1c6d 1c6d <halt> ; Flow R
1c6e 1c6e <halt> ; Flow R
1c6f 1c6f <halt> ; Flow R
1c70 1c70 <halt> ; Flow R
1c71 1c71 <halt> ; Flow R
1c72 1c72 <halt> ; Flow R
1c73 1c73 <halt> ; Flow R
1c74 1c74 <halt> ; Flow R
1c75 1c75 <halt> ; Flow R
1c76 1c76 <halt> ; Flow R
1c77 1c77 <halt> ; Flow R
1c78 1c78 <halt> ; Flow R
1c79 1c79 <halt> ; Flow R
1c7a 1c7a <halt> ; Flow R
1c7b 1c7b <halt> ; Flow R
1c7c 1c7c <halt> ; Flow R
1c7d 1c7d <halt> ; Flow R
1c7e 1c7e <halt> ; Flow R
1c7f 1c7f <halt> ; Flow R
1c80 1c80 <halt> ; Flow R
1c81 1c81 <halt> ; Flow R
1c82 1c82 <halt> ; Flow R
1c83 1c83 <halt> ; Flow R
1c84 1c84 <halt> ; Flow R
1c85 1c85 <halt> ; Flow R
1c86 1c86 <halt> ; Flow R
1c87 1c87 <halt> ; Flow R
1c88 1c88 <halt> ; Flow R
1c89 1c89 <halt> ; Flow R
1c8a 1c8a <halt> ; Flow R
1c8b 1c8b <halt> ; Flow R
1c8c 1c8c <halt> ; Flow R
1c8d 1c8d <halt> ; Flow R
1c8e 1c8e <halt> ; Flow R
1c8f 1c8f <halt> ; Flow R
1c90 1c90 <halt> ; Flow R
1c91 1c91 <halt> ; Flow R
1c92 1c92 <halt> ; Flow R
1c93 1c93 <halt> ; Flow R
1c94 1c94 <halt> ; Flow R
1c95 1c95 <halt> ; Flow R
1c96 1c96 <halt> ; Flow R
1c97 1c97 <halt> ; Flow R
1c98 1c98 <halt> ; Flow R
1c99 1c99 <halt> ; Flow R
1c9a 1c9a <halt> ; Flow R
1c9b 1c9b <halt> ; Flow R
1c9c 1c9c <halt> ; Flow R
1c9d 1c9d <halt> ; Flow R
1c9e 1c9e <halt> ; Flow R
1c9f 1c9f <halt> ; Flow R
1ca0 1ca0 <halt> ; Flow R
1ca1 1ca1 <halt> ; Flow R
1ca2 1ca2 <halt> ; Flow R
1ca3 1ca3 <halt> ; Flow R
1ca4 1ca4 <halt> ; Flow R
1ca5 1ca5 <halt> ; Flow R
1ca6 1ca6 <halt> ; Flow R
1ca7 1ca7 <halt> ; Flow R
1ca8 1ca8 <halt> ; Flow R
1ca9 1ca9 <halt> ; Flow R
1caa 1caa <halt> ; Flow R
1cab 1cab <halt> ; Flow R
1cac 1cac <halt> ; Flow R
1cad 1cad <halt> ; Flow R
1cae 1cae <halt> ; Flow R
1caf 1caf <halt> ; Flow R
1cb0 1cb0 <halt> ; Flow R
1cb1 1cb1 <halt> ; Flow R
1cb2 1cb2 <halt> ; Flow R
1cb3 1cb3 <halt> ; Flow R
1cb4 1cb4 <halt> ; Flow R
1cb5 1cb5 <halt> ; Flow R
1cb6 1cb6 <halt> ; Flow R
1cb7 1cb7 <halt> ; Flow R
1cb8 1cb8 <halt> ; Flow R
1cb9 1cb9 <halt> ; Flow R
1cba 1cba <halt> ; Flow R
1cbb 1cbb <halt> ; Flow R
1cbc 1cbc <halt> ; Flow R
1cbd 1cbd <halt> ; Flow R
1cbe 1cbe <halt> ; Flow R
1cbf 1cbf <halt> ; Flow R
1cc0 1cc0 <halt> ; Flow R
1cc1 1cc1 <halt> ; Flow R
1cc2 1cc2 <halt> ; Flow R
1cc3 1cc3 <halt> ; Flow R
1cc4 1cc4 <halt> ; Flow R
1cc5 1cc5 <halt> ; Flow R
1cc6 1cc6 <halt> ; Flow R
1cc7 1cc7 <halt> ; Flow R
1cc8 1cc8 <halt> ; Flow R
1cc9 1cc9 <halt> ; Flow R
1cca 1cca <halt> ; Flow R
1ccb 1ccb <halt> ; Flow R
1ccc 1ccc <halt> ; Flow R
1ccd 1ccd <halt> ; Flow R
1cce 1cce <halt> ; Flow R
1ccf 1ccf <halt> ; Flow R
1cd0 1cd0 <halt> ; Flow R
1cd1 1cd1 <halt> ; Flow R
1cd2 1cd2 <halt> ; Flow R
1cd3 1cd3 <halt> ; Flow R
1cd4 1cd4 <halt> ; Flow R
1cd5 1cd5 <halt> ; Flow R
1cd6 1cd6 <halt> ; Flow R
1cd7 1cd7 <halt> ; Flow R
1cd8 1cd8 <halt> ; Flow R
1cd9 1cd9 <halt> ; Flow R
1cda 1cda <halt> ; Flow R
1cdb 1cdb <halt> ; Flow R
1cdc 1cdc <halt> ; Flow R
1cdd 1cdd <halt> ; Flow R
1cde 1cde <halt> ; Flow R
1cdf 1cdf <halt> ; Flow R
1ce0 1ce0 <halt> ; Flow R
1ce1 1ce1 <halt> ; Flow R
1ce2 1ce2 <halt> ; Flow R
1ce3 1ce3 <halt> ; Flow R
1ce4 1ce4 <halt> ; Flow R
1ce5 1ce5 <halt> ; Flow R
1ce6 1ce6 <halt> ; Flow R
1ce7 1ce7 <halt> ; Flow R
1ce8 1ce8 <halt> ; Flow R
1ce9 1ce9 <halt> ; Flow R
1cea 1cea <halt> ; Flow R
1ceb 1ceb <halt> ; Flow R
1cec 1cec <halt> ; Flow R
1ced 1ced <halt> ; Flow R
1cee 1cee <halt> ; Flow R
1cef 1cef <halt> ; Flow R
1cf0 1cf0 <halt> ; Flow R
1cf1 1cf1 <halt> ; Flow R
1cf2 1cf2 <halt> ; Flow R
1cf3 1cf3 <halt> ; Flow R
1cf4 1cf4 <halt> ; Flow R
1cf5 1cf5 <halt> ; Flow R
1cf6 1cf6 <halt> ; Flow R
1cf7 1cf7 <halt> ; Flow R
1cf8 1cf8 <halt> ; Flow R
1cf9 1cf9 <halt> ; Flow R
1cfa 1cfa <halt> ; Flow R
1cfb 1cfb <halt> ; Flow R
1cfc 1cfc <halt> ; Flow R
1cfd 1cfd <halt> ; Flow R
1cfe 1cfe <halt> ; Flow R
1cff 1cff <halt> ; Flow R
1d00 1d00 <halt> ; Flow R
1d01 1d01 <halt> ; Flow R
1d02 1d02 <halt> ; Flow R
1d03 1d03 <halt> ; Flow R
1d04 1d04 <halt> ; Flow R
1d05 1d05 <halt> ; Flow R
1d06 1d06 <halt> ; Flow R
1d07 1d07 <halt> ; Flow R
1d08 1d08 <halt> ; Flow R
1d09 1d09 <halt> ; Flow R
1d0a 1d0a <halt> ; Flow R
1d0b 1d0b <halt> ; Flow R
1d0c 1d0c <halt> ; Flow R
1d0d 1d0d <halt> ; Flow R
1d0e 1d0e <halt> ; Flow R
1d0f 1d0f <halt> ; Flow R
1d10 1d10 <halt> ; Flow R
1d11 1d11 <halt> ; Flow R
1d12 1d12 <halt> ; Flow R
1d13 1d13 <halt> ; Flow R
1d14 1d14 <halt> ; Flow R
1d15 1d15 <halt> ; Flow R
1d16 1d16 <halt> ; Flow R
1d17 1d17 <halt> ; Flow R
1d18 1d18 <halt> ; Flow R
1d19 1d19 <halt> ; Flow R
1d1a 1d1a <halt> ; Flow R
1d1b 1d1b <halt> ; Flow R
1d1c 1d1c <halt> ; Flow R
1d1d 1d1d <halt> ; Flow R
1d1e 1d1e <halt> ; Flow R
1d1f 1d1f <halt> ; Flow R
1d20 1d20 <halt> ; Flow R
1d21 1d21 <halt> ; Flow R
1d22 1d22 <halt> ; Flow R
1d23 1d23 <halt> ; Flow R
1d24 1d24 <halt> ; Flow R
1d25 1d25 <halt> ; Flow R
1d26 1d26 <halt> ; Flow R
1d27 1d27 <halt> ; Flow R
1d28 1d28 <halt> ; Flow R
1d29 1d29 <halt> ; Flow R
1d2a 1d2a <halt> ; Flow R
1d2b 1d2b <halt> ; Flow R
1d2c 1d2c <halt> ; Flow R
1d2d 1d2d <halt> ; Flow R
1d2e 1d2e <halt> ; Flow R
1d2f 1d2f <halt> ; Flow R
1d30 1d30 <halt> ; Flow R
1d31 1d31 <halt> ; Flow R
1d32 1d32 <halt> ; Flow R
1d33 1d33 <halt> ; Flow R
1d34 1d34 <halt> ; Flow R
1d35 1d35 <halt> ; Flow R
1d36 1d36 <halt> ; Flow R
1d37 1d37 <halt> ; Flow R
1d38 1d38 <halt> ; Flow R
1d39 1d39 <halt> ; Flow R
1d3a 1d3a <halt> ; Flow R
1d3b 1d3b <halt> ; Flow R
1d3c 1d3c <halt> ; Flow R
1d3d 1d3d <halt> ; Flow R
1d3e 1d3e <halt> ; Flow R
1d3f 1d3f <halt> ; Flow R
1d40 1d40 <halt> ; Flow R
1d41 1d41 <halt> ; Flow R
1d42 1d42 <halt> ; Flow R
1d43 1d43 <halt> ; Flow R
1d44 1d44 <halt> ; Flow R
1d45 1d45 <halt> ; Flow R
1d46 1d46 <halt> ; Flow R
1d47 1d47 <halt> ; Flow R
1d48 1d48 <halt> ; Flow R
1d49 1d49 <halt> ; Flow R
1d4a 1d4a <halt> ; Flow R
1d4b 1d4b <halt> ; Flow R
1d4c 1d4c <halt> ; Flow R
1d4d 1d4d <halt> ; Flow R
1d4e 1d4e <halt> ; Flow R
1d4f 1d4f <halt> ; Flow R
1d50 1d50 <halt> ; Flow R
1d51 1d51 <halt> ; Flow R
1d52 1d52 <halt> ; Flow R
1d53 1d53 <halt> ; Flow R
1d54 1d54 <halt> ; Flow R
1d55 1d55 <halt> ; Flow R
1d56 1d56 <halt> ; Flow R
1d57 1d57 <halt> ; Flow R
1d58 1d58 <halt> ; Flow R
1d59 1d59 <halt> ; Flow R
1d5a 1d5a <halt> ; Flow R
1d5b 1d5b <halt> ; Flow R
1d5c 1d5c <halt> ; Flow R
1d5d 1d5d <halt> ; Flow R
1d5e 1d5e <halt> ; Flow R
1d5f 1d5f <halt> ; Flow R
1d60 1d60 <halt> ; Flow R
1d61 1d61 <halt> ; Flow R
1d62 1d62 <halt> ; Flow R
1d63 1d63 <halt> ; Flow R
1d64 1d64 <halt> ; Flow R
1d65 1d65 <halt> ; Flow R
1d66 1d66 <halt> ; Flow R
1d67 1d67 <halt> ; Flow R
1d68 1d68 <halt> ; Flow R
1d69 1d69 <halt> ; Flow R
1d6a 1d6a <halt> ; Flow R
1d6b 1d6b <halt> ; Flow R
1d6c 1d6c <halt> ; Flow R
1d6d 1d6d <halt> ; Flow R
1d6e 1d6e <halt> ; Flow R
1d6f 1d6f <halt> ; Flow R
1d70 1d70 <halt> ; Flow R
1d71 1d71 <halt> ; Flow R
1d72 1d72 <halt> ; Flow R
1d73 1d73 <halt> ; Flow R
1d74 1d74 <halt> ; Flow R
1d75 1d75 <halt> ; Flow R
1d76 1d76 <halt> ; Flow R
1d77 1d77 <halt> ; Flow R
1d78 1d78 <halt> ; Flow R
1d79 1d79 <halt> ; Flow R
1d7a 1d7a <halt> ; Flow R
1d7b 1d7b <halt> ; Flow R
1d7c 1d7c <halt> ; Flow R
1d7d 1d7d <halt> ; Flow R
1d7e 1d7e <halt> ; Flow R
1d7f 1d7f <halt> ; Flow R
1d80 1d80 <halt> ; Flow R
1d81 1d81 <halt> ; Flow R
1d82 1d82 <halt> ; Flow R
1d83 1d83 <halt> ; Flow R
1d84 1d84 <halt> ; Flow R
1d85 1d85 <halt> ; Flow R
1d86 1d86 <halt> ; Flow R
1d87 1d87 <halt> ; Flow R
1d88 1d88 <halt> ; Flow R
1d89 1d89 <halt> ; Flow R
1d8a 1d8a <halt> ; Flow R
1d8b 1d8b <halt> ; Flow R
1d8c 1d8c <halt> ; Flow R
1d8d 1d8d <halt> ; Flow R
1d8e 1d8e <halt> ; Flow R
1d8f 1d8f <halt> ; Flow R
1d90 1d90 <halt> ; Flow R
1d91 1d91 <halt> ; Flow R
1d92 1d92 <halt> ; Flow R
1d93 1d93 <halt> ; Flow R
1d94 1d94 <halt> ; Flow R
1d95 1d95 <halt> ; Flow R
1d96 1d96 <halt> ; Flow R
1d97 1d97 <halt> ; Flow R
1d98 1d98 <halt> ; Flow R
1d99 1d99 <halt> ; Flow R
1d9a 1d9a <halt> ; Flow R
1d9b 1d9b <halt> ; Flow R
1d9c 1d9c <halt> ; Flow R
1d9d 1d9d <halt> ; Flow R
1d9e 1d9e <halt> ; Flow R
1d9f 1d9f <halt> ; Flow R
1da0 1da0 <halt> ; Flow R
1da1 1da1 <halt> ; Flow R
1da2 1da2 <halt> ; Flow R
1da3 1da3 <halt> ; Flow R
1da4 1da4 <halt> ; Flow R
1da5 1da5 <halt> ; Flow R
1da6 1da6 <halt> ; Flow R
1da7 1da7 <halt> ; Flow R
1da8 1da8 <halt> ; Flow R
1da9 1da9 <halt> ; Flow R
1daa 1daa <halt> ; Flow R
1dab 1dab <halt> ; Flow R
1dac 1dac <halt> ; Flow R
1dad 1dad <halt> ; Flow R
1dae 1dae <halt> ; Flow R
1daf 1daf <halt> ; Flow R
1db0 1db0 <halt> ; Flow R
1db1 1db1 <halt> ; Flow R
1db2 1db2 <halt> ; Flow R
1db3 1db3 <halt> ; Flow R
1db4 1db4 <halt> ; Flow R
1db5 1db5 <halt> ; Flow R
1db6 1db6 <halt> ; Flow R
1db7 1db7 <halt> ; Flow R
1db8 1db8 <halt> ; Flow R
1db9 1db9 <halt> ; Flow R
1dba 1dba <halt> ; Flow R
1dbb 1dbb <halt> ; Flow R
1dbc 1dbc <halt> ; Flow R
1dbd 1dbd <halt> ; Flow R
1dbe 1dbe <halt> ; Flow R
1dbf 1dbf <halt> ; Flow R
1dc0 1dc0 <halt> ; Flow R
1dc1 1dc1 <halt> ; Flow R
1dc2 1dc2 <halt> ; Flow R
1dc3 1dc3 <halt> ; Flow R
1dc4 1dc4 <halt> ; Flow R
1dc5 1dc5 <halt> ; Flow R
1dc6 1dc6 <halt> ; Flow R
1dc7 1dc7 <halt> ; Flow R
1dc8 1dc8 <halt> ; Flow R
1dc9 1dc9 <halt> ; Flow R
1dca 1dca <halt> ; Flow R
1dcb 1dcb <halt> ; Flow R
1dcc 1dcc <halt> ; Flow R
1dcd 1dcd <halt> ; Flow R
1dce 1dce <halt> ; Flow R
1dcf 1dcf <halt> ; Flow R
1dd0 1dd0 <halt> ; Flow R
1dd1 1dd1 <halt> ; Flow R
1dd2 1dd2 <halt> ; Flow R
1dd3 1dd3 <halt> ; Flow R
1dd4 1dd4 <halt> ; Flow R
1dd5 1dd5 <halt> ; Flow R
1dd6 1dd6 <halt> ; Flow R
1dd7 1dd7 <halt> ; Flow R
1dd8 1dd8 <halt> ; Flow R
1dd9 1dd9 <halt> ; Flow R
1dda 1dda <halt> ; Flow R
1ddb 1ddb <halt> ; Flow R
1ddc 1ddc <halt> ; Flow R
1ddd 1ddd <halt> ; Flow R
1dde 1dde <halt> ; Flow R
1ddf 1ddf <halt> ; Flow R
1de0 1de0 <halt> ; Flow R
1de1 1de1 <halt> ; Flow R
1de2 1de2 <halt> ; Flow R
1de3 1de3 <halt> ; Flow R
1de4 1de4 <halt> ; Flow R
1de5 1de5 <halt> ; Flow R
1de6 1de6 <halt> ; Flow R
1de7 1de7 <halt> ; Flow R
1de8 1de8 <halt> ; Flow R
1de9 1de9 <halt> ; Flow R
1dea 1dea <halt> ; Flow R
1deb 1deb <halt> ; Flow R
1dec 1dec <halt> ; Flow R
1ded 1ded <halt> ; Flow R
1dee 1dee <halt> ; Flow R
1def 1def <halt> ; Flow R
1df0 1df0 <halt> ; Flow R
1df1 1df1 <halt> ; Flow R
1df2 1df2 <halt> ; Flow R
1df3 1df3 <halt> ; Flow R
1df4 1df4 <halt> ; Flow R
1df5 1df5 <halt> ; Flow R
1df6 1df6 <halt> ; Flow R
1df7 1df7 <halt> ; Flow R
1df8 1df8 <halt> ; Flow R
1df9 1df9 <halt> ; Flow R
1dfa 1dfa <halt> ; Flow R
1dfb 1dfb <halt> ; Flow R
1dfc 1dfc <halt> ; Flow R
1dfd 1dfd <halt> ; Flow R
1dfe 1dfe <halt> ; Flow R
1dff 1dff <halt> ; Flow R
1e00 ; --------------------------------------------------------------------------------------
1e00 ; 1E00 - 22DD SEQ_TEST
1e00 ; --------------------------------------------------------------------------------------
1e00 1e00 val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1e01 1e01 seq_b_timing 0 Early Condition; Flow J cc=True 0x1e04
seq_br_type 1 Branch True
seq_branch_adr 1e04 0x1e04
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e02 1e02 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e01
seq_br_type 0 Branch False
seq_branch_adr 1e01 0x1e01
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_random 06 Pop_stack+?
val_rand 2 DEC_LOOP_COUNTER
1e03 1e03 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e04 1e04 seq_br_type 2 Push (branch address); Flow J 0x1e05
seq_branch_adr 1e04 0x1e04
1e05 1e05 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e06 1e06 seq_random 06 Pop_stack+?
1e07 1e07 seq_b_timing 0 Early Condition; Flow J cc=True 0x1e09
seq_br_type 1 Branch True
seq_branch_adr 1e09 0x1e09
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e08 1e08 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e09 1e09 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
1e0a 1e0a seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
1e0b 1e0b seq_br_type 2 Push (branch address); Flow J 0x1e0c
seq_branch_adr 1e0a 0x1e0a
val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
1e0c 1e0c seq_br_type 8 Return True; Flow R cc=True
seq_branch_adr 1e0d 0x1e0d
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e0d 1e0d seq_b_timing 3 Late Condition, Hint False; Flow R cc=True
seq_br_type 8 Return True
seq_branch_adr 1e0e 0x1e0e
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e0e 1e0e seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e0f 1e0f seq_br_type 5 Call True; Flow C cc=True 0x1e0a
seq_branch_adr 1e0a 0x1e0a
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e10 1e10 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e11 1e11 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1e0a
seq_br_type 5 Call True
seq_branch_adr 1e0a 0x1e0a
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e12 1e12 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e13 1e13 seq_random 06 Pop_stack+?
1e14 1e14 seq_b_timing 0 Early Condition; Flow J cc=True 0x1e16
seq_br_type 1 Branch True
seq_branch_adr 1e16 0x1e16
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e15 1e15 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e16 1e16 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
1e17 1e17 seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
1e18 1e18 seq_br_type 2 Push (branch address); Flow J 0x1e19
seq_branch_adr 1e17 0x1e17
val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
1e19 1e19 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e1b
seq_br_type 1 Branch True
seq_branch_adr 1e1b 0x1e1b
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e1a 1e1a seq_random 06 Pop_stack+?
1e1b 1e1b seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e1c 1e1c seq_br_type 5 Call True; Flow C cc=True 0x1e1f
seq_branch_adr 1e1f 0x1e1f
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e1d 1e1d seq_b_timing 0 Early Condition; Flow J cc=False 0x1e20
seq_br_type 0 Branch False
seq_branch_adr 1e20 0x1e20
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e1e 1e1e seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e1f 1e1f seq_random 06 Pop_stack+?
1e20 1e20 seq_random 06 Pop_stack+?
1e21 1e21 seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e22 1e22 seq_br_type 2 Push (branch address); Flow J 0x1e23
seq_branch_adr 1e17 0x1e17
1e23 1e23 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e25
seq_br_type 1 Branch True
seq_branch_adr 1e25 0x1e25
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e24 1e24 seq_br_type a Unconditional Return; Flow R
1e25 1e25 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e26 1e26 seq_br_type 5 Call True; Flow C cc=True 0x1e29
seq_branch_adr 1e29 0x1e29
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e27 1e27 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e2a
seq_br_type 0 Branch False
seq_branch_adr 1e2a 0x1e2a
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e28 1e28 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e29 1e29 seq_br_type a Unconditional Return; Flow R
1e2a 1e2a seq_random 06 Pop_stack+?
1e2b 1e2b seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e2c 1e2c seq_br_type 2 Push (branch address); Flow J 0x1e2d
seq_branch_adr 1e17 0x1e17
1e2d 1e2d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e2f
seq_br_type 1 Branch True
seq_branch_adr 1e2f 0x1e2f
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e2e 1e2e fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 20 Clear_stack+Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
1e2f 1e2f seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e30 1e30 seq_br_type 5 Call True; Flow C cc=True 0x1e33
seq_branch_adr 1e33 0x1e33
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e31 1e31 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e34
seq_br_type 0 Branch False
seq_branch_adr 1e34 0x1e34
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e32 1e32 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e33 1e33 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 20 Clear_stack+Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
1e34 1e34 seq_random 06 Pop_stack+?
1e35 1e35 seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e36 1e36 seq_br_type 2 Push (branch address); Flow J 0x1e37
seq_branch_adr 1e17 0x1e17
1e37 1e37 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e39
seq_br_type 1 Branch True
seq_branch_adr 1e39 0x1e39
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e38 1e38 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e39 1e39 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e3a 1e3a seq_br_type 5 Call True; Flow C cc=True 0x1e3d
seq_branch_adr 1e3d 0x1e3d
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e3b 1e3b seq_b_timing 0 Early Condition; Flow J cc=False 0x1e3e
seq_br_type 0 Branch False
seq_branch_adr 1e3e 0x1e3e
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e3c 1e3c seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e3d 1e3d seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e3e 1e3e seq_random 06 Pop_stack+?
1e3f 1e3f seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e40 1e40 seq_br_type 2 Push (branch address); Flow J 0x1e41
seq_branch_adr 1e17 0x1e17
1e41 1e41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e43
seq_br_type 1 Branch True
seq_branch_adr 1e43 0x1e43
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e42 1e42 seq_br_type 2 Push (branch address); Flow J 0x1e43
seq_branch_adr 1e17 0x1e17
1e43 1e43 seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e44 1e44 seq_br_type 5 Call True; Flow C cc=True 0x1e47
seq_branch_adr 1e47 0x1e47
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e45 1e45 seq_b_timing 0 Early Condition; Flow J cc=False 0x1e48
seq_br_type 0 Branch False
seq_branch_adr 1e48 0x1e48
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e46 1e46 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e47 1e47 seq_br_type 2 Push (branch address); Flow J 0x1e48
seq_branch_adr 1e17 0x1e17
1e48 1e48 seq_random 06 Pop_stack+?
1e49 1e49 seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e4a 1e4a seq_br_type 2 Push (branch address); Flow J 0x1e4b
seq_branch_adr 1e17 0x1e17
1e4b 1e4b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e4d
seq_br_type 1 Branch True
seq_branch_adr 1e4d 0x1e4d
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e4c 1e4c ioc_fiubs 2 typ ; Flow C cc=#0x0 0x1e17
seq_b_timing 3 Late Condition, Hint False
seq_br_type f Unconditional Case Call
seq_branch_adr 1e17 0x1e17
typ_a_adr 14 ZEROS
1e4d 1e4d seq_b_timing 0 Early Condition; Flow C cc=True 0x22dc
seq_br_type 5 Call True
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e4e 1e4e seq_br_type 5 Call True; Flow C cc=True 0x1e51
seq_branch_adr 1e51 0x1e51
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_frame 10
1e4f 1e4f seq_b_timing 0 Early Condition; Flow J cc=False 0x1e53
seq_br_type 0 Branch False
seq_branch_adr 1e53 0x1e53
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e50 1e50 seq_br_type 7 Unconditional Call; Flow C 0x22dc
seq_branch_adr 22dc MICRO_STACK_ERROR
1e51 1e51 ioc_fiubs 2 typ ; Flow C cc=#0x0 0x1e17
seq_b_timing 3 Late Condition, Hint False
seq_br_type f Unconditional Case Call
seq_branch_adr 1e17 0x1e17
typ_a_adr 14 ZEROS
1e52 1e52 seq_br_type 3 Unconditional Branch; Flow J 0x318
seq_branch_adr 0318 0x0318
1e53 1e53 seq_random 06 Pop_stack+?
1e54 1e54 seq_b_timing 0 Early Condition; Flow C cc=False 0x22dc
seq_br_type 4 Call False
seq_branch_adr 22dc MICRO_STACK_ERROR
seq_cond_sel 47 SEQ.#_entries_in_stack_zero
1e55 1e55 seq_br_type 2 Push (branch address); Flow J 0x1e56
seq_branch_adr 1e17 0x1e17
1e56 1e56 ioc_adrbs 1 val
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 13 ONES
1e57 1e57 typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
1e58 1e58 typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
1e59 1e59 typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
1e5a 1e5a typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
1e5b 1e5b seq_cond_sel 17 VAL.FALSE(early)
seq_latch 1
1e5c 1e5c seq_cond_sel 26 TYP.TRUE (early)
seq_en_micro 0
1e5d 1e5d seq_b_timing 0 Early Condition; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 0f VAL.PREVIOUS(early)
seq_en_micro 0
1e5e 1e5e seq_b_timing 0 Early Condition; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
1e5f 1e5f seq_b_timing 1 Latch Condition; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_en_micro 0
1e60 1e60 seq_cond_sel 26 TYP.TRUE (early)
seq_latch 1
1e61 1e61 seq_cond_sel 25 TYP.FALSE (early)
seq_en_micro 0
1e62 1e62 seq_b_timing 0 Early Condition; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 27 TYP.PREVIOUS (early)
seq_en_micro 0
1e63 1e63 seq_b_timing 0 Early Condition; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 56 SEQ.LATCHED_COND
seq_en_micro 0
1e64 1e64 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e66
seq_br_type 1 Branch True
seq_branch_adr 1e66 0x1e66
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e65 1e65 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e66 1e66 seq_br_type 5 Call True; Flow C cc=True 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e67 1e67 seq_b_timing 0 Early Condition; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 56 SEQ.LATCHED_COND
seq_en_micro 0
1e68 1e68 typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
1e69 1e69 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1e6b
seq_br_type 0 Branch False
seq_branch_adr 1e6b 0x1e6b
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e6a 1e6a seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e6b 1e6b seq_br_type 5 Call True; Flow C cc=True 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
val_rand 1 INC_LOOP_COUNTER
1e6c 1e6c seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e6d 1e6d seq_br_type 1 Branch True; Flow J cc=True 0x1e6f
seq_branch_adr 1e6f 0x1e6f
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e6e 1e6e seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e6f 1e6f typ_rand e CHECK_CLASS_SYSTEM_B
1e70 1e70 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e71 1e71 seq_br_type 1 Branch True; Flow J cc=True 0x1e73
seq_branch_adr 1e73 0x1e73
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e72 1e72 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e73 1e73 val_rand 2 DEC_LOOP_COUNTER
1e74 1e74 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e75 1e75 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early))
1e76 1e76 seq_br_type 0 Branch False; Flow J cc=False 0x1e78
seq_branch_adr 1e78 0x1e78
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e77 1e77 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e78 1e78 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e79 1e79 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e7a 1e7a seq_br_type 1 Branch True; Flow J cc=True 0x1e7c
seq_branch_adr 1e7c 0x1e7c
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e7b 1e7b seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e7c 1e7c seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e7d 1e7d seq_br_type 1 Branch True; Flow J cc=True 0x1e7f
seq_branch_adr 1e7f 0x1e7f
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e7e 1e7e seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e7f 1e7f seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e80 1e80 seq_br_type 1 Branch True; Flow J cc=True 0x1e82
seq_branch_adr 1e82 0x1e82
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e81 1e81 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e82 1e82 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e84
seq_br_type 1 Branch True
seq_branch_adr 1e84 0x1e84
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e83 1e83 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e84 1e84 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e85 1e85 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e86 1e86 seq_br_type 1 Branch True; Flow J cc=True 0x1e88
seq_branch_adr 1e88 0x1e88
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e87 1e87 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e88 1e88 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e89 1e89 seq_br_type 1 Branch True; Flow J cc=True 0x1e8b
seq_branch_adr 1e8b 0x1e8b
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e8a 1e8a seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e8b 1e8b seq_br_type 5 Call True; Flow C cc=True 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e8c 1e8c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1e8e
seq_br_type 0 Branch False
seq_branch_adr 1e8e 0x1e8e
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e8d 1e8d seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e8e 1e8e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e90
seq_br_type 1 Branch True
seq_branch_adr 1e90 0x1e90
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e8f 1e8f seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e90 1e90 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e91 1e91 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e92 1e92 seq_br_type 1 Branch True; Flow J cc=True 0x1e94
seq_branch_adr 1e94 0x1e94
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e93 1e93 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e94 1e94 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e95 1e95 seq_br_type 1 Branch True; Flow J cc=True 0x1e97
seq_branch_adr 1e97 0x1e97
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e96 1e96 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e97 1e97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e98 1e98 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1e9a
seq_br_type 0 Branch False
seq_branch_adr 1e9a 0x1e9a
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e99 1e99 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e9a 1e9a seq_br_type 0 Branch False; Flow J cc=False 0x1e9c
seq_branch_adr 1e9c 0x1e9c
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e9b 1e9b seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1e9c 1e9c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1e9d 1e9d seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e9e 1e9e seq_br_type 1 Branch True; Flow J cc=True 0x1ea0
seq_branch_adr 1ea0 0x1ea0
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1e9f 1e9f seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ea0 1ea0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ea1 1ea1 seq_br_type 1 Branch True; Flow J cc=True 0x1ea3
seq_branch_adr 1ea3 0x1ea3
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ea2 1ea2 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ea3 1ea3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1ea4 1ea4 seq_br_type 1 Branch True; Flow J cc=True 0x1ea6
seq_branch_adr 1ea6 0x1ea6
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1ea5 1ea5 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ea6 1ea6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ea8
seq_br_type 1 Branch True
seq_branch_adr 1ea8 0x1ea8
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ea7 1ea7 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ea8 1ea8 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ea9 1ea9 seq_br_type 5 Call True; Flow C cc=True 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eaa 1eaa seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1eac
seq_br_type 0 Branch False
seq_branch_adr 1eac 0x1eac
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eab 1eab seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1eac 1eac seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ead 1ead seq_br_type 1 Branch True; Flow J cc=True 0x1eaf
seq_branch_adr 1eaf 0x1eaf
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eae 1eae seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1eaf 1eaf seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eb0 1eb0 seq_br_type 1 Branch True; Flow J cc=True 0x1eb2
seq_branch_adr 1eb2 0x1eb2
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eb1 1eb1 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1eb2 1eb2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1eb4
seq_br_type 1 Branch True
seq_branch_adr 1eb4 0x1eb4
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eb3 1eb3 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1eb4 1eb4 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eb5 1eb5 seq_br_type 5 Call True; Flow C cc=True 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eb6 1eb6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1eb8
seq_br_type 0 Branch False
seq_branch_adr 1eb8 0x1eb8
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1eb7 1eb7 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1eb8 1eb8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eb9 1eb9 seq_br_type 1 Branch True; Flow J cc=True 0x1ebb
seq_branch_adr 1ebb 0x1ebb
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eba 1eba seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ebb 1ebb seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1ebc 1ebc seq_br_type 1 Branch True; Flow J cc=True 0x1ebe
seq_branch_adr 1ebe 0x1ebe
seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo))
typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_frame 10
1ebd 1ebd seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ebe 1ebe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ebf 1ebf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1ec1
seq_br_type 0 Branch False
seq_branch_adr 1ec1 0x1ec1
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec0 1ec0 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ec1 1ec1 seq_br_type 1 Branch True; Flow J cc=True 0x1ec3
seq_branch_adr 1ec3 0x1ec3
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec2 1ec2 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ec3 1ec3 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec4 1ec4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec5 1ec5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ec7
seq_br_type 1 Branch True
seq_branch_adr 1ec7 0x1ec7
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec6 1ec6 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ec7 1ec7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ec9
seq_br_type 1 Branch True
seq_branch_adr 1ec9 0x1ec9
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1ec8 1ec8 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ec9 1ec9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1eca 1eca seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ecc
seq_br_type 1 Branch True
seq_branch_adr 1ecc 0x1ecc
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 25 VR13:05
val_alu_func 7 INC_A
val_frame 13
1ecb 1ecb seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ecc 1ecc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 2c VR15:0c
val_alu_func 7 INC_A
val_frame 15
1ecd 1ecd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ecf
seq_br_type 1 Branch True
seq_branch_adr 1ecf 0x1ecf
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 25 TR13:05
typ_alu_func 7 INC_A
typ_frame 13
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ece 1ece seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ecf 1ecf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 24 TR16:04
typ_alu_func 7 INC_A
typ_frame 16
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed0 1ed0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed1 1ed1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1ed3
seq_br_type 0 Branch False
seq_branch_adr 1ed3 0x1ed3
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed2 1ed2 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ed3 1ed3 seq_br_type 1 Branch True; Flow J cc=True 0x1ed5
seq_branch_adr 1ed5 0x1ed5
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed4 1ed4 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ed5 1ed5 seq_br_type 4 Call False; Flow C cc=False 0x226c
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed6 1ed6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed7 1ed7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ed9
seq_br_type 1 Branch True
seq_branch_adr 1ed9 0x1ed9
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ed8 1ed8 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ed9 1ed9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1edb
seq_br_type 1 Branch True
seq_branch_adr 1edb 0x1edb
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 6 A_MINUS_B
val_b_adr 20 VR10:00
val_frame 10
1eda 1eda seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1edb 1edb seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x226c
seq_br_type 4 Call False
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 6 A_MINUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1edc 1edc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ede
seq_br_type 1 Branch True
seq_branch_adr 1ede 0x1ede
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 25 VR13:05
val_alu_func 7 INC_A
val_frame 13
1edd 1edd seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ede 1ede seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 20 TR10:00
typ_alu_func 1 A_PLUS_B
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 2c VR15:0c
val_alu_func 7 INC_A
val_frame 15
1edf 1edf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1ee1
seq_br_type 1 Branch True
seq_branch_adr 1ee1 0x1ee1
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 25 TR13:05
typ_alu_func 7 INC_A
typ_frame 13
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ee0 1ee0 seq_br_type 7 Unconditional Call; Flow C 0x226c
seq_branch_adr 226c COND_ERROR
1ee1 1ee1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226c
seq_br_type 5 Call True
seq_branch_adr 226c COND_ERROR
seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late))
typ_a_adr 24 TR16:04
typ_alu_func 7 INC_A
typ_frame 16
val_a_adr 20 VR10:00
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR10:00
val_frame 10
1ee2 1ee2 seq_br_type 3 Unconditional Branch; Flow J 0x318
seq_branch_adr 0318 0x0318
1ee3 ; --------------------------------------------------------------------------------------
1ee3 ; Comes from:
1ee3 ; 0318 C from color DIAGNOSTIC_START
1ee3 ; --------------------------------------------------------------------------------------
1ee3 1ee3 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1ee4 1ee4 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 21 VR15:01
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1ee5 1ee5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2270
seq_br_type 5 Call True
seq_branch_adr 2270 BAD_LEX_VAL
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR15:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1ee6 1ee6 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1ee7 1ee7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2272
seq_br_type 5 Call True
seq_branch_adr 2272 BAD_MACRO_PC_REF
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR15:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1ee8 1ee8 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 23 VR15:03
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1ee9 1ee9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2274
seq_br_type 5 Call True
seq_branch_adr 2274 BAD_MACRO_PC_SEG
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR15:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1eea 1eea seq_random 55 ?
1eeb 1eeb ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_a_adr 21 VR15:01
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1eec 1eec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2270
seq_br_type 5 Call True
seq_branch_adr 2270 BAD_LEX_VAL
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR15:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1eed 1eed ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1eee 1eee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227e
seq_br_type 5 Call True
seq_branch_adr 227e BAD_RETURN_PC_REF
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR15:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1eef 1eef ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_a_adr 23 VR15:03
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1ef0 1ef0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2280
seq_br_type 5 Call True
seq_branch_adr 2280 BAD_RETURN_PC_SEG
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 23 VR15:03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1ef1 1ef1 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1ef2 1ef2 val_a_adr 29 VR15:09
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1ef3 1ef3 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1ef4 1ef4 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 55 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1ef5 1ef5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1ef6 1ef6 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1ef7 1ef7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1ef8 1ef8 seq_b_timing 0 Early Condition; Flow J cc=False 0x1ef3
seq_br_type 0 Branch False
seq_branch_adr 1ef3 0x1ef3
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 3 LEFT_I_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1ef9 1ef9 val_a_adr 20 VR05:00
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1efa 1efa val_a_adr 2a VR15:0a
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1efb 1efb seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1efc 1efc ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 55 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1efd 1efd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1efe 1efe ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1eff 1eff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f00 1f00 seq_b_timing 0 Early Condition; Flow J cc=False 0x1efb
seq_br_type 0 Branch False
seq_branch_adr 1efb 0x1efb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 3 LEFT_I_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f01 1f01 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f02 1f02 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2276
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2276 BAD_CODE_MUX
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_int_reads 4 SAVE OFFSET
seq_random 55 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
1f03 1f03 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2282
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2282 BAD_RETURN_PC_LOAD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
1f04 1f04 val_a_adr 20 VR04:00
val_alu_func 10 NOT_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f05 1f05 val_a_adr 29 VR15:09
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f06 1f06 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f07 1f07 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 55 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1f08 1f08 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1d A_AND_NOT_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f09 1f09 val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR15:0b
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f0a 1f0a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f0b 1f0b ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1f0c 1f0c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1d A_AND_NOT_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f0d 1f0d val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR15:0b
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f0e 1f0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f0f 1f0f seq_b_timing 0 Early Condition; Flow J cc=False 0x1f06
seq_br_type 0 Branch False
seq_branch_adr 1f06 0x1f06
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 4 LEFT_I_A_INC
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f10 1f10 val_a_adr 20 VR05:00
val_alu_func 10 NOT_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 5
1f11 1f11 val_a_adr 2a VR15:0a
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f12 1f12 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f13 1f13 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 55 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1f14 1f14 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1d A_AND_NOT_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f15 1f15 val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR15:0b
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f16 1f16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226e
seq_br_type 5 Call True
seq_branch_adr 226e BAD_MACRO_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f17 1f17 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 5b ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1f18 1f18 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1d A_AND_NOT_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f19 1f19 val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2b VR15:0b
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f1a 1f1a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227c
seq_br_type 5 Call True
seq_branch_adr 227c BAD_RETURN_PC
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f1b 1f1b seq_b_timing 0 Early Condition; Flow J cc=False 0x1f12
seq_br_type 0 Branch False
seq_branch_adr 1f12 0x1f12
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 4 LEFT_I_A_INC
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f1c 1f1c seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f1d 1f1d typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f1e 1f1e ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
1f1f 1f1f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2276
seq_br_type 5 Call True
seq_branch_adr 2276 BAD_CODE_MUX
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 0 PASS_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f20 1f20 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f21 1f21 seq_random 16 ?
1f22 1f22 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f23 1f23 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2278
seq_br_type 5 Call True
seq_branch_adr 2278 BAD_MACRO_PC_IND
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1f24 1f24 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f25 1f25 ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f26 1f26 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1f27 1f27 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f28 1f28 ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f29 1f29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1f2a 1f2a seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f2b 1f2b ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f2c 1f2c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1f2d 1f2d seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f2e 1f2e ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f2f 1f2f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1f30 1f30 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f31 1f31 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_b_adr 20 VR15:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f32 1f32 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f33 1f33 ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f34 1f34 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f35 1f35 seq_b_timing 0 Early Condition; Flow J cc=False 0x1f32
seq_br_type 0 Branch False
seq_branch_adr 1f32 0x1f32
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 3 LEFT_I_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f36 1f36 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f37 1f37 val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f38 1f38 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f39 1f39 ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f3a 1f3a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f3b 1f3b seq_b_timing 0 Early Condition; Flow J cc=False 0x1f38
seq_br_type 0 Branch False
seq_branch_adr 1f38 0x1f38
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 3 LEFT_I_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f3c 1f3c val_a_adr 20 VR04:00
val_alu_func 10 NOT_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f3d 1f3d val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f3e 1f3e seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 0d GP0d
1f3f 1f3f ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f40 1f40 val_a_adr 01 GP01
val_alu_func 17 A_OR_NOT_B
val_b_adr 2c VR10:0c
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f41 1f41 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f42 1f42 seq_b_timing 0 Early Condition; Flow J cc=False 0x1f3e
seq_br_type 0 Branch False
seq_branch_adr 1f3e 0x1f3e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 4 LEFT_I_A_INC
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f43 1f43 val_a_adr 20 VR04:00
val_alu_func 10 NOT_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f44 1f44 val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f45 1f45 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 0d GP0d
1f46 1f46 ioc_tvbs 5 seq+seq
seq_int_reads 1 CURRENT MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f47 1f47 val_a_adr 01 GP01
val_alu_func 17 A_OR_NOT_B
val_b_adr 2c VR10:0c
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
1f48 1f48 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x229e
seq_br_type 5 Call True
seq_branch_adr 229e BAD_CURRENT_INSTR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f49 1f49 seq_b_timing 0 Early Condition; Flow J cc=False 0x1f45
seq_br_type 0 Branch False
seq_branch_adr 1f45 0x1f45
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 4 LEFT_I_A_INC
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f4a 1f4a seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f4b 1f4b seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f4c 1f4c seq_random 36 Load_ibuff+?
1f4d 1f4d ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f4e 1f4e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227a
seq_br_type 5 Call True
seq_branch_adr 227a BAD_MACRO_PC_ADD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
1f4f 1f4f seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f50 1f50 seq_random 36 Load_ibuff+?
1f51 1f51 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f52 1f52 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227a
seq_br_type 5 Call True
seq_branch_adr 227a BAD_MACRO_PC_ADD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 22 VR15:02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1f53 1f53 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 4
1f54 1f54 val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 4
1f55 1f55 val_a_adr 2d VR15:0d
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
1f56 1f56 seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f57 1f57 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f58 1f58 seq_random 36 Load_ibuff+?
1f59 1f59 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f5a 1f5a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227a
seq_br_type 5 Call True
seq_branch_adr 227a BAD_MACRO_PC_ADD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 04 GP04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
1f5b 1f5b val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
1f5c 1f5c seq_b_timing 0 Early Condition; Flow J cc=False 0x1f56
seq_br_type 0 Branch False
seq_branch_adr 1f56 0x1f56
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 0d GP0d
val_alu_func 3 LEFT_I_A
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
1f5d 1f5d seq_int_reads 0 TYP VAL BUS
seq_random 52 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f5e 1f5e seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0d GP0d
1f5f 1f5f seq_random 36 Load_ibuff+?
1f60 1f60 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 22 VR15:02
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
1f61 1f61 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x227a
seq_br_type 5 Call True
seq_branch_adr 227a BAD_MACRO_PC_ADD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2e VR15:0e
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
1f62 1f62 seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f63 1f63 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2284
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f64 1f64 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2286
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f65 1f65 seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f66 1f66 ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f67 1f67 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2284
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1f68 1f68 ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f69 1f69 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2286
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1f6a 1f6a seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f6b 1f6b ioc_tvbs 5 seq+seq; Flow C cc=True 0x2284
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f6c 1f6c ioc_tvbs 5 seq+seq; Flow C cc=True 0x2286
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f6d 1f6d typ_a_adr 27 TR04:07
typ_alu_func 0 PASS_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 4
1f6e 1f6e typ_a_adr 39 TR16:19
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
1f6f 1f6f seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 0d GP0d
val_b_adr 20 VR10:00
val_frame 10
1f70 1f70 ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f71 1f71 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2284
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f72 1f72 ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f73 1f73 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2286
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f74 1f74 seq_b_timing 0 Early Condition; Flow J cc=False 0x1f6f
seq_br_type 0 Branch False
seq_branch_adr 1f6f 0x1f6f
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 0d GP0d
typ_alu_func 3 LEFT_I_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1f75 1f75 typ_a_adr 27 TR04:07
typ_alu_func 10 NOT_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 4
1f76 1f76 typ_a_adr 39 TR16:19
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
1f77 1f77 seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 0d GP0d
val_b_adr 20 VR10:00
val_frame 10
1f78 1f78 ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f79 1f79 typ_a_adr 01 GP01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 27 TR14:07
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f7a 1f7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2284
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f7b 1f7b ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f7c 1f7c typ_a_adr 01 GP01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 27 TR14:07
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f7d 1f7d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2286
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f7e 1f7e seq_b_timing 0 Early Condition; Flow J cc=False 0x1f77
seq_br_type 0 Branch False
seq_branch_adr 1f77 0x1f77
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 0d GP0d
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1f7f 1f7f seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f80 1f80 seq_int_reads 6 CONTROL TOP
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1f81 1f81 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2288
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2288 BAD_SEQUENCER_BUS
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f82 1f82 ioc_fiubs 1 val
seq_random 58 Load_control_pred+Load_control_pred+?
val_a_adr 20 VR10:00
val_frame 10
1f83 1f83 ioc_tvbs 5 seq+seq; Flow C cc=True 0x228a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 228a BAD2_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_frame 14
1f84 1f84 ioc_tvbs 5 seq+seq; Flow C cc=True 0x228c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 228c BAD2_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_frame 14
1f85 1f85 ioc_fiubs 1 val
seq_random 58 Load_control_pred+Load_control_pred+?
val_a_adr 22 VR10:02
val_frame 10
1f86 1f86 ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f87 1f87 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x228a
seq_br_type 5 Call True
seq_branch_adr 228a BAD2_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1f88 1f88 ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f89 1f89 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x228c
seq_br_type 5 Call True
seq_branch_adr 228c BAD2_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1f8a 1f8a typ_a_adr 27 TR04:07
typ_alu_func 0 PASS_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 4
1f8b 1f8b typ_a_adr 39 TR16:19
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
1f8c 1f8c ioc_fiubs 2 typ
seq_random 58 Load_control_pred+Load_control_pred+?
typ_a_adr 0d GP0d
1f8d 1f8d ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f8e 1f8e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2284
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f8f 1f8f ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f90 1f90 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2286
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f91 1f91 seq_b_timing 0 Early Condition; Flow J cc=False 0x1f8c
seq_br_type 0 Branch False
seq_branch_adr 1f8c 0x1f8c
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 0d GP0d
typ_alu_func 3 LEFT_I_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1f92 1f92 typ_a_adr 27 TR04:07
typ_alu_func 10 NOT_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 4
1f93 1f93 typ_a_adr 39 TR16:19
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
1f94 1f94 ioc_fiubs 2 typ
seq_random 58 Load_control_pred+Load_control_pred+?
typ_a_adr 0d GP0d
1f95 1f95 ioc_tvbs 5 seq+seq
seq_int_reads 7 CONTROL PRED
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f96 1f96 typ_a_adr 01 GP01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 27 TR14:07
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f97 1f97 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2284
seq_br_type 5 Call True
seq_branch_adr 2284 BAD_CONTROL_PRED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f98 1f98 ioc_tvbs 5 seq+seq
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f99 1f99 typ_a_adr 01 GP01
typ_alu_func 17 A_OR_NOT_B
typ_b_adr 27 TR14:07
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f9a 1f9a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2286
seq_br_type 5 Call True
seq_branch_adr 2286 BAD_CONTROL_TOP
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0d GP0d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1f9b 1f9b seq_b_timing 0 Early Condition; Flow J cc=False 0x1f94
seq_br_type 0 Branch False
seq_branch_adr 1f94 0x1f94
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 0d GP0d
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
1f9c 1f9c seq_int_reads 0 TYP VAL BUS
seq_random 56 Load_control_pred+Load_control_pred+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1f9d 1f9d typ_csa_cntl 2 PUSH_CSA
1f9e 1f9e ioc_tvbs 5 seq+seq; Flow C cc=True 0x228e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 228e BAD_CONTROL_TOP_INC
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1f9f 1f9f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x228e
seq_br_type 5 Call True
seq_branch_adr 228e BAD_CONTROL_TOP_INC
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_a_adr 27 TR04:07
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_frame 4
val_b_adr 20 VR10:00
val_frame 10
1fa0 1fa0 typ_csa_cntl 3 POP_CSA
1fa1 1fa1 ioc_tvbs 5 seq+seq; Flow C cc=True 0x2290
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2290 BAD_CONTROL_TOP_DEC
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fa2 1fa2 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22b0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22b0 BAD_NUMBER_VALID
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 2a TR14:0a
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fa3 1fa3 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22b2
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22b2 BAD_NUMBER_VALID2
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 2a TR14:0a
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_csa_cntl 2 PUSH_CSA
typ_frame 14
1fa4 1fa4 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22b4
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22b4 BAD_NUMBER_VALID3
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 2a TR14:0a
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_frame 14
1fa5 1fa5 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22b6
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22b6 BAD_NUMBER_VALID4
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_int_reads 6 CONTROL TOP
typ_a_adr 2a TR14:0a
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_csa_cntl 3 POP_CSA
typ_frame 14
1fa6 1fa6 val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fa7 1fa7 seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fa8 1fa8 seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1fa9 1fa9 ioc_tvbs 5 seq+seq; Flow C cc=True 0x229a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 229a VALIDATE_BAD2
seq_cond_sel 43 SEQ.loop_counter_zero
seq_int_reads 5 RESOLVE RAM
1faa 1faa ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fab 1fab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2292
seq_br_type 5 Call True
seq_branch_adr 2292 BAD_RESOLVE
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 0 PASS_A
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fac 1fac seq_br_type 1 Branch True; Flow J cc=True 0x1fa7
seq_branch_adr 1fa7 0x1fa7
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fad 1fad seq_random 0a ?
1fae 1fae val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1faf 1faf seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fb0 1fb0 seq_br_type 4 Call False; Flow C cc=False 0x229c
seq_branch_adr 229c BAD_INVALIDATE
seq_cond_sel 43 SEQ.loop_counter_zero
1fb1 1fb1 seq_br_type 1 Branch True; Flow J cc=True 0x1faf
seq_branch_adr 1faf 0x1faf
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fb2 1fb2 val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fb3 1fb3 seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fb4 1fb4 seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
1fb5 1fb5 ioc_tvbs 5 seq+seq; Flow C cc=True 0x229a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 229a VALIDATE_BAD2
seq_cond_sel 43 SEQ.loop_counter_zero
seq_int_reads 5 RESOLVE RAM
1fb6 1fb6 ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fb7 1fb7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2296
seq_br_type 5 Call True
seq_branch_adr 2296 BAD_RESOLVE2
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 29 TR14:09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 14
1fb8 1fb8 seq_br_type 1 Branch True; Flow J cc=True 0x1fb3
seq_branch_adr 1fb3 0x1fb3
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fb9 1fb9 val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fba 1fba typ_a_adr 20 TR10:00
typ_alu_func 7 INC_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 10
1fbb 1fbb seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fbc 1fbc seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 0d GP0d
val_b_adr 20 VR10:00
val_frame 10
1fbd 1fbd ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fbe 1fbe typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 0d GP0d
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fbf 1fbf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2296
seq_br_type 5 Call True
seq_branch_adr 2296 BAD_RESOLVE2
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fc0 1fc0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1fbb
seq_br_type 0 Branch False
seq_branch_adr 1fbb 0x1fbb
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 0d GP0d
typ_alu_func 3 LEFT_I_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
1fc1 1fc1 seq_br_type 1 Branch True; Flow J cc=True 0x1fba
seq_branch_adr 1fba 0x1fba
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fc2 1fc2 val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fc3 1fc3 typ_a_adr 20 TR04:00
typ_alu_func 10 NOT_A
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_frame 4
1fc4 1fc4 seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fc5 1fc5 seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 0d GP0d
val_b_adr 22 VR10:02
val_frame 10
1fc6 1fc6 ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fc7 1fc7 typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 0d GP0d
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fc8 1fc8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2296
seq_br_type 5 Call True
seq_branch_adr 2296 BAD_RESOLVE2
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fc9 1fc9 seq_br_type 1 Branch True; Flow J cc=True 0x1fc4
seq_branch_adr 1fc4 0x1fc4
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 0d GP0d
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
1fca 1fca seq_br_type 1 Branch True; Flow J cc=True 0x1fc3
seq_branch_adr 1fc3 0x1fc3
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fcb 1fcb typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fcc 1fcc seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fcd 1fcd seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_b_adr 03 GP03
val_b_adr 22 VR10:02
val_frame 10
1fce 1fce ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fcf 1fcf typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 03 GP03
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fd0 1fd0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2296
seq_br_type 5 Call True
seq_branch_adr 2296 BAD_RESOLVE2
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fd1 1fd1 seq_br_type 1 Branch True; Flow J cc=True 0x1fcc
seq_branch_adr 1fcc 0x1fcc
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2c TR17:0c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fd2 1fd2 typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
1fd3 1fd3 ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
seq_lex_adr 2
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fd4 1fd4 typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 03 GP03
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fd5 1fd5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2298
seq_br_type 5 Call True
seq_branch_adr 2298 BAD_RESOLVE_ADDRESS
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fd6 1fd6 typ_a_adr 2c TR17:0c
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
1fd7 1fd7 ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
seq_lex_adr 3
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fd8 1fd8 typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 03 GP03
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fd9 1fd9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2298
seq_br_type 5 Call True
seq_branch_adr 2298 BAD_RESOLVE_ADDRESS
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fda 1fda typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fdb 1fdb seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fdc 1fdc ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fdd 1fdd typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 03 GP03
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fde 1fde seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2298
seq_br_type 5 Call True
seq_branch_adr 2298 BAD_RESOLVE_ADDRESS
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fdf 1fdf seq_br_type 1 Branch True; Flow J cc=True 0x1fdb
seq_branch_adr 1fdb 0x1fdb
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2c TR17:0c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fe0 1fe0 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 20 VR04:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 4
1fe1 1fe1 seq_int_reads 0 TYP VAL BUS
seq_lex_adr 1
seq_random 3e ?
typ_b_adr 03 GP03
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fe2 1fe2 seq_br_type 1 Branch True; Flow J cc=True 0x1fe1
seq_branch_adr 1fe1 0x1fe1
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2c TR17:0c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 24 VR04:04
val_frame 4
1fe3 1fe3 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
1fe4 1fe4 seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_b_adr 09 GP09
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
1fe5 1fe5 ioc_tvbs 5 seq+seq
seq_int_reads 5 RESOLVE RAM
typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fe6 1fe6 typ_a_adr 29 TR14:09
typ_alu_func 1e A_AND_B
typ_b_adr 03 GP03
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1fe7 1fe7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2298
seq_br_type 5 Call True
seq_branch_adr 2298 BAD_RESOLVE_ADDRESS
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1fe8 1fe8 seq_br_type 1 Branch True; Flow J cc=True 0x1fe4
seq_branch_adr 1fe4 0x1fe4
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2c TR17:0c
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 09 GP09
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
1fe9 1fe9 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1fea 1fea typ_a_adr 20 TR05:00
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1feb 1feb seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 3e ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1fec 1fec seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 3e ?
typ_b_adr 03 GP03
val_b_adr 20 VR10:00
val_frame 10
1fed 1fed seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 5c Load_current_name+Load_save_offset+?
typ_b_adr 04 GP04
val_b_adr 20 VR10:00
val_frame 10
1fee 1fee ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1fef 1fef typ_a_adr 03 GP03
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1ff0 1ff0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a8
seq_br_type 5 Call True
seq_branch_adr 22a8 BAD_SAVE_OFFSET
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ff1 1ff1 ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
typ_a_adr 24 TR10:04
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1ff2 1ff2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22aa
seq_br_type 5 Call True
seq_branch_adr 22aa BAD_CURRENT_NAME
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 04 GP04
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ff3 1ff3 typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
1ff4 1ff4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1feb
seq_br_type 0 Branch False
seq_branch_adr 1feb 0x1feb
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 04 GP04
typ_alu_func 3 LEFT_I_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
1ff5 1ff5 typ_a_adr 20 TR04:00
typ_alu_func 10 NOT_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
1ff6 1ff6 typ_a_adr 20 TR05:00
typ_alu_func 10 NOT_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
1ff7 1ff7 seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 3e ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
1ff8 1ff8 seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 3e ?
typ_b_adr 03 GP03
val_b_adr 20 VR10:00
val_frame 10
1ff9 1ff9 seq_int_reads 0 TYP VAL BUS
seq_lex_adr 2
seq_random 5c Load_current_name+Load_save_offset+?
typ_b_adr 04 GP04
val_b_adr 20 VR10:00
val_frame 10
1ffa 1ffa ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
typ_a_adr 27 TR14:07
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
1ffb 1ffb typ_a_adr 03 GP03
typ_alu_func 1e A_AND_B
typ_b_adr 27 TR14:07
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 14
1ffc 1ffc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a8
seq_br_type 5 Call True
seq_branch_adr 22a8 BAD_SAVE_OFFSET
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
1ffd 1ffd ioc_tvbs 5 seq+seq
seq_int_reads 4 SAVE OFFSET
typ_a_adr 24 TR10:04
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 10
1ffe 1ffe typ_a_adr 04 GP04
typ_alu_func 1e A_AND_B
typ_b_adr 24 TR10:04
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
typ_frame 10
1fff 1fff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22aa
seq_br_type 5 Call True
seq_branch_adr 22aa BAD_CURRENT_NAME
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 0b GP0b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2000 2000 typ_a_adr 03 GP03
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2001 2001 seq_br_type 1 Branch True; Flow J cc=True 0x1ff7
seq_branch_adr 1ff7 0x1ff7
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 04 GP04
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
2002 2002 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2003 2003 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 4
2004 2004 val_a_adr 3f VR15:1f
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
2005 2005 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
val_b_adr 03 GP03
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
2006 2006 seq_int_reads 0 TYP VAL BUS
seq_random 59 ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2007 2007 ioc_tvbs 5 seq+seq
seq_int_reads 2 DECODING MACRO INSTRUCTION
seq_random 5d ?
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
2008 2008 seq_br_type 1 Branch True; Flow J cc=True 0x200b
seq_branch_adr 200b 0x200b
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 0a GP0a
2009 2009 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a2
seq_br_type 5 Call True
seq_branch_adr 22a2 BAD_IBUFFER
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 04 GP04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
200a 200a seq_br_type 3 Unconditional Branch; Flow J 0x200c
seq_branch_adr 200c 0x200c
200b 200b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a2
seq_br_type 5 Call True
seq_branch_adr 22a2 BAD_IBUFFER
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 0 PASS_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
200c 200c seq_b_timing 0 Early Condition; Flow J cc=False 0x2007
seq_br_type 0 Branch False
seq_branch_adr 2007 0x2007
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 1 INC_LOOP_COUNTER
200d 200d val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
200e 200e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2012
seq_br_type 1 Branch True
seq_branch_adr 2012 0x2012
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
200f 200f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2005
seq_br_type 0 Branch False
seq_branch_adr 2005 0x2005
seq_cond_sel 08 VAL.ALU_CARRY(late)
val_a_adr 04 GP04
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 2f VR04:0f
val_frame 4
2010 2010 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 4
2011 2011 seq_br_type 3 Unconditional Branch; Flow J 0x2005
seq_branch_adr 2005 0x2005
val_a_adr 0a GP0a
val_alu_func 1c DEC_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
2012 2012 typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 20 VR04:00
val_alu_func 10 NOT_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2013 2013 val_a_adr 2c VR10:0c
val_alu_func 1c DEC_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2014 2014 val_a_adr 3f VR15:1f
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
2015 2015 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
val_b_adr 03 GP03
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
2016 2016 seq_int_reads 0 TYP VAL BUS
seq_random 59 ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2017 2017 ioc_tvbs 5 seq+seq
seq_int_reads 2 DECODING MACRO INSTRUCTION
seq_random 5d ?
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 10
2018 2018 seq_br_type 1 Branch True; Flow J cc=True 0x201b
seq_branch_adr 201b 0x201b
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 0a GP0a
2019 2019 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a2
seq_br_type 5 Call True
seq_branch_adr 22a2 BAD_IBUFFER
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 04 GP04
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
201a 201a seq_br_type 3 Unconditional Branch; Flow J 0x201c
seq_branch_adr 201c 0x201c
201b 201b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22a2
seq_br_type 5 Call True
seq_branch_adr 22a2 BAD_IBUFFER
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
201c 201c seq_b_timing 0 Early Condition; Flow J cc=False 0x2017
seq_br_type 0 Branch False
seq_branch_adr 2017 0x2017
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 1 INC_LOOP_COUNTER
201d 201d val_a_adr 03 GP03
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
201e 201e seq_br_type 0 Branch False; Flow J cc=False 0x2023
seq_branch_adr 2023 0x2023
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
201f 201f val_a_adr 04 GP04
val_alu_func 1e A_AND_B
val_b_adr 2c VR10:0c
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2020 2020 seq_br_type 1 Branch True; Flow J cc=True 0x2015
seq_branch_adr 2015 0x2015
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 2c VR10:0c
val_frame 10
2021 2021 val_a_adr 2c VR10:0c
val_alu_func 1c DEC_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2022 2022 seq_br_type 3 Unconditional Branch; Flow J 0x2015
seq_branch_adr 2015 0x2015
val_a_adr 0a GP0a
val_alu_func 1c DEC_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
2023 2023 seq_br_type 3 Unconditional Branch; Flow J 0x2024
seq_branch_adr 2024 0x2024
2024 2024 typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
2025 2025 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_b_adr 22 VR10:02
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2026 2026 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 03 GP03
val_b_adr 03 GP03
2027 2027 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 03 GP03
val_b_adr 03 GP03
2028 2028 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2029 2029 seq_br_type 5 Call True; Flow C cc=True 0x22b8
seq_branch_adr 22b8 BAD_DISPATCH_ZERO
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_alu_func 1a PASS_B
typ_b_adr 03 GP03
val_a_adr 03 GP03
val_alu_func 10 NOT_A
202a 202a ioc_tvbs 5 seq+seq; Flow J cc=True 0x2028
seq_br_type 1 Branch True
seq_branch_adr 2028 0x2028
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 24 VR15:04
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 15
202b 202b seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 2d TR14:0d
typ_frame 14
val_b_adr 27 VR15:07
val_frame 15
202c 202c fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
202d 202d seq_br_type 5 Call True; Flow C cc=True 0x22ba
seq_branch_adr 22ba BAD_DISPATCH_ONE
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
val_alu_func 1a PASS_B
val_b_adr 03 GP03
202e 202e ioc_tvbs 5 seq+seq; Flow J cc=True 0x202c
seq_br_type 1 Branch True
seq_branch_adr 202c 0x202c
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_int_reads 4 SAVE OFFSET
seq_random 15 ?
val_a_adr 24 VR15:04
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 15
202f 202f seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 22 TR10:02
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
2030 2030 seq_cond_sel 17 VAL.FALSE(early)
seq_latch 1
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2031 2031 seq_int_reads 0 TYP VAL BUS
seq_random 63 Load_ibuff+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2032 2032 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22c4
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22c4 BAD_CONDITIONA_LOAD_IBUFF
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_int_reads 2 DECODING MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 10
2033 2033 seq_cond_sel 16 VAL.TRUE(early)
seq_latch 1
2034 2034 seq_int_reads 0 TYP VAL BUS
seq_random 63 Load_ibuff+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2035 2035 ioc_tvbs 5 seq+seq; Flow C cc=True 0x22c6
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22c6 BAD_CONDITIONA_LOAD_IBUFF2
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_int_reads 2 DECODING MACRO INSTRUCTION
val_a_adr 2c VR10:0c
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 10
2036 2036 seq_br_type 3 Unconditional Branch; Flow J 0x2052
seq_branch_adr 2052 0x2052
2037 2037 <halt> ; Flow R
2038 ; --------------------------------------------------------------------------------------
2038 ; 0x0fc0-0x0fff Execute_Immediate Equal,uimmediate
2038 ; --------------------------------------------------------------------------------------
2038 MACRO_Execute_Immediate_Equal,uimmediate:
2038 2038 dispatch_brk_class 0 ; Flow J 0x202d
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_uadr 2038
seq_br_type 3 Unconditional Branch
seq_branch_adr 202d 0x202d
typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2039 2039 <halt> ; Flow R
203a ; --------------------------------------------------------------------------------------
203a ; 0x0000 Action Illegal,>R
203a ; 0x0001 Illegal -
203a ; --------------------------------------------------------------------------------------
203a MACRO_Action_Illegal,>R:
203a MACRO_Illegal_-:
203a 203a dispatch_brk_class 0 ; Flow J 0x2029
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 203a
seq_br_type 3 Unconditional Branch
seq_branch_adr 2029 0x2029
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
203b 203b typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
203c 203c typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 3e VR15:1e
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
203d 203d seq_br_type 7 Unconditional Call; Flow C 0x2048
seq_branch_adr 2048 0x2048
val_c_adr 30 GP0f
val_c_mux_sel 2 ALU
203e 203e seq_b_timing 0 Early Condition; Flow C cc=False 0x22be
seq_br_type 4 Call False
seq_branch_adr 22be IBUFF_FILL_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
203f 203f typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
2040 2040 typ_a_adr 33 TR14:13
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
val_a_adr 22 VR04:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2041 2041 seq_br_type 7 Unconditional Call; Flow C 0x2048
seq_branch_adr 2048 0x2048
val_a_adr 3f VR16:1f
val_alu_func 0 PASS_A
val_c_adr 30 GP0f
val_c_mux_sel 2 ALU
val_frame 16
2042 2042 seq_b_timing 0 Early Condition; Flow C cc=False 0x22be
seq_br_type 4 Call False
seq_branch_adr 22be IBUFF_FILL_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
2043 2043 typ_alu_func 13 ONES
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
2044 2044 typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
2045 2045 seq_br_type 7 Unconditional Call; Flow C 0x2048
seq_branch_adr 2048 0x2048
val_a_adr 31 VR10:11
val_alu_func 0 PASS_A
val_c_adr 30 GP0f
val_c_mux_sel 2 ALU
val_frame 10
2046 2046 seq_b_timing 0 Early Condition; Flow C cc=False 0x22be
seq_br_type 4 Call False
seq_branch_adr 22be IBUFF_FILL_ERROR
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
2047 2047 seq_br_type 3 Unconditional Branch; Flow J 0x2052
seq_branch_adr 2052 0x2052
2048 ; --------------------------------------------------------------------------------------
2048 ; Comes from:
2048 ; 203d C from color 0x1ee3
2048 ; 2041 C from color 0x1ee3
2048 ; 2045 C from color 0x1ee3
2048 ; --------------------------------------------------------------------------------------
2048 2048 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0f GP0f
2049 2049 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 3e TR16:1e
typ_frame 16
val_b_adr 32 VR10:12
val_frame 10
204a 204a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
204b 204b <halt> ; Flow R
204c ; --------------------------------------------------------------------------------------
204c ; 0x0350 Declare_Type Array,Defined,Bounds_With_Object
204c ; --------------------------------------------------------------------------------------
204c MACRO_Declare_Type_Array,Defined,Bounds_With_Object:
204c 204c dispatch_brk_class 0 ; Flow R
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 204c
fiu_mem_start 2 start-rd
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
204d 204d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
204e ; --------------------------------------------------------------------------------------
204e ; 0x0351 Declare_Type Array,Defined,Visible,Bounds_With_Object
204e ; --------------------------------------------------------------------------------------
204e MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object:
204e 204e dispatch_brk_class 0 ; Flow C cc=False 0x22c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 204e
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 22c0 DISPATCH_INDEX_ERROR
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_alu_func 13 ONES
typ_c_adr 32 GP0d
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
204f 204f fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2050 ; --------------------------------------------------------------------------------------
2050 ; 0x0352 Illegal -
2050 ; --------------------------------------------------------------------------------------
2050 MACRO_Illegal_-:
2050 2050 dispatch_brk_class 0 ; Flow C cc=True 0x22be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2050
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22be IBUFF_FILL_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 0d GP0d
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2051 2051 seq_br_type a Unconditional Return; Flow R
2052 2052 typ_alu_func 1a PASS_B
typ_b_adr 2b TR14:0b
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2053 2053 seq_int_reads 0 TYP VAL BUS
seq_random 12 Load_current_lex+?
typ_b_adr 03 GP03
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2054 2054 seq_int_reads 0 TYP VAL BUS
seq_random 3e ?
typ_a_adr 2e TR14:0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
val_b_adr 20 VR10:00
val_frame 10
2055 2055 seq_br_type 1 Branch True; Flow J cc=True 0x2053
seq_branch_adr 2053 0x2053
seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late)
val_a_adr 03 GP03
val_alu_func 5 DEC_A_MINUS_B
val_b_adr 21 VR15:01
val_frame 15
2056 2056 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 2f TR14:0f
typ_frame 14
val_b_adr 25 VR15:05
val_frame 15
2057 2057 typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 14
2058 2058 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2059 2059 <halt> ; Flow R
205a ; --------------------------------------------------------------------------------------
205a ; 0xe000-0xfe3f Load llvl,ldelta
205a ; --------------------------------------------------------------------------------------
205a MACRO_Load_llvl,ldelta:
205a 205a dispatch_brk_class 0 ; Flow J cc=True 0x205c
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA
dispatch_uadr 205a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 205c 0x205c
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 03 GP03
typ_alu_func 1c DEC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
205b 205b seq_br_type 3 Unconditional Branch; Flow J 0x2058
seq_branch_adr 2058 0x2058
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
205c 205c seq_br_type 3 Unconditional Branch; Flow J 0x205d
seq_branch_adr 205d 0x205d
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
205d 205d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22c8
seq_br_type 5 Call True
seq_branch_adr 22c8 TOS_VALIDATE_FAILED
seq_cond_sel 44 SEQ.TOS_LATCH_valid
seq_int_reads 0 TYP VAL BUS
seq_random 60 Validate_tos_optimizer+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
205e 205e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22ca
seq_br_type 5 Call True
seq_branch_adr 22ca TOS_LATCH_DIDNT_HOLD
seq_cond_sel 44 SEQ.TOS_LATCH_valid
205f 205f seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 2c TR14:0c
typ_frame 14
val_b_adr 26 VR15:06
val_frame 15
2060 2060 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2061 FAILED_DISPATCH:
2061 2061 <halt> ; Flow R
2062 2062 seq_br_type 3 Unconditional Branch; Flow J 0x2061
seq_branch_adr 2061 FAILED_DISPATCH
2063 2063 <halt> ; Flow R
2064 ; --------------------------------------------------------------------------------------
2064 ; 0xd000-0xd03f Store llvl,ldelta
2064 ; --------------------------------------------------------------------------------------
2064 MACRO_Store_llvl,ldelta:
2064 2064 dispatch_brk_class 0 ; Flow C cc=False 0x22cc
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK
dispatch_uadr 2064
dispatch_uses_tos 1
seq_br_type 4 Call False
seq_branch_adr 22cc DISPATCH_DIDNT_INVALIDATE
seq_cond_sel 44 SEQ.TOS_LATCH_valid
2065 2065 seq_br_type 3 Unconditional Branch; Flow J 0x2067
seq_branch_adr 2067 0x2067
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2066 BAD_OPTIMIZATION_ERROR:
2066 2066 <halt> ; Flow R
2067 2067 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2068 2068 typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TR04:1d
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 4
2069 2069 fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
206a 206a fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
206b 206b seq_en_micro 0
206c 206c seq_b_timing 1 Latch Condition; Flow C cc=False 0x22ce
seq_br_type 4 Call False
seq_branch_adr 22ce DIDNT_TAKE_MICRO_EVENT
206d 206d seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
206e 206e seq_int_reads 0 TYP VAL BUS
seq_random 09 ?
typ_alu_func 1a PASS_B
typ_b_adr 22 TR10:02
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_alu_func 1a PASS_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
206f 206f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d0
seq_br_type 5 Call True
seq_branch_adr 22d0 FIELD_NUMBER_TEST_FAILED
seq_cond_sel 57 SEQ.FIELD_NUM_ERR
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 09 ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 22 VR10:02
val_frame 10
2070 2070 typ_alu_func 1a PASS_B
typ_b_adr 20 TR10:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_alu_func 1a PASS_B
val_b_adr 22 VR10:02
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2071 2071 seq_int_reads 0 TYP VAL BUS
seq_random 09 ?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 03 GP03
2072 2072 seq_br_type 3 Unconditional Branch; Flow J 0x2073
seq_branch_adr 2073 0x2073
2073 2073 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2074 2074 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 20 TR17:00
typ_frame 17
val_b_adr 3a VR15:1a
val_frame 15
2075 2075 val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 10
2076 2076 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 10
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2077 2077 <halt> ; Flow R
2078 ; --------------------------------------------------------------------------------------
2078 ; 0x0010 Halt InMicrocode
2078 ; --------------------------------------------------------------------------------------
2078 MACRO_Halt_InMicrocode:
2078 2078 dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2078
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2079 2079 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
207a 207a val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
207b 207b fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
207c 207c <halt> ; Flow R
207d 207d <halt> ; Flow R
207e ; --------------------------------------------------------------------------------------
207e ; 0x0011 QQUnknown InMicrocode
207e ; --------------------------------------------------------------------------------------
207e MACRO_207e_QQUnknown_InMicrocode:
207e 207e dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 1
dispatch_ignore 1
dispatch_uadr 207e
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
207f 207f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_frame 4
2080 2080 val_a_adr 21 VR04:01
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
2081 2081 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2082 2082 <halt> ; Flow R
2083 2083 <halt> ; Flow R
2084 ; --------------------------------------------------------------------------------------
2084 ; 0x0012 QQUnknown InMicrocode
2084 ; --------------------------------------------------------------------------------------
2084 MACRO_2084_QQUnknown_InMicrocode:
2084 2084 dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 2
dispatch_ignore 1
dispatch_uadr 2084
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2085 2085 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_frame 4
2086 2086 val_a_adr 3c VR15:1c
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
2087 2087 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2088 2088 <halt> ; Flow R
2089 2089 <halt> ; Flow R
208a ; --------------------------------------------------------------------------------------
208a ; 0x0013 QQUnknown InMicrocode
208a ; --------------------------------------------------------------------------------------
208a MACRO_208a_QQUnknown_InMicrocode:
208a 208a dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 3
dispatch_ignore 1
dispatch_uadr 208a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
208b 208b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 3c VR15:1c
val_frame 15
208c 208c val_a_adr 22 VR04:02
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
208d 208d fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
208e 208e <halt> ; Flow R
208f 208f <halt> ; Flow R
2090 ; --------------------------------------------------------------------------------------
2090 ; 0x0014 QQUnknown InMicrocode
2090 ; --------------------------------------------------------------------------------------
2090 MACRO_2090_QQUnknown_InMicrocode:
2090 2090 dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 4
dispatch_ignore 1
dispatch_uadr 2090
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2091 2091 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 22 VR04:02
val_frame 4
2092 2092 val_a_adr 3d VR15:1d
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
2093 2093 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2094 2094 <halt> ; Flow R
2095 2095 <halt> ; Flow R
2096 ; --------------------------------------------------------------------------------------
2096 ; 0x0015 QQUnknown InMicrocode
2096 ; --------------------------------------------------------------------------------------
2096 MACRO_2096_QQUnknown_InMicrocode:
2096 2096 dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 5
dispatch_ignore 1
dispatch_uadr 2096
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2097 2097 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 3d VR15:1d
val_frame 15
2098 2098 val_a_adr 3e VR15:1e
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
2099 2099 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
209a 209a <halt> ; Flow R
209b 209b <halt> ; Flow R
209c ; --------------------------------------------------------------------------------------
209c ; 0x0016 QQUnknown InMicrocode
209c ; --------------------------------------------------------------------------------------
209c MACRO_209c_QQUnknown_InMicrocode:
209c 209c dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 6
dispatch_ignore 1
dispatch_uadr 209c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
209d 209d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 3e VR15:1e
val_frame 15
209e 209e val_a_adr 3f VR15:1f
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
209f 209f fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
20a0 20a0 <halt> ; Flow R
20a1 20a1 <halt> ; Flow R
20a2 ; --------------------------------------------------------------------------------------
20a2 ; 0x0017 QQUnknown InMicrocode
20a2 ; --------------------------------------------------------------------------------------
20a2 MACRO_20a2_QQUnknown_InMicrocode:
20a2 20a2 dispatch_brk_class 0 ; Flow C cc=True 0x22d2
dispatch_csa_valid 7
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 20a2
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20a3 20a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d2
seq_br_type 5 Call True
seq_branch_adr 22d2 NVE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 3f VR15:1f
val_frame 15
20a4 20a4 seq_br_type 3 Unconditional Branch; Flow J 0x20a5
seq_branch_adr 20a5 0x20a5
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
20a5 20a5 typ_csa_cntl 2 PUSH_CSA
20a6 20a6 typ_csa_cntl 2 PUSH_CSA
20a7 20a7 typ_csa_cntl 2 PUSH_CSA
20a8 20a8 typ_csa_cntl 2 PUSH_CSA
20a9 20a9 typ_csa_cntl 2 PUSH_CSA
20aa 20aa typ_csa_cntl 2 PUSH_CSA
20ab 20ab typ_csa_cntl 2 PUSH_CSA
20ac 20ac typ_csa_cntl 2 PUSH_CSA
20ad 20ad seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20ae 20ae seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 21 TR17:01
typ_frame 17
val_b_adr 20 VR10:00
val_frame 10
20af 20af val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 10
20b0 20b0 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 10
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
20b1 20b1 <halt> ; Flow R
20b2 ; --------------------------------------------------------------------------------------
20b2 ; 0x0020 Illegal -
20b2 ; --------------------------------------------------------------------------------------
20b2 MACRO_Illegal_-:
20b2 20b2 dispatch_brk_class 0 ; Flow C cc=True 0x22d4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 20b2
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20b3 20b3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d4
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20b4 20b4 val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
20b5 20b5 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
20b6 20b6 <halt> ; Flow R
20b7 20b7 <halt> ; Flow R
20b8 ; --------------------------------------------------------------------------------------
20b8 ; 0x0021 Illegal -
20b8 ; --------------------------------------------------------------------------------------
20b8 MACRO_Illegal_-:
20b8 20b8 dispatch_brk_class 0 ; Flow C cc=True 0x22d4
dispatch_csa_free 1
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 20b8
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20b9 20b9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d4
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_frame 4
20ba 20ba val_a_adr 21 VR04:01
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 4
20bb 20bb fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
20bc 20bc <halt> ; Flow R
20bd 20bd <halt> ; Flow R
20be ; --------------------------------------------------------------------------------------
20be ; 0x0022 Illegal -
20be ; --------------------------------------------------------------------------------------
20be MACRO_Illegal_-:
20be 20be dispatch_brk_class 0 ; Flow C cc=True 0x22d4
dispatch_csa_free 2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 20be
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20bf 20bf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d4
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_frame 4
20c0 20c0 val_a_adr 3c VR15:1c
val_alu_func 0 PASS_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 15
20c1 20c1 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
20c2 20c2 <halt> ; Flow R
20c3 20c3 <halt> ; Flow R
20c4 ; --------------------------------------------------------------------------------------
20c4 ; 0x0023 Illegal -
20c4 ; --------------------------------------------------------------------------------------
20c4 MACRO_Illegal_-:
20c4 20c4 dispatch_brk_class 0 ; Flow C cc=True 0x22d4
dispatch_csa_free 3
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 20c4
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20c5 20c5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x22d4
seq_br_type 5 Call True
seq_branch_adr 22d4 NFREE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 3c VR15:1c
val_frame 15
20c6 20c6 seq_br_type 3 Unconditional Branch; Flow J 0x20c7
seq_branch_adr 20c7 0x20c7
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
20c7 20c7 seq_random 0a ?
20c8 20c8 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20c9 20c9 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 22 TR17:02
typ_frame 17
val_b_adr 20 VR10:00
val_frame 10
20ca 20ca typ_a_adr 2b TR14:0b
typ_alu_func 0 PASS_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
typ_frame 14
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
20cb 20cb fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
20cc 20cc <halt> ; Flow R
20cd 20cd <halt> ; Flow R
20ce ; --------------------------------------------------------------------------------------
20ce ; 0x8000-0x803f Call llvl,ldelta
20ce ; --------------------------------------------------------------------------------------
20ce MACRO_Call_llvl,ldelta:
20ce 20ce dispatch_brk_class 0 ; Flow C cc=True 0x22d6
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA
dispatch_uadr 20ce
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d6 RES_REF_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20cf 20cf seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
20d0 20d0 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
20d1 20d1 <halt> ; Flow R
20d2 ; --------------------------------------------------------------------------------------
20d2 ; 0x8200-0x823f Call llvl,ldelta
20d2 ; --------------------------------------------------------------------------------------
20d2 MACRO_Call_llvl,ldelta:
20d2 20d2 dispatch_brk_class 0 ; Flow C cc=True 0x22d6
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA
dispatch_uadr 20d2
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d6 RES_REF_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20d3 20d3 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
20d4 20d4 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
20d5 20d5 <halt> ; Flow R
20d6 ; --------------------------------------------------------------------------------------
20d6 ; 0x8400-0x843f Call llvl,ldelta
20d6 ; --------------------------------------------------------------------------------------
20d6 MACRO_Call_llvl,ldelta:
20d6 20d6 dispatch_brk_class 0 ; Flow C cc=True 0x22d6
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA
dispatch_uadr 20d6
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d6 RES_REF_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20d7 20d7 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
val_a_adr 09 GP09
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
20d8 20d8 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
20d9 20d9 <halt> ; Flow R
20da ; --------------------------------------------------------------------------------------
20da ; 0x8600-0x863f Call llvl,ldelta
20da ; --------------------------------------------------------------------------------------
20da MACRO_Call_llvl,ldelta:
20da 20da dispatch_brk_class 0 ; Flow C cc=True 0x22d6
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA
dispatch_uadr 20da
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d6 RES_REF_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20db 20db seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
20dc 20dc seq_br_type 3 Unconditional Branch; Flow J 0x20dd
seq_branch_adr 20dd 0x20dd
20dd 20dd seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20de 20de seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 23 TR17:03
typ_frame 17
val_b_adr 20 VR10:00
val_frame 10
20df 20df seq_int_reads 0 TYP VAL BUS
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20e0 20e0 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 10
20e1 20e1 <halt> ; Flow R
20e2 ; --------------------------------------------------------------------------------------
20e2 ; 0xa000-0xa03f Reference zdelta
20e2 ; --------------------------------------------------------------------------------------
20e2 MACRO_Reference_zdelta:
20e2 20e2 dispatch_brk_class 0 ; Flow C cc=True 0x22d9
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK
dispatch_uadr 20e2
dispatch_uses_tos 1
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d9 TOS_OP_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20e3 20e3 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
seq_random 04 Load_save_offset+?
typ_alu_func 13 ONES
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 10
20e4 20e4 <halt> ; Flow R
20e5 20e5 <halt> ; Flow R
20e6 ; --------------------------------------------------------------------------------------
20e6 ; 0xa200-0xa23f Store_Unchecked llvl,ldelta
20e6 ; --------------------------------------------------------------------------------------
20e6 MACRO_Store_Unchecked_llvl,ldelta:
20e6 20e6 dispatch_brk_class 0 ; Flow C cc=True 0x22d9
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK
dispatch_uadr 20e6
dispatch_uses_tos 1
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d9 TOS_OP_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20e7 20e7 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 08 Validate_tos_optimizer+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20e8 20e8 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 10
20e9 20e9 <halt> ; Flow R
20ea ; --------------------------------------------------------------------------------------
20ea ; 0xa400-0xa43f Store_Unchecked llvl,ldelta
20ea ; --------------------------------------------------------------------------------------
20ea MACRO_Store_Unchecked_llvl,ldelta:
20ea 20ea dispatch_brk_class 0 ; Flow C cc=True 0x22d9
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK
dispatch_uadr 20ea
dispatch_uses_tos 1
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d9 TOS_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20eb 20eb seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 10
20ec 20ec fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_int_reads 0 TYP VAL BUS
seq_random 24 Load_save_offset+Validate_tos_optimizer+?
typ_b_adr 20 TR10:00
typ_frame 10
typ_mar_cntl e LOAD_MAR_CONTROL
val_b_adr 20 VR10:00
val_frame 10
20ed 20ed <halt> ; Flow R
20ee ; --------------------------------------------------------------------------------------
20ee ; 0xa600-0xa63f Store_Unchecked llvl,ldelta
20ee ; --------------------------------------------------------------------------------------
20ee MACRO_Store_Unchecked_llvl,ldelta:
20ee 20ee dispatch_brk_class 0 ; Flow C cc=True 0x22d9
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK
dispatch_uadr 20ee
dispatch_uses_tos 1
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 22d9 TOS_OP_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
20ef 20ef seq_br_type 3 Unconditional Branch; Flow J 0x20f0
seq_branch_adr 20f0 0x20f0
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 10
20f0 20f0 seq_int_reads 0 TYP VAL BUS
seq_random 59 ?
typ_alu_func 1a PASS_B
typ_b_adr 20 TR10:00
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
20f1 20f1 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 30 TR14:10
typ_frame 14
val_a_adr 21 VR15:01
val_alu_func 0 PASS_A
val_b_adr 28 VR15:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
20f2 20f2 seq_b_timing 0 Early Condition; Flow J cc=True 0x20f7
seq_br_type 1 Branch True
seq_branch_adr 20f7 0x20f7
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_random 16 ?
val_rand 2 DEC_LOOP_COUNTER
20f3 20f3 fiu_mem_start 2 start-rd; Flow R cc=False
ioc_adrbs 3 seq
seq_b_timing 3 Late Condition, Hint False
seq_br_type d Dispatch False
seq_branch_adr 20f4 0x20f4
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_random 04 Load_save_offset+?
typ_a_adr 28 TR14:08
typ_alu_func 0 PASS_A
typ_frame 14
typ_mar_cntl e LOAD_MAR_CONTROL
20f4 20f4 seq_br_type 3 Unconditional Branch; Flow J 0x20f2
seq_branch_adr 20f2 0x20f2
20f5 20f5 <halt> ; Flow R
20f6 ; --------------------------------------------------------------------------------------
20f6 ; 0x4000-0x403f Illegal -
20f6 ; --------------------------------------------------------------------------------------
20f6 BAD_USUALLY_DISPATCH:
20f6 MACRO_Illegal_-:
20f6 20f6 dispatch_brk_class 0 ; Flow R
dispatch_csa_valid 0
dispatch_uadr 20f6
ioc_random 14 clear cpu running
seq_en_micro 0
seq_random 01 Halt+?
20f7 20f7 ioc_fiubs 2 typ
typ_a_adr 20 TR04:00
typ_frame 4
20f8 20f8 ioc_fiubs 2 typ ; Flow J cc=True 0x20f9
; Flow J cc=#0x0 0x20fa
seq_b_timing 3 Late Condition, Hint False
seq_br_type b Case False
seq_branch_adr 20fa UNSUCCESSFUL_USUALLY_CASE
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_frame 4
20f9 20f9 ioc_fiubs 2 typ ; Flow J 0x20fc
seq_br_type 3 Unconditional Branch
seq_branch_adr 20fc 0x20fc
typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_frame 4
20fa UNSUCCESSFUL_USUALLY_CASE:
20fa 20fa <halt> ; Flow R
20fb 20fb <halt> ; Flow R
20fc 20fc ioc_fiubs 2 typ ; Flow J cc=True 0x20fd
; Flow J cc=#0x0 0x20fe
seq_br_type b Case False
seq_branch_adr 20fe WRONG_CASE_VALUE
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_frame 4
20fd 20fd <halt> ; Flow R
20fe WRONG_CASE_VALUE:
20fe 20fe <halt> ; Flow R
20ff 20ff seq_br_type 3 Unconditional Branch; Flow J 0x2100
seq_branch_adr 2100 0x2100
2100 2100 seq_br_type 3 Unconditional Branch; Flow J 0x2101
seq_branch_adr 2101 0x2101
2101 2101 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
val_a_adr 2a VR16:0a
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 16
2102 2102 typ_a_adr 2f TR17:0f
typ_alu_func 0 PASS_A
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 28 VR04:08
val_alu_func 0 PASS_A
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2103 2103 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2104 2104 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2105 2105 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2106 2106 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2107 2107 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2108 2108 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2109 2109 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
210a 210a seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
210b 210b seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
210c 210c typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
210d 210d seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
210e 210e seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
210f 210f seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2110 2110 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2111 2111 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2112 2112 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2113 2113 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2114 2114 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2115 2115 val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2116 2116 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2117 2117 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2118 2118 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2119 2119 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
211a 211a val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
211b 211b typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
211c 211c seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
211d 211d seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
211e 211e seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
211f 211f val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2120 2120 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2121 2121 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2122 2122 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2123 2123 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2124 2124 val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2125 2125 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2126 2126 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2127 2127 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2128 2128 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2129 2129 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
212a 212a typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
212b 212b seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
212c 212c seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
212d 212d seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
212e 212e seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
212f 212f typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2130 2130 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2131 2131 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2132 2132 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2133 2133 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2134 2134 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2135 2135 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2136 2136 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2137 2137 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2138 2138 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2139 2139 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
213a 213a seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
213b 213b seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
213c 213c seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
213d 213d seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
213e 213e typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
213f 213f seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2140 2140 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2141 2141 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2142 2142 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2143 2143 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2144 2144 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2145 2145 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2146 2146 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2147 2147 seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2148 2148 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2149 2149 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
214a 214a seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
214b 214b seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
214c 214c seq_br_type 7 Unconditional Call; Flow C 0x219a
seq_branch_adr 219a 0x219a
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
214d 214d val_a_adr 30 VR04:10
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 4
214e 214e typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
214f 214f seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2150 2150 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2151 2151 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2152 2152 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2153 2153 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2154 2154 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2155 2155 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2156 2156 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2157 2157 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2158 2158 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2159 2159 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
215a 215a seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
215b 215b seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
215c 215c seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
215d 215d typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
215e 215e seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
215f 215f seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2160 2160 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2161 2161 val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2162 2162 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2163 2163 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2164 2164 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2165 2165 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2166 2166 val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2167 2167 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2168 2168 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2169 2169 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
216a 216a seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
216b 216b val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
216c 216c typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
216d 216d seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
216e 216e seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
216f 216f seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2170 2170 val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2171 2171 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2172 2172 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2173 2173 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2174 2174 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2175 2175 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2176 2176 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2177 2177 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2178 2178 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2179 2179 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
217a 217a seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
217b 217b typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
217c 217c seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
217d 217d seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
217e 217e seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
217f 217f seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2180 2180 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2181 2181 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2182 2182 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2183 2183 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2184 2184 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2185 2185 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2186 2186 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2187 2187 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2188 2188 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2189 2189 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
218a 218a typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
218b 218b seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
218c 218c seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
218d 218d seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
218e 218e seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
218f 218f typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2190 2190 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2191 2191 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2192 2192 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2193 2193 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2194 2194 typ_a_adr 0e GP0e
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR17:10
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR04:04
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
2195 2195 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_a_adr 04 GP04
val_alu_func 3 LEFT_I_A
val_b_adr 20 VR10:00
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2196 2196 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_alu_func 13 ONES
typ_b_adr 0e GP0e
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_b_adr 0e GP0e
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2197 2197 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 20 VR10:00
val_frame 10
2198 2198 seq_br_type 7 Unconditional Call; Flow C 0x21ab
seq_branch_adr 21ab 0x21ab
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2199 2199 seq_br_type a Unconditional Return; Flow R
219a ; --------------------------------------------------------------------------------------
219a ; Comes from:
219a ; 2106 C from color 0x20ff
219a ; 210b C from color 0x20ff
219a ; 2110 C from color 0x20ff
219a ; 2129 C from color 0x20ff
219a ; 212e C from color 0x20ff
219a ; 2133 C from color 0x20ff
219a ; 2138 C from color 0x20ff
219a ; 213d C from color 0x20ff
219a ; 2142 C from color 0x20ff
219a ; 2147 C from color 0x20ff
219a ; 214c C from color 0x20ff
219a ; --------------------------------------------------------------------------------------
219a 219a val_a_adr 0e GP0e
val_alu_func 1d A_AND_NOT_B
val_b_adr 21 VR15:01
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 15
219b 219b seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
219c 219c fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
219d 219d seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 24 VR04:04
val_frame 4
219e 219e seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
typ_alu_func 13 ONES
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_b_adr 03 GP03
219f 219f val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
21a0 21a0 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
21a1 21a1 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
21a2 21a2 val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
21a3 21a3 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
21a4 21a4 typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
21a5 21a5 seq_br_type 1 Branch True; Flow J cc=True 0x21a7
seq_branch_adr 21a7 0x21a7
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 03 GP03
val_alu_func 1e A_AND_B
val_b_adr 3f VR04:1f
val_frame 4
21a6 21a6 val_a_adr 2a VR16:0a
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 16
21a7 21a7 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 25 VR04:05
val_frame 4
21a8 21a8 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
typ_alu_func 13 ONES
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_b_adr 03 GP03
21a9 21a9 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
21aa 21aa seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x21a4
seq_br_type 8 Return True
seq_branch_adr 21a4 0x21a4
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
21ab ; --------------------------------------------------------------------------------------
21ab ; Comes from:
21ab ; 2152 C from color 0x20ff
21ab ; 2157 C from color 0x20ff
21ab ; 215c C from color 0x20ff
21ab ; 2175 C from color 0x20ff
21ab ; 217a C from color 0x20ff
21ab ; 217f C from color 0x20ff
21ab ; 2184 C from color 0x20ff
21ab ; 2189 C from color 0x20ff
21ab ; 218e C from color 0x20ff
21ab ; 2193 C from color 0x20ff
21ab ; 2198 C from color 0x20ff
21ab ; --------------------------------------------------------------------------------------
21ab 21ab val_a_adr 0e GP0e
val_alu_func 1d A_AND_NOT_B
val_b_adr 21 VR15:01
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 15
21ac 21ac seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
21ad 21ad fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
21ae 21ae seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 24 VR04:04
val_frame 4
21af 21af seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_b_adr 03 GP03
21b0 21b0 val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
21b1 21b1 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
21b2 21b2 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
21b3 21b3 val_a_adr 0e GP0e
val_alu_func 1 A_PLUS_B
val_b_adr 20 VR04:00
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 4
21b4 21b4 seq_int_reads 0 TYP VAL BUS
seq_random 11 Load_current_instr+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 0e GP0e
21b5 21b5 typ_alu_func 13 ONES
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
21b6 21b6 seq_br_type 1 Branch True; Flow J cc=True 0x21b8
seq_branch_adr 21b8 0x21b8
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 03 GP03
val_alu_func 1e A_AND_B
val_b_adr 3f VR04:1f
val_frame 4
21b7 21b7 val_a_adr 30 VR04:10
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
21b8 21b8 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 25 VR04:05
val_frame 4
21b9 21b9 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
typ_alu_func 13 ONES
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_b_adr 03 GP03
21ba 21ba fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
21bb 21bb seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x21b5
seq_br_type 8 Return True
seq_branch_adr 21b5 0x21b5
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
21bc 21bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21bd 21bd seq_br_type 3 Unconditional Branch; Flow J 0x219d
seq_branch_adr 219d 0x219d
21be 21be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21bf 21bf seq_br_type 3 Unconditional Branch; Flow J 0x21a2
seq_branch_adr 21a2 0x21a2
21c0 21c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21c1 21c1 seq_br_type 3 Unconditional Branch; Flow J 0x21aa
seq_branch_adr 21aa 0x21aa
21c2 21c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21c3 21c3 seq_br_type 3 Unconditional Branch; Flow J 0x21ae
seq_branch_adr 21ae 0x21ae
21c4 21c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21c5 21c5 seq_br_type 3 Unconditional Branch; Flow J 0x21b3
seq_branch_adr 21b3 0x21b3
21c6 21c6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x226b
seq_br_type 5 Call True
seq_branch_adr 226b BREAK_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 0c GP0c
val_alu_func 0 PASS_A
21c7 21c7 seq_br_type 3 Unconditional Branch; Flow J 0x21bb
seq_branch_adr 21bb 0x21bb
21c8 ; --------------------------------------------------------------------------------------
21c8 ; 0x0100 Execute Exception,Raise,>R
21c8 ; --------------------------------------------------------------------------------------
21c8 MACRO_Execute_Exception,Raise,>R:
21c8 21c8 dispatch_brk_class f ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21c8
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
21c9 21c9 <halt> ; Flow R
21ca ; --------------------------------------------------------------------------------------
21ca ; 0x0101 Execute Exception,Reraise,>R
21ca ; --------------------------------------------------------------------------------------
21ca MACRO_Execute_Exception,Reraise,>R:
21ca 21ca dispatch_brk_class f ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21ca
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
21cb 21cb <halt> ; Flow R
21cc ; --------------------------------------------------------------------------------------
21cc ; 0x0102 Illegal -
21cc ; --------------------------------------------------------------------------------------
21cc MACRO_Illegal_-:
21cc 21cc dispatch_brk_class f ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21cc
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
21cd 21cd <halt> ; Flow R
21ce ; --------------------------------------------------------------------------------------
21ce ; 0x01f0 Illegal -
21ce ; --------------------------------------------------------------------------------------
21ce MACRO_Illegal_-:
21ce 21ce dispatch_brk_class f ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21ce
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
21cf 21cf <halt> ; Flow R
21d0 ; --------------------------------------------------------------------------------------
21d0 ; 0x01f1 Illegal -
21d0 ; --------------------------------------------------------------------------------------
21d0 MACRO_Illegal_-:
21d0 21d0 dispatch_brk_class f ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21d0
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
21d1 21d1 <halt> ; Flow R
21d2 ; --------------------------------------------------------------------------------------
21d2 ; 0x01f2 Illegal -
21d2 ; --------------------------------------------------------------------------------------
21d2 MACRO_Illegal_-:
21d2 21d2 dispatch_brk_class f ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21d2
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
21d3 21d3 <halt> ; Flow R
21d4 ; --------------------------------------------------------------------------------------
21d4 ; 0x0110 Execute Any,Is_Initialization_Repeated
21d4 ; --------------------------------------------------------------------------------------
21d4 MACRO_Execute_Any,Is_Initialization_Repeated:
21d4 21d4 dispatch_brk_class b ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21d4
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
21d5 21d5 <halt> ; Flow R
21d6 ; --------------------------------------------------------------------------------------
21d6 ; 0x0111 Execute Any,Has_Repeated_Initialization
21d6 ; --------------------------------------------------------------------------------------
21d6 MACRO_Execute_Any,Has_Repeated_Initialization:
21d6 21d6 dispatch_brk_class b ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21d6
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
21d7 21d7 <halt> ; Flow R
21d8 ; --------------------------------------------------------------------------------------
21d8 ; 0x0112 Execute Any,Make_Constrained
21d8 ; --------------------------------------------------------------------------------------
21d8 MACRO_Execute_Any,Make_Constrained:
21d8 21d8 dispatch_brk_class b ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21d8
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
21d9 21d9 <halt> ; Flow R
21da ; --------------------------------------------------------------------------------------
21da ; 0x0200 Illegal -
21da ; --------------------------------------------------------------------------------------
21da MACRO_Illegal_-:
21da 21da dispatch_brk_class b ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21da
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
21db 21db <halt> ; Flow R
21dc ; --------------------------------------------------------------------------------------
21dc ; 0x0201 Illegal -
21dc ; --------------------------------------------------------------------------------------
21dc MACRO_Illegal_-:
21dc 21dc dispatch_brk_class b ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21dc
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
21dd 21dd <halt> ; Flow R
21de ; --------------------------------------------------------------------------------------
21de ; 0x0202 Illegal -
21de ; --------------------------------------------------------------------------------------
21de MACRO_Illegal_-:
21de 21de dispatch_brk_class b ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21de
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
21df 21df <halt> ; Flow R
21e0 ; --------------------------------------------------------------------------------------
21e0 ; 0x0120 Execute Any,Is_Value
21e0 ; --------------------------------------------------------------------------------------
21e0 MACRO_Execute_Any,Is_Value:
21e0 21e0 dispatch_brk_class d ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21e0
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
21e1 21e1 <halt> ; Flow R
21e2 ; --------------------------------------------------------------------------------------
21e2 ; 0x0121 Execute Any,Is_Default
21e2 ; --------------------------------------------------------------------------------------
21e2 MACRO_Execute_Any,Is_Default:
21e2 21e2 dispatch_brk_class d ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21e2
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
21e3 21e3 <halt> ; Flow R
21e4 ; --------------------------------------------------------------------------------------
21e4 ; 0x0122 Execute Any,Make_Root_Type
21e4 ; --------------------------------------------------------------------------------------
21e4 MACRO_Execute_Any,Make_Root_Type:
21e4 21e4 dispatch_brk_class d ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21e4
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
21e5 21e5 <halt> ; Flow R
21e6 ; --------------------------------------------------------------------------------------
21e6 ; 0x0210 Execute Heap_Access,Get_Segment
21e6 ; --------------------------------------------------------------------------------------
21e6 MACRO_Execute_Heap_Access,Get_Segment:
21e6 21e6 dispatch_brk_class d ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21e6
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
21e7 21e7 <halt> ; Flow R
21e8 ; --------------------------------------------------------------------------------------
21e8 ; 0x0211 Execute Heap_Access,Convert_Reference
21e8 ; --------------------------------------------------------------------------------------
21e8 MACRO_Execute_Heap_Access,Convert_Reference:
21e8 21e8 dispatch_brk_class d ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21e8
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
21e9 21e9 <halt> ; Flow R
21ea ; --------------------------------------------------------------------------------------
21ea ; 0x0212 Execute Heap_Access,Address
21ea ; --------------------------------------------------------------------------------------
21ea MACRO_Execute_Heap_Access,Address:
21ea 21ea dispatch_brk_class d ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21ea
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
21eb 21eb <halt> ; Flow R
21ec ; --------------------------------------------------------------------------------------
21ec ; 0x0170 Illegal -
21ec ; --------------------------------------------------------------------------------------
21ec MACRO_Illegal_-:
21ec 21ec dispatch_brk_class 8 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21ec
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
21ed 21ed <halt> ; Flow R
21ee ; --------------------------------------------------------------------------------------
21ee ; 0x0171 Illegal -
21ee ; --------------------------------------------------------------------------------------
21ee MACRO_Illegal_-:
21ee 21ee dispatch_brk_class 8 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21ee
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
21ef 21ef <halt> ; Flow R
21f0 ; --------------------------------------------------------------------------------------
21f0 ; 0x0172 Illegal -
21f0 ; --------------------------------------------------------------------------------------
21f0 MACRO_Illegal_-:
21f0 21f0 dispatch_brk_class 8 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21f0
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
21f1 21f1 <halt> ; Flow R
21f2 ; --------------------------------------------------------------------------------------
21f2 ; 0x0260 Execute Discrete,In_Type
21f2 ; --------------------------------------------------------------------------------------
21f2 MACRO_Execute_Discrete,In_Type:
21f2 21f2 dispatch_brk_class 8 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21f2
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
21f3 21f3 <halt> ; Flow R
21f4 ; --------------------------------------------------------------------------------------
21f4 ; 0x0261 Execute Discrete,Not_In_Range
21f4 ; --------------------------------------------------------------------------------------
21f4 MACRO_Execute_Discrete,Not_In_Range:
21f4 21f4 dispatch_brk_class 8 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21f4
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
21f5 21f5 <halt> ; Flow R
21f6 ; --------------------------------------------------------------------------------------
21f6 ; 0x0262 Execute Discrete,In_Range
21f6 ; --------------------------------------------------------------------------------------
21f6 MACRO_Execute_Discrete,In_Range:
21f6 21f6 dispatch_brk_class 8 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21f6
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
21f7 21f7 <halt> ; Flow R
21f8 ; --------------------------------------------------------------------------------------
21f8 ; 0x0180 Illegal -
21f8 ; --------------------------------------------------------------------------------------
21f8 MACRO_Illegal_-:
21f8 21f8 dispatch_brk_class 7 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21f8
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
21f9 21f9 <halt> ; Flow R
21fa ; --------------------------------------------------------------------------------------
21fa ; 0x0181 Illegal -
21fa ; --------------------------------------------------------------------------------------
21fa MACRO_Illegal_-:
21fa 21fa dispatch_brk_class 7 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21fa
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
21fb 21fb <halt> ; Flow R
21fc ; --------------------------------------------------------------------------------------
21fc ; 0x0182 Illegal -
21fc ; --------------------------------------------------------------------------------------
21fc MACRO_Illegal_-:
21fc 21fc dispatch_brk_class 7 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21fc
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
21fd 21fd <halt> ; Flow R
21fe ; --------------------------------------------------------------------------------------
21fe ; 0x0270 Execute Discrete,Divide
21fe ; --------------------------------------------------------------------------------------
21fe MACRO_Execute_Discrete,Divide:
21fe 21fe dispatch_brk_class 7 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 21fe
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
21ff 21ff <halt> ; Flow R
2200 ; --------------------------------------------------------------------------------------
2200 ; 0x0271 Execute Discrete,Times
2200 ; --------------------------------------------------------------------------------------
2200 MACRO_Execute_Discrete,Times:
2200 2200 dispatch_brk_class 7 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2200
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
2201 2201 <halt> ; Flow R
2202 ; --------------------------------------------------------------------------------------
2202 ; 0x0272 Execute Discrete,Minus
2202 ; --------------------------------------------------------------------------------------
2202 MACRO_Execute_Discrete,Minus:
2202 2202 dispatch_brk_class 7 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2202
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
2203 2203 <halt> ; Flow R
2204 ; --------------------------------------------------------------------------------------
2204 ; 0x0190 Illegal -
2204 ; --------------------------------------------------------------------------------------
2204 MACRO_Illegal_-:
2204 2204 dispatch_brk_class 3 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2204
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
2205 2205 <halt> ; Flow R
2206 ; --------------------------------------------------------------------------------------
2206 ; 0x0191 Illegal -
2206 ; --------------------------------------------------------------------------------------
2206 MACRO_Illegal_-:
2206 2206 dispatch_brk_class 3 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2206
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
2207 2207 <halt> ; Flow R
2208 ; --------------------------------------------------------------------------------------
2208 ; 0x0192 Illegal -
2208 ; --------------------------------------------------------------------------------------
2208 MACRO_Illegal_-:
2208 2208 dispatch_brk_class 3 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2208
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
2209 2209 <halt> ; Flow R
220a ; --------------------------------------------------------------------------------------
220a ; 0x0280 Illegal -
220a ; --------------------------------------------------------------------------------------
220a MACRO_Illegal_-:
220a 220a dispatch_brk_class 3 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 220a
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
220b 220b <halt> ; Flow R
220c ; --------------------------------------------------------------------------------------
220c ; 0x0281 Illegal -
220c ; --------------------------------------------------------------------------------------
220c MACRO_Illegal_-:
220c 220c dispatch_brk_class 3 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 220c
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
220d 220d <halt> ; Flow R
220e ; --------------------------------------------------------------------------------------
220e ; 0x0282 Illegal -
220e ; --------------------------------------------------------------------------------------
220e MACRO_Illegal_-:
220e 220e dispatch_brk_class 3 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 220e
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
220f 220f <halt> ; Flow R
2210 ; --------------------------------------------------------------------------------------
2210 ; 0x01a0 Illegal -
2210 ; --------------------------------------------------------------------------------------
2210 MACRO_Illegal_-:
2210 2210 dispatch_brk_class 5 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2210
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
2211 2211 <halt> ; Flow R
2212 ; --------------------------------------------------------------------------------------
2212 ; 0x01a1 Illegal -
2212 ; --------------------------------------------------------------------------------------
2212 MACRO_Illegal_-:
2212 2212 dispatch_brk_class 5 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2212
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
2213 2213 <halt> ; Flow R
2214 ; --------------------------------------------------------------------------------------
2214 ; 0x01a2 Illegal -
2214 ; --------------------------------------------------------------------------------------
2214 MACRO_Illegal_-:
2214 2214 dispatch_brk_class 5 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2214
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
2215 2215 <halt> ; Flow R
2216 ; --------------------------------------------------------------------------------------
2216 ; 0x0290 Illegal -
2216 ; --------------------------------------------------------------------------------------
2216 MACRO_Illegal_-:
2216 2216 dispatch_brk_class 5 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2216
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
2217 2217 <halt> ; Flow R
2218 ; --------------------------------------------------------------------------------------
2218 ; 0x0291 Illegal -
2218 ; --------------------------------------------------------------------------------------
2218 MACRO_Illegal_-:
2218 2218 dispatch_brk_class 5 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2218
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
2219 2219 <halt> ; Flow R
221a ; --------------------------------------------------------------------------------------
221a ; 0x0292 Illegal -
221a ; --------------------------------------------------------------------------------------
221a MACRO_Illegal_-:
221a 221a dispatch_brk_class 5 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 221a
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
221b 221b <halt> ; Flow R
221c ; --------------------------------------------------------------------------------------
221c ; 0x01b0 Illegal -
221c ; --------------------------------------------------------------------------------------
221c MACRO_Illegal_-:
221c 221c dispatch_brk_class 1 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 221c
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
221d 221d <halt> ; Flow R
221e ; --------------------------------------------------------------------------------------
221e ; 0x01b1 Illegal -
221e ; --------------------------------------------------------------------------------------
221e MACRO_Illegal_-:
221e 221e dispatch_brk_class 1 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 221e
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
221f 221f <halt> ; Flow R
2220 ; --------------------------------------------------------------------------------------
2220 ; 0x01b2 Illegal -
2220 ; --------------------------------------------------------------------------------------
2220 MACRO_Illegal_-:
2220 2220 dispatch_brk_class 1 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2220
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
2221 2221 <halt> ; Flow R
2222 ; --------------------------------------------------------------------------------------
2222 ; 0x02a0 Declare_Subprogram Null_Subprogram
2222 ; --------------------------------------------------------------------------------------
2222 MACRO_Declare_Subprogram_Null_Subprogram:
2222 2222 dispatch_brk_class 1 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2222
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
2223 2223 <halt> ; Flow R
2224 ; --------------------------------------------------------------------------------------
2224 ; 0x02a1 Illegal -
2224 ; --------------------------------------------------------------------------------------
2224 MACRO_Illegal_-:
2224 2224 dispatch_brk_class 1 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2224
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
2225 2225 <halt> ; Flow R
2226 ; --------------------------------------------------------------------------------------
2226 ; 0x02a2 Declare_Subprogram For_Accept,With_Address
2226 ; --------------------------------------------------------------------------------------
2226 MACRO_Declare_Subprogram_For_Accept,With_Address:
2226 2226 dispatch_brk_class 1 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2226
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
2227 2227 <halt> ; Flow R
2228 ; --------------------------------------------------------------------------------------
2228 ; 0x01c0 Execute Vector,Greater_Equal
2228 ; --------------------------------------------------------------------------------------
2228 MACRO_Execute_Vector,Greater_Equal:
2228 2228 dispatch_brk_class 6 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2228
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
2229 2229 <halt> ; Flow R
222a ; --------------------------------------------------------------------------------------
222a ; 0x01c1 Execute Vector,Less
222a ; --------------------------------------------------------------------------------------
222a MACRO_Execute_Vector,Less:
222a 222a dispatch_brk_class 6 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 222a
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
222b 222b <halt> ; Flow R
222c ; --------------------------------------------------------------------------------------
222c ; 0x01c2 Execute Vector,Greater
222c ; --------------------------------------------------------------------------------------
222c MACRO_Execute_Vector,Greater:
222c 222c dispatch_brk_class 6 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 222c
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
222d 222d <halt> ; Flow R
222e ; --------------------------------------------------------------------------------------
222e ; 0x02b0 Illegal -
222e ; --------------------------------------------------------------------------------------
222e MACRO_Illegal_-:
222e 222e dispatch_brk_class 6 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 222e
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
222f 222f <halt> ; Flow R
2230 ; --------------------------------------------------------------------------------------
2230 ; 0x02b1 Illegal -
2230 ; --------------------------------------------------------------------------------------
2230 MACRO_Illegal_-:
2230 2230 dispatch_brk_class 6 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2230
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
2231 2231 <halt> ; Flow R
2232 ; --------------------------------------------------------------------------------------
2232 ; 0x02b2 Illegal -
2232 ; --------------------------------------------------------------------------------------
2232 MACRO_Illegal_-:
2232 2232 dispatch_brk_class 6 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2232
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
2233 2233 <halt> ; Flow R
2234 ; --------------------------------------------------------------------------------------
2234 ; 0x01d0 Execute Vector,Complement
2234 ; --------------------------------------------------------------------------------------
2234 MACRO_Execute_Vector,Complement:
2234 2234 dispatch_brk_class 2 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2234
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
2235 2235 <halt> ; Flow R
2236 ; --------------------------------------------------------------------------------------
2236 ; 0x01d1 Execute Vector,Xor
2236 ; --------------------------------------------------------------------------------------
2236 MACRO_Execute_Vector,Xor:
2236 2236 dispatch_brk_class 2 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2236
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
2237 2237 <halt> ; Flow R
2238 ; --------------------------------------------------------------------------------------
2238 ; 0x01d2 Execute Vector,Or
2238 ; --------------------------------------------------------------------------------------
2238 MACRO_Execute_Vector,Or:
2238 2238 dispatch_brk_class 2 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2238
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
2239 2239 <halt> ; Flow R
223a ; --------------------------------------------------------------------------------------
223a ; 0x02c0 Illegal -
223a ; --------------------------------------------------------------------------------------
223a MACRO_Illegal_-:
223a 223a dispatch_brk_class 2 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 223a
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
223b 223b <halt> ; Flow R
223c ; --------------------------------------------------------------------------------------
223c ; 0x02c1 Illegal -
223c ; --------------------------------------------------------------------------------------
223c MACRO_Illegal_-:
223c 223c dispatch_brk_class 2 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 223c
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
223d 223d <halt> ; Flow R
223e ; --------------------------------------------------------------------------------------
223e ; 0x02c2 Illegal -
223e ; --------------------------------------------------------------------------------------
223e MACRO_Illegal_-:
223e 223e dispatch_brk_class 2 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 223e
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
223f 223f <halt> ; Flow R
2240 ; --------------------------------------------------------------------------------------
2240 ; 0x01e0 Illegal -
2240 ; --------------------------------------------------------------------------------------
2240 MACRO_Illegal_-:
2240 2240 dispatch_brk_class 4 ; Flow J 0x21bc
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2240
seq_br_type 3 Unconditional Branch
seq_branch_adr 21bc 0x21bc
2241 2241 <halt> ; Flow R
2242 ; --------------------------------------------------------------------------------------
2242 ; 0x01e1 Illegal -
2242 ; --------------------------------------------------------------------------------------
2242 MACRO_Illegal_-:
2242 2242 dispatch_brk_class 4 ; Flow J 0x21be
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2242
seq_br_type 3 Unconditional Branch
seq_branch_adr 21be 0x21be
2243 2243 <halt> ; Flow R
2244 ; --------------------------------------------------------------------------------------
2244 ; 0x01e2 Illegal -
2244 ; --------------------------------------------------------------------------------------
2244 MACRO_Illegal_-:
2244 2244 dispatch_brk_class 4 ; Flow J 0x21c0
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2244
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c0 0x21c0
2245 2245 <halt> ; Flow R
2246 ; --------------------------------------------------------------------------------------
2246 ; 0x02d0 Illegal -
2246 ; --------------------------------------------------------------------------------------
2246 MACRO_Illegal_-:
2246 2246 dispatch_brk_class 4 ; Flow J 0x21c2
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2246
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c2 0x21c2
2247 2247 <halt> ; Flow R
2248 ; --------------------------------------------------------------------------------------
2248 ; 0x02d1 Illegal -
2248 ; --------------------------------------------------------------------------------------
2248 MACRO_Illegal_-:
2248 2248 dispatch_brk_class 4 ; Flow J 0x21c4
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 2248
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c4 0x21c4
2249 2249 <halt> ; Flow R
224a ; --------------------------------------------------------------------------------------
224a ; 0x02d2 Illegal -
224a ; --------------------------------------------------------------------------------------
224a MACRO_Illegal_-:
224a 224a dispatch_brk_class 4 ; Flow J 0x21c6
dispatch_csa_valid 0
dispatch_ignore 1
dispatch_uadr 224a
seq_br_type 3 Unconditional Branch
seq_branch_adr 21c6 0x21c6
224b 224b <halt> ; Flow R
224c ; --------------------------------------------------------------------------------------
224c ; 0x0400-0x043f Execute_Immediate Set_Value_Visible_Unchecked,uimmediate
224c ; --------------------------------------------------------------------------------------
224c MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate:
224c 224c dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 224c
224d 224d <halt> ; Flow R
224e ; --------------------------------------------------------------------------------------
224e ; 0x0440-0x047f Execute_Immediate Set_Value_Visible_Unchecked,uimmediate
224e ; --------------------------------------------------------------------------------------
224e MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate:
224e 224e dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 224e
224f 224f <halt> ; Flow R
2250 ; --------------------------------------------------------------------------------------
2250 ; 0x0480-0x04bf Execute_Immediate Set_Value_Visible_Unchecked,uimmediate
2250 ; --------------------------------------------------------------------------------------
2250 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate:
2250 2250 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2250
2251 2251 <halt> ; Flow R
2252 ; --------------------------------------------------------------------------------------
2252 ; 0x04c0-0x04ff Execute_Immediate Set_Value_Visible_Unchecked,uimmediate
2252 ; --------------------------------------------------------------------------------------
2252 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate:
2252 2252 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2252
2253 2253 <halt> ; Flow R
2254 ; --------------------------------------------------------------------------------------
2254 ; 0x0500-0x053f Execute_Immediate Set_Value_Visible,uimmediate
2254 ; --------------------------------------------------------------------------------------
2254 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate:
2254 2254 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2254
2255 2255 <halt> ; Flow R
2256 ; --------------------------------------------------------------------------------------
2256 ; 0x0540-0x057f Execute_Immediate Set_Value_Visible,uimmediate
2256 ; --------------------------------------------------------------------------------------
2256 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate:
2256 2256 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2256
2257 2257 <halt> ; Flow R
2258 ; --------------------------------------------------------------------------------------
2258 ; 0x0580-0x05bf Execute_Immediate Set_Value_Visible,uimmediate
2258 ; --------------------------------------------------------------------------------------
2258 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate:
2258 2258 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2258
2259 2259 <halt> ; Flow R
225a ; --------------------------------------------------------------------------------------
225a ; 0x05c0-0x05ff Execute_Immediate Set_Value_Visible,uimmediate
225a ; --------------------------------------------------------------------------------------
225a MACRO_Execute_Immediate_Set_Value_Visible,uimmediate:
225a 225a dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 225a
225b 225b <halt> ; Flow R
225c ; --------------------------------------------------------------------------------------
225c ; 0x0600-0x063f Execute_Immediate Set_Value_Unchecked,uimmediate
225c ; --------------------------------------------------------------------------------------
225c MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate:
225c 225c dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 225c
225d 225d <halt> ; Flow R
225e ; --------------------------------------------------------------------------------------
225e ; 0x0640-0x067f Execute_Immediate Set_Value_Unchecked,uimmediate
225e ; --------------------------------------------------------------------------------------
225e MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate:
225e 225e dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 225e
225f 225f <halt> ; Flow R
2260 ; --------------------------------------------------------------------------------------
2260 ; 0x0680-0x06bf Execute_Immediate Set_Value_Unchecked,uimmediate
2260 ; --------------------------------------------------------------------------------------
2260 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate:
2260 2260 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2260
2261 2261 <halt> ; Flow R
2262 ; --------------------------------------------------------------------------------------
2262 ; 0x06c0-0x06ff Execute_Immediate Set_Value_Unchecked,uimmediate
2262 ; --------------------------------------------------------------------------------------
2262 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate:
2262 2262 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2262
2263 2263 <halt> ; Flow R
2264 ; --------------------------------------------------------------------------------------
2264 ; 0x0700-0x073f Execute_Immediate Set_Value,uimmediate
2264 ; --------------------------------------------------------------------------------------
2264 MACRO_Execute_Immediate_Set_Value,uimmediate:
2264 2264 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2264
2265 2265 <halt> ; Flow R
2266 ; --------------------------------------------------------------------------------------
2266 ; 0x0740-0x077f Execute_Immediate Set_Value,uimmediate
2266 ; --------------------------------------------------------------------------------------
2266 MACRO_Execute_Immediate_Set_Value,uimmediate:
2266 2266 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2266
2267 2267 <halt> ; Flow R
2268 ; --------------------------------------------------------------------------------------
2268 ; 0x0780-0x07bf Execute_Immediate Set_Value,uimmediate
2268 ; --------------------------------------------------------------------------------------
2268 MACRO_Execute_Immediate_Set_Value,uimmediate:
2268 2268 dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 2268
2269 2269 <halt> ; Flow R
226a ; --------------------------------------------------------------------------------------
226a ; 0x07c0-0x07ff Execute_Immediate Set_Value,uimmediate
226a ; --------------------------------------------------------------------------------------
226a MACRO_Execute_Immediate_Set_Value,uimmediate:
226a 226a dispatch_brk_class 4
dispatch_csa_valid 0
dispatch_uadr 226a
226b ; --------------------------------------------------------------------------------------
226b ; Comes from:
226b ; 0148 C True from color ML_break_class
226b ; 21bc C True from color 0x219d
226b ; 21be C True from color 0x21a2
226b ; 21c0 C True from color 0x21a2
226b ; 21c2 C True from color 0x21ae
226b ; 21c4 C True from color 0x21b3
226b ; 21c6 C True from color 0x21b3
226b ; --------------------------------------------------------------------------------------
226b BREAK_ERROR:
226b BREAK_ERROR:
226b 226b ioc_random 14 clear cpu running; Flow R
seq_br_type a Unconditional Return
seq_en_micro 0
seq_random 01 Halt+?
226c ; --------------------------------------------------------------------------------------
226c ; Comes from:
226c ; 1e5d C True from color DIAGNOSTIC_START
226c ; 1e5e C False from color DIAGNOSTIC_START
226c ; 1e5f C True from color DIAGNOSTIC_START
226c ; 1e62 C True from color DIAGNOSTIC_START
226c ; 1e63 C True from color DIAGNOSTIC_START
226c ; 1e65 C from color DIAGNOSTIC_START
226c ; 1e66 C True from color DIAGNOSTIC_START
226c ; 1e67 C True from color DIAGNOSTIC_START
226c ; 1e6a C from color DIAGNOSTIC_START
226c ; 1e6b C True from color DIAGNOSTIC_START
226c ; 1e6c C False from color DIAGNOSTIC_START
226c ; 1e6e C from color DIAGNOSTIC_START
226c ; 1e70 C False from color DIAGNOSTIC_START
226c ; 1e72 C from color DIAGNOSTIC_START
226c ; 1e74 C False from color DIAGNOSTIC_START
226c ; 1e75 C False from color DIAGNOSTIC_START
226c ; 1e77 C from color DIAGNOSTIC_START
226c ; 1e78 C True from color DIAGNOSTIC_START
226c ; 1e79 C False from color DIAGNOSTIC_START
226c ; 1e7b C from color DIAGNOSTIC_START
226c ; 1e7c C False from color DIAGNOSTIC_START
226c ; 1e7e C from color DIAGNOSTIC_START
226c ; 1e7f C False from color DIAGNOSTIC_START
226c ; 1e81 C from color DIAGNOSTIC_START
226c ; 1e83 C from color DIAGNOSTIC_START
226c ; 1e84 C False from color DIAGNOSTIC_START
226c ; 1e85 C False from color DIAGNOSTIC_START
226c ; 1e87 C from color DIAGNOSTIC_START
226c ; 1e88 C False from color DIAGNOSTIC_START
226c ; 1e8a C from color DIAGNOSTIC_START
226c ; 1e8b C True from color DIAGNOSTIC_START
226c ; 1e8d C from color DIAGNOSTIC_START
226c ; 1e8f C from color DIAGNOSTIC_START
226c ; 1e90 C False from color DIAGNOSTIC_START
226c ; 1e91 C False from color DIAGNOSTIC_START
226c ; 1e93 C from color DIAGNOSTIC_START
226c ; 1e94 C False from color DIAGNOSTIC_START
226c ; 1e96 C from color DIAGNOSTIC_START
226c ; 1e97 C True from color DIAGNOSTIC_START
226c ; 1e99 C from color DIAGNOSTIC_START
226c ; 1e9b C from color DIAGNOSTIC_START
226c ; 1e9c C True from color DIAGNOSTIC_START
226c ; 1e9d C False from color DIAGNOSTIC_START
226c ; 1e9f C from color DIAGNOSTIC_START
226c ; 1ea0 C False from color DIAGNOSTIC_START
226c ; 1ea2 C from color DIAGNOSTIC_START
226c ; 1ea3 C False from color DIAGNOSTIC_START
226c ; 1ea5 C from color DIAGNOSTIC_START
226c ; 1ea7 C from color DIAGNOSTIC_START
226c ; 1ea8 C False from color DIAGNOSTIC_START
226c ; 1ea9 C True from color DIAGNOSTIC_START
226c ; 1eab C from color DIAGNOSTIC_START
226c ; 1eac C False from color DIAGNOSTIC_START
226c ; 1eae C from color DIAGNOSTIC_START
226c ; 1eaf C False from color DIAGNOSTIC_START
226c ; 1eb1 C from color DIAGNOSTIC_START
226c ; 1eb3 C from color DIAGNOSTIC_START
226c ; 1eb4 C False from color DIAGNOSTIC_START
226c ; 1eb5 C True from color DIAGNOSTIC_START
226c ; 1eb7 C from color DIAGNOSTIC_START
226c ; 1eb8 C False from color DIAGNOSTIC_START
226c ; 1eba C from color DIAGNOSTIC_START
226c ; 1ebb C False from color DIAGNOSTIC_START
226c ; 1ebd C from color DIAGNOSTIC_START
226c ; 1ebe C True from color DIAGNOSTIC_START
226c ; 1ec0 C from color DIAGNOSTIC_START
226c ; 1ec2 C from color DIAGNOSTIC_START
226c ; 1ec3 C False from color DIAGNOSTIC_START
226c ; 1ec4 C False from color DIAGNOSTIC_START
226c ; 1ec6 C from color DIAGNOSTIC_START
226c ; 1ec8 C from color DIAGNOSTIC_START
226c ; 1ec9 C False from color DIAGNOSTIC_START
226c ; 1ecb C from color DIAGNOSTIC_START
226c ; 1ecc C True from color DIAGNOSTIC_START
226c ; 1ece C from color DIAGNOSTIC_START
226c ; 1ecf C True from color DIAGNOSTIC_START
226c ; 1ed0 C True from color DIAGNOSTIC_START
226c ; 1ed2 C from color DIAGNOSTIC_START
226c ; 1ed4 C from color DIAGNOSTIC_START
226c ; 1ed5 C False from color DIAGNOSTIC_START
226c ; 1ed6 C False from color DIAGNOSTIC_START
226c ; 1ed8 C from color DIAGNOSTIC_START
226c ; 1eda C from color DIAGNOSTIC_START
226c ; 1edb C False from color DIAGNOSTIC_START
226c ; 1edd C from color DIAGNOSTIC_START
226c ; 1ede C True from color DIAGNOSTIC_START
226c ; 1ee0 C from color DIAGNOSTIC_START
226c ; 1ee1 C True from color DIAGNOSTIC_START
226c ; --------------------------------------------------------------------------------------
226c COND_ERROR:
226c COND_ERROR:
226c 226c <halt> ; Flow R
226d 226d seq_br_type a Unconditional Return; Flow R
226e ; --------------------------------------------------------------------------------------
226e ; Comes from:
226e ; 1ef5 C True from color 0x1ee3
226e ; 1efd C True from color 0x1ee3
226e ; 1f08 C True from color 0x1ee3
226e ; 1f0a C True from color 0x1ee3
226e ; 1f14 C True from color 0x1ee3
226e ; 1f16 C True from color 0x1ee3
226e ; --------------------------------------------------------------------------------------
226e BAD_MACRO_PC:
226e 226e <halt> ; Flow R
226f 226f seq_br_type a Unconditional Return; Flow R
2270 ; --------------------------------------------------------------------------------------
2270 ; Comes from:
2270 ; 1ee5 C True from color 0x1ee3
2270 ; 1eec C True from color 0x1ee3
2270 ; --------------------------------------------------------------------------------------
2270 BAD_LEX_VAL:
2270 2270 <halt> ; Flow R
2271 2271 seq_br_type a Unconditional Return; Flow R
2272 ; --------------------------------------------------------------------------------------
2272 ; Comes from:
2272 ; 1ee7 C True from color 0x1ee3
2272 ; --------------------------------------------------------------------------------------
2272 BAD_MACRO_PC_REF:
2272 2272 <halt> ; Flow R
2273 2273 seq_br_type a Unconditional Return; Flow R
2274 ; --------------------------------------------------------------------------------------
2274 ; Comes from:
2274 ; 1ee9 C True from color 0x1ee3
2274 ; --------------------------------------------------------------------------------------
2274 BAD_MACRO_PC_SEG:
2274 2274 <halt> ; Flow R
2275 2275 seq_br_type a Unconditional Return; Flow R
2276 ; --------------------------------------------------------------------------------------
2276 ; Comes from:
2276 ; 1f02 C True from color 0x1ee3
2276 ; 1f1f C True from color 0x1ee3
2276 ; --------------------------------------------------------------------------------------
2276 BAD_CODE_MUX:
2276 2276 <halt> ; Flow R
2277 2277 seq_br_type a Unconditional Return; Flow R
2278 ; --------------------------------------------------------------------------------------
2278 ; Comes from:
2278 ; 1f23 C True from color 0x1ee3
2278 ; --------------------------------------------------------------------------------------
2278 BAD_MACRO_PC_IND:
2278 2278 <halt> ; Flow R
2279 2279 seq_br_type a Unconditional Return; Flow R
227a ; --------------------------------------------------------------------------------------
227a ; Comes from:
227a ; 1f4e C True from color 0x1ee3
227a ; 1f52 C True from color 0x1ee3
227a ; 1f5a C True from color 0x1ee3
227a ; 1f61 C True from color 0x1ee3
227a ; --------------------------------------------------------------------------------------
227a BAD_MACRO_PC_ADD:
227a 227a <halt> ; Flow R
227b 227b seq_br_type a Unconditional Return; Flow R
227c ; --------------------------------------------------------------------------------------
227c ; Comes from:
227c ; 1ef7 C True from color 0x1ee3
227c ; 1eff C True from color 0x1ee3
227c ; 1f0c C True from color 0x1ee3
227c ; 1f0e C True from color 0x1ee3
227c ; 1f18 C True from color 0x1ee3
227c ; 1f1a C True from color 0x1ee3
227c ; --------------------------------------------------------------------------------------
227c BAD_RETURN_PC:
227c 227c <halt> ; Flow R
227d 227d seq_br_type a Unconditional Return; Flow R
227e ; --------------------------------------------------------------------------------------
227e ; Comes from:
227e ; 1eee C True from color 0x1ee3
227e ; --------------------------------------------------------------------------------------
227e BAD_RETURN_PC_REF:
227e 227e <halt> ; Flow R
227f 227f seq_br_type a Unconditional Return; Flow R
2280 ; --------------------------------------------------------------------------------------
2280 ; Comes from:
2280 ; 1ef0 C True from color 0x1ee3
2280 ; --------------------------------------------------------------------------------------
2280 BAD_RETURN_PC_SEG:
2280 2280 <halt> ; Flow R
2281 2281 seq_br_type a Unconditional Return; Flow R
2282 ; --------------------------------------------------------------------------------------
2282 ; Comes from:
2282 ; 1f03 C True from color 0x1ee3
2282 ; --------------------------------------------------------------------------------------
2282 BAD_RETURN_PC_LOAD:
2282 2282 <halt> ; Flow R
2283 2283 seq_br_type a Unconditional Return; Flow R
2284 ; --------------------------------------------------------------------------------------
2284 ; Comes from:
2284 ; 1f63 C True from color 0x1ee3
2284 ; 1f67 C True from color 0x1ee3
2284 ; 1f6b C True from color 0x1ee3
2284 ; 1f71 C True from color 0x1ee3
2284 ; 1f7a C True from color 0x1ee3
2284 ; 1f8e C True from color 0x1ee3
2284 ; 1f97 C True from color 0x1ee3
2284 ; --------------------------------------------------------------------------------------
2284 BAD_CONTROL_PRED:
2284 2284 <halt> ; Flow R
2285 2285 seq_br_type a Unconditional Return; Flow R
2286 ; --------------------------------------------------------------------------------------
2286 ; Comes from:
2286 ; 1f64 C True from color 0x1ee3
2286 ; 1f69 C True from color 0x1ee3
2286 ; 1f6c C True from color 0x1ee3
2286 ; 1f73 C True from color 0x1ee3
2286 ; 1f7d C True from color 0x1ee3
2286 ; 1f90 C True from color 0x1ee3
2286 ; 1f9a C True from color 0x1ee3
2286 ; --------------------------------------------------------------------------------------
2286 BAD_CONTROL_TOP:
2286 2286 <halt> ; Flow R
2287 2287 seq_br_type a Unconditional Return; Flow R
2288 ; --------------------------------------------------------------------------------------
2288 ; Comes from:
2288 ; 1f81 C True from color 0x1ee3
2288 ; --------------------------------------------------------------------------------------
2288 BAD_SEQUENCER_BUS:
2288 2288 <halt> ; Flow R
2289 2289 seq_br_type a Unconditional Return; Flow R
228a ; --------------------------------------------------------------------------------------
228a ; Comes from:
228a ; 1f83 C True from color 0x1ee3
228a ; 1f87 C True from color 0x1ee3
228a ; --------------------------------------------------------------------------------------
228a BAD2_CONTROL_PRED:
228a 228a <halt> ; Flow R
228b 228b seq_br_type a Unconditional Return; Flow R
228c ; --------------------------------------------------------------------------------------
228c ; Comes from:
228c ; 1f84 C True from color 0x1ee3
228c ; 1f89 C True from color 0x1ee3
228c ; --------------------------------------------------------------------------------------
228c BAD2_CONTROL_TOP:
228c 228c <halt> ; Flow R
228d 228d seq_br_type a Unconditional Return; Flow R
228e ; --------------------------------------------------------------------------------------
228e ; Comes from:
228e ; 1f9e C True from color 0x1ee3
228e ; 1f9f C True from color 0x1ee3
228e ; --------------------------------------------------------------------------------------
228e BAD_CONTROL_TOP_INC:
228e 228e <halt> ; Flow R
228f 228f seq_br_type a Unconditional Return; Flow R
2290 ; --------------------------------------------------------------------------------------
2290 ; Comes from:
2290 ; 1fa1 C True from color 0x1ee3
2290 ; --------------------------------------------------------------------------------------
2290 BAD_CONTROL_TOP_DEC:
2290 2290 <halt> ; Flow R
2291 2291 seq_br_type a Unconditional Return; Flow R
2292 ; --------------------------------------------------------------------------------------
2292 ; Comes from:
2292 ; 1fab C True from color 0x1ee3
2292 ; --------------------------------------------------------------------------------------
2292 BAD_RESOLVE:
2292 2292 <halt> ; Flow R
2293 2293 seq_br_type a Unconditional Return; Flow R
2294 VALIDATE_BAD:
2294 2294 <halt> ; Flow R
2295 2295 seq_br_type a Unconditional Return; Flow R
2296 ; --------------------------------------------------------------------------------------
2296 ; Comes from:
2296 ; 1fb7 C True from color 0x1ee3
2296 ; 1fbf C True from color 0x1ee3
2296 ; 1fc8 C True from color 0x1ee3
2296 ; 1fd0 C True from color 0x1ee3
2296 ; --------------------------------------------------------------------------------------
2296 BAD_RESOLVE2:
2296 2296 <halt> ; Flow R
2297 2297 seq_br_type a Unconditional Return; Flow R
2298 ; --------------------------------------------------------------------------------------
2298 ; Comes from:
2298 ; 1fd5 C True from color 0x1ee3
2298 ; 1fd9 C True from color 0x1ee3
2298 ; 1fde C True from color 0x1ee3
2298 ; 1fe7 C True from color 0x1ee3
2298 ; --------------------------------------------------------------------------------------
2298 BAD_RESOLVE_ADDRESS:
2298 2298 <halt> ; Flow R
2299 2299 seq_br_type a Unconditional Return; Flow R
229a ; --------------------------------------------------------------------------------------
229a ; Comes from:
229a ; 1fa9 C True from color 0x1ee3
229a ; 1fb5 C True from color 0x1ee3
229a ; --------------------------------------------------------------------------------------
229a VALIDATE_BAD2:
229a 229a <halt> ; Flow R
229b 229b seq_br_type a Unconditional Return; Flow R
229c ; --------------------------------------------------------------------------------------
229c ; Comes from:
229c ; 1fb0 C False from color 0x1ee3
229c ; --------------------------------------------------------------------------------------
229c BAD_INVALIDATE:
229c 229c <halt> ; Flow R
229d 229d seq_br_type a Unconditional Return; Flow R
229e ; --------------------------------------------------------------------------------------
229e ; Comes from:
229e ; 1f26 C True from color 0x1ee3
229e ; 1f29 C True from color 0x1ee3
229e ; 1f2c C True from color 0x1ee3
229e ; 1f2f C True from color 0x1ee3
229e ; 1f34 C True from color 0x1ee3
229e ; 1f3a C True from color 0x1ee3
229e ; 1f41 C True from color 0x1ee3
229e ; 1f48 C True from color 0x1ee3
229e ; --------------------------------------------------------------------------------------
229e BAD_CURRENT_INSTR:
229e 229e <halt> ; Flow R
229f 229f seq_br_type a Unconditional Return; Flow R
22a0 BAD_CURRENT_INSTR1:
22a0 22a0 <halt> ; Flow R
22a1 22a1 seq_br_type a Unconditional Return; Flow R
22a2 ; --------------------------------------------------------------------------------------
22a2 ; Comes from:
22a2 ; 2009 C True from color 0x1ee3
22a2 ; 200b C True from color 0x1ee3
22a2 ; 2019 C True from color 0x1ee3
22a2 ; 201b C True from color 0x1ee3
22a2 ; --------------------------------------------------------------------------------------
22a2 BAD_IBUFFER:
22a2 22a2 <halt> ; Flow R
22a3 22a3 seq_br_type a Unconditional Return; Flow R
22a4 BAD_IBUFFER2:
22a4 22a4 <halt> ; Flow R
22a5 22a5 seq_br_type a Unconditional Return; Flow R
22a6 BAD_IBUFFER3:
22a6 22a6 <halt> ; Flow R
22a7 22a7 seq_br_type a Unconditional Return; Flow R
22a8 ; --------------------------------------------------------------------------------------
22a8 ; Comes from:
22a8 ; 1ff0 C True from color 0x1ee3
22a8 ; 1ffc C True from color 0x1ee3
22a8 ; --------------------------------------------------------------------------------------
22a8 BAD_SAVE_OFFSET:
22a8 22a8 <halt> ; Flow R
22a9 22a9 seq_br_type a Unconditional Return; Flow R
22aa ; --------------------------------------------------------------------------------------
22aa ; Comes from:
22aa ; 1ff2 C True from color 0x1ee3
22aa ; 1fff C True from color 0x1ee3
22aa ; --------------------------------------------------------------------------------------
22aa BAD_CURRENT_NAME:
22aa 22aa <halt> ; Flow R
22ab 22ab seq_br_type a Unconditional Return; Flow R
22ac BAD2_SAVE_OFFSET:
22ac 22ac <halt> ; Flow R
22ad 22ad seq_br_type a Unconditional Return; Flow R
22ae BAD2_CURRENT_NAME:
22ae 22ae <halt> ; Flow R
22af 22af seq_br_type a Unconditional Return; Flow R
22b0 ; --------------------------------------------------------------------------------------
22b0 ; Comes from:
22b0 ; 1fa2 C True from color 0x1ee3
22b0 ; --------------------------------------------------------------------------------------
22b0 BAD_NUMBER_VALID:
22b0 22b0 <halt> ; Flow R
22b1 22b1 seq_br_type a Unconditional Return; Flow R
22b2 ; --------------------------------------------------------------------------------------
22b2 ; Comes from:
22b2 ; 1fa3 C True from color 0x1ee3
22b2 ; --------------------------------------------------------------------------------------
22b2 BAD_NUMBER_VALID2:
22b2 22b2 <halt> ; Flow R
22b3 22b3 seq_br_type a Unconditional Return; Flow R
22b4 ; --------------------------------------------------------------------------------------
22b4 ; Comes from:
22b4 ; 1fa4 C True from color 0x1ee3
22b4 ; --------------------------------------------------------------------------------------
22b4 BAD_NUMBER_VALID3:
22b4 22b4 <halt> ; Flow R
22b5 22b5 seq_br_type a Unconditional Return; Flow R
22b6 ; --------------------------------------------------------------------------------------
22b6 ; Comes from:
22b6 ; 1fa5 C True from color 0x1ee3
22b6 ; --------------------------------------------------------------------------------------
22b6 BAD_NUMBER_VALID4:
22b6 22b6 <halt> ; Flow R
22b7 22b7 seq_br_type a Unconditional Return; Flow R
22b8 ; --------------------------------------------------------------------------------------
22b8 ; Comes from:
22b8 ; 2029 C True from color 0x1ee3
22b8 ; --------------------------------------------------------------------------------------
22b8 BAD_DISPATCH_ZERO:
22b8 22b8 <halt> ; Flow R
22b9 22b9 seq_br_type a Unconditional Return; Flow R
22ba ; --------------------------------------------------------------------------------------
22ba ; Comes from:
22ba ; 202d C True from color 0x1ee3
22ba ; --------------------------------------------------------------------------------------
22ba BAD_DISPATCH_ONE:
22ba 22ba <halt> ; Flow R
22bb 22bb seq_br_type a Unconditional Return; Flow R
22bc ; --------------------------------------------------------------------------------------
22bc ; Comes from:
22bc ; 0145 C True from color ML_IBUF_empty
22bc ; --------------------------------------------------------------------------------------
22bc PC_UPDATE_ERROR:
22bc 22bc <halt> ; Flow R
22bd 22bd seq_br_type a Unconditional Return; Flow R
22be ; --------------------------------------------------------------------------------------
22be ; Comes from:
22be ; 203e C False from color 0x1ee3
22be ; 2042 C False from color 0x1ee3
22be ; 2046 C False from color 0x1ee3
22be ; 2050 C True from color MACRO_Illegal_-
22be ; --------------------------------------------------------------------------------------
22be IBUFF_FILL_ERROR:
22be 22be <halt> ; Flow R
22bf 22bf seq_br_type a Unconditional Return; Flow R
22c0 ; --------------------------------------------------------------------------------------
22c0 ; Comes from:
22c0 ; 204e C False from color MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object
22c0 ; --------------------------------------------------------------------------------------
22c0 DISPATCH_INDEX_ERROR:
22c0 22c0 <halt> ; Flow R
22c1 22c1 seq_br_type a Unconditional Return; Flow R
22c2 ; --------------------------------------------------------------------------------------
22c2 ; Comes from:
22c2 ; 0141 C True from color ML_IBUF_empty
22c2 ; --------------------------------------------------------------------------------------
22c2 IFILL_ERROR:
22c2 22c2 <halt> ; Flow R
22c3 22c3 seq_br_type a Unconditional Return; Flow R
22c4 ; --------------------------------------------------------------------------------------
22c4 ; Comes from:
22c4 ; 2032 C True from color 0x1ee3
22c4 ; --------------------------------------------------------------------------------------
22c4 BAD_CONDITIONA_LOAD_IBUFF:
22c4 22c4 <halt> ; Flow R
22c5 22c5 seq_br_type a Unconditional Return; Flow R
22c6 ; --------------------------------------------------------------------------------------
22c6 ; Comes from:
22c6 ; 2035 C True from color 0x1ee3
22c6 ; --------------------------------------------------------------------------------------
22c6 BAD_CONDITIONA_LOAD_IBUFF2:
22c6 22c6 <halt> ; Flow R
22c7 22c7 seq_br_type a Unconditional Return; Flow R
22c8 ; --------------------------------------------------------------------------------------
22c8 ; Comes from:
22c8 ; 205d C True from color 0x1ee3
22c8 ; --------------------------------------------------------------------------------------
22c8 TOS_VALIDATE_FAILED:
22c8 22c8 <halt> ; Flow R
22c9 22c9 seq_br_type a Unconditional Return; Flow R
22ca ; --------------------------------------------------------------------------------------
22ca ; Comes from:
22ca ; 205e C True from color 0x1ee3
22ca ; --------------------------------------------------------------------------------------
22ca TOS_LATCH_DIDNT_HOLD:
22ca 22ca <halt> ; Flow R
22cb 22cb seq_br_type a Unconditional Return; Flow R
22cc ; --------------------------------------------------------------------------------------
22cc ; Comes from:
22cc ; 2064 C False from color MACRO_Store_llvl,ldelta
22cc ; --------------------------------------------------------------------------------------
22cc DISPATCH_DIDNT_INVALIDATE:
22cc 22cc ioc_random 14 clear cpu running; Flow R
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
seq_random 01 Halt+?
22cd 22cd seq_br_type a Unconditional Return; Flow R
22ce ; --------------------------------------------------------------------------------------
22ce ; Comes from:
22ce ; 206c C False from color MACRO_Store_llvl,ldelta
22ce ; --------------------------------------------------------------------------------------
22ce DIDNT_TAKE_MICRO_EVENT:
22ce 22ce <halt> ; Flow R
22cf 22cf seq_br_type a Unconditional Return; Flow R
22d0 ; --------------------------------------------------------------------------------------
22d0 ; Comes from:
22d0 ; 206f C True from color MACRO_Store_llvl,ldelta
22d0 ; --------------------------------------------------------------------------------------
22d0 FIELD_NUMBER_TEST_FAILED:
22d0 22d0 <halt> ; Flow R
22d1 22d1 seq_br_type a Unconditional Return; Flow R
22d2 ; --------------------------------------------------------------------------------------
22d2 ; Comes from:
22d2 ; 0178 C True from color ML_CSA_overflow
22d2 ; 2078 C True from color MACRO_Halt_InMicrocode
22d2 ; 2079 C True from color MACRO_Halt_InMicrocode
22d2 ; 207e C True from color MACRO_207e_QQUnknown_InMicrocode
22d2 ; 207f C True from color MACRO_207e_QQUnknown_InMicrocode
22d2 ; 2084 C True from color MACRO_2084_QQUnknown_InMicrocode
22d2 ; 2085 C True from color MACRO_2084_QQUnknown_InMicrocode
22d2 ; 208a C True from color MACRO_208a_QQUnknown_InMicrocode
22d2 ; 208b C True from color MACRO_208a_QQUnknown_InMicrocode
22d2 ; 2090 C True from color MACRO_2090_QQUnknown_InMicrocode
22d2 ; 2091 C True from color MACRO_2090_QQUnknown_InMicrocode
22d2 ; 2096 C True from color MACRO_2096_QQUnknown_InMicrocode
22d2 ; 2097 C True from color MACRO_2096_QQUnknown_InMicrocode
22d2 ; 209c C True from color MACRO_209c_QQUnknown_InMicrocode
22d2 ; 209d C True from color MACRO_209c_QQUnknown_InMicrocode
22d2 ; 20a2 C True from color MACRO_20a2_QQUnknown_InMicrocode
22d2 ; 20a3 C True from color MACRO_20a2_QQUnknown_InMicrocode
22d2 ; --------------------------------------------------------------------------------------
22d2 NVE_ERROR:
22d2 22d2 <halt> ; Flow R
22d3 22d3 seq_br_type a Unconditional Return; Flow R
22d4 ; --------------------------------------------------------------------------------------
22d4 ; Comes from:
22d4 ; 0170 C True from color ML_CSA_Underflow
22d4 ; 20b2 C True from color MACRO_Illegal_-
22d4 ; 20b3 C True from color MACRO_Illegal_-
22d4 ; 20b8 C True from color MACRO_Illegal_-
22d4 ; 20b9 C True from color MACRO_Illegal_-
22d4 ; 20be C True from color MACRO_Illegal_-
22d4 ; 20bf C True from color MACRO_Illegal_-
22d4 ; 20c4 C True from color MACRO_Illegal_-
22d4 ; 20c5 C True from color MACRO_Illegal_-
22d4 ; --------------------------------------------------------------------------------------
22d4 NFREE_ERROR:
22d4 22d4 <halt> ; Flow R
22d5 22d5 seq_br_type a Unconditional Return; Flow R
22d6 ; --------------------------------------------------------------------------------------
22d6 ; Comes from:
22d6 ; 0160 C True from color ML_Resolve Reference
22d6 ; 20ce C True from color MACRO_Call_llvl,ldelta
22d6 ; 20d2 C True from color MACRO_Call_llvl,ldelta
22d6 ; 20d6 C True from color MACRO_Call_llvl,ldelta
22d6 ; 20da C True from color MACRO_Call_llvl,ldelta
22d6 ; --------------------------------------------------------------------------------------
22d6 RES_REF_ERROR:
22d6 22d6 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
22d7 RES_REF_ERROR_1:
22d7 22d7 <halt> ; Flow R
22d8 22d8 seq_br_type a Unconditional Return; Flow R
22d9 ; --------------------------------------------------------------------------------------
22d9 ; Comes from:
22d9 ; 0158 C True from color ML_TOS_INVLD
22d9 ; 20e2 C True from color MACRO_Reference_zdelta
22d9 ; 20e6 C True from color MACRO_Store_Unchecked_llvl,ldelta
22d9 ; 20ea C True from color MACRO_Store_Unchecked_llvl,ldelta
22d9 ; 20ee C True from color MACRO_Store_Unchecked_llvl,ldelta
22d9 ; --------------------------------------------------------------------------------------
22d9 TOS_OP_ERROR:
22d9 22d9 seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
22da TOS_OP_ERROR_ONE:
22da 22da <halt> ; Flow R
22db 22db seq_br_type a Unconditional Return; Flow R
22dc ; --------------------------------------------------------------------------------------
22dc ; Comes from:
22dc ; 1e03 C from color DIAGNOSTIC_START
22dc ; 1e05 C True from color DIAGNOSTIC_START
22dc ; 1e08 C from color DIAGNOSTIC_START
22dc ; 1e0a C False from color DIAGNOSTIC_START
22dc ; 1e0e C True from color DIAGNOSTIC_START
22dc ; 1e10 C True from color DIAGNOSTIC_START
22dc ; 1e12 C True from color DIAGNOSTIC_START
22dc ; 1e15 C from color DIAGNOSTIC_START
22dc ; 1e17 C False from color DIAGNOSTIC_START
22dc ; 1e1b C True from color DIAGNOSTIC_START
22dc ; 1e1e C from color DIAGNOSTIC_START
22dc ; 1e21 C False from color DIAGNOSTIC_START
22dc ; 1e25 C True from color DIAGNOSTIC_START
22dc ; 1e28 C from color DIAGNOSTIC_START
22dc ; 1e2b C False from color DIAGNOSTIC_START
22dc ; 1e2f C True from color DIAGNOSTIC_START
22dc ; 1e32 C from color DIAGNOSTIC_START
22dc ; 1e35 C False from color DIAGNOSTIC_START
22dc ; 1e38 C from color DIAGNOSTIC_START
22dc ; 1e39 C True from color DIAGNOSTIC_START
22dc ; 1e3c C from color DIAGNOSTIC_START
22dc ; 1e3d C from color DIAGNOSTIC_START
22dc ; 1e3f C False from color DIAGNOSTIC_START
22dc ; 1e43 C True from color DIAGNOSTIC_START
22dc ; 1e46 C from color DIAGNOSTIC_START
22dc ; 1e49 C False from color DIAGNOSTIC_START
22dc ; 1e4d C True from color DIAGNOSTIC_START
22dc ; 1e50 C from color DIAGNOSTIC_START
22dc ; 1e54 C False from color DIAGNOSTIC_START
22dc ; --------------------------------------------------------------------------------------
22dc MICRO_STACK_ERROR:
22dc 22dc <halt> ; Flow R
22dd 22dd seq_br_type a Unconditional Return; Flow R
22de 22de <halt> ; Flow R
22df 22df <halt> ; Flow R
22e0 22e0 <halt> ; Flow R
22e1 22e1 <halt> ; Flow R
22e2 22e2 <halt> ; Flow R
22e3 22e3 <halt> ; Flow R
22e4 22e4 <halt> ; Flow R
22e5 22e5 <halt> ; Flow R
22e6 22e6 <halt> ; Flow R
22e7 22e7 <halt> ; Flow R
22e8 22e8 <halt> ; Flow R
22e9 22e9 <halt> ; Flow R
22ea 22ea <halt> ; Flow R
22eb 22eb <halt> ; Flow R
22ec 22ec <halt> ; Flow R
22ed 22ed <halt> ; Flow R
22ee 22ee <halt> ; Flow R
22ef 22ef <halt> ; Flow R
22f0 22f0 <halt> ; Flow R
22f1 22f1 <halt> ; Flow R
22f2 22f2 <halt> ; Flow R
22f3 22f3 <halt> ; Flow R
22f4 22f4 <halt> ; Flow R
22f5 22f5 <halt> ; Flow R
22f6 22f6 <halt> ; Flow R
22f7 22f7 <halt> ; Flow R
22f8 22f8 <halt> ; Flow R
22f9 22f9 <halt> ; Flow R
22fa 22fa <halt> ; Flow R
22fb 22fb <halt> ; Flow R
22fc 22fc <halt> ; Flow R
22fd 22fd <halt> ; Flow R
22fe 22fe <halt> ; Flow R
22ff 22ff <halt> ; Flow R
2300 2300 <halt> ; Flow R
2301 2301 <halt> ; Flow R
2302 2302 <halt> ; Flow R
2303 2303 <halt> ; Flow R
2304 2304 <halt> ; Flow R
2305 2305 <halt> ; Flow R
2306 2306 <halt> ; Flow R
2307 2307 <halt> ; Flow R
2308 2308 <halt> ; Flow R
2309 2309 <halt> ; Flow R
230a 230a <halt> ; Flow R
230b 230b <halt> ; Flow R
230c 230c <halt> ; Flow R
230d 230d <halt> ; Flow R
230e 230e <halt> ; Flow R
230f 230f <halt> ; Flow R
2310 2310 <halt> ; Flow R
2311 2311 <halt> ; Flow R
2312 2312 <halt> ; Flow R
2313 2313 <halt> ; Flow R
2314 2314 <halt> ; Flow R
2315 2315 <halt> ; Flow R
2316 2316 <halt> ; Flow R
2317 2317 <halt> ; Flow R
2318 2318 <halt> ; Flow R
2319 2319 <halt> ; Flow R
231a 231a <halt> ; Flow R
231b 231b <halt> ; Flow R
231c 231c <halt> ; Flow R
231d 231d <halt> ; Flow R
231e 231e <halt> ; Flow R
231f 231f <halt> ; Flow R
2320 2320 <halt> ; Flow R
2321 2321 <halt> ; Flow R
2322 2322 <halt> ; Flow R
2323 2323 <halt> ; Flow R
2324 2324 <halt> ; Flow R
2325 2325 <halt> ; Flow R
2326 2326 <halt> ; Flow R
2327 2327 <halt> ; Flow R
2328 2328 <halt> ; Flow R
2329 2329 <halt> ; Flow R
232a 232a <halt> ; Flow R
232b 232b <halt> ; Flow R
232c 232c <halt> ; Flow R
232d 232d <halt> ; Flow R
232e 232e <halt> ; Flow R
232f 232f <halt> ; Flow R
2330 2330 <halt> ; Flow R
2331 2331 <halt> ; Flow R
2332 2332 <halt> ; Flow R
2333 2333 <halt> ; Flow R
2334 2334 <halt> ; Flow R
2335 2335 <halt> ; Flow R
2336 2336 <halt> ; Flow R
2337 2337 <halt> ; Flow R
2338 2338 <halt> ; Flow R
2339 2339 <halt> ; Flow R
233a 233a <halt> ; Flow R
233b 233b <halt> ; Flow R
233c 233c <halt> ; Flow R
233d 233d <halt> ; Flow R
233e 233e <halt> ; Flow R
233f 233f <halt> ; Flow R
2340 2340 <halt> ; Flow R
2341 2341 <halt> ; Flow R
2342 2342 <halt> ; Flow R
2343 2343 <halt> ; Flow R
2344 2344 <halt> ; Flow R
2345 2345 <halt> ; Flow R
2346 2346 <halt> ; Flow R
2347 2347 <halt> ; Flow R
2348 2348 <halt> ; Flow R
2349 2349 <halt> ; Flow R
234a 234a <halt> ; Flow R
234b 234b <halt> ; Flow R
234c 234c <halt> ; Flow R
234d 234d <halt> ; Flow R
234e 234e <halt> ; Flow R
234f 234f <halt> ; Flow R
2350 2350 <halt> ; Flow R
2351 2351 <halt> ; Flow R
2352 2352 <halt> ; Flow R
2353 2353 <halt> ; Flow R
2354 2354 <halt> ; Flow R
2355 2355 <halt> ; Flow R
2356 2356 <halt> ; Flow R
2357 2357 <halt> ; Flow R
2358 2358 <halt> ; Flow R
2359 2359 <halt> ; Flow R
235a 235a <halt> ; Flow R
235b 235b <halt> ; Flow R
235c 235c <halt> ; Flow R
235d 235d <halt> ; Flow R
235e 235e <halt> ; Flow R
235f 235f <halt> ; Flow R
2360 2360 <halt> ; Flow R
2361 2361 <halt> ; Flow R
2362 2362 <halt> ; Flow R
2363 2363 <halt> ; Flow R
2364 2364 <halt> ; Flow R
2365 2365 <halt> ; Flow R
2366 2366 <halt> ; Flow R
2367 2367 <halt> ; Flow R
2368 2368 <halt> ; Flow R
2369 2369 <halt> ; Flow R
236a 236a <halt> ; Flow R
236b 236b <halt> ; Flow R
236c 236c <halt> ; Flow R
236d 236d <halt> ; Flow R
236e 236e <halt> ; Flow R
236f 236f <halt> ; Flow R
2370 2370 <halt> ; Flow R
2371 2371 <halt> ; Flow R
2372 2372 <halt> ; Flow R
2373 2373 <halt> ; Flow R
2374 2374 <halt> ; Flow R
2375 2375 <halt> ; Flow R
2376 2376 <halt> ; Flow R
2377 2377 <halt> ; Flow R
2378 2378 <halt> ; Flow R
2379 2379 <halt> ; Flow R
237a 237a <halt> ; Flow R
237b 237b <halt> ; Flow R
237c 237c <halt> ; Flow R
237d 237d <halt> ; Flow R
237e 237e <halt> ; Flow R
237f 237f <halt> ; Flow R
2380 2380 <halt> ; Flow R
2381 2381 <halt> ; Flow R
2382 2382 <halt> ; Flow R
2383 2383 <halt> ; Flow R
2384 2384 <halt> ; Flow R
2385 2385 <halt> ; Flow R
2386 2386 <halt> ; Flow R
2387 2387 <halt> ; Flow R
2388 2388 <halt> ; Flow R
2389 2389 <halt> ; Flow R
238a 238a <halt> ; Flow R
238b 238b <halt> ; Flow R
238c 238c <halt> ; Flow R
238d 238d <halt> ; Flow R
238e 238e <halt> ; Flow R
238f 238f <halt> ; Flow R
2390 2390 <halt> ; Flow R
2391 2391 <halt> ; Flow R
2392 2392 <halt> ; Flow R
2393 2393 <halt> ; Flow R
2394 2394 <halt> ; Flow R
2395 2395 <halt> ; Flow R
2396 2396 <halt> ; Flow R
2397 2397 <halt> ; Flow R
2398 2398 <halt> ; Flow R
2399 2399 <halt> ; Flow R
239a 239a <halt> ; Flow R
239b 239b <halt> ; Flow R
239c 239c <halt> ; Flow R
239d 239d <halt> ; Flow R
239e 239e <halt> ; Flow R
239f 239f <halt> ; Flow R
23a0 23a0 <halt> ; Flow R
23a1 23a1 <halt> ; Flow R
23a2 23a2 <halt> ; Flow R
23a3 23a3 <halt> ; Flow R
23a4 23a4 <halt> ; Flow R
23a5 23a5 <halt> ; Flow R
23a6 23a6 <halt> ; Flow R
23a7 23a7 <halt> ; Flow R
23a8 23a8 <halt> ; Flow R
23a9 23a9 <halt> ; Flow R
23aa 23aa <halt> ; Flow R
23ab 23ab <halt> ; Flow R
23ac 23ac <halt> ; Flow R
23ad 23ad <halt> ; Flow R
23ae 23ae <halt> ; Flow R
23af 23af <halt> ; Flow R
23b0 23b0 <halt> ; Flow R
23b1 23b1 <halt> ; Flow R
23b2 23b2 <halt> ; Flow R
23b3 23b3 <halt> ; Flow R
23b4 23b4 <halt> ; Flow R
23b5 23b5 <halt> ; Flow R
23b6 23b6 <halt> ; Flow R
23b7 23b7 <halt> ; Flow R
23b8 23b8 <halt> ; Flow R
23b9 23b9 <halt> ; Flow R
23ba 23ba <halt> ; Flow R
23bb 23bb <halt> ; Flow R
23bc 23bc <halt> ; Flow R
23bd 23bd <halt> ; Flow R
23be 23be <halt> ; Flow R
23bf 23bf <halt> ; Flow R
23c0 23c0 <halt> ; Flow R
23c1 23c1 <halt> ; Flow R
23c2 23c2 <halt> ; Flow R
23c3 23c3 <halt> ; Flow R
23c4 23c4 <halt> ; Flow R
23c5 23c5 <halt> ; Flow R
23c6 23c6 <halt> ; Flow R
23c7 23c7 <halt> ; Flow R
23c8 23c8 <halt> ; Flow R
23c9 23c9 <halt> ; Flow R
23ca 23ca <halt> ; Flow R
23cb 23cb <halt> ; Flow R
23cc 23cc <halt> ; Flow R
23cd 23cd <halt> ; Flow R
23ce 23ce <halt> ; Flow R
23cf 23cf <halt> ; Flow R
23d0 23d0 <halt> ; Flow R
23d1 23d1 <halt> ; Flow R
23d2 23d2 <halt> ; Flow R
23d3 23d3 <halt> ; Flow R
23d4 23d4 <halt> ; Flow R
23d5 23d5 <halt> ; Flow R
23d6 23d6 <halt> ; Flow R
23d7 23d7 <halt> ; Flow R
23d8 23d8 <halt> ; Flow R
23d9 23d9 <halt> ; Flow R
23da 23da <halt> ; Flow R
23db 23db <halt> ; Flow R
23dc 23dc <halt> ; Flow R
23dd 23dd <halt> ; Flow R
23de 23de <halt> ; Flow R
23df 23df <halt> ; Flow R
23e0 23e0 <halt> ; Flow R
23e1 23e1 <halt> ; Flow R
23e2 23e2 <halt> ; Flow R
23e3 23e3 <halt> ; Flow R
23e4 23e4 <halt> ; Flow R
23e5 23e5 <halt> ; Flow R
23e6 23e6 <halt> ; Flow R
23e7 23e7 <halt> ; Flow R
23e8 23e8 <halt> ; Flow R
23e9 23e9 <halt> ; Flow R
23ea 23ea <halt> ; Flow R
23eb 23eb <halt> ; Flow R
23ec 23ec <halt> ; Flow R
23ed 23ed <halt> ; Flow R
23ee 23ee <halt> ; Flow R
23ef 23ef <halt> ; Flow R
23f0 23f0 <halt> ; Flow R
23f1 23f1 <halt> ; Flow R
23f2 23f2 <halt> ; Flow R
23f3 23f3 <halt> ; Flow R
23f4 23f4 <halt> ; Flow R
23f5 23f5 <halt> ; Flow R
23f6 23f6 <halt> ; Flow R
23f7 23f7 <halt> ; Flow R
23f8 23f8 <halt> ; Flow R
23f9 23f9 <halt> ; Flow R
23fa 23fa <halt> ; Flow R
23fb 23fb <halt> ; Flow R
23fc 23fc <halt> ; Flow R
23fd 23fd <halt> ; Flow R
23fe 23fe <halt> ; Flow R
23ff 23ff <halt> ; Flow R
2400 ; --------------------------------------------------------------------------------------
2400 ; 2400 - 2734 MEM_TEST
2400 ; Comes from:
2400 ; 031a C from color DIAGNOSTIC_START
2400 ; --------------------------------------------------------------------------------------
2400 2400 fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 22 TR10:02
typ_frame 10
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_a_adr 22 VR10:02
val_alu_func 0 PASS_A
val_frame 10
2401 2401 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
2402 2402 seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2403 2403 seq_en_micro 0
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2404 2404 fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 5c
fiu_rdata_src 0 rotator
fiu_tivi_src 3 tar_frame
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
2405 2405 seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 7 INC_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2406 2406 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2407 2407 seq_en_micro 0
2408 2408 seq_br_type 0 Branch False; Flow J cc=False 0x240a
seq_branch_adr 240a 0x240a
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2409 2409 seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1b A_OR_B
typ_b_adr 30 TR05:10
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
240a 240a seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
240b 240b seq_br_type 1 Branch True; Flow J cc=True 0x2406
seq_branch_adr 2406 0x2406
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
240c 240c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
240d 240d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
240e 240e fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 2 typ
seq_en_micro 0
typ_a_adr 05 GP05
240f 240f fiu_len_fill_lit 43 zero-fill 0x3
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
2410 2410 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2412
seq_br_type 1 Branch True
seq_branch_adr 2412 0x2412
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2411 2411 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2412 2412 fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 04
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
2413 2413 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2415
seq_br_type 1 Branch True
seq_branch_adr 2415 0x2415
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2414 2414 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2415 2415 fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 08
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
2416 2416 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2418
seq_br_type 1 Branch True
seq_branch_adr 2418 0x2418
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2417 2417 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2418 2418 fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 0c
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 3e GP01
val_c_source 0 FIU_BUS
2419 2419 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x241b
seq_br_type 1 Branch True
seq_branch_adr 241b 0x241b
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
241a 241a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2727
seq_br_type 5 Call True
seq_branch_adr 2727 INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
241b 241b seq_en_micro 0
241c 241c fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
seq_en_micro 0
typ_a_adr 20 TR04:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 4
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
241d 241d fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2729
fiu_oreg_src 0 rotator output
fiu_tivi_src c mar_0xc
ioc_adrbs 2 typ
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 10 NOT_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
241e 241e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
241f 241f fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 45 Load_current_name+?
typ_b_adr 03 GP03
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 0 PASS_A
2420 2420 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_fiubs 2 typ
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_random 0f Load_control_top+?
typ_a_adr 03 GP03
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2421 2421 fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 10 NOT_A
2422 2422 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_adrbs 3 seq
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_int_reads 6 CONTROL TOP
seq_random 13 ?
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 03 GP03
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2423 2423 fiu_tivi_src c mar_0xc
ioc_fiubs 2 typ
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
seq_random 0f Load_control_top+?
typ_a_adr 04 GP04
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2424 2424 fiu_len_fill_reg_ctl 2 ; Flow C cc=True 0x2729
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 45 Load_current_name+?
typ_alu_func 1a PASS_B
typ_b_adr 04 GP04
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_a_adr 33 VR16:13
val_alu_func 1e A_AND_B
val_b_adr 02 GP02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2425 2425 fiu_tivi_src c mar_0xc
ioc_adrbs 3 seq
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
seq_int_reads 6 CONTROL TOP
seq_random 13 ?
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
2426 2426 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 35 TR10:15
typ_alu_func 1e A_AND_B
typ_b_adr 02 GP02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 03 GP03
val_alu_func 16 A_XNOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2427 2427 fiu_len_fill_reg_ctl 2 ; Flow C cc=True 0x2729
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_a_adr 33 VR16:13
val_alu_func 1e A_AND_B
val_b_adr 02 GP02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2428 2428 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2429 2429 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2729
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 35 TR10:15
typ_alu_func 1e A_AND_B
typ_b_adr 02 GP02
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
242a 242a fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x241d
fiu_oreg_src 0 rotator output
ioc_adrbs 2 typ
seq_br_type 1 Branch True
seq_branch_adr 241d 0x241d
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 0 ALU << 1
242b 242b fiu_len_fill_reg_ctl 2
fiu_load_oreg 1 hold_oreg
fiu_oreg_src 0 rotator output
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 22 TR10:02
typ_frame 10
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
242c 242c fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
typ_a_adr 36 TR10:16
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
242d 242d fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
242e 242e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
242f 242f fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_alu_func 13 ONES
2430 2430 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2431 2431 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
2432 2432 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2433 2433 fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl f LOAD_MAR_RESERVED
2434 2434 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2435 2435 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2436 2436 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2437 2437 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
2438 2438 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2439 2439 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
243a 243a fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
243b 243b fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
243c 243c fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
243d 243d seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
243e 243e fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
243f 243f fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2440 2440 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
2441 2441 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2442 2442 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2443 2443 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2444 2444 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2445 2445 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2446 2446 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2447 2447 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
2448 2448 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2449 2449 fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 13 ONES
244a 244a fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
244b 244b fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
244c 244c fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
244d 244d fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl e LOAD_MAR_CONTROL
244e 244e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
244f 244f fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2450 2450 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2451 2451 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
2452 2452 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2453 2453 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2454 2454 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2455 2455 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2456 2456 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2457 2457 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
2458 2458 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2459 2459 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
245a 245a fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
245b 245b fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
245c 245c fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
245d 245d fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
245e 245e fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
245f 245f fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2460 2460 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2461 2461 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl d LOAD_MAR_TYPE
2462 2462 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2463 2463 fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl d LOAD_MAR_TYPE
val_alu_func 13 ONES
2464 2464 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2465 2465 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl d LOAD_MAR_TYPE
2466 2466 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2467 2467 fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl d LOAD_MAR_TYPE
2468 2468 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2469 2469 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
246a 246a fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
246b 246b fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
246c 246c fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
246d 246d fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
246e 246e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
246f 246f fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2470 2470 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2471 2471 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
2472 2472 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2473 2473 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2474 2474 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
2475 2475 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2476 2476 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2477 2477 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2478 2478 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2479 2479 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
247a 247a seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
247b 247b fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl c LOAD_MAR_QUEUE
247c 247c fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
247d 247d fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl c LOAD_MAR_QUEUE
val_alu_func 13 ONES
247e 247e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
247f 247f fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl c LOAD_MAR_QUEUE
2480 2480 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2481 2481 fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl c LOAD_MAR_QUEUE
2482 2482 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2483 2483 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2484 2484 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2485 2485 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
2486 2486 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2487 2487 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
2488 2488 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2489 2489 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
248a 248a fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
248b 248b seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
248c 248c fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
248d 248d fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
248e 248e fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
248f 248f fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2490 2490 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2491 2491 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2492 2492 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
2493 2493 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
2494 2494 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2495 2495 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
2496 2496 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2497 2497 fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 13 ONES
2498 2498 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2499 2499 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
249a 249a fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
249b 249b fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl b LOAD_MAR_DATA
249c 249c fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
249d 249d fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
249e 249e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
249f 249f fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
24a0 24a0 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24a1 24a1 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24a2 24a2 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24a3 24a3 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24a4 24a4 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24a5 24a5 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
24a6 24a6 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24a7 24a7 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24a8 24a8 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
24a9 24a9 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24aa 24aa fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24ab 24ab fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24ac 24ac fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24ad 24ad fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2e VR10:0e
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24ae 24ae seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
24af 24af fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl a LOAD_MAR_IMPORT
24b0 24b0 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24b1 24b1 fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl a LOAD_MAR_IMPORT
val_alu_func 13 ONES
24b2 24b2 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24b3 24b3 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl a LOAD_MAR_IMPORT
24b4 24b4 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24b5 24b5 fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl a LOAD_MAR_IMPORT
24b6 24b6 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24b7 24b7 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24b8 24b8 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24b9 24b9 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
24ba 24ba fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24bb 24bb fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24bc 24bc fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24bd 24bd fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24be 24be fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24bf 24bf seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
24c0 24c0 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24c1 24c1 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24c2 24c2 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
24c3 24c3 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24c4 24c4 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24c5 24c5 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24c6 24c6 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24c7 24c7 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24c8 24c8 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
24c9 24c9 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl 9 LOAD_MAR_CODE
24ca 24ca fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24cb 24cb fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl 9 LOAD_MAR_CODE
val_alu_func 13 ONES
24cc 24cc fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24cd 24cd fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl 9 LOAD_MAR_CODE
24ce 24ce fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24cf 24cf fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl 9 LOAD_MAR_CODE
24d0 24d0 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24d1 24d1 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24d2 24d2 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24d3 24d3 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
24d4 24d4 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24d5 24d5 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24d6 24d6 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24d7 24d7 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24d8 24d8 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24d9 24d9 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
24da 24da fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24db 24db fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24dc 24dc fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
24dd 24dd fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24de 24de fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24df 24df fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24e0 24e0 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24e1 24e1 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24e2 24e2 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
24e3 24e3 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl 8 LOAD_MAR_SYSTEM
24e4 24e4 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24e5 24e5 fiu_load_oreg 1 hold_oreg
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl 8 LOAD_MAR_SYSTEM
val_alu_func 13 ONES
24e6 24e6 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24e7 24e7 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
ioc_adrbs 2 typ
seq_en_micro 0
typ_mar_cntl 8 LOAD_MAR_SYSTEM
24e8 24e8 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24e9 24e9 fiu_load_oreg 1 hold_oreg
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_mar_cntl 8 LOAD_MAR_SYSTEM
24ea 24ea fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24eb 24eb fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24ec 24ec fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24ed 24ed fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
val_alu_func 13 ONES
24ee 24ee fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24ef 24ef fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24f0 24f0 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24f1 24f1 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 03 GP03
typ_mar_cntl 5 RESTORE_MAR_REFRESH
24f2 24f2 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24f3 24f3 seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_b_adr 20 TR11:00
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 11
typ_rand 5 CHECK_CLASS_B_LIT
24f4 24f4 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24f5 24f5 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24f6 24f6 fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
val_alu_func 13 ONES
24f7 24f7 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24f8 24f8 fiu_load_oreg 1 hold_oreg
fiu_offs_lit 7f
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24f9 24f9 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 2d VR10:0d
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
24fa 24fa fiu_load_oreg 1 hold_oreg
fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_b_adr 04 GP04
typ_mar_cntl 4 RESTORE_MAR
24fb 24fb fiu_tivi_src c mar_0xc; Flow C cc=True 0x2729
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2729 MAR_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 33 VR16:13
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 16
24fc 24fc seq_br_type 3 Unconditional Branch; Flow J 0x258a
seq_branch_adr 258a 0x258a
seq_en_micro 0
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
24fd ; --------------------------------------------------------------------------------------
24fd ; Comes from:
24fd ; 256a C from color 0x2564
24fd ; 256c C from color 0x2564
24fd ; 256e C from color 0x2564
24fd ; 2572 C from color 0x2564
24fd ; 257c C from color 0x2564
24fd ; --------------------------------------------------------------------------------------
24fd 24fd fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
ioc_load_wdr 0
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
24fe 24fe fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 06 GP06
24ff 24ff seq_en_micro 0
2500 2500 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x24ff
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 24ff 0x24ff
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2501 2501 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
2502 2502 seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x24fe
seq_br_type 9 Return False
seq_branch_adr 24fe 0x24fe
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR05:05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
2503 ; --------------------------------------------------------------------------------------
2503 ; Comes from:
2503 ; 256b C from color 0x2564
2503 ; 256d C from color 0x2564
2503 ; 256f C from color 0x2564
2503 ; 257b C from color 0x2564
2503 ; 2585 C from color 0x2564
2503 ; --------------------------------------------------------------------------------------
2503 2503 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2504 2504 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2505 2505 fiu_mem_start 15 setup_tag_read; Flow C cc=True 0x272d
ioc_tvbs 1 typ+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2506 2506 fiu_load_var 1 hold_var; Flow J cc=True 0x2505
fiu_mem_start f start_physical_tag_rd
fiu_tivi_src 1 tar_val
ioc_adrbs 1 val
ioc_tvbs 8 typ+mem
seq_br_type 1 Branch True
seq_branch_adr 2505 0x2505
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2507 2507 fiu_mem_start 15 setup_tag_read; Flow C cc=True 0x272d
ioc_tvbs 1 typ+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2508 2508 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
2509 2509 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2504
seq_br_type 1 Branch True
seq_branch_adr 2504 0x2504
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR05:05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
250a 250a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x272d
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
250b 250b seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
250c ; --------------------------------------------------------------------------------------
250c ; Comes from:
250c ; 2570 C from color 0x2564
250c ; 2586 C from color 0x2564
250c ; --------------------------------------------------------------------------------------
250c 250c fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
250d 250d fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_alu_func 1a PASS_B
val_b_adr 06 GP06
250e 250e ioc_load_wdr 0
seq_en_micro 0
val_b_adr 06 GP06
250f 250f fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x250e
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 250e 0x250e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2510 2510 fiu_mem_start 10 start_physical_tag_wr
ioc_load_wdr 0
seq_en_micro 0
val_a_adr 21 VR18:01
val_alu_func 1e A_AND_B
val_b_adr 06 GP06
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
2511 2511 seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x250d
seq_br_type 9 Return False
seq_branch_adr 250d 0x250d
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR05:05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
2512 ; --------------------------------------------------------------------------------------
2512 ; Comes from:
2512 ; 2571 C from color 0x2564
2512 ; 2593 C from color 0x2400
2512 ; 2595 C from color 0x2400
2512 ; 259a C from color 0x2400
2512 ; 259c C from color 0x2400
2512 ; --------------------------------------------------------------------------------------
2512 2512 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2513 2513 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2514 2514 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2515 2515 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272d
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2516 2516 fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x2514
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 2514 0x2514
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2517 2517 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2518 2518 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272d
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2519 2519 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
251a 251a seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x2513
seq_br_type 9 Return False
seq_branch_adr 2513 0x2513
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR05:05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
251b ; --------------------------------------------------------------------------------------
251b ; Comes from:
251b ; 2568 C from color 0x2564
251b ; --------------------------------------------------------------------------------------
251b 251b seq_en_micro 0
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
251c 251c fiu_mem_start 10 start_physical_tag_wr
ioc_load_wdr 0
seq_en_micro 0
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
251d 251d seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
val_a_adr 03 GP03
val_alu_func 0 PASS_A
251e 251e fiu_mem_start f start_physical_tag_rd
seq_en_micro 0
251f 251f fiu_mem_start 15 setup_tag_read
ioc_load_wdr 0
seq_en_micro 0
val_b_adr 04 GP04
2520 2520 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2521 2521 seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2522 2522 fiu_mem_start f start_physical_tag_rd
seq_en_micro 0
2523 2523 fiu_mem_start 15 setup_tag_read
ioc_load_wdr 0
seq_en_micro 0
val_b_adr 03 GP03
2524 2524 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2525 2525 seq_en_micro 0
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2526 2526 fiu_mem_start f start_physical_tag_rd; Flow R cc=False
; Flow J cc=True 0x251f
seq_b_timing 1 Latch Condition
seq_br_type 9 Return False
seq_branch_adr 251f 0x251f
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
val_a_adr 03 GP03
val_alu_func 0 PASS_A
2527 ; --------------------------------------------------------------------------------------
2527 ; Comes from:
2527 ; 2575 C from color 0x2564
2527 ; 2576 C from color 0x2564
2527 ; 2579 C from color 0x2564
2527 ; 257a C from color 0x2564
2527 ; 257f C from color 0x2564
2527 ; 2580 C from color 0x2564
2527 ; 2583 C from color 0x2564
2527 ; 2584 C from color 0x2564
2527 ; --------------------------------------------------------------------------------------
2527 2527 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 3 LEFT_I_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
2528 2528 seq_br_type 1 Branch True; Flow J cc=True 0x253a
seq_branch_adr 253a 0x253a
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
2529 2529 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_mem_start f start_physical_tag_rd
fiu_offs_lit 1a
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
252a 252a fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_mem_start 15 setup_tag_read
fiu_offs_lit 27
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
252b 252b fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
252c 252c fiu_len_fill_lit 4b zero-fill 0xb
fiu_offs_lit 27
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_en_micro 0
val_b_adr 04 GP04
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
252d 252d fiu_mem_start 10 start_physical_tag_wr
ioc_load_wdr 0
seq_en_micro 0
val_b_adr 03 GP03
252e 252e seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 09 GP09
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
252f 252f fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_mem_start 10 start_physical_tag_wr
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
ioc_load_wdr 0
seq_en_micro 0
val_a_adr 06 GP06
val_b_adr 04 GP04
2530 2530 fiu_len_fill_lit 4a zero-fill 0xa
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offs_lit 28
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
2531 2531 fiu_len_fill_lit 74 zero-fill 0x34
fiu_load_var 1 hold_var
fiu_mem_start f start_physical_tag_rd
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
2532 2532 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_mem_start 15 setup_tag_read
fiu_offs_lit 1a
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
2533 2533 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2534 2534 ioc_load_wdr 0
seq_en_micro 0
val_b_adr 03 GP03
2535 2535 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_mem_start 10 start_physical_tag_wr
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_b_adr 04 GP04
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
2536 2536 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2529
seq_br_type 1 Branch True
seq_branch_adr 2529 0x2529
seq_en_micro 0
2537 2537 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2538 2538 ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2539 2539 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
253a 253a fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offs_lit 1a
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
253b 253b fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 26
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
253c 253c fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 1b
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
253d 253d fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 25
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
253e 253e fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x2540
fiu_offs_lit 25
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_br_type 3 Unconditional Branch
seq_branch_adr 2540 0x2540
seq_en_micro 0
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
253f 253f fiu_len_fill_lit 3f sign-fill 0x3f
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
seq_en_micro 0
val_c_adr 39 GP06
val_c_source 0 FIU_BUS
2540 2540 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 0 PASS_A
2541 2541 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
2542 2542 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2543 2543 ioc_load_wdr 0
seq_en_micro 0
val_b_adr 04 GP04
2544 2544 fiu_mem_start 10 start_physical_tag_wr
ioc_load_wdr 0
seq_en_micro 0
val_b_adr 03 GP03
2545 2545 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 09 GP09
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2546 2546 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_mem_start 10 start_physical_tag_wr
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
ioc_load_wdr 0
seq_en_micro 0
val_a_adr 06 GP06
val_b_adr 04 GP04
2547 2547 fiu_len_fill_lit 4b zero-fill 0xb
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offs_lit 27
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
2548 2548 fiu_len_fill_lit 73 zero-fill 0x33
fiu_load_var 1 hold_var
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
2549 2549 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 1a
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
254a 254a fiu_len_fill_lit 7e zero-fill 0x3e
fiu_load_var 1 hold_var
fiu_mem_start f start_physical_tag_rd
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
254b 254b fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_mem_start 15 setup_tag_read
fiu_offs_lit 1b
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
254c 254c fiu_mem_start 10 start_physical_tag_wr; Flow C cc=True 0x272d
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272d TAG_STORE_DATA_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
254d 254d ioc_load_wdr 0
seq_en_micro 0
val_b_adr 03 GP03
254e 254e fiu_mem_start 10 start_physical_tag_wr
ioc_load_wdr 0
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_b_adr 04 GP04
254f 254f fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x253f
fiu_tivi_src c mar_0xc
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 253f 0x253f
seq_en_micro 0
2550 2550 fiu_load_var 1 hold_var
fiu_tivi_src 1 tar_val
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2551 2551 ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2552 2552 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2553 ; --------------------------------------------------------------------------------------
2553 ; Comes from:
2553 ; 2569 C from color 0x2564
2553 ; --------------------------------------------------------------------------------------
2553 2553 fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2554 2554 ioc_load_wdr 0
seq_en_micro 0
val_b_adr 20 VR10:00
val_frame 10
2555 2555 fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 38 VR04:18
val_frame 4
2556 2556 ioc_load_wdr 0
seq_en_micro 0
val_b_adr 22 VR10:02
val_frame 10
2557 2557 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2558 2558 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
2559 2559 ioc_tvbs 8 typ+mem; Flow J cc=True 0x255f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 255f 0x255f
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
255a 255a seq_br_type 1 Branch True; Flow J cc=True 0x255c
seq_branch_adr 255c 0x255c
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
255b 255b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272b
seq_br_type 5 Call True
seq_branch_adr 272b MEM_BOARDS_NOT_ALL_SAME_SIZE
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
255c 255c seq_en_micro 0
typ_a_adr 2c TR04:0c
typ_alu_func 0 PASS_A
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 4
255d 255d seq_en_micro 0
typ_a_adr 25 TR04:05
typ_alu_func 0 PASS_A
typ_c_adr 30 GP0f
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 27 VR05:07
val_alu_func 0 PASS_A
val_c_adr 30 GP0f
val_c_mux_sel 2 ALU
val_frame 5
255e 255e seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 7 INC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_a_adr 26 VR05:06
val_alu_func 0 PASS_A
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 5
255f 255f seq_br_type 1 Branch True; Flow J cc=True 0x2561
seq_branch_adr 2561 0x2561
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2560 2560 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272b
seq_br_type 5 Call True
seq_branch_adr 272b MEM_BOARDS_NOT_ALL_SAME_SIZE
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2561 2561 seq_en_micro 0
typ_a_adr 2b TR04:0b
typ_alu_func 0 PASS_A
typ_c_adr 31 GP0e
typ_c_mux_sel 0 ALU
typ_frame 4
2562 2562 seq_en_micro 0
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 30 GP0f
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 26 VR05:06
val_alu_func 0 PASS_A
val_c_adr 30 GP0f
val_c_mux_sel 2 ALU
val_frame 5
2563 2563 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 7 INC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_a_adr 24 VR05:04
val_alu_func 0 PASS_A
val_c_adr 31 GP0e
val_c_mux_sel 2 ALU
val_frame 5
2564 2564 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2565 ; --------------------------------------------------------------------------------------
2565 ; Comes from:
2565 ; 258a C from color 0x2400
2565 ; 258b C from color 0x2400
2565 ; --------------------------------------------------------------------------------------
2565 2565 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2566 2566 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
2567 2567 seq_br_type 9 Return False; Flow R cc=False
seq_branch_adr 2568 0x2568
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2568 2568 seq_br_type 7 Unconditional Call; Flow C 0x251b
seq_branch_adr 251b 0x251b
seq_en_micro 0
2569 2569 seq_br_type 7 Unconditional Call; Flow C 0x2553
seq_branch_adr 2553 0x2553
seq_en_micro 0
256a 256a seq_br_type 7 Unconditional Call; Flow C 0x24fd
seq_branch_adr 24fd 0x24fd
seq_en_micro 0
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
256b 256b seq_br_type 7 Unconditional Call; Flow C 0x2503
seq_branch_adr 2503 0x2503
seq_en_micro 0
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
256c 256c seq_br_type 7 Unconditional Call; Flow C 0x24fd
seq_branch_adr 24fd 0x24fd
seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
256d 256d seq_br_type 7 Unconditional Call; Flow C 0x2503
seq_branch_adr 2503 0x2503
seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
256e 256e seq_br_type 7 Unconditional Call; Flow C 0x24fd
seq_branch_adr 24fd 0x24fd
seq_en_micro 0
val_a_adr 3e VR17:1e
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 17
256f 256f seq_br_type 7 Unconditional Call; Flow C 0x2503
seq_branch_adr 2503 0x2503
seq_en_micro 0
val_a_adr 3e VR17:1e
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 17
2570 2570 seq_br_type 7 Unconditional Call; Flow C 0x250c
seq_branch_adr 250c 0x250c
seq_en_micro 0
2571 2571 seq_br_type 7 Unconditional Call; Flow C 0x2512
seq_branch_adr 2512 0x2512
seq_en_micro 0
2572 2572 seq_br_type 7 Unconditional Call; Flow C 0x24fd
seq_branch_adr 24fd 0x24fd
seq_en_micro 0
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2573 2573 seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2574 2574 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2575 2575 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2527
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2576 2576 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2527
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2577 2577 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2578 2578 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 1c DEC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2579 2579 seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
257a 257a seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
257b 257b seq_br_type 7 Unconditional Call; Flow C 0x2503
seq_branch_adr 2503 0x2503
seq_en_micro 0
257c 257c seq_br_type 7 Unconditional Call; Flow C 0x24fd
seq_branch_adr 24fd 0x24fd
seq_en_micro 0
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
257d 257d seq_en_micro 0
val_a_adr 3e VR17:1e
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 17
257e 257e seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
257f 257f seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2580 2580 seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2581 2581 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2582 2582 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 1c DEC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2583 2583 seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2584 2584 seq_br_type 7 Unconditional Call; Flow C 0x2527
seq_branch_adr 2527 0x2527
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2585 2585 seq_br_type 7 Unconditional Call; Flow C 0x2503
seq_branch_adr 2503 0x2503
seq_en_micro 0
2586 2586 seq_br_type 7 Unconditional Call; Flow C 0x250c
seq_branch_adr 250c 0x250c
seq_en_micro 0
2587 2587 seq_br_type 8 Return True; Flow R cc=True
seq_branch_adr 2588 0x2588
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2588 2588 seq_br_type 1 Branch True; Flow J cc=True 0x2564
seq_branch_adr 2564 0x2564
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1e A_AND_B
val_b_adr 24 VR05:04
val_frame 5
2589 2589 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
258a 258a seq_br_type 7 Unconditional Call; Flow C 0x2565
seq_branch_adr 2565 0x2565
seq_en_micro 0
258b 258b seq_br_type 7 Unconditional Call; Flow C 0x2565
seq_branch_adr 2565 0x2565
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
258c 258c seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
258d 258d seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0f GP0f
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
258e 258e seq_br_type 1 Branch True; Flow J cc=True 0x258a
seq_branch_adr 258a 0x258a
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
258f 258f seq_en_micro 0
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2590 2590 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2591 2591 seq_en_micro 0
2592 2592 seq_br_type 0 Branch False; Flow J cc=False 0x2597
seq_branch_adr 2597 0x2597
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2593 2593 fiu_mem_start 18 acknowledge_refresh; Flow C 0x2512
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 2512 0x2512
seq_en_micro 0
2594 2594 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2597
seq_br_type 1 Branch True
seq_branch_adr 2597 0x2597
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2595 2595 seq_br_type 7 Unconditional Call; Flow C 0x2512
seq_branch_adr 2512 0x2512
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2596 2596 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2597 2597 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2598 2598 seq_en_micro 0
2599 2599 seq_br_type 0 Branch False; Flow J cc=False 0x259e
seq_branch_adr 259e 0x259e
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
259a 259a seq_br_type 7 Unconditional Call; Flow C 0x2512
seq_branch_adr 2512 0x2512
seq_en_micro 0
259b 259b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x259e
seq_br_type 1 Branch True
seq_branch_adr 259e 0x259e
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
259c 259c seq_br_type 7 Unconditional Call; Flow C 0x2512
seq_branch_adr 2512 0x2512
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
259d 259d seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
259e 259e seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
259f 259f seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0f GP0f
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
25a0 25a0 seq_br_type 1 Branch True; Flow J cc=True 0x2590
seq_branch_adr 2590 0x2590
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
25a1 25a1 seq_br_type 3 Unconditional Branch; Flow J 0x2603
seq_branch_adr 2603 0x2603
seq_en_micro 0
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
25a2 ; --------------------------------------------------------------------------------------
25a2 ; Comes from:
25a2 ; 2606 C from color 0x2400
25a2 ; 2608 C from color 0x2400
25a2 ; 260d C from color 0x2400
25a2 ; 260f C from color 0x2400
25a2 ; --------------------------------------------------------------------------------------
25a2 25a2 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
25a3 25a3 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
25a4 25a4 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
25a5 25a5 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2f VR04:0f
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25a6 25a6 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25a7 25a7 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
25a8 25a8 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2d VR04:0d
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25a9 25a9 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25aa 25aa fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2a VR05:0a
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25ab 25ab fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 33 VR04:13
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25ac 25ac ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25ad 25ad fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2b VR05:0b
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25ae 25ae fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 32 VR04:12
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25af 25af ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25b0 25b0 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2c VR05:0c
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25b1 25b1 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 31 VR04:11
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25b2 25b2 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25b3 25b3 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2d VR05:0d
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25b4 25b4 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 30 VR04:10
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25b5 25b5 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25b6 25b6 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2e VR05:0e
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25b7 25b7 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 34 VR04:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25b8 25b8 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25b9 25b9 seq_br_type 1 Branch True; Flow J cc=True 0x25bc
seq_branch_adr 25bc 0x25bc
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
25ba 25ba fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2f VR05:0f
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25bb 25bb fiu_mem_start 15 setup_tag_read; Flow J 0x25c1
seq_br_type 3 Unconditional Branch
seq_branch_adr 25c1 0x25c1
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2e VR04:0e
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25bc 25bc fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 2f VR05:0f
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25bd 25bd fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 38 VR04:18
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25be 25be fiu_mem_start 18 acknowledge_refresh; Flow C cc=True 0x272f
fiu_tivi_src c mar_0xc
ioc_tvbs 8 typ+mem
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25bf 25bf fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 33 VR05:13
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25c0 25c0 fiu_mem_start 15 setup_tag_read; Flow J 0x25c1
seq_br_type 3 Unconditional Branch
seq_branch_adr 25c1 0x25c1
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2e VR04:0e
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25c1 25c1 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25c2 25c2 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 30 VR05:10
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25c3 25c3 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 35 VR04:15
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25c4 25c4 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25c5 25c5 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 31 VR05:11
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25c6 25c6 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 36 VR04:16
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25c7 25c7 ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25c8 25c8 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 32 VR05:12
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
val_frame 5
25c9 25c9 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 37 VR04:17
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
25ca 25ca ioc_tvbs 8 typ+mem; Flow C cc=True 0x272f
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
25cb 25cb seq_br_type 1 Branch True; Flow J cc=True 0x25a4
seq_branch_adr 25a4 0x25a4
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
25cc 25cc seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
25cd 25cd fiu_mem_start 18 acknowledge_refresh; Flow R cc=False
; Flow J cc=True 0x25a3
fiu_tivi_src c mar_0xc
seq_b_timing 1 Latch Condition
seq_br_type 9 Return False
seq_branch_adr 25a3 0x25a3
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR05:05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
25ce ; --------------------------------------------------------------------------------------
25ce ; Comes from:
25ce ; 2639 C from color 0x2400
25ce ; 2643 C from color 0x2400
25ce ; --------------------------------------------------------------------------------------
25ce 25ce seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x25e8
seq_br_type 1 Branch True
seq_branch_adr 25e8 0x25e8
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
25cf 25cf fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 72
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25d0 25d0 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 16
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 14 ZEROS
25d1 25d1 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 32
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25d2 25d2 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 71
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25d3 25d3 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 10
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25d4 25d4 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 70
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25d5 25d5 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 17
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25d6 25d6 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 30
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25d7 25d7 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6f
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25d8 25d8 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 12
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25d9 25d9 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6e
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25da 25da fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 13
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25db 25db fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6d
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25dc 25dc fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 14
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25dd 25dd fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6c
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25de 25de fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 15
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25df 25df fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6b
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25e0 25e0 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 11
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25e1 25e1 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6a
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25e2 25e2 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0f
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25e3 25e3 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 69
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25e4 25e4 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0e
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25e5 25e5 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 68
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25e6 25e6 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0d
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25e7 25e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
seq_br_type a Unconditional Return
seq_en_micro 0
val_c_adr 3b GP04
val_c_source 0 FIU_BUS
25e8 25e8 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 72
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25e9 25e9 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 16
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 14 ZEROS
25ea 25ea fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 32
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25eb 25eb fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 71
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25ec 25ec fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0c
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25ed 25ed fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 70
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25ee 25ee fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 17
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25ef 25ef fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 30
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25f0 25f0 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6f
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25f1 25f1 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 12
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25f2 25f2 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6e
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25f3 25f3 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 13
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25f4 25f4 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6d
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25f5 25f5 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 14
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25f6 25f6 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6c
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25f7 25f7 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 15
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25f8 25f8 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6b
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25f9 25f9 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 11
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25fa 25fa fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 6a
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25fb 25fb fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0f
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25fc 25fc fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 69
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25fd 25fd fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0e
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
25fe 25fe fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 68
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
25ff 25ff fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 0d
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
2600 2600 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_var 1 hold_var
fiu_offs_lit 67
fiu_rdata_src 0 rotator
fiu_tivi_src c mar_0xc
fiu_vmux_sel 1 fill value
seq_en_micro 0
2601 2601 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 10
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
2602 2602 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
seq_br_type a Unconditional Return
seq_en_micro 0
val_c_adr 3b GP04
val_c_source 0 FIU_BUS
2603 2603 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2604 2604 seq_en_micro 0
2605 2605 seq_br_type 0 Branch False; Flow J cc=False 0x260a
seq_branch_adr 260a 0x260a
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2606 2606 seq_br_type 7 Unconditional Call; Flow C 0x25a2
seq_branch_adr 25a2 0x25a2
seq_en_micro 0
2607 2607 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x260a
seq_br_type 1 Branch True
seq_branch_adr 260a 0x260a
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2608 2608 seq_br_type 7 Unconditional Call; Flow C 0x25a2
seq_branch_adr 25a2 0x25a2
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2609 2609 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
260a 260a fiu_mem_start f start_physical_tag_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
260b 260b seq_en_micro 0
260c 260c seq_br_type 0 Branch False; Flow J cc=False 0x2611
seq_branch_adr 2611 0x2611
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
260d 260d seq_br_type 7 Unconditional Call; Flow C 0x25a2
seq_branch_adr 25a2 0x25a2
seq_en_micro 0
260e 260e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2611
seq_br_type 1 Branch True
seq_branch_adr 2611 0x2611
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
260f 260f seq_br_type 7 Unconditional Call; Flow C 0x25a2
seq_branch_adr 25a2 0x25a2
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2610 2610 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2611 2611 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2612 2612 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0f GP0f
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2613 2613 seq_br_type 1 Branch True; Flow J cc=True 0x2603
seq_branch_adr 2603 0x2603
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
2614 2614 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2615 2615 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2616 2616 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2617 2617 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 37 VR04:17
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2618 2618 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2619 2619 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR05:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
261a 261a ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 32 VR05:12
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
261b 261b fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
261c 261c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
261d 261d ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 37 VR04:17
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
261e 261e fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
261f 261f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 32 VR05:12
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
2620 2620 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2621 2621 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2622 2622 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2623 2623 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2624 2624 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2625 2625 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR17:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2626 2626 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2d VR04:0d
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2627 2627 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2628 2628 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2629 2629 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
262a 262a fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
262b 262b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 34 VR17:14
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
262c 262c ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
262d 262d fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
262e 262e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
262f 262f ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2630 2630 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2631 2631 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR10:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2632 2632 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 2f VR04:0f
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2633 2633 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2634 2634 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2635 2635 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2636 2636 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 18
2637 2637 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR10:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2638 2638 seq_en_micro 0
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2639 2639 ioc_adrbs 1 val ; Flow C 0x25ce
ioc_fiubs 1 val
seq_br_type 7 Unconditional Call
seq_branch_adr 25ce 0x25ce
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 24 VR04:04
val_alu_func 1a PASS_B
val_b_adr 06 GP06
val_c_adr 28 LOOP_COUNTER
val_c_source 0 FIU_BUS
val_frame 4
263a 263a ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
263b 263b fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
263c 263c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 02 GP02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 18
263d 263d ioc_adrbs 1 val ; Flow J cc=False 0x263a
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 263a 0x263a
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2e VR05:0e
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
263e 263e seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 36 VR16:16
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
263f 263f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2641
seq_br_type 1 Branch True
seq_branch_adr 2641 0x2641
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 30 VR04:10
val_frame 4
2640 2640 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 36 VR10:16
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2641 2641 seq_b_timing 0 Early Condition; Flow J cc=False 0x2639
seq_br_type 0 Branch False
seq_branch_adr 2639 0x2639
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
2642 2642 seq_en_micro 0
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2643 2643 ioc_adrbs 1 val ; Flow C 0x25ce
ioc_fiubs 1 val
seq_br_type 7 Unconditional Call
seq_branch_adr 25ce 0x25ce
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 24 VR04:04
val_alu_func 1a PASS_B
val_b_adr 06 GP06
val_c_adr 28 LOOP_COUNTER
val_c_source 0 FIU_BUS
val_frame 4
2644 2644 ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO)
2645 2645 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2646 2646 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x272f
seq_br_type 5 Call True
seq_branch_adr 272f HASH_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 27 VR18:07
val_alu_func 1e A_AND_B
val_b_adr 02 GP02
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 18
2647 2647 ioc_adrbs 1 val ; Flow J cc=False 0x2644
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2644 0x2644
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR05:0a
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 5
2648 2648 seq_b_timing 0 Early Condition; Flow J cc=False 0x2643
seq_br_type 0 Branch False
seq_branch_adr 2643 0x2643
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 37 VR16:17
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
2649 2649 seq_br_type 3 Unconditional Branch; Flow J 0x2674
seq_branch_adr 2674 0x2674
seq_en_micro 0
264a ; --------------------------------------------------------------------------------------
264a ; Comes from:
264a ; 2675 C from color 0x2400
264a ; 2682 C from color 0x2400
264a ; --------------------------------------------------------------------------------------
264a 264a fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
ioc_load_wdr 0
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 09 GP09
val_alu_func 0 PASS_A
val_b_adr 20 VR10:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
264b 264b seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
264c 264c fiu_mem_start 10 start_physical_tag_wr; Flow R cc=False
ioc_adrbs 1 val
seq_br_type 9 Return False
seq_branch_adr 264d 0x264d
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
264d 264d seq_en_micro 0
264e 264e fiu_mem_start 10 start_physical_tag_wr; Flow R cc=False
; Flow J cc=True 0x264d
ioc_adrbs 1 val
seq_br_type 9 Return False
seq_branch_adr 264d 0x264d
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 09 GP09
typ_alu_func 1c DEC_A
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
264f ; --------------------------------------------------------------------------------------
264f ; Comes from:
264f ; 267a C from color 0x2400
264f ; 267b C from color 0x2400
264f ; 267c C from color 0x2400
264f ; 267e C from color 0x2400
264f ; 267f C from color 0x2400
264f ; 2680 C from color 0x2400
264f ; --------------------------------------------------------------------------------------
264f 264f seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 1e A_AND_B
val_b_adr 37 VR10:17
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
2650 2650 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1b A_OR_B
val_b_adr 26 VR04:06
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 4
2651 2651 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1b A_OR_B
val_b_adr 08 GP08
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2652 2652 seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 1e A_AND_B
val_b_adr 37 VR10:17
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2653 2653 fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 06 GP06
typ_mar_cntl 4 RESTORE_MAR
val_a_adr 06 GP06
val_alu_func 0 PASS_A
2654 2654 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2657
fiu_load_mdr 1 hold_mdr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_tivi_src 3 tar_frame
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2657 0x2657
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2655 2655 fiu_len_fill_lit 49 zero-fill 0x9
fiu_load_var 1 hold_var
fiu_offs_lit 4c
fiu_op_sel 3 insert
fiu_tivi_src 1 tar_val
seq_en_micro 0
val_b_adr 09 GP09
2656 2656 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2659
fiu_load_var 1 hold_var
fiu_offs_lit 70
fiu_op_sel 3 insert
seq_br_type 3 Unconditional Branch
seq_branch_adr 2659 0x2659
seq_en_micro 0
2657 2657 fiu_len_fill_lit 48 zero-fill 0x8
fiu_load_var 1 hold_var
fiu_offs_lit 4d
fiu_op_sel 3 insert
fiu_tivi_src 1 tar_val
seq_en_micro 0
val_b_adr 09 GP09
2658 2658 fiu_len_fill_lit 42 zero-fill 0x2
fiu_load_var 1 hold_var
fiu_offs_lit 70
fiu_op_sel 3 insert
seq_en_micro 0
2659 2659 fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
265a 265a ioc_load_wdr 0
seq_en_micro 0
val_b_adr 07 GP07
265b 265b fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_var 1 hold_var
fiu_mem_start 11 start_tag_query
fiu_rdata_src 0 rotator
fiu_tivi_src 8 type_var
ioc_adrbs 1 val
seq_en_micro 0
typ_b_adr 06 GP06
typ_mar_cntl 4 RESTORE_MAR
val_a_adr 06 GP06
val_alu_func 0 PASS_A
265c 265c ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1b A_OR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
265d 265d seq_br_type 0 Branch False; Flow J cc=False 0x2662
seq_branch_adr 2662 0x2662
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1e A_AND_B
val_b_adr 20 VR18:00
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
val_frame 18
265e 265e fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 16
265f 265f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 09 GP09
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2660 2660 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 0b GP0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2661 2661 seq_br_type 3 Unconditional Branch; Flow J 0x2667
seq_branch_adr 2667 0x2667
seq_en_micro 0
2662 2662 fiu_tivi_src 3 tar_frame; Flow J cc=True 0x2665
ioc_tvbs 1 typ+fiu
seq_br_type 1 Branch True
seq_branch_adr 2665 0x2665
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 16
2663 2663 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 25 VR05:05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
2664 2664 seq_br_type 3 Unconditional Branch; Flow J 0x2666
seq_branch_adr 2666 0x2666
seq_en_micro 0
2665 2665 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 28 VR18:08
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 18
2666 2666 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 0b GP0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2667 2667 fiu_mem_start 14 start_name_query
seq_en_micro 0
val_a_adr 0a GP0a
val_alu_func 1e A_AND_B
val_b_adr 25 VR10:05
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 10
2668 2668 seq_en_micro 0
val_a_adr 0b GP0b
val_alu_func 1e A_AND_B
val_b_adr 25 VR10:05
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
val_frame 10
2669 2669 seq_br_type 0 Branch False; Flow J cc=False 0x266e
seq_branch_adr 266e 0x266e
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
266a 266a fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 16
266b 266b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 09 GP09
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
266c 266c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 0b GP0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
266d 266d seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
266e 266e fiu_tivi_src 3 tar_frame; Flow J cc=True 0x2671
ioc_tvbs 1 typ+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2671 0x2671
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 25 TR04:05
typ_frame 4
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 16
266f 266f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 25 VR05:05
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 5
2670 2670 seq_br_type 3 Unconditional Branch; Flow J 0x2672
seq_branch_adr 2672 0x2672
seq_en_micro 0
2671 2671 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 28 VR18:08
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 18
2672 2672 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2731
seq_br_type 5 Call True
seq_branch_adr 2731 TAG_STORE_COMPARE_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 0a GP0a
val_alu_func 19 X_XOR_B
val_b_adr 0b GP0b
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2673 2673 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2674 2674 ioc_load_wdr 0
seq_en_micro 0
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_b_adr 20 VR10:00
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 10
2675 2675 fiu_mem_start 18 acknowledge_refresh; Flow C 0x264a
fiu_tivi_src c mar_0xc
seq_br_type 7 Unconditional Call
seq_branch_adr 264a 0x264a
seq_en_micro 0
typ_rand d SET_PASS_PRIVACY_BIT
2676 2676 seq_b_timing 0 Early Condition; Flow J cc=False 0x2675
seq_br_type 0 Branch False
seq_branch_adr 2675 0x2675
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 09 GP09
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 5
2677 2677 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
typ_mar_cntl f LOAD_MAR_RESERVED
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2678 2678 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 22 VR04:02
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 4
2679 2679 seq_br_type 0 Branch False; Flow J cc=False 0x2684
seq_branch_adr 2684 0x2684
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 36 VR04:16
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
267a 267a seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
267b 267b seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
267c 267c seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
267d 267d seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 10 NOT_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
267e 267e seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
267f 267f seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2680 2680 seq_br_type 7 Unconditional Call; Flow C 0x264f
seq_branch_adr 264f 0x264f
seq_en_micro 0
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2681 2681 seq_br_type 1 Branch True; Flow J cc=True 0x267a
seq_branch_adr 267a 0x267a
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 10 NOT_A
val_c_adr 3c GP03
val_c_mux_sel 0 ALU << 1
2682 2682 seq_br_type 7 Unconditional Call; Flow C 0x264a
seq_branch_adr 264a 0x264a
seq_en_micro 0
2683 2683 seq_en_micro 0
2684 2684 fiu_mem_start d start_physical_rd; Flow J cc=False 0x2678
ioc_adrbs 1 val
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2678 0x2678
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 09 GP09
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 5
2685 2685 seq_en_micro 0
2686 2686 fiu_tivi_src 8 type_var
seq_en_micro 0
typ_b_adr 34 TR10:14
typ_frame 10
typ_mar_cntl 4 RESTORE_MAR
2687 2687 seq_br_type 3 Unconditional Branch; Flow J 0x270b
seq_branch_adr 270b 0x270b
seq_en_micro 0
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2688 ; --------------------------------------------------------------------------------------
2688 ; Comes from:
2688 ; 26cc C from color 0x26b9
2688 ; 26de C from color 0x26b9
2688 ; 26e6 C from color 0x26e0
2688 ; 26e9 C from color 0x26e0
2688 ; 26ec C from color 0x26e0
2688 ; 26ef C from color 0x26e0
2688 ; 26f2 C from color 0x26e0
2688 ; 26fd C from color 0x26e0
2688 ; 2715 C from color 0x2400
2688 ; 2718 C from color 0x2400
2688 ; 271e C from color 0x2400
2688 ; 2721 C from color 0x2400
2688 ; --------------------------------------------------------------------------------------
2688 2688 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_en_micro 0
typ_a_adr 37 TR10:17
typ_alu_func 0 PASS_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_frame 10
2689 2689 seq_br_type 1 Branch True; Flow J cc=True 0x2689
seq_branch_adr 2689 0x2689
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 07 GP07
typ_alu_func 1c DEC_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
268a 268a fiu_mem_start 18 acknowledge_refresh; Flow R
fiu_tivi_src c mar_0xc
seq_br_type a Unconditional Return
seq_en_micro 0
268b ; --------------------------------------------------------------------------------------
268b ; Comes from:
268b ; 26e5 C from color 0x26e0
268b ; 26e8 C from color 0x26e0
268b ; 26eb C from color 0x26e0
268b ; 26f1 C from color 0x26e0
268b ; 26fc C from color 0x26e0
268b ; --------------------------------------------------------------------------------------
268b 268b ioc_load_wdr 0
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
268c 268c fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 06 GP06
268d 268d seq_en_micro 0
268e 268e fiu_mem_start e start_physical_wr; Flow J cc=True 0x268d
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 268d 0x268d
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
268f 268f seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
2690 2690 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x268c
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 268c 0x268c
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2691 2691 seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x268c
seq_br_type 9 Return False
seq_branch_adr 268c 0x268c
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 35 VR16:15
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
2692 ; --------------------------------------------------------------------------------------
2692 ; Comes from:
2692 ; 26e7 C from color 0x26e0
2692 ; 26ea C from color 0x26e0
2692 ; 26ed C from color 0x26e0
2692 ; 26fb C from color 0x26e0
2692 ; 2706 C from color 0x26e0
2692 ; --------------------------------------------------------------------------------------
2692 2692 fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2693 2693 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2694 2694 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x2733
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2695 2695 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2694
fiu_load_var 1 hold_var
fiu_mem_start d start_physical_rd
fiu_tivi_src 9 type_val
ioc_adrbs 1 val
ioc_tvbs c mem+mem+csa+dummy
seq_br_type 1 Branch True
seq_branch_adr 2694 0x2694
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2696 2696 ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x2733
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2697 2697 fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
2698 2698 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x2693
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2693 0x2693
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2699 2699 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2693
seq_br_type 1 Branch True
seq_branch_adr 2693 0x2693
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 35 VR16:15
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
269a 269a ioc_tvbs 3 fiu+fiu; Flow C cc=True 0x2733
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
269b 269b seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
269c ; --------------------------------------------------------------------------------------
269c ; Comes from:
269c ; 26ee C from color 0x26e0
269c ; 2707 C from color 0x26e0
269c ; --------------------------------------------------------------------------------------
269c 269c seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
269d 269d fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 06 GP06
269e 269e fiu_tivi_src 4 fiu_var
ioc_fiubs 1 val
ioc_load_wdr 0
ioc_tvbs 2 fiu+val
seq_en_micro 0
val_a_adr 06 GP06
val_b_adr 06 GP06
269f 269f fiu_mem_start e start_physical_wr; Flow J cc=True 0x269e
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 269e 0x269e
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
26a0 26a0 fiu_mem_start e start_physical_wr
fiu_tivi_src 6 fiu_fiu
ioc_fiubs 1 val
ioc_load_wdr 0
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
26a1 26a1 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x269d
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 269d 0x269d
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
26a2 26a2 seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x269d
seq_br_type 9 Return False
seq_branch_adr 269d 0x269d
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 35 VR16:15
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
26a3 ; --------------------------------------------------------------------------------------
26a3 ; Comes from:
26a3 ; 26f0 C from color 0x26e0
26a3 ; 2714 C from color 0x2400
26a3 ; 2717 C from color 0x2400
26a3 ; 271d C from color 0x2400
26a3 ; 2720 C from color 0x2400
26a3 ; --------------------------------------------------------------------------------------
26a3 26a3 seq_cond_sel 16 VAL.TRUE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
26a4 26a4 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 0e GP0e
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 06 GP06
26a5 26a5 ioc_fiubs 1 val
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_source 0 FIU_BUS
val_a_adr 06 GP06
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
26a6 26a6 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2733
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26a7 26a7 fiu_mem_start d start_physical_rd; Flow J cc=True 0x26a5
ioc_adrbs 1 val
seq_br_type 1 Branch True
seq_branch_adr 26a5 0x26a5
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 1c DEC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 2d VR04:0d
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
26a8 26a8 ioc_fiubs 1 val
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_source 0 FIU_BUS
val_a_adr 06 GP06
val_c_adr 3c GP03
val_c_source 0 FIU_BUS
26a9 26a9 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2733
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26aa 26aa seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 21 VR18:01
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 18
26ab 26ab fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x26a4
fiu_tivi_src c mar_0xc
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 26a4 0x26a4
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
26ac 26ac seq_b_timing 1 Latch Condition; Flow R cc=False
; Flow J cc=True 0x26a4
seq_br_type 9 Return False
seq_branch_adr 26a4 0x26a4
seq_cond_sel 17 VAL.FALSE(early)
seq_en_micro 0
seq_latch 1
typ_a_adr 26 TR04:06
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 06 GP06
val_alu_func 1 A_PLUS_B
val_b_adr 35 VR16:15
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
26ad ; --------------------------------------------------------------------------------------
26ad ; Comes from:
26ad ; 26e4 C from color 0x26e0
26ad ; --------------------------------------------------------------------------------------
26ad 26ad seq_en_micro 0
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 20 VR04:00
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
26ae 26ae fiu_mem_start e start_physical_wr
ioc_load_wdr 0
seq_en_micro 0
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
26af 26af seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
seq_latch 1
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
val_a_adr 03 GP03
val_alu_func 0 PASS_A
26b0 26b0 fiu_mem_start d start_physical_rd
seq_en_micro 0
26b1 26b1 ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_b_adr 04 GP04
26b2 26b2 fiu_mem_start e start_physical_wr; Flow C cc=True 0x2733
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26b3 26b3 seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 3 LEFT_I_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26b4 26b4 fiu_mem_start d start_physical_rd
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
26b5 26b5 ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
26b6 26b6 fiu_mem_start e start_physical_wr; Flow C cc=True 0x2733
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26b7 26b7 seq_en_micro 0
typ_alu_func 15 NOT_B
typ_b_adr 03 GP03
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 15 NOT_B
val_b_adr 03 GP03
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
26b8 26b8 fiu_mem_start d start_physical_rd; Flow R cc=False
; Flow J cc=True 0x26b1
seq_b_timing 1 Latch Condition
seq_br_type 9 Return False
seq_branch_adr 26b1 0x26b1
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
seq_latch 1
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
val_a_adr 03 GP03
val_alu_func 0 PASS_A
26b9 ; --------------------------------------------------------------------------------------
26b9 ; Comes from:
26b9 ; 26f5 C from color 0x26e0
26b9 ; 26f6 C from color 0x26e0
26b9 ; 26f9 C from color 0x26e0
26b9 ; 26fa C from color 0x26e0
26b9 ; 2700 C from color 0x26e0
26b9 ; 2701 C from color 0x26e0
26b9 ; 2704 C from color 0x26e0
26b9 ; 2705 C from color 0x26e0
26b9 ; --------------------------------------------------------------------------------------
26b9 26b9 fiu_len_fill_lit 78 zero-fill 0x38
fiu_load_var 1 hold_var
fiu_offs_lit 40
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
fiu_vmux_sel 1 fill value
ioc_fiubs 2 typ
seq_en_micro 0
typ_a_adr 0e GP0e
26ba 26ba ioc_fiubs 0 fiu ; Flow J cc=True 0x26ce
seq_br_type 1 Branch True
seq_branch_adr 26ce 0x26ce
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_c_adr 3a GP05
typ_c_source 0 FIU_BUS
typ_frame 4
26bb 26bb seq_b_timing 3 Late Condition, Hint False; Flow R cc=True
seq_br_type 8 Return True
seq_branch_adr 26bc 0x26bc
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 20 TR19:00
typ_alu_func 1c DEC_A
typ_frame 19
val_a_adr 07 GP07
val_alu_func 1e A_AND_B
val_b_adr 24 VR05:04
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_frame 5
26bc 26bc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x26cf
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_mem_start d start_physical_rd
fiu_offs_lit 39
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_br_type 1 Branch True
seq_branch_adr 26cf 0x26cf
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
26bd 26bd fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_tar 1 hold_tar
fiu_offs_lit 21
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
26be 26be fiu_len_fill_lit 61 zero-fill 0x21; Flow C cc=True 0x2733
fiu_load_var 1 hold_var
fiu_mem_start e start_physical_wr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26bf 26bf fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 20
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_b_adr 04 GP04
26c0 26c0 fiu_len_fill_lit 52 zero-fill 0x12
fiu_mem_start e start_physical_wr
fiu_offs_lit 20
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
26c1 26c1 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 09 GP09
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26c2 26c2 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_mem_start e start_physical_wr
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_a_adr 06 GP06
val_b_adr 04 GP04
26c3 26c3 fiu_len_fill_lit 4b zero-fill 0xb
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offs_lit 27
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
26c4 26c4 fiu_len_fill_lit 73 zero-fill 0x33
fiu_load_var 1 hold_var
fiu_mem_start d start_physical_rd
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
26c5 26c5 fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_tar 1 hold_tar
fiu_offs_lit 33
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
26c6 26c6 fiu_len_fill_lit 79 zero-fill 0x39; Flow C cc=True 0x2733
fiu_load_var 1 hold_var
fiu_mem_start e start_physical_wr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26c7 26c7 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 1a
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
26c8 26c8 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_mem_start e start_physical_wr
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_b_adr 04 GP04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_b_adr 04 GP04
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
26c9 26c9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x26bb
fiu_tivi_src c mar_0xc
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 26bb 0x26bb
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1b A_OR_B
val_b_adr 0a GP0a
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26ca 26ca fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26cb 26cb ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
26cc 26cc seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26cd 26cd seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
26ce 26ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x26cf
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_mem_start d start_physical_rd
fiu_offs_lit 39
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_br_type 1 Branch True
seq_branch_adr 26cf 0x26cf
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
26cf 26cf fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_tar 1 hold_tar
fiu_offs_lit 22
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
26d0 26d0 fiu_len_fill_lit 61 zero-fill 0x21; Flow C cc=True 0x2733
fiu_load_var 1 hold_var
fiu_mem_start e start_physical_wr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26d1 26d1 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 21
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_b_adr 04 GP04
26d2 26d2 fiu_len_fill_lit 51 zero-fill 0x11
fiu_mem_start e start_physical_wr
fiu_offs_lit 21
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
26d3 26d3 seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 09 GP09
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26d4 26d4 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_mem_start e start_physical_wr
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_a_adr 06 GP06
val_b_adr 04 GP04
26d5 26d5 fiu_len_fill_lit 4a zero-fill 0xa
fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_offs_lit 28
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 07 GP07
26d6 26d6 fiu_len_fill_lit 74 zero-fill 0x34
fiu_load_var 1 hold_var
fiu_mem_start d start_physical_rd
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
26d7 26d7 fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_tar 1 hold_tar
fiu_offs_lit 33
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
seq_en_micro 0
26d8 26d8 fiu_len_fill_lit 79 zero-fill 0x39; Flow C cc=True 0x2733
fiu_load_var 1 hold_var
fiu_mem_start e start_physical_wr
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2733 RAM_PLANE_DATA_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
26d9 26d9 fiu_len_fill_lit 40 zero-fill 0x0
fiu_load_tar 1 hold_tar
fiu_offs_lit 1a
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 03 GP03
val_b_adr 03 GP03
26da 26da fiu_len_fill_lit 3f sign-fill 0x3f
fiu_mem_start e start_physical_wr
fiu_rdata_src 0 rotator
ioc_fiubs 0 fiu
ioc_load_wdr 0
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
typ_a_adr 05 GP05
typ_alu_func 1c DEC_A
typ_b_adr 04 GP04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_b_adr 04 GP04
val_c_adr 38 GP07
val_c_source 0 FIU_BUS
26db 26db fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x26ce
fiu_tivi_src c mar_0xc
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 26ce 0x26ce
seq_en_micro 0
26dc 26dc fiu_load_tar 1 hold_tar
fiu_load_var 1 hold_var
fiu_tivi_src 9 type_val
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 0 PASS_A
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 0 PASS_A
val_b_adr 03 GP03
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26dd 26dd ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
26de 26de seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26df 26df seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
26e0 26e0 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
26e1 ; --------------------------------------------------------------------------------------
26e1 ; Comes from:
26e1 ; 270b C from color 0x2400
26e1 ; 270c C from color 0x2400
26e1 ; --------------------------------------------------------------------------------------
26e1 26e1 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
26e2 26e2 seq_en_micro 0
26e3 26e3 seq_br_type 9 Return False; Flow R cc=False
seq_branch_adr 26e4 0x26e4
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
26e4 26e4 seq_br_type 7 Unconditional Call; Flow C 0x26ad
seq_branch_adr 26ad 0x26ad
seq_en_micro 0
26e5 26e5 seq_br_type 7 Unconditional Call; Flow C 0x268b
seq_branch_adr 268b 0x268b
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26e6 26e6 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26e7 26e7 seq_br_type 7 Unconditional Call; Flow C 0x2692
seq_branch_adr 2692 0x2692
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26e8 26e8 seq_br_type 7 Unconditional Call; Flow C 0x268b
seq_branch_adr 268b 0x268b
seq_en_micro 0
typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26e9 26e9 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26ea 26ea seq_br_type 7 Unconditional Call; Flow C 0x2692
seq_branch_adr 2692 0x2692
seq_en_micro 0
typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26eb 26eb seq_br_type 7 Unconditional Call; Flow C 0x268b
seq_branch_adr 268b 0x268b
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 3a VR17:1a
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 17
26ec 26ec seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26ed 26ed seq_br_type 7 Unconditional Call; Flow C 0x2692
seq_branch_adr 2692 0x2692
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 3a VR17:1a
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 17
26ee 26ee seq_br_type 7 Unconditional Call; Flow C 0x269c
seq_branch_adr 269c 0x269c
seq_en_micro 0
26ef 26ef seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26f0 26f0 seq_br_type 7 Unconditional Call; Flow C 0x26a3
seq_branch_adr 26a3 0x26a3
seq_en_micro 0
26f1 26f1 seq_br_type 7 Unconditional Call; Flow C 0x268b
seq_branch_adr 268b 0x268b
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
26f2 26f2 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26f3 26f3 seq_en_micro 0
typ_alu_func 13 ONES
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
26f4 26f4 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
26f5 26f5 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26f6 26f6 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26f7 26f7 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
26f8 26f8 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 1c DEC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
26f9 26f9 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26fa 26fa seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
26fb 26fb seq_br_type 7 Unconditional Call; Flow C 0x2692
seq_branch_adr 2692 0x2692
seq_en_micro 0
26fc 26fc seq_br_type 7 Unconditional Call; Flow C 0x268b
seq_branch_adr 268b 0x268b
seq_en_micro 0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 2d VR05:0d
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 5
26fd 26fd seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
26fe 26fe seq_en_micro 0
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 3b VR17:1b
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 17
26ff 26ff seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 7 INC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2700 2700 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2701 2701 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2702 2702 seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2703 2703 seq_en_micro 0
val_a_adr 14 ZEROS
val_alu_func 1c DEC_A
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
2704 2704 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2705 2705 seq_br_type 7 Unconditional Call; Flow C 0x26b9
seq_branch_adr 26b9 0x26b9
seq_en_micro 0
val_a_adr 08 GP08
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2706 2706 seq_br_type 7 Unconditional Call; Flow C 0x2692
seq_branch_adr 2692 0x2692
seq_en_micro 0
2707 2707 seq_br_type 7 Unconditional Call; Flow C 0x269c
seq_branch_adr 269c 0x269c
seq_en_micro 0
2708 2708 seq_br_type 8 Return True; Flow R cc=True
seq_branch_adr 2709 0x2709
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2709 2709 seq_br_type 1 Branch True; Flow J cc=True 0x26e0
seq_branch_adr 26e0 0x26e0
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1e A_AND_B
val_b_adr 24 VR05:04
val_frame 5
270a 270a seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
270b 270b seq_br_type 7 Unconditional Call; Flow C 0x26e1
seq_branch_adr 26e1 0x26e1
seq_en_micro 0
270c 270c seq_br_type 7 Unconditional Call; Flow C 0x26e1
seq_branch_adr 26e1 0x26e1
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
270d 270d seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
270e 270e seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0f GP0f
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
270f 270f seq_br_type 1 Branch True; Flow J cc=True 0x270b
seq_branch_adr 270b 0x270b
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
2710 2710 seq_en_micro 0
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2711 2711 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2712 2712 seq_en_micro 0
2713 2713 seq_br_type 0 Branch False; Flow J cc=False 0x271a
seq_branch_adr 271a 0x271a
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2714 2714 seq_br_type 7 Unconditional Call; Flow C 0x26a3
seq_branch_adr 26a3 0x26a3
seq_en_micro 0
2715 2715 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
2716 2716 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x271a
seq_br_type 1 Branch True
seq_branch_adr 271a 0x271a
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2717 2717 seq_br_type 7 Unconditional Call; Flow C 0x26a3
seq_branch_adr 26a3 0x26a3
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2718 2718 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
2719 2719 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
271a 271a fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
271b 271b seq_en_micro 0
271c 271c seq_br_type 0 Branch False; Flow J cc=False 0x2723
seq_branch_adr 2723 0x2723
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
271d 271d seq_br_type 7 Unconditional Call; Flow C 0x26a3
seq_branch_adr 26a3 0x26a3
seq_en_micro 0
271e 271e seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
271f 271f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2723
seq_br_type 1 Branch True
seq_branch_adr 2723 0x2723
seq_cond_sel 18 TYP.ALU_ZERO(late)
seq_en_micro 0
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2720 2720 seq_br_type 7 Unconditional Call; Flow C 0x26a3
seq_branch_adr 26a3 0x26a3
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2721 2721 seq_br_type 7 Unconditional Call; Flow C 0x2688
seq_branch_adr 2688 0x2688
seq_en_micro 0
2722 2722 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 24 VR05:04
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2723 2723 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 6 A_MINUS_B
val_b_adr 0e GP0e
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2724 2724 seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 0f GP0f
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2725 2725 seq_br_type 1 Branch True; Flow J cc=True 0x2711
seq_branch_adr 2711 0x2711
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
2726 2726 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2727 ; --------------------------------------------------------------------------------------
2727 ; Comes from:
2727 ; 240c C True from color 0x2400
2727 ; 240d C True from color 0x2400
2727 ; 2411 C True from color 0x2400
2727 ; 2414 C True from color 0x2400
2727 ; 2417 C True from color 0x2400
2727 ; 241a C True from color 0x2400
2727 ; --------------------------------------------------------------------------------------
2727 INIT_ERROR:
2727 2727 <halt> ; Flow R
2728 2728 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2729 ; --------------------------------------------------------------------------------------
2729 ; Comes from:
2729 ; 241d C True from color 0x2400
2729 ; 241e C True from color 0x2400
2729 ; 2420 C True from color 0x2400
2729 ; 2422 C True from color 0x2400
2729 ; 2424 C True from color 0x2400
2729 ; 2426 C True from color 0x2400
2729 ; 2427 C True from color 0x2400
2729 ; 2429 C True from color 0x2400
2729 ; 242e C True from color 0x2400
2729 ; 2430 C True from color 0x2400
2729 ; 2432 C True from color 0x2400
2729 ; 2434 C True from color 0x2400
2729 ; 2436 C True from color 0x2400
2729 ; 2438 C True from color 0x2400
2729 ; 243a C True from color 0x2400
2729 ; 243c C True from color 0x2400
2729 ; 243f C True from color 0x2400
2729 ; 2441 C True from color 0x2400
2729 ; 2443 C True from color 0x2400
2729 ; 2445 C True from color 0x2400
2729 ; 2448 C True from color 0x2400
2729 ; 244a C True from color 0x2400
2729 ; 244c C True from color 0x2400
2729 ; 244e C True from color 0x2400
2729 ; 2450 C True from color 0x2400
2729 ; 2452 C True from color 0x2400
2729 ; 2454 C True from color 0x2400
2729 ; 2456 C True from color 0x2400
2729 ; 2459 C True from color 0x2400
2729 ; 245b C True from color 0x2400
2729 ; 245d C True from color 0x2400
2729 ; 245f C True from color 0x2400
2729 ; 2462 C True from color 0x2400
2729 ; 2464 C True from color 0x2400
2729 ; 2466 C True from color 0x2400
2729 ; 2468 C True from color 0x2400
2729 ; 246a C True from color 0x2400
2729 ; 246c C True from color 0x2400
2729 ; 246e C True from color 0x2400
2729 ; 2470 C True from color 0x2400
2729 ; 2473 C True from color 0x2400
2729 ; 2475 C True from color 0x2400
2729 ; 2477 C True from color 0x2400
2729 ; 2479 C True from color 0x2400
2729 ; 247c C True from color 0x2400
2729 ; 247e C True from color 0x2400
2729 ; 2480 C True from color 0x2400
2729 ; 2482 C True from color 0x2400
2729 ; 2484 C True from color 0x2400
2729 ; 2486 C True from color 0x2400
2729 ; 2488 C True from color 0x2400
2729 ; 248a C True from color 0x2400
2729 ; 248d C True from color 0x2400
2729 ; 248f C True from color 0x2400
2729 ; 2491 C True from color 0x2400
2729 ; 2493 C True from color 0x2400
2729 ; 2496 C True from color 0x2400
2729 ; 2498 C True from color 0x2400
2729 ; 249a C True from color 0x2400
2729 ; 249c C True from color 0x2400
2729 ; 249e C True from color 0x2400
2729 ; 24a0 C True from color 0x2400
2729 ; 24a2 C True from color 0x2400
2729 ; 24a4 C True from color 0x2400
2729 ; 24a7 C True from color 0x2400
2729 ; 24a9 C True from color 0x2400
2729 ; 24ab C True from color 0x2400
2729 ; 24ad C True from color 0x2400
2729 ; 24b0 C True from color 0x2400
2729 ; 24b2 C True from color 0x2400
2729 ; 24b4 C True from color 0x2400
2729 ; 24b6 C True from color 0x2400
2729 ; 24b8 C True from color 0x2400
2729 ; 24ba C True from color 0x2400
2729 ; 24bc C True from color 0x2400
2729 ; 24be C True from color 0x2400
2729 ; 24c1 C True from color 0x2400
2729 ; 24c3 C True from color 0x2400
2729 ; 24c5 C True from color 0x2400
2729 ; 24c7 C True from color 0x2400
2729 ; 24ca C True from color 0x2400
2729 ; 24cc C True from color 0x2400
2729 ; 24ce C True from color 0x2400
2729 ; 24d0 C True from color 0x2400
2729 ; 24d2 C True from color 0x2400
2729 ; 24d4 C True from color 0x2400
2729 ; 24d6 C True from color 0x2400
2729 ; 24d8 C True from color 0x2400
2729 ; 24db C True from color 0x2400
2729 ; 24dd C True from color 0x2400
2729 ; 24df C True from color 0x2400
2729 ; 24e1 C True from color 0x2400
2729 ; 24e4 C True from color 0x2400
2729 ; 24e6 C True from color 0x2400
2729 ; 24e8 C True from color 0x2400
2729 ; 24ea C True from color 0x2400
2729 ; 24ec C True from color 0x2400
2729 ; 24ee C True from color 0x2400
2729 ; 24f0 C True from color 0x2400
2729 ; 24f2 C True from color 0x2400
2729 ; 24f5 C True from color 0x2400
2729 ; 24f7 C True from color 0x2400
2729 ; 24f9 C True from color 0x2400
2729 ; 24fb C True from color 0x2400
2729 ; --------------------------------------------------------------------------------------
2729 MAR_ERROR:
2729 2729 <halt> ; Flow R
272a 272a seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
272b ; --------------------------------------------------------------------------------------
272b ; Comes from:
272b ; 255b C True from color 0x2553
272b ; 2560 C True from color 0x2553
272b ; --------------------------------------------------------------------------------------
272b MEM_BOARDS_NOT_ALL_SAME_SIZE:
272b 272b <halt> ; Flow R
272c 272c seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
272d ; --------------------------------------------------------------------------------------
272d ; Comes from:
272d ; 2505 C True from color 0x2503
272d ; 2507 C True from color 0x2503
272d ; 250a C True from color 0x2503
272d ; 2515 C True from color 0x2512
272d ; 2518 C True from color 0x2512
272d ; 2520 C True from color 0x251b
272d ; 2524 C True from color 0x251b
272d ; 252b C True from color 0x2527
272d ; 2533 C True from color 0x2527
272d ; 2542 C True from color 0x2527
272d ; 254c C True from color 0x2527
272d ; --------------------------------------------------------------------------------------
272d TAG_STORE_DATA_ERROR:
272d 272d <halt> ; Flow R
272e 272e seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
272f ; --------------------------------------------------------------------------------------
272f ; Comes from:
272f ; 25a6 C True from color 0x25a2
272f ; 25a9 C True from color 0x25a2
272f ; 25ac C True from color 0x25a2
272f ; 25af C True from color 0x25a2
272f ; 25b2 C True from color 0x25a2
272f ; 25b5 C True from color 0x25a2
272f ; 25b8 C True from color 0x25a2
272f ; 25be C True from color 0x25a2
272f ; 25c1 C True from color 0x25a2
272f ; 25c4 C True from color 0x25a2
272f ; 25c7 C True from color 0x25a2
272f ; 25ca C True from color 0x25a2
272f ; 2616 C True from color 0x2400
272f ; 2619 C True from color 0x2400
272f ; 261c C True from color 0x2400
272f ; 261f C True from color 0x2400
272f ; 2622 C True from color 0x2400
272f ; 2625 C True from color 0x2400
272f ; 2628 C True from color 0x2400
272f ; 262b C True from color 0x2400
272f ; 262e C True from color 0x2400
272f ; 2631 C True from color 0x2400
272f ; 2634 C True from color 0x2400
272f ; 2637 C True from color 0x2400
272f ; 263c C True from color 0x2400
272f ; 2646 C True from color 0x2400
272f ; --------------------------------------------------------------------------------------
272f HASH_ERROR:
272f 272f <halt> ; Flow R
2730 2730 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2731 ; --------------------------------------------------------------------------------------
2731 ; Comes from:
2731 ; 265f C True from color 0x264f
2731 ; 2660 C True from color 0x264f
2731 ; 2663 C True from color 0x264f
2731 ; 2665 C True from color 0x264f
2731 ; 2666 C True from color 0x264f
2731 ; 266b C True from color 0x264f
2731 ; 266c C True from color 0x264f
2731 ; 266f C True from color 0x264f
2731 ; 2671 C True from color 0x264f
2731 ; 2672 C True from color 0x264f
2731 ; --------------------------------------------------------------------------------------
2731 TAG_STORE_COMPARE_ERROR:
2731 2731 <halt> ; Flow R
2732 2732 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2733 ; --------------------------------------------------------------------------------------
2733 ; Comes from:
2733 ; 2694 C True from color 0x2692
2733 ; 2696 C True from color 0x2692
2733 ; 269a C True from color 0x2692
2733 ; 26a6 C True from color 0x26a3
2733 ; 26a9 C True from color 0x26a3
2733 ; 26b2 C True from color 0x26ad
2733 ; 26b6 C True from color 0x26ad
2733 ; 26be C True from color 0x26b9
2733 ; 26c6 C True from color 0x26b9
2733 ; 26d0 C True from color 0x26b9
2733 ; 26d8 C True from color 0x26b9
2733 ; --------------------------------------------------------------------------------------
2733 RAM_PLANE_DATA_ERROR:
2733 2733 <halt> ; Flow R
2734 2734 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2735 2735 <halt> ; Flow R
2736 2736 <halt> ; Flow R
2737 2737 <halt> ; Flow R
2738 2738 <halt> ; Flow R
2739 2739 <halt> ; Flow R
273a 273a <halt> ; Flow R
273b 273b <halt> ; Flow R
273c 273c <halt> ; Flow R
273d 273d <halt> ; Flow R
273e 273e <halt> ; Flow R
273f 273f <halt> ; Flow R
2740 2740 <halt> ; Flow R
2741 2741 <halt> ; Flow R
2742 2742 <halt> ; Flow R
2743 2743 <halt> ; Flow R
2744 2744 <halt> ; Flow R
2745 2745 <halt> ; Flow R
2746 2746 <halt> ; Flow R
2747 2747 <halt> ; Flow R
2748 2748 <halt> ; Flow R
2749 2749 <halt> ; Flow R
274a 274a <halt> ; Flow R
274b 274b <halt> ; Flow R
274c 274c <halt> ; Flow R
274d 274d <halt> ; Flow R
274e 274e <halt> ; Flow R
274f 274f <halt> ; Flow R
2750 2750 <halt> ; Flow R
2751 2751 <halt> ; Flow R
2752 2752 <halt> ; Flow R
2753 2753 <halt> ; Flow R
2754 2754 <halt> ; Flow R
2755 2755 <halt> ; Flow R
2756 2756 <halt> ; Flow R
2757 2757 <halt> ; Flow R
2758 2758 <halt> ; Flow R
2759 2759 <halt> ; Flow R
275a 275a <halt> ; Flow R
275b 275b <halt> ; Flow R
275c 275c <halt> ; Flow R
275d 275d <halt> ; Flow R
275e 275e <halt> ; Flow R
275f 275f <halt> ; Flow R
2760 2760 <halt> ; Flow R
2761 2761 <halt> ; Flow R
2762 2762 <halt> ; Flow R
2763 2763 <halt> ; Flow R
2764 2764 <halt> ; Flow R
2765 2765 <halt> ; Flow R
2766 2766 <halt> ; Flow R
2767 2767 <halt> ; Flow R
2768 2768 <halt> ; Flow R
2769 2769 <halt> ; Flow R
276a 276a <halt> ; Flow R
276b 276b <halt> ; Flow R
276c 276c <halt> ; Flow R
276d 276d <halt> ; Flow R
276e 276e <halt> ; Flow R
276f 276f <halt> ; Flow R
2770 2770 <halt> ; Flow R
2771 2771 <halt> ; Flow R
2772 2772 <halt> ; Flow R
2773 2773 <halt> ; Flow R
2774 2774 <halt> ; Flow R
2775 2775 <halt> ; Flow R
2776 2776 <halt> ; Flow R
2777 2777 <halt> ; Flow R
2778 2778 <halt> ; Flow R
2779 2779 <halt> ; Flow R
277a 277a <halt> ; Flow R
277b 277b <halt> ; Flow R
277c 277c <halt> ; Flow R
277d 277d <halt> ; Flow R
277e 277e <halt> ; Flow R
277f 277f <halt> ; Flow R
2780 2780 <halt> ; Flow R
2781 2781 <halt> ; Flow R
2782 2782 <halt> ; Flow R
2783 2783 <halt> ; Flow R
2784 2784 <halt> ; Flow R
2785 2785 <halt> ; Flow R
2786 2786 <halt> ; Flow R
2787 2787 <halt> ; Flow R
2788 2788 <halt> ; Flow R
2789 2789 <halt> ; Flow R
278a 278a <halt> ; Flow R
278b 278b <halt> ; Flow R
278c 278c <halt> ; Flow R
278d 278d <halt> ; Flow R
278e 278e <halt> ; Flow R
278f 278f <halt> ; Flow R
2790 2790 <halt> ; Flow R
2791 2791 <halt> ; Flow R
2792 2792 <halt> ; Flow R
2793 2793 <halt> ; Flow R
2794 2794 <halt> ; Flow R
2795 2795 <halt> ; Flow R
2796 2796 <halt> ; Flow R
2797 2797 <halt> ; Flow R
2798 2798 <halt> ; Flow R
2799 2799 <halt> ; Flow R
279a 279a <halt> ; Flow R
279b 279b <halt> ; Flow R
279c 279c <halt> ; Flow R
279d 279d <halt> ; Flow R
279e 279e <halt> ; Flow R
279f 279f <halt> ; Flow R
27a0 27a0 <halt> ; Flow R
27a1 27a1 <halt> ; Flow R
27a2 27a2 <halt> ; Flow R
27a3 27a3 <halt> ; Flow R
27a4 27a4 <halt> ; Flow R
27a5 27a5 <halt> ; Flow R
27a6 27a6 <halt> ; Flow R
27a7 27a7 <halt> ; Flow R
27a8 27a8 <halt> ; Flow R
27a9 27a9 <halt> ; Flow R
27aa 27aa <halt> ; Flow R
27ab 27ab <halt> ; Flow R
27ac 27ac <halt> ; Flow R
27ad 27ad <halt> ; Flow R
27ae 27ae <halt> ; Flow R
27af 27af <halt> ; Flow R
27b0 27b0 <halt> ; Flow R
27b1 27b1 <halt> ; Flow R
27b2 27b2 <halt> ; Flow R
27b3 27b3 <halt> ; Flow R
27b4 27b4 <halt> ; Flow R
27b5 27b5 <halt> ; Flow R
27b6 27b6 <halt> ; Flow R
27b7 27b7 <halt> ; Flow R
27b8 27b8 <halt> ; Flow R
27b9 27b9 <halt> ; Flow R
27ba 27ba <halt> ; Flow R
27bb 27bb <halt> ; Flow R
27bc 27bc <halt> ; Flow R
27bd 27bd <halt> ; Flow R
27be 27be <halt> ; Flow R
27bf 27bf <halt> ; Flow R
27c0 27c0 <halt> ; Flow R
27c1 27c1 <halt> ; Flow R
27c2 27c2 <halt> ; Flow R
27c3 27c3 <halt> ; Flow R
27c4 27c4 <halt> ; Flow R
27c5 27c5 <halt> ; Flow R
27c6 27c6 <halt> ; Flow R
27c7 27c7 <halt> ; Flow R
27c8 27c8 <halt> ; Flow R
27c9 27c9 <halt> ; Flow R
27ca 27ca <halt> ; Flow R
27cb 27cb <halt> ; Flow R
27cc 27cc <halt> ; Flow R
27cd 27cd <halt> ; Flow R
27ce 27ce <halt> ; Flow R
27cf 27cf <halt> ; Flow R
27d0 27d0 <halt> ; Flow R
27d1 27d1 <halt> ; Flow R
27d2 27d2 <halt> ; Flow R
27d3 27d3 <halt> ; Flow R
27d4 27d4 <halt> ; Flow R
27d5 27d5 <halt> ; Flow R
27d6 27d6 <halt> ; Flow R
27d7 27d7 <halt> ; Flow R
27d8 27d8 <halt> ; Flow R
27d9 27d9 <halt> ; Flow R
27da 27da <halt> ; Flow R
27db 27db <halt> ; Flow R
27dc 27dc <halt> ; Flow R
27dd 27dd <halt> ; Flow R
27de 27de <halt> ; Flow R
27df 27df <halt> ; Flow R
27e0 27e0 <halt> ; Flow R
27e1 27e1 <halt> ; Flow R
27e2 27e2 <halt> ; Flow R
27e3 27e3 <halt> ; Flow R
27e4 27e4 <halt> ; Flow R
27e5 27e5 <halt> ; Flow R
27e6 27e6 <halt> ; Flow R
27e7 27e7 <halt> ; Flow R
27e8 27e8 <halt> ; Flow R
27e9 27e9 <halt> ; Flow R
27ea 27ea <halt> ; Flow R
27eb 27eb <halt> ; Flow R
27ec 27ec <halt> ; Flow R
27ed 27ed <halt> ; Flow R
27ee 27ee <halt> ; Flow R
27ef 27ef <halt> ; Flow R
27f0 27f0 <halt> ; Flow R
27f1 27f1 <halt> ; Flow R
27f2 27f2 <halt> ; Flow R
27f3 27f3 <halt> ; Flow R
27f4 27f4 <halt> ; Flow R
27f5 27f5 <halt> ; Flow R
27f6 27f6 <halt> ; Flow R
27f7 27f7 <halt> ; Flow R
27f8 27f8 <halt> ; Flow R
27f9 27f9 <halt> ; Flow R
27fa 27fa <halt> ; Flow R
27fb 27fb <halt> ; Flow R
27fc 27fc <halt> ; Flow R
27fd 27fd <halt> ; Flow R
27fe 27fe <halt> ; Flow R
27ff 27ff <halt> ; Flow R
2800 ; --------------------------------------------------------------------------------------
2800 ; 2800 - 29F7 MEM_TEST_TWO
2800 ; Comes from:
2800 ; 031c C from color DIAGNOSTIC_START
2800 ; --------------------------------------------------------------------------------------
2800 2800 typ_c_adr 1e TR1a:01
typ_c_mux_sel 0 ALU
typ_frame 1a
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2801 2801 fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2802 2802 <default>
2803 2803 seq_br_type 0 Branch False; Flow J cc=False 0x2805
seq_branch_adr 2805 0x2805
seq_cond_sel 6b CACHE_MISS~
2804 2804 typ_a_adr 21 TR1a:01
typ_alu_func 7 INC_A
typ_c_adr 1e TR1a:01
typ_c_mux_sel 0 ALU
typ_frame 1a
2805 2805 val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 26 VR05:06
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 5
2806 2806 seq_br_type 1 Branch True; Flow J cc=True 0x2801
seq_branch_adr 2801 0x2801
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 28 VR05:08
val_frame 5
2807 2807 val_alu_func 13 ONES
val_c_adr 1f TOP - 0x0
val_c_mux_sel 2 ALU
val_frame 1a
2808 2808 val_c_adr 1e VR1a:01
val_c_mux_sel 2 ALU
val_frame 1a
2809 2809 typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
280a 280a ioc_random 10 load checkbit register
typ_b_adr 3e TR17:1e
typ_frame 17
val_a_adr 2d VR10:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
280b 280b typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
280c 280c fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
typ_alu_func 13 ONES
typ_c_adr 1f TOP - 0x0
typ_c_mux_sel 0 ALU
typ_frame 1a
typ_mar_cntl f LOAD_MAR_RESERVED
280d 280d ioc_load_wdr 0
ioc_random 18 drive diagnostic checkbits
typ_b_adr 04 GP04
val_b_adr 04 GP04
280e 280e <default>
280f 280f fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
typ_mar_cntl f LOAD_MAR_RESERVED
2810 2810 <default>
2811 2811 ioc_tvbs c mem+mem+csa+dummy
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2812 2812 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f2
seq_br_type 5 Call True
seq_branch_adr 29f2 ECC_EVENT_NOT_TAKEN
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR1a:00
typ_alu_func 0 PASS_A
typ_frame 1a
2813 2813 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f4
seq_br_type 5 Call True
seq_branch_adr 29f4 ECC_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2814 2814 val_a_adr 04 GP04
val_alu_func 1 A_PLUS_B
val_b_adr 04 GP04
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2815 2815 seq_b_timing 0 Early Condition; Flow J cc=False 0x280c
seq_br_type 0 Branch False
seq_branch_adr 280c 0x280c
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 1 A_PLUS_B
typ_b_adr 04 GP04
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_rand 2 DEC_LOOP_COUNTER
2816 2816 typ_alu_func 13 ONES
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_a_adr 24 VR10:04
val_alu_func 0 PASS_A
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
val_frame 10
2817 2817 ioc_random 10 load checkbit register
typ_b_adr 3e TR17:1e
typ_frame 17
val_a_adr 2d VR10:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 10
2818 2818 typ_alu_func 13 ONES
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2819 2819 fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
typ_alu_func 13 ONES
typ_c_adr 1f TOP - 0x0
typ_c_mux_sel 0 ALU
typ_frame 1a
typ_mar_cntl b LOAD_MAR_DATA
281a 281a ioc_load_wdr 0
ioc_random 18 drive diagnostic checkbits
typ_b_adr 04 GP04
val_b_adr 04 GP04
281b 281b <default>
281c 281c fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
281d 281d <default>
281e 281e ioc_tvbs c mem+mem+csa+dummy
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
281f 281f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f2
seq_br_type 5 Call True
seq_branch_adr 29f2 ECC_EVENT_NOT_TAKEN
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR1a:00
typ_alu_func 0 PASS_A
typ_frame 1a
2820 2820 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f4
seq_br_type 5 Call True
seq_branch_adr 29f4 ECC_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2821 2821 val_a_adr 04 GP04
val_alu_func 4 LEFT_I_A_INC
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2822 2822 seq_b_timing 0 Early Condition; Flow J cc=False 0x2819
seq_br_type 0 Branch False
seq_branch_adr 2819 0x2819
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 1 A_PLUS_B
typ_b_adr 04 GP04
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_rand 4 CHECK_CLASS_A_LIT
val_rand 2 DEC_LOOP_COUNTER
2823 2823 typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2824 2824 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2825 2825 val_a_adr 23 VR04:03
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 4
2826 2826 typ_a_adr 27 TR04:07
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 05 GP05
val_alu_func 0 PASS_A
val_c_adr 14 VR1a:0b
val_c_mux_sel 2 ALU
val_frame 1a
2827 2827 typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_c_adr 14 TR1a:0b
typ_c_mux_sel 0 ALU
typ_frame 1a
val_a_adr 23 VR04:03
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2828 2828 typ_a_adr 3e TR17:1e
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 17
2829 2829 typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 2b TR1a:0b
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 1a
282a 282a ioc_random 10 load checkbit register
typ_b_adr 05 GP05
val_alu_func 13 ONES
val_c_adr 1e VR1a:01
val_c_mux_sel 2 ALU
val_frame 1a
282b 282b fiu_mem_start e start_physical_wr
ioc_adrbs 1 val
typ_alu_func 13 ONES
typ_c_adr 1f TOP - 0x0
typ_c_mux_sel 0 ALU
typ_frame 1a
typ_mar_cntl b LOAD_MAR_DATA
282c 282c ioc_load_wdr 0
ioc_random 18 drive diagnostic checkbits
typ_b_adr 04 GP04
val_b_adr 04 GP04
282d 282d <default>
282e 282e fiu_mem_start d start_physical_rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
282f 282f <default>
2830 2830 ioc_tvbs c mem+mem+csa+dummy
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2831 2831 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f2
seq_br_type 5 Call True
seq_branch_adr 29f2 ECC_EVENT_NOT_TAKEN
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 20 TR1a:00
typ_alu_func 0 PASS_A
typ_frame 1a
2832 2832 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f4
seq_br_type 5 Call True
seq_branch_adr 29f4 ECC_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2833 2833 typ_a_adr 2b TR1a:0b
typ_alu_func 3 LEFT_I_A
typ_c_adr 14 TR1a:0b
typ_c_mux_sel 0 ALU
typ_frame 1a
2834 2834 val_a_adr 2b VR1a:0b
val_alu_func 1c DEC_A
val_c_adr 14 VR1a:0b
val_c_mux_sel 2 ALU
val_frame 1a
2835 2835 seq_b_timing 0 Early Condition; Flow J cc=False 0x2828
seq_br_type 0 Branch False
seq_branch_adr 2828 0x2828
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_rand 2 DEC_LOOP_COUNTER
2836 2836 val_c_adr 1f TOP - 0x0
val_c_mux_sel 2 ALU
val_frame 1a
2837 2837 seq_en_micro 0
typ_a_adr 3d TR14:1d
typ_alu_func 1b A_OR_B
typ_b_adr 3f TR14:1f
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 14
2838 2838 fiu_tivi_src 8 type_var
ioc_adrbs 2 typ
seq_en_micro 0
typ_b_adr 01 GP01
typ_mar_cntl 4 RESTORE_MAR
2839 2839 fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 2 typ
ioc_load_wdr 0
seq_en_micro 0
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 2f VR15:0f
val_alu_func 0 PASS_A
val_b_adr 2f VR15:0f
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
283a 283a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_a_adr 3e TR14:1e
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 14
283b 283b fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_a_adr 3e TR14:1e
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 14
283c 283c fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_a_adr 3e TR14:1e
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_frame 14
283d 283d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 1e A_AND_B
typ_b_adr 39 TR04:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
283e 283e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 05 GP05
typ_alu_func 1e A_AND_B
typ_b_adr 3a TR04:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
283f 283f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 06 GP06
typ_alu_func 1e A_AND_B
typ_b_adr 39 TR04:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
2840 2840 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 06 GP06
typ_alu_func 1e A_AND_B
typ_b_adr 3a TR04:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
2841 2841 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 07 GP07
typ_alu_func 1e A_AND_B
typ_b_adr 39 TR04:19
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
2842 2842 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29d8
seq_br_type 5 Call True
seq_branch_adr 29d8 FLAG_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 1e A_AND_B
typ_b_adr 3a TR04:1a
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
2843 2843 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x294d
seq_br_type 1 Branch True
seq_branch_adr 294d 0x294d
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 0f GP0f
typ_alu_func 19 X_XOR_B
typ_b_adr 23 TR04:03
typ_frame 4
2844 2844 typ_a_adr 21 TR04:01
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
2845 2845 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2864
seq_br_type 1 Branch True
seq_branch_adr 2864 0x2864
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 21 TR1a:01
typ_alu_func 6 A_MINUS_B
typ_b_adr 05 GP05
typ_frame 1a
2846 2846 seq_br_type 7 Unconditional Call; Flow C 0x287b
seq_branch_adr 287b 0x287b
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2847 2847 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2848 2848 fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 20 TR18:00
typ_alu_func 0 PASS_A
typ_frame 18
typ_mar_cntl b LOAD_MAR_DATA
2849 2849 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
284a 284a typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
284b 284b fiu_mem_start 12 start_lru_query
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
284c 284c seq_br_type 7 Unconditional Call; Flow C 0x288a
seq_branch_adr 288a 0x288a
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_frame 4
284d 284d seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
284e 284e seq_br_type 1 Branch True; Flow J cc=True 0x284b
seq_branch_adr 284b 0x284b
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 1c DEC_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_a_adr 07 GP07
val_alu_func 7 INC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
284f 284f fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_frame 10
typ_mar_cntl b LOAD_MAR_DATA
2850 2850 seq_br_type 7 Unconditional Call; Flow C 0x2887
seq_branch_adr 2887 0x2887
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2851 2851 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2852 2852 fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 3b TR04:1b
typ_alu_func 0 PASS_A
typ_frame 4
typ_mar_cntl b LOAD_MAR_DATA
2853 2853 val_a_adr 22 VR18:02
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR18:04
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
2854 2854 val_a_adr 20 VR0f:00
val_alu_func 1c DEC_A
val_c_adr 1f TOP - 0x0
val_c_mux_sel 2 ALU
val_frame f
2855 2855 seq_br_type 7 Unconditional Call; Flow C 0x2888
seq_branch_adr 2888 0x2888
typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2856 2856 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2857 2857 fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 22 TR18:02
typ_alu_func 0 PASS_A
typ_frame 18
typ_mar_cntl b LOAD_MAR_DATA
2858 2858 val_a_adr 22 VR18:02
val_alu_func 1 A_PLUS_B
val_b_adr 24 VR18:04
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
2859 2859 val_a_adr 20 VR0f:00
val_alu_func 1c DEC_A
val_c_adr 1f TOP - 0x0
val_c_mux_sel 2 ALU
val_frame f
val_rand 2 DEC_LOOP_COUNTER
285a 285a seq_br_type 7 Unconditional Call; Flow C 0x2888
seq_branch_adr 2888 0x2888
typ_a_adr 22 TR04:02
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
285b 285b seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
285c 285c fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 22 TR18:02
typ_alu_func 0 PASS_A
typ_frame 18
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 23 VR04:03
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
285d 285d fiu_mem_start 12 start_lru_query
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 1e VR0f:01
val_c_mux_sel 2 ALU
val_frame f
285e 285e <default>
285f 285f fiu_mem_start 12 start_lru_query
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_c_adr 1d VR0f:02
val_c_mux_sel 2 ALU
val_frame f
2860 2860 seq_br_type 7 Unconditional Call; Flow C 0x288a
seq_branch_adr 288a 0x288a
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2861 2861 seq_br_type 7 Unconditional Call; Flow C 0x288a
seq_branch_adr 288a 0x288a
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 23 VR04:03
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2862 2862 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2863 2863 seq_br_type 3 Unconditional Branch; Flow J 0x288b
seq_branch_adr 288b 0x288b
2864 2864 seq_br_type 7 Unconditional Call; Flow C 0x287b
seq_branch_adr 287b 0x287b
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2865 2865 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2866 2866 fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 21 TR18:01
typ_alu_func 0 PASS_A
typ_frame 18
typ_mar_cntl b LOAD_MAR_DATA
2867 2867 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2868 2868 typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
2869 2869 fiu_mem_start 12 start_lru_query
val_a_adr 07 GP07
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
286a 286a seq_br_type 7 Unconditional Call; Flow C 0x288a
seq_branch_adr 288a 0x288a
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_frame 4
286b 286b seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
286c 286c seq_br_type 1 Branch True; Flow J cc=True 0x2869
seq_branch_adr 2869 0x2869
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 1c DEC_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_a_adr 07 GP07
val_alu_func 7 INC_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
286d 286d fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 20 TR10:00
typ_alu_func 0 PASS_A
typ_frame 10
typ_mar_cntl b LOAD_MAR_DATA
286e 286e seq_br_type 7 Unconditional Call; Flow C 0x2887
seq_branch_adr 2887 0x2887
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 24 VR04:04
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
286f 286f seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2870 2870 fiu_mem_start 3 start-wr; Flow C 0x2876
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 2876 0x2876
typ_a_adr 3c TR04:1c
typ_alu_func 0 PASS_A
typ_frame 4
typ_mar_cntl b LOAD_MAR_DATA
2871 2871 val_a_adr 22 VR18:02
val_alu_func 1 A_PLUS_B
val_b_adr 25 VR18:05
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
2872 2872 val_a_adr 20 VR0f:00
val_alu_func 1c DEC_A
val_c_adr 1f TOP - 0x0
val_c_mux_sel 2 ALU
val_frame f
2873 2873 seq_br_type 7 Unconditional Call; Flow C 0x2888
seq_branch_adr 2888 0x2888
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 24 VR04:04
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 4
2874 2874 seq_br_type 7 Unconditional Call; Flow C 0x2881
seq_branch_adr 2881 0x2881
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
2875 2875 seq_br_type 3 Unconditional Branch; Flow J 0x28d0
seq_branch_adr 28d0 0x28d0
2876 ; --------------------------------------------------------------------------------------
2876 ; Comes from:
2876 ; 2848 C from color 0x2800
2876 ; 284f C from color 0x2800
2876 ; 2852 C from color 0x2800
2876 ; 2857 C from color 0x2800
2876 ; 285c C from color 0x2800
2876 ; 2866 C from color 0x2800
2876 ; 286d C from color 0x2800
2876 ; 2870 C from color 0x2800
2876 ; --------------------------------------------------------------------------------------
2876 2876 ioc_load_wdr 0
typ_b_adr 20 TR11:00
typ_frame 11
val_b_adr 21 VR11:01
val_frame 11
2877 2877 fiu_mem_start 2 start-rd; Flow C cc=False 0x29e8
seq_b_timing 3 Late Condition, Hint False
seq_br_type 4 Call False
seq_branch_adr 29e8 LRU_MRU_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2878 2878 fiu_mem_start 3 start-wr; Flow C cc=False 0x29e8
ioc_tvbs c mem+mem+csa+dummy
seq_br_type 4 Call False
seq_branch_adr 29e8 LRU_MRU_ERROR
seq_cond_sel 6b CACHE_MISS~
typ_a_adr 20 TR11:00
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 11
val_a_adr 21 VR11:01
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 11
2879 2879 ioc_load_wdr 0
typ_b_adr 21 TR11:01
typ_frame 11
val_b_adr 20 VR11:00
val_frame 11
287a 287a seq_br_type a Unconditional Return; Flow R
287b ; --------------------------------------------------------------------------------------
287b ; Comes from:
287b ; 2846 C from color 0x2800
287b ; 2864 C from color 0x2800
287b ; --------------------------------------------------------------------------------------
287b 287b val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
287c 287c typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
287d 287d val_a_adr 23 VR18:03
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
287e 287e fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 2 typ
typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
287f 287f ioc_load_wdr 0
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_b_adr 07 GP07
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2880 2880 seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x287e
seq_br_type 8 Return True
seq_branch_adr 287e 0x287e
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR05:04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 29 VR18:09
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
val_rand 1 INC_LOOP_COUNTER
2881 ; --------------------------------------------------------------------------------------
2881 ; Comes from:
2881 ; 2847 C from color 0x2800
2881 ; 2849 C from color 0x2800
2881 ; 284d C from color 0x2800
2881 ; 2851 C from color 0x2800
2881 ; 2856 C from color 0x2800
2881 ; 285b C from color 0x2800
2881 ; 2862 C from color 0x2800
2881 ; 2865 C from color 0x2800
2881 ; 2867 C from color 0x2800
2881 ; 286b C from color 0x2800
2881 ; 286f C from color 0x2800
2881 ; 2874 C from color 0x2800
2881 ; --------------------------------------------------------------------------------------
2881 2881 typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
2882 2882 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 13 LOOP_REG
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2883 2883 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
2884 2884 fiu_len_fill_lit 43 zero-fill 0x3
fiu_load_var 1 hold_var
fiu_offs_lit 74
fiu_rdata_src 0 rotator
fiu_tivi_src 9 type_val
fiu_vmux_sel 1 fill value
ioc_tvbs 8 typ+mem
seq_en_micro 0
2885 2885 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x29e8
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29e8 LRU_MRU_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
2886 2886 seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x2882
seq_br_type 8 Return True
seq_branch_adr 2882 0x2882
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR05:04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
2887 ; --------------------------------------------------------------------------------------
2887 ; Comes from:
2887 ; 2850 C from color 0x2800
2887 ; 286e C from color 0x2800
2887 ; --------------------------------------------------------------------------------------
2887 2887 val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
2888 ; --------------------------------------------------------------------------------------
2888 ; Comes from:
2888 ; 2855 C from color 0x2800
2888 ; 285a C from color 0x2800
2888 ; 2873 C from color 0x2800
2888 ; --------------------------------------------------------------------------------------
2888 2888 typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 06 GP06
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
2889 2889 seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x2889
seq_br_type 8 Return True
seq_branch_adr 2889 0x2889
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 13 LOOP_REG
val_alu_func 1c DEC_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
288a ; --------------------------------------------------------------------------------------
288a ; Comes from:
288a ; 284c C from color 0x2800
288a ; 2860 C from color 0x2800
288a ; 2861 C from color 0x2800
288a ; 286a C from color 0x2800
288a ; --------------------------------------------------------------------------------------
288a 288a seq_br_type 3 Unconditional Branch; Flow J 0x2889
seq_branch_adr 2889 0x2889
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 22 VR18:02
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 18
288b 288b fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
288c 288c <default>
288d 288d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
288e 288e fiu_mem_start 13 start_available_query
288f 288f seq_en_micro 0
typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
2890 2890 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR05:04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
2891 2891 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_mar_cntl f LOAD_MAR_RESERVED
2892 2892 fiu_mem_start 15 setup_tag_read
2893 2893 fiu_mem_start 10 start_physical_tag_wr
ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
2894 2894 ioc_load_wdr 0
val_b_adr 05 GP05
2895 2895 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
2896 2896 <default>
2897 2897 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2898 2898 fiu_mem_start 13 start_available_query
2899 2899 seq_en_micro 0
289a 289a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x29f6
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 3 tar_frame
seq_br_type 4 Call False
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
289b 289b fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 18
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
typ_c_adr 3a GP05
typ_c_source 0 FIU_BUS
289c 289c fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x29f6
fiu_offs_lit 0c
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 39 GP06
typ_c_source 0 FIU_BUS
typ_frame 4
289d 289d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR04:01
typ_frame 4
289e 289e fiu_mem_start f start_physical_tag_rd
fiu_tivi_src 3 tar_frame
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 26 VR18:06
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 18
289f 289f fiu_mem_start 15 setup_tag_read
28a0 28a0 ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28a1 28a1 fiu_mem_start 10 start_physical_tag_wr
val_a_adr 2a VR18:0a
val_alu_func 1b A_OR_B
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28a2 28a2 ioc_load_wdr 0
val_b_adr 05 GP05
28a3 28a3 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
28a4 28a4 <default>
28a5 28a5 seq_br_type 4 Call False; Flow C cc=False 0x29f6
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28a6 28a6 typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
28a7 28a7 seq_br_type 7 Unconditional Call; Flow C 0x28ad
seq_branch_adr 28ad 0x28ad
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
28a8 28a8 typ_a_adr 39 TR04:19
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 2e VR18:0e
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
28a9 28a9 seq_br_type 7 Unconditional Call; Flow C 0x28b0
seq_branch_adr 28b0 0x28b0
seq_cond_sel 16 VAL.TRUE(early)
seq_latch 1
typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
28aa 28aa typ_a_adr 23 TR04:03
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
28ab 28ab seq_br_type 7 Unconditional Call; Flow C 0x28b9
seq_branch_adr 28b9 0x28b9
typ_a_adr 39 TR04:19
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
28ac 28ac seq_br_type 3 Unconditional Branch; Flow J 0x294d
seq_branch_adr 294d 0x294d
28ad ; --------------------------------------------------------------------------------------
28ad ; Comes from:
28ad ; 28a7 C from color 0x2800
28ad ; 28ec C from color 0x2800
28ad ; --------------------------------------------------------------------------------------
28ad 28ad fiu_mem_start 10 start_physical_tag_wr
ioc_adrbs 2 typ
typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_mar_cntl f LOAD_MAR_RESERVED
28ae 28ae ioc_load_wdr 0
typ_rand d SET_PASS_PRIVACY_BIT
val_b_adr 07 GP07
28af 28af seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x28ad
seq_br_type 8 Return True
seq_branch_adr 28ad 0x28ad
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR05:04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 28 VR04:08
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 4
28b0 ; --------------------------------------------------------------------------------------
28b0 ; Comes from:
28b0 ; 28a9 C from color 0x2800
28b0 ; 28ee C from color 0x2800
28b0 ; --------------------------------------------------------------------------------------
28b0 28b0 fiu_mem_start 2 start-rd; Flow C 0x28c2
ioc_adrbs 2 typ
seq_br_type 7 Unconditional Call
seq_branch_adr 28c2 0x28c2
typ_a_adr 06 GP06
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
typ_rand d SET_PASS_PRIVACY_BIT
28b1 28b1 seq_b_timing 0 Early Condition; Flow J cc=False 0x28b0
seq_br_type 0 Branch False
seq_branch_adr 28b0 0x28b0
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 06 GP06
typ_alu_func 1 A_PLUS_B
typ_b_adr 39 TR04:19
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 07 GP07
val_alu_func 1 A_PLUS_B
val_b_adr 39 VR04:19
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 4
28b2 28b2 fiu_mem_start 2 start-rd
ioc_adrbs 2 typ
typ_a_adr 06 GP06
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
28b3 28b3 <default>
28b4 28b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28b5 28b5 fiu_mem_start 13 start_available_query
28b6 28b6 <default>
28b7 28b7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28b8 28b8 seq_br_type a Unconditional Return; Flow R
28b9 ; --------------------------------------------------------------------------------------
28b9 ; Comes from:
28b9 ; 28ab C from color 0x2800
28b9 ; 28f0 C from color 0x2800
28b9 ; --------------------------------------------------------------------------------------
28b9 28b9 fiu_mem_start 2 start-rd
ioc_adrbs 2 typ
typ_a_adr 06 GP06
typ_alu_func 0 PASS_A
typ_mar_cntl b LOAD_MAR_DATA
typ_rand d SET_PASS_PRIVACY_BIT
28ba 28ba <default>
28bb 28bb seq_br_type 4 Call False; Flow C cc=False 0x29f6
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28bc 28bc seq_b_timing 0 Early Condition; Flow J cc=False 0x28b9
seq_br_type 0 Branch False
seq_branch_adr 28b9 0x28b9
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 06 GP06
typ_alu_func 1 A_PLUS_B
typ_b_adr 39 TR04:19
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
28bd 28bd fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_frame 4
28be 28be fiu_mem_start 15 setup_tag_read
28bf 28bf ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28c0 28c0 fiu_mem_start 10 start_physical_tag_wr
val_a_adr 05 GP05
val_alu_func 1b A_OR_B
val_b_adr 23 VR18:03
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28c1 28c1 ioc_load_wdr 0 ; Flow R
seq_br_type a Unconditional Return
val_b_adr 05 GP05
28c2 ; --------------------------------------------------------------------------------------
28c2 ; Comes from:
28c2 ; 28b0 C from color 0x28b0
28c2 ; --------------------------------------------------------------------------------------
28c2 28c2 <default>
28c3 28c3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28c4 28c4 fiu_mem_start 13 start_available_query
28c5 28c5 seq_en_micro 0
28c6 28c6 seq_br_type 4 Call False; Flow C cc=False 0x29f6
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28c7 28c7 fiu_mem_start f start_physical_tag_rd
fiu_tivi_src 3 tar_frame
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 26 VR18:06
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 18
28c8 28c8 fiu_mem_start 15 setup_tag_read
28c9 28c9 ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28ca 28ca fiu_mem_start 10 start_physical_tag_wr
val_a_adr 07 GP07
val_alu_func 1b A_OR_B
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
28cb 28cb ioc_load_wdr 0 ; Flow R cc=True
seq_b_timing 1 Latch Condition
seq_br_type 8 Return True
seq_branch_adr 28cc 0x28cc
seq_cond_sel 17 VAL.FALSE(early)
seq_latch 1
val_b_adr 05 GP05
28cc 28cc fiu_mem_start 2 start-rd
ioc_adrbs 2 typ
typ_a_adr 39 TR04:19
typ_alu_func 0 PASS_A
typ_frame 4
typ_mar_cntl b LOAD_MAR_DATA
28cd 28cd <default>
28ce 28ce seq_br_type 4 Call False; Flow C cc=False 0x29f6
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28cf 28cf seq_br_type a Unconditional Return; Flow R
28d0 28d0 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
28d1 28d1 <default>
28d2 28d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28d3 28d3 fiu_mem_start 13 start_available_query
28d4 28d4 seq_en_micro 0
typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
28d5 28d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 24 TR05:04
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
28d6 28d6 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_a_adr 05 GP05
typ_alu_func 0 PASS_A
typ_mar_cntl f LOAD_MAR_RESERVED
28d7 28d7 fiu_mem_start 15 setup_tag_read
28d8 28d8 fiu_mem_start 10 start_physical_tag_wr
ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28d9 28d9 ioc_load_wdr 0
val_b_adr 05 GP05
28da 28da fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
28db 28db <default>
28dc 28dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28dd 28dd fiu_mem_start 13 start_available_query
28de 28de seq_en_micro 0
28df 28df fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x29f6
fiu_load_tar 1 hold_tar
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 3 tar_frame
seq_br_type 4 Call False
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28e0 28e0 fiu_len_fill_lit 43 zero-fill 0x3
fiu_offs_lit 18
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
typ_c_adr 3a GP05
typ_c_source 0 FIU_BUS
28e1 28e1 fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x29f6
fiu_offs_lit 0c
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_c_adr 39 GP06
typ_c_source 0 FIU_BUS
typ_frame 4
28e2 28e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29f6
seq_br_type 5 Call True
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR04:01
typ_frame 4
28e3 28e3 fiu_mem_start f start_physical_tag_rd
fiu_tivi_src 3 tar_frame
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 26 VR18:06
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 18
28e4 28e4 fiu_mem_start 15 setup_tag_read
28e5 28e5 ioc_tvbs 8 typ+mem
val_a_adr 2b VR18:0b
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28e6 28e6 fiu_mem_start 10 start_physical_tag_wr
val_a_adr 2a VR18:0a
val_alu_func 1b A_OR_B
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 18
28e7 28e7 ioc_load_wdr 0
val_b_adr 05 GP05
28e8 28e8 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 3d VR04:1d
val_alu_func 0 PASS_A
val_frame 4
28e9 28e9 <default>
28ea 28ea seq_br_type 4 Call False; Flow C cc=False 0x29f6
seq_branch_adr 29f6 AVAIL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
28eb 28eb typ_a_adr 2d TR04:0d
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 4
28ec 28ec seq_br_type 7 Unconditional Call; Flow C 0x28ad
seq_branch_adr 28ad 0x28ad
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 20 VR10:00
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 10
28ed 28ed typ_a_adr 39 TR04:19
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 2e VR18:0e
val_alu_func 0 PASS_A
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
val_frame 18
28ee 28ee seq_br_type 7 Unconditional Call; Flow C 0x28b0
seq_branch_adr 28b0 0x28b0
seq_cond_sel 16 VAL.TRUE(early)
seq_latch 1
typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
28ef 28ef typ_a_adr 24 TR04:04
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 4
28f0 28f0 seq_br_type 7 Unconditional Call; Flow C 0x28b9
seq_branch_adr 28b9 0x28b9
typ_a_adr 39 TR04:19
typ_alu_func 0 PASS_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 4
28f1 28f1 seq_br_type 3 Unconditional Branch; Flow J 0x294d
seq_branch_adr 294d 0x294d
28f2 28f2 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_alu_func 1a PASS_B
typ_b_adr 01 GP01
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 2f VR15:0f
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 15
28f3 28f3 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
28f4 28f4 ioc_tvbs 8 typ+mem; Flow C cc=True 0x29f0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f0 VERIFY_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
28f5 28f5 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_mar_cntl b LOAD_MAR_DATA
28f6 28f6 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
28f7 28f7 ioc_tvbs 8 typ+mem; Flow C cc=True 0x29f0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f0 VERIFY_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
28f8 28f8 fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_alu_func 1a PASS_B
typ_b_adr 06 GP06
typ_mar_cntl b LOAD_MAR_DATA
28f9 28f9 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
28fa 28fa ioc_tvbs 8 typ+mem; Flow C cc=True 0x29f0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f0 VERIFY_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
28fb 28fb fiu_mem_start f start_physical_tag_rd
ioc_adrbs 2 typ
typ_alu_func 1a PASS_B
typ_b_adr 07 GP07
typ_mar_cntl b LOAD_MAR_DATA
28fc 28fc fiu_mem_start 15 setup_tag_read
seq_en_micro 0
28fd 28fd ioc_tvbs 8 typ+mem; Flow C cc=True 0x29f0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29f0 VERIFY_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
28fe 28fe typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
28ff 28ff fiu_mem_start 3 start-wr
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl b LOAD_MAR_DATA
2900 2900 ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 04 GP04
val_b_adr 04 GP04
2901 2901 seq_en_micro 0
2902 2902 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x29ec
ioc_tvbs 1 typ+fiu
seq_br_type 4 Call False
seq_branch_adr 29ec LOGICAL_ERROR
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
val_a_adr 31 VR15:11
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
2903 2903 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ec
seq_br_type 5 Call True
seq_branch_adr 29ec LOGICAL_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 0d GP0d
val_alu_func 19 X_XOR_B
val_b_adr 33 VR15:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2904 2904 fiu_mem_start 15 setup_tag_read
seq_en_micro 0
2905 2905 ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
2906 2906 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ec
seq_br_type 5 Call True
seq_branch_adr 29ec LOGICAL_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2907 2907 fiu_mem_start 2 start-rd
seq_en_micro 0
2908 2908 seq_en_micro 0
2909 2909 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
290a 290a ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 36 GP09
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
290b 290b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ec
seq_br_type 5 Call True
seq_branch_adr 29ec LOGICAL_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 08 GP08
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 08 GP08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
290c 290c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ec
seq_br_type 5 Call True
seq_branch_adr 29ec LOGICAL_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 09 GP09
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 09 GP09
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
290d 290d fiu_mem_start 3 start-wr
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
290e 290e ioc_load_wdr 0
typ_b_adr 05 GP05
val_b_adr 05 GP05
290f 290f seq_br_type 7 Unconditional Call; Flow C 0x29d6
seq_branch_adr 29d6 0x29d6
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1e A_AND_B
val_b_adr 34 VR15:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 15
2910 2910 fiu_mem_start 15 setup_tag_read
2911 2911 ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
2912 2912 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ee
seq_br_type 5 Call True
seq_branch_adr 29ee TVR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2913 2913 ioc_fiubs 2 typ
typ_a_adr 05 GP05
val_c_adr 37 GP08
val_c_source 0 FIU_BUS
2914 2914 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 16
2915 2915 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e2
seq_br_type 5 Call True
seq_branch_adr 29e2 FRAME_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 09 GP09
val_alu_func 19 X_XOR_B
val_b_adr 08 GP08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2916 2916 fiu_mem_start 3 start-wr
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2917 2917 ioc_load_wdr 0
typ_b_adr 06 GP06
val_b_adr 06 GP06
2918 2918 seq_br_type 7 Unconditional Call; Flow C 0x29d6
seq_branch_adr 29d6 0x29d6
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 34 VR15:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 15
2919 2919 fiu_mem_start 15 setup_tag_read
291a 291a ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
291b 291b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ee
seq_br_type 5 Call True
seq_branch_adr 29ee TVR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
291c 291c ioc_fiubs 2 typ
typ_a_adr 06 GP06
val_c_adr 37 GP08
val_c_source 0 FIU_BUS
291d 291d fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 16
291e 291e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e2
seq_br_type 5 Call True
seq_branch_adr 29e2 FRAME_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 09 GP09
val_alu_func 19 X_XOR_B
val_b_adr 08 GP08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
291f 291f fiu_mem_start 3 start-wr
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 07 GP07
2920 2920 ioc_load_wdr 0
typ_b_adr 07 GP07
val_b_adr 07 GP07
2921 2921 seq_br_type 7 Unconditional Call; Flow C 0x29d6
seq_branch_adr 29d6 0x29d6
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1e A_AND_B
val_b_adr 34 VR15:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 15
2922 2922 fiu_mem_start 15 setup_tag_read
2923 2923 ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
2924 2924 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ee
seq_br_type 5 Call True
seq_branch_adr 29ee TVR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2925 2925 ioc_fiubs 2 typ
typ_a_adr 07 GP07
val_c_adr 37 GP08
val_c_source 0 FIU_BUS
2926 2926 fiu_tivi_src 3 tar_frame
ioc_tvbs 1 typ+fiu
val_a_adr 39 VR16:19
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 36 GP09
val_c_mux_sel 2 ALU
val_frame 16
2927 2927 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e2
seq_br_type 5 Call True
seq_branch_adr 29e2 FRAME_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 09 GP09
val_alu_func 19 X_XOR_B
val_b_adr 08 GP08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2928 2928 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2929 2929 <default>
292a 292a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29dc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29dc READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 06 GP06
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
292b 292b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29dc
seq_br_type 5 Call True
seq_branch_adr 29dc READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
292c 292c seq_br_type 7 Unconditional Call; Flow C 0x29d6
seq_branch_adr 29d6 0x29d6
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 1e A_AND_B
val_b_adr 34 VR15:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 15
292d 292d fiu_mem_start 15 setup_tag_read
292e 292e ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
292f 292f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ee
seq_br_type 5 Call True
seq_branch_adr 29ee TVR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2930 2930 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 07 GP07
2931 2931 <default>
2932 2932 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29dc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29dc READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2933 2933 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29dc
seq_br_type 5 Call True
seq_branch_adr 29dc READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 08 GP08
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2934 2934 seq_br_type 7 Unconditional Call; Flow C 0x29d6
seq_branch_adr 29d6 0x29d6
seq_en_micro 0
val_a_adr 07 GP07
val_alu_func 1e A_AND_B
val_b_adr 34 VR15:14
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 15
2935 2935 fiu_mem_start 15 setup_tag_read
2936 2936 ioc_tvbs 8 typ+mem
seq_en_micro 0
val_a_adr 34 VR15:14
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 32 GP0d
val_c_mux_sel 2 ALU
val_frame 15
2937 2937 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ee
seq_br_type 5 Call True
seq_branch_adr 29ee TVR_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 0d GP0d
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2938 2938 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
2939 2939 <default>
293a 293a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x29e0
seq_br_type 4 Call False
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
293b 293b fiu_mem_start 5 start_rd_if_true
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
293c 293c <default>
293d 293d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29e0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
293e 293e seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
293f 293f fiu_mem_start 5 start_rd_if_true
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2940 2940 <default>
2941 2941 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29e0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2942 2942 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
2943 2943 <default>
2944 2944 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x29e0
seq_br_type 4 Call False
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2945 2945 typ_b_adr 24 TR10:04
typ_frame 10
typ_mar_cntl 1 RESTORE_RDR
val_b_adr 25 VR13:05
val_frame 13
2946 2946 fiu_mem_start 6 start_rd_if_false
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 05 GP05
val_alu_func 0 PASS_A
2947 2947 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29e0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 24 TR10:04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 25 VR13:05
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
2948 2948 seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
2949 2949 typ_b_adr 24 TR10:04
typ_frame 10
typ_mar_cntl 1 RESTORE_RDR
val_b_adr 25 VR13:05
val_frame 13
294a 294a fiu_mem_start 6 start_rd_if_false
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
val_a_adr 06 GP06
val_alu_func 0 PASS_A
294b 294b <default>
294c 294c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29e0
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29e0 COND_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 24 TR10:04
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 25 VR13:05
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 13
294d 294d typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
294e 294e val_alu_func 1a PASS_B
val_b_adr 37 VR15:17
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
294f 294f fiu_load_oreg 1 hold_oreg
fiu_mem_start 3 start-wr
fiu_oreg_src 0 rotator output
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
2950 2950 fiu_mem_start 4 continue; Flow J cc=False 0x2950
ioc_load_wdr 0
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2950 0x2950
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 0a GP0a
typ_alu_func 7 INC_A
typ_b_adr 0a GP0a
typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 0a GP0a
val_alu_func 7 INC_A
val_b_adr 0a GP0a
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2951 2951 ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 0a GP0a
val_b_adr 0a GP0a
2952 2952 seq_en_micro 0
2953 2953 fiu_tivi_src c mar_0xc; Flow C cc=True 0x29de
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29de PAGE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 35 VR15:15
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2954 2954 typ_a_adr 0a GP0a
typ_alu_func 7 INC_A
typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
val_a_adr 0a GP0a
val_alu_func 7 INC_A
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
2955 2955 val_alu_func 1a PASS_B
val_b_adr 37 VR15:17
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2956 2956 fiu_mem_start 3 start-wr; Flow J cc=False 0x2957
fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2957 0x2957
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
2957 2957 fiu_mem_start 4 continue; Flow J cc=False 0x2957
ioc_load_wdr 0
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2957 0x2957
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 0a GP0a
typ_alu_func 7 INC_A
typ_b_adr 0a GP0a
typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 0a GP0a
val_alu_func 7 INC_A
val_b_adr 0a GP0a
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2958 2958 ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 0a GP0a
val_b_adr 0a GP0a
2959 2959 seq_en_micro 0
295a 295a typ_c_adr 35 GP0a
typ_c_mux_sel 0 ALU
val_c_adr 35 GP0a
val_c_mux_sel 2 ALU
295b 295b typ_alu_func 1a PASS_B
typ_b_adr 20 TR16:00
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 36 VR15:16
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
295c 295c fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
295d 295d fiu_mem_start 4 continue
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
295e 295e fiu_mem_start 4 continue; Flow J cc=False 0x295e
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 295e 0x295e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
295f 295f ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 34 GP0b
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 34 GP0b
val_c_mux_sel 2 ALU
2960 2960 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 33 GP0c
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 33 GP0c
val_c_mux_sel 2 ALU
2961 2961 seq_en_micro 0
2962 2962 typ_alu_func 1a PASS_B
typ_b_adr 20 TR16:00
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 36 VR15:16
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2963 2963 typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2964 2964 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29de
seq_br_type 5 Call True
seq_branch_adr 29de PAGE_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2965 2965 seq_b_timing 0 Early Condition; Flow J cc=False 0x2964
seq_br_type 0 Branch False
seq_branch_adr 2964 0x2964
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2966 2966 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29de
seq_br_type 5 Call True
seq_branch_adr 29de PAGE_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 0b GP0b
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 0b GP0b
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2967 2967 typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2968 2968 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29de
seq_br_type 5 Call True
seq_branch_adr 29de PAGE_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 0c GP0c
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 0c GP0c
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2969 2969 fiu_tivi_src c mar_0xc; Flow C cc=False 0x29e4
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
296a 296a fiu_tivi_src c mar_0xc; Flow C cc=False 0x29e4
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
296b 296b fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
296c 296c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 22 VR17:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 17
296d 296d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 05 GP05
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
val_a_adr 05 GP05
val_alu_func 1e A_AND_B
val_b_adr 22 VR17:02
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 17
296e 296e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 06 GP06
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
296f 296f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR15:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2970 2970 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 35 VR15:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2971 2971 seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
2972 2972 fiu_tivi_src c mar_0xc; Flow C cc=True 0x29e4
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2973 2973 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 4
val_a_adr 01 GP01
val_alu_func 1e A_AND_B
val_b_adr 22 VR17:02
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
val_frame 17
2974 2974 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 35 VR15:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2975 2975 typ_alu_func 1a PASS_B
typ_b_adr 3a TR16:1a
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 38 VR15:18
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2976 2976 ioc_adrbs 2 typ
typ_mar_cntl b LOAD_MAR_DATA
2977 2977 fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2978 2978 seq_b_timing 0 Early Condition; Flow C cc=False 0x29e4
seq_br_type 4 Call False
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
2979 2979 seq_b_timing 0 Early Condition; Flow J cc=False 0x2977
seq_br_type 0 Branch False
seq_branch_adr 2977 0x2977
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
297a 297a fiu_tivi_src c mar_0xc
ioc_tvbs 3 fiu+fiu
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
297b 297b fiu_tivi_src c mar_0xc; Flow C cc=True 0x29e4
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
297c 297c fiu_tivi_src c mar_0xc; Flow C cc=False 0x29e4
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
297d 297d typ_alu_func 1a PASS_B
typ_b_adr 3a TR16:1a
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 38 VR15:18
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
297e 297e val_c_adr 3c GP03
val_c_mux_sel 2 ALU
297f 297f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
typ_rand d SET_PASS_PRIVACY_BIT
2980 2980 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2981 2981 seq_b_timing 0 Early Condition; Flow J cc=False 0x297f
seq_br_type 0 Branch False
seq_branch_adr 297f 0x297f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_a_adr 03 GP03
val_alu_func 1 A_PLUS_B
val_b_adr 27 VR04:07
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 4
2982 2982 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 01 GP01
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
2983 2983 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2984 2984 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 05 GP05
typ_alu_func 1e A_AND_B
typ_b_adr 3d TR04:1d
typ_frame 4
2985 2985 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 35 VR15:15
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 15
2986 2986 typ_a_adr 3c TR14:1c
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
val_a_adr 23 VR17:03
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2987 2987 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
2988 2988 fiu_mem_start 4 continue
typ_mar_cntl 6 INCREMENT_MAR
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
2989 2989 fiu_mem_start 4 continue; Flow J cc=False 0x2989
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2989 0x2989
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
298a 298a ioc_tvbs c mem+mem+csa+dummy
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
298b 298b ioc_tvbs c mem+mem+csa+dummy
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
298c 298c typ_a_adr 3c TR14:1c
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
val_a_adr 23 VR17:03
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
298d 298d typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
298e 298e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
298f 298f seq_b_timing 0 Early Condition; Flow J cc=False 0x298e
seq_br_type 0 Branch False
seq_branch_adr 298e 0x298e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2990 2990 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2991 2991 typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2992 2992 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29e4
seq_br_type 5 Call True
seq_branch_adr 29e4 PAGE_XING_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 06 GP06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2993 2993 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
typ_mar_cntl b LOAD_MAR_DATA
2994 2994 fiu_mem_start 9 start_continue_if_true
typ_mar_cntl 6 INCREMENT_MAR
2995 2995 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29ea
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2996 2996 ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2997 2997 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ea
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2998 2998 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
2999 2999 <default>
299a 299a <default>
299b 299b fiu_mem_start 2 start-rd
ioc_adrbs 1 val
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
typ_mar_cntl b LOAD_MAR_DATA
299c 299c fiu_mem_start a start_continue_if_false
typ_mar_cntl 6 INCREMENT_MAR
299d 299d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29ea
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
299e 299e ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
299f 299f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29ea
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29a0 29a0 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29a1 29a1 <default>
29a2 29a2 <default>
29a3 29a3 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
typ_mar_cntl b LOAD_MAR_DATA
29a4 29a4 fiu_mem_start a start_continue_if_false
typ_mar_cntl 6 INCREMENT_MAR
29a5 29a5 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29ea
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29a6 29a6 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29ea
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29ea COND_CONT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29a7 29a7 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29a8 29a8 <default>
29a9 29a9 <default>
29aa 29aa seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
29ab 29ab fiu_mem_start 5 start_rd_if_true
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
29ac 29ac fiu_mem_start d start_physical_rd
typ_mar_cntl 6 INCREMENT_MAR
29ad 29ad <default>
29ae 29ae ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
29af 29af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29da
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29b0 29b0 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29b1 29b1 <default>
29b2 29b2 <default>
29b3 29b3 seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
29b4 29b4 fiu_mem_start 6 start_rd_if_false
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
29b5 29b5 fiu_mem_start d start_physical_rd
typ_mar_cntl 6 INCREMENT_MAR
29b6 29b6 <default>
29b7 29b7 ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
29b8 29b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29da
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29b9 29b9 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29ba 29ba <default>
29bb 29bb <default>
29bc 29bc seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_latch 1
29bd 29bd fiu_mem_start 5 start_rd_if_true
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
29be 29be fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29bf 29bf <default>
29c0 29c0 ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
29c1 29c1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29da
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29c2 29c2 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29c3 29c3 <default>
29c4 29c4 <default>
29c5 29c5 seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
29c6 29c6 fiu_mem_start 6 start_rd_if_false
ioc_adrbs 1 val
typ_mar_cntl b LOAD_MAR_DATA
29c7 29c7 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29c8 29c8 <default>
29c9 29c9 ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
29ca 29ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29da
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29cb 29cb fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29cc 29cc <default>
29cd 29cd <default>
29ce 29ce fiu_mem_start 2 start-rd
ioc_adrbs 1 val
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_latch 1
typ_mar_cntl b LOAD_MAR_DATA
29cf 29cf fiu_mem_start a start_continue_if_false
typ_mar_cntl 6 INCREMENT_MAR
29d0 29d0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x29da
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
29d1 29d1 fiu_mem_start 2 start-rd
typ_mar_cntl 6 INCREMENT_MAR
29d2 29d2 <default>
29d3 29d3 ioc_tvbs c mem+mem+csa+dummy
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
29d4 29d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x29da
seq_br_type 5 Call True
seq_branch_adr 29da E_ABORT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR04:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 4
29d5 29d5 seq_br_type a Unconditional Return; Flow R
29d6 ; --------------------------------------------------------------------------------------
29d6 ; Comes from:
29d6 ; 290f C from color 0x2800
29d6 ; 2918 C from color 0x2800
29d6 ; 2921 C from color 0x2800
29d6 ; 292c C from color 0x2800
29d6 ; 2934 C from color 0x2800
29d6 ; --------------------------------------------------------------------------------------
29d6 29d6 seq_en_micro 0
29d7 29d7 fiu_mem_start f start_physical_tag_rd; Flow R
fiu_tivi_src 3 tar_frame
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
seq_br_type a Unconditional Return
typ_mar_cntl f LOAD_MAR_RESERVED
val_a_adr 26 VR18:06
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 18
29d8 ; --------------------------------------------------------------------------------------
29d8 ; Comes from:
29d8 ; 283d C True from color 0x2800
29d8 ; 283e C True from color 0x2800
29d8 ; 283f C True from color 0x2800
29d8 ; 2840 C True from color 0x2800
29d8 ; 2841 C True from color 0x2800
29d8 ; 2842 C True from color 0x2800
29d8 ; --------------------------------------------------------------------------------------
29d8 FLAG_ERROR:
29d8 29d8 <halt> ; Flow R
29d9 29d9 seq_br_type a Unconditional Return; Flow R
29da ; --------------------------------------------------------------------------------------
29da ; Comes from:
29da ; 29af C True from color 0x2800
29da ; 29b8 C True from color 0x2800
29da ; 29c1 C True from color 0x2800
29da ; 29ca C True from color 0x2800
29da ; 29d0 C True from color 0x2800
29da ; 29d4 C True from color 0x2800
29da ; --------------------------------------------------------------------------------------
29da E_ABORT_ERROR:
29da 29da <halt> ; Flow R
29db 29db seq_br_type a Unconditional Return; Flow R
29dc ; --------------------------------------------------------------------------------------
29dc ; Comes from:
29dc ; 292a C True from color 0x2800
29dc ; 292b C True from color 0x2800
29dc ; 2932 C True from color 0x2800
29dc ; 2933 C True from color 0x2800
29dc ; --------------------------------------------------------------------------------------
29dc READ_ERROR:
29dc 29dc <halt> ; Flow R
29dd 29dd seq_br_type a Unconditional Return; Flow R
29de ; --------------------------------------------------------------------------------------
29de ; Comes from:
29de ; 2953 C True from color 0x2800
29de ; 2964 C True from color 0x2800
29de ; 2966 C True from color 0x2800
29de ; 2968 C True from color 0x2800
29de ; --------------------------------------------------------------------------------------
29de PAGE_ERROR:
29de 29de <halt> ; Flow R
29df 29df seq_br_type a Unconditional Return; Flow R
29e0 ; --------------------------------------------------------------------------------------
29e0 ; Comes from:
29e0 ; 293a C False from color 0x2800
29e0 ; 293d C True from color 0x2800
29e0 ; 2941 C True from color 0x2800
29e0 ; 2944 C False from color 0x2800
29e0 ; 2947 C True from color 0x2800
29e0 ; 294c C True from color 0x2800
29e0 ; --------------------------------------------------------------------------------------
29e0 COND_ERROR:
29e0 29e0 <halt> ; Flow R
29e1 29e1 seq_br_type a Unconditional Return; Flow R
29e2 ; --------------------------------------------------------------------------------------
29e2 ; Comes from:
29e2 ; 2915 C True from color 0x2800
29e2 ; 291e C True from color 0x2800
29e2 ; 2927 C True from color 0x2800
29e2 ; --------------------------------------------------------------------------------------
29e2 FRAME_ERROR:
29e2 29e2 <halt> ; Flow R
29e3 29e3 seq_br_type a Unconditional Return; Flow R
29e4 ; --------------------------------------------------------------------------------------
29e4 ; Comes from:
29e4 ; 2969 C False from color 0x2800
29e4 ; 296a C False from color 0x2800
29e4 ; 296c C True from color 0x2800
29e4 ; 296d C True from color 0x2800
29e4 ; 296e C True from color 0x2800
29e4 ; 296f C True from color 0x2800
29e4 ; 2970 C True from color 0x2800
29e4 ; 2972 C True from color 0x2800
29e4 ; 2973 C True from color 0x2800
29e4 ; 2974 C True from color 0x2800
29e4 ; 2978 C False from color 0x2800
29e4 ; 297b C True from color 0x2800
29e4 ; 297c C False from color 0x2800
29e4 ; 297f C True from color 0x2800
29e4 ; 2980 C True from color 0x2800
29e4 ; 2982 C True from color 0x2800
29e4 ; 2983 C True from color 0x2800
29e4 ; 2984 C True from color 0x2800
29e4 ; 2985 C True from color 0x2800
29e4 ; 298e C True from color 0x2800
29e4 ; 2990 C True from color 0x2800
29e4 ; 2992 C True from color 0x2800
29e4 ; --------------------------------------------------------------------------------------
29e4 PAGE_XING_ERROR:
29e4 29e4 <halt> ; Flow R
29e5 29e5 seq_br_type a Unconditional Return; Flow R
29e6 INIT_ERROR:
29e6 29e6 <halt> ; Flow R
29e7 29e7 seq_br_type a Unconditional Return; Flow R
29e8 ; --------------------------------------------------------------------------------------
29e8 ; Comes from:
29e8 ; 2877 C False from color 0x2876
29e8 ; 2878 C False from color 0x2876
29e8 ; 2885 C True from color 0x2881
29e8 ; --------------------------------------------------------------------------------------
29e8 LRU_MRU_ERROR:
29e8 29e8 <halt> ; Flow R
29e9 29e9 seq_br_type a Unconditional Return; Flow R
29ea ; --------------------------------------------------------------------------------------
29ea ; Comes from:
29ea ; 2995 C True from color 0x2800
29ea ; 2997 C True from color 0x2800
29ea ; 299d C True from color 0x2800
29ea ; 299f C True from color 0x2800
29ea ; 29a5 C True from color 0x2800
29ea ; 29a6 C True from color 0x2800
29ea ; --------------------------------------------------------------------------------------
29ea COND_CONT_ERROR:
29ea 29ea <halt> ; Flow R
29eb 29eb seq_br_type a Unconditional Return; Flow R
29ec ; --------------------------------------------------------------------------------------
29ec ; Comes from:
29ec ; 2902 C False from color 0x2800
29ec ; 2903 C True from color 0x2800
29ec ; 2906 C True from color 0x2800
29ec ; 290b C True from color 0x2800
29ec ; 290c C True from color 0x2800
29ec ; --------------------------------------------------------------------------------------
29ec LOGICAL_ERROR:
29ec 29ec <halt> ; Flow R
29ed 29ed seq_br_type a Unconditional Return; Flow R
29ee ; --------------------------------------------------------------------------------------
29ee ; Comes from:
29ee ; 2912 C True from color 0x2800
29ee ; 291b C True from color 0x2800
29ee ; 2924 C True from color 0x2800
29ee ; 292f C True from color 0x2800
29ee ; 2937 C True from color 0x2800
29ee ; --------------------------------------------------------------------------------------
29ee TVR_ERROR:
29ee 29ee <halt> ; Flow R
29ef 29ef seq_br_type a Unconditional Return; Flow R
29f0 ; --------------------------------------------------------------------------------------
29f0 ; Comes from:
29f0 ; 28f4 C True from color 0x2800
29f0 ; 28f7 C True from color 0x2800
29f0 ; 28fa C True from color 0x2800
29f0 ; 28fd C True from color 0x2800
29f0 ; --------------------------------------------------------------------------------------
29f0 VERIFY_ERROR:
29f0 29f0 <halt> ; Flow R
29f1 29f1 seq_br_type a Unconditional Return; Flow R
29f2 ; --------------------------------------------------------------------------------------
29f2 ; Comes from:
29f2 ; 2812 C True from color 0x2800
29f2 ; 281f C True from color 0x2800
29f2 ; 2831 C True from color 0x2800
29f2 ; --------------------------------------------------------------------------------------
29f2 ECC_EVENT_NOT_TAKEN:
29f2 29f2 <halt> ; Flow R
29f3 29f3 seq_br_type a Unconditional Return; Flow R
29f4 ; --------------------------------------------------------------------------------------
29f4 ; Comes from:
29f4 ; 2813 C True from color 0x2800
29f4 ; 2820 C True from color 0x2800
29f4 ; 2832 C True from color 0x2800
29f4 ; --------------------------------------------------------------------------------------
29f4 ECC_ERROR:
29f4 29f4 <halt> ; Flow R
29f5 29f5 seq_br_type a Unconditional Return; Flow R
29f6 ; --------------------------------------------------------------------------------------
29f6 ; Comes from:
29f6 ; 288d C True from color 0x2800
29f6 ; 2890 C True from color 0x2800
29f6 ; 2897 C True from color 0x2800
29f6 ; 289a C False from color 0x2800
29f6 ; 289c C True from color 0x2800
29f6 ; 289d C True from color 0x2800
29f6 ; 28a5 C False from color 0x2800
29f6 ; 28b4 C True from color 0x28b0
29f6 ; 28b7 C True from color 0x28b0
29f6 ; 28bb C False from color 0x28b9
29f6 ; 28c3 C True from color 0x28c2
29f6 ; 28c6 C False from color 0x28c2
29f6 ; 28ce C False from color 0x28c2
29f6 ; 28d2 C True from color 0x2800
29f6 ; 28d5 C True from color 0x2800
29f6 ; 28dc C True from color 0x2800
29f6 ; 28df C False from color 0x2800
29f6 ; 28e1 C True from color 0x2800
29f6 ; 28e2 C True from color 0x2800
29f6 ; 28ea C False from color 0x2800
29f6 ; --------------------------------------------------------------------------------------
29f6 AVAIL_ERROR:
29f6 29f6 <halt> ; Flow R
29f7 29f7 seq_br_type a Unconditional Return; Flow R
29f8 29f8 <halt> ; Flow R
29f9 29f9 <halt> ; Flow R
29fa 29fa <halt> ; Flow R
29fb 29fb <halt> ; Flow R
29fc 29fc <halt> ; Flow R
29fd 29fd <halt> ; Flow R
29fe 29fe <halt> ; Flow R
29ff 29ff <halt> ; Flow R
2a00 2a00 <halt> ; Flow R
2a01 2a01 <halt> ; Flow R
2a02 2a02 <halt> ; Flow R
2a03 2a03 <halt> ; Flow R
2a04 2a04 <halt> ; Flow R
2a05 2a05 <halt> ; Flow R
2a06 2a06 <halt> ; Flow R
2a07 2a07 <halt> ; Flow R
2a08 2a08 <halt> ; Flow R
2a09 2a09 <halt> ; Flow R
2a0a 2a0a <halt> ; Flow R
2a0b 2a0b <halt> ; Flow R
2a0c 2a0c <halt> ; Flow R
2a0d 2a0d <halt> ; Flow R
2a0e 2a0e <halt> ; Flow R
2a0f 2a0f <halt> ; Flow R
2a10 2a10 <halt> ; Flow R
2a11 2a11 <halt> ; Flow R
2a12 2a12 <halt> ; Flow R
2a13 2a13 <halt> ; Flow R
2a14 2a14 <halt> ; Flow R
2a15 2a15 <halt> ; Flow R
2a16 2a16 <halt> ; Flow R
2a17 2a17 <halt> ; Flow R
2a18 2a18 <halt> ; Flow R
2a19 2a19 <halt> ; Flow R
2a1a 2a1a <halt> ; Flow R
2a1b 2a1b <halt> ; Flow R
2a1c 2a1c <halt> ; Flow R
2a1d 2a1d <halt> ; Flow R
2a1e 2a1e <halt> ; Flow R
2a1f 2a1f <halt> ; Flow R
2a20 2a20 <halt> ; Flow R
2a21 2a21 <halt> ; Flow R
2a22 2a22 <halt> ; Flow R
2a23 2a23 <halt> ; Flow R
2a24 2a24 <halt> ; Flow R
2a25 2a25 <halt> ; Flow R
2a26 2a26 <halt> ; Flow R
2a27 2a27 <halt> ; Flow R
2a28 2a28 <halt> ; Flow R
2a29 2a29 <halt> ; Flow R
2a2a 2a2a <halt> ; Flow R
2a2b 2a2b <halt> ; Flow R
2a2c 2a2c <halt> ; Flow R
2a2d 2a2d <halt> ; Flow R
2a2e 2a2e <halt> ; Flow R
2a2f 2a2f <halt> ; Flow R
2a30 2a30 <halt> ; Flow R
2a31 2a31 <halt> ; Flow R
2a32 2a32 <halt> ; Flow R
2a33 2a33 <halt> ; Flow R
2a34 2a34 <halt> ; Flow R
2a35 2a35 <halt> ; Flow R
2a36 2a36 <halt> ; Flow R
2a37 2a37 <halt> ; Flow R
2a38 2a38 <halt> ; Flow R
2a39 2a39 <halt> ; Flow R
2a3a 2a3a <halt> ; Flow R
2a3b 2a3b <halt> ; Flow R
2a3c 2a3c <halt> ; Flow R
2a3d 2a3d <halt> ; Flow R
2a3e 2a3e <halt> ; Flow R
2a3f 2a3f <halt> ; Flow R
2a40 2a40 <halt> ; Flow R
2a41 2a41 <halt> ; Flow R
2a42 2a42 <halt> ; Flow R
2a43 2a43 <halt> ; Flow R
2a44 2a44 <halt> ; Flow R
2a45 2a45 <halt> ; Flow R
2a46 2a46 <halt> ; Flow R
2a47 2a47 <halt> ; Flow R
2a48 2a48 <halt> ; Flow R
2a49 2a49 <halt> ; Flow R
2a4a 2a4a <halt> ; Flow R
2a4b 2a4b <halt> ; Flow R
2a4c 2a4c <halt> ; Flow R
2a4d 2a4d <halt> ; Flow R
2a4e 2a4e <halt> ; Flow R
2a4f 2a4f <halt> ; Flow R
2a50 2a50 <halt> ; Flow R
2a51 2a51 <halt> ; Flow R
2a52 2a52 <halt> ; Flow R
2a53 2a53 <halt> ; Flow R
2a54 2a54 <halt> ; Flow R
2a55 2a55 <halt> ; Flow R
2a56 2a56 <halt> ; Flow R
2a57 2a57 <halt> ; Flow R
2a58 2a58 <halt> ; Flow R
2a59 2a59 <halt> ; Flow R
2a5a 2a5a <halt> ; Flow R
2a5b 2a5b <halt> ; Flow R
2a5c 2a5c <halt> ; Flow R
2a5d 2a5d <halt> ; Flow R
2a5e 2a5e <halt> ; Flow R
2a5f 2a5f <halt> ; Flow R
2a60 2a60 <halt> ; Flow R
2a61 2a61 <halt> ; Flow R
2a62 2a62 <halt> ; Flow R
2a63 2a63 <halt> ; Flow R
2a64 2a64 <halt> ; Flow R
2a65 2a65 <halt> ; Flow R
2a66 2a66 <halt> ; Flow R
2a67 2a67 <halt> ; Flow R
2a68 2a68 <halt> ; Flow R
2a69 2a69 <halt> ; Flow R
2a6a 2a6a <halt> ; Flow R
2a6b 2a6b <halt> ; Flow R
2a6c 2a6c <halt> ; Flow R
2a6d 2a6d <halt> ; Flow R
2a6e 2a6e <halt> ; Flow R
2a6f 2a6f <halt> ; Flow R
2a70 2a70 <halt> ; Flow R
2a71 2a71 <halt> ; Flow R
2a72 2a72 <halt> ; Flow R
2a73 2a73 <halt> ; Flow R
2a74 2a74 <halt> ; Flow R
2a75 2a75 <halt> ; Flow R
2a76 2a76 <halt> ; Flow R
2a77 2a77 <halt> ; Flow R
2a78 2a78 <halt> ; Flow R
2a79 2a79 <halt> ; Flow R
2a7a 2a7a <halt> ; Flow R
2a7b 2a7b <halt> ; Flow R
2a7c 2a7c <halt> ; Flow R
2a7d 2a7d <halt> ; Flow R
2a7e 2a7e <halt> ; Flow R
2a7f 2a7f <halt> ; Flow R
2a80 2a80 <halt> ; Flow R
2a81 2a81 <halt> ; Flow R
2a82 2a82 <halt> ; Flow R
2a83 2a83 <halt> ; Flow R
2a84 2a84 <halt> ; Flow R
2a85 2a85 <halt> ; Flow R
2a86 2a86 <halt> ; Flow R
2a87 2a87 <halt> ; Flow R
2a88 2a88 <halt> ; Flow R
2a89 2a89 <halt> ; Flow R
2a8a 2a8a <halt> ; Flow R
2a8b 2a8b <halt> ; Flow R
2a8c 2a8c <halt> ; Flow R
2a8d 2a8d <halt> ; Flow R
2a8e 2a8e <halt> ; Flow R
2a8f 2a8f <halt> ; Flow R
2a90 2a90 <halt> ; Flow R
2a91 2a91 <halt> ; Flow R
2a92 2a92 <halt> ; Flow R
2a93 2a93 <halt> ; Flow R
2a94 2a94 <halt> ; Flow R
2a95 2a95 <halt> ; Flow R
2a96 2a96 <halt> ; Flow R
2a97 2a97 <halt> ; Flow R
2a98 2a98 <halt> ; Flow R
2a99 2a99 <halt> ; Flow R
2a9a 2a9a <halt> ; Flow R
2a9b 2a9b <halt> ; Flow R
2a9c 2a9c <halt> ; Flow R
2a9d 2a9d <halt> ; Flow R
2a9e 2a9e <halt> ; Flow R
2a9f 2a9f <halt> ; Flow R
2aa0 2aa0 <halt> ; Flow R
2aa1 2aa1 <halt> ; Flow R
2aa2 2aa2 <halt> ; Flow R
2aa3 2aa3 <halt> ; Flow R
2aa4 2aa4 <halt> ; Flow R
2aa5 2aa5 <halt> ; Flow R
2aa6 2aa6 <halt> ; Flow R
2aa7 2aa7 <halt> ; Flow R
2aa8 2aa8 <halt> ; Flow R
2aa9 2aa9 <halt> ; Flow R
2aaa 2aaa <halt> ; Flow R
2aab 2aab <halt> ; Flow R
2aac 2aac <halt> ; Flow R
2aad 2aad <halt> ; Flow R
2aae 2aae <halt> ; Flow R
2aaf 2aaf <halt> ; Flow R
2ab0 2ab0 <halt> ; Flow R
2ab1 2ab1 <halt> ; Flow R
2ab2 2ab2 <halt> ; Flow R
2ab3 2ab3 <halt> ; Flow R
2ab4 2ab4 <halt> ; Flow R
2ab5 2ab5 <halt> ; Flow R
2ab6 2ab6 <halt> ; Flow R
2ab7 2ab7 <halt> ; Flow R
2ab8 2ab8 <halt> ; Flow R
2ab9 2ab9 <halt> ; Flow R
2aba 2aba <halt> ; Flow R
2abb 2abb <halt> ; Flow R
2abc 2abc <halt> ; Flow R
2abd 2abd <halt> ; Flow R
2abe 2abe <halt> ; Flow R
2abf 2abf <halt> ; Flow R
2ac0 2ac0 <halt> ; Flow R
2ac1 2ac1 <halt> ; Flow R
2ac2 2ac2 <halt> ; Flow R
2ac3 2ac3 <halt> ; Flow R
2ac4 2ac4 <halt> ; Flow R
2ac5 2ac5 <halt> ; Flow R
2ac6 2ac6 <halt> ; Flow R
2ac7 2ac7 <halt> ; Flow R
2ac8 2ac8 <halt> ; Flow R
2ac9 2ac9 <halt> ; Flow R
2aca 2aca <halt> ; Flow R
2acb 2acb <halt> ; Flow R
2acc 2acc <halt> ; Flow R
2acd 2acd <halt> ; Flow R
2ace 2ace <halt> ; Flow R
2acf 2acf <halt> ; Flow R
2ad0 2ad0 <halt> ; Flow R
2ad1 2ad1 <halt> ; Flow R
2ad2 2ad2 <halt> ; Flow R
2ad3 2ad3 <halt> ; Flow R
2ad4 2ad4 <halt> ; Flow R
2ad5 2ad5 <halt> ; Flow R
2ad6 2ad6 <halt> ; Flow R
2ad7 2ad7 <halt> ; Flow R
2ad8 2ad8 <halt> ; Flow R
2ad9 2ad9 <halt> ; Flow R
2ada 2ada <halt> ; Flow R
2adb 2adb <halt> ; Flow R
2adc 2adc <halt> ; Flow R
2add 2add <halt> ; Flow R
2ade 2ade <halt> ; Flow R
2adf 2adf <halt> ; Flow R
2ae0 2ae0 <halt> ; Flow R
2ae1 2ae1 <halt> ; Flow R
2ae2 2ae2 <halt> ; Flow R
2ae3 2ae3 <halt> ; Flow R
2ae4 2ae4 <halt> ; Flow R
2ae5 2ae5 <halt> ; Flow R
2ae6 2ae6 <halt> ; Flow R
2ae7 2ae7 <halt> ; Flow R
2ae8 2ae8 <halt> ; Flow R
2ae9 2ae9 <halt> ; Flow R
2aea 2aea <halt> ; Flow R
2aeb 2aeb <halt> ; Flow R
2aec 2aec <halt> ; Flow R
2aed 2aed <halt> ; Flow R
2aee 2aee <halt> ; Flow R
2aef 2aef <halt> ; Flow R
2af0 2af0 <halt> ; Flow R
2af1 2af1 <halt> ; Flow R
2af2 2af2 <halt> ; Flow R
2af3 2af3 <halt> ; Flow R
2af4 2af4 <halt> ; Flow R
2af5 2af5 <halt> ; Flow R
2af6 2af6 <halt> ; Flow R
2af7 2af7 <halt> ; Flow R
2af8 2af8 <halt> ; Flow R
2af9 2af9 <halt> ; Flow R
2afa 2afa <halt> ; Flow R
2afb 2afb <halt> ; Flow R
2afc 2afc <halt> ; Flow R
2afd 2afd <halt> ; Flow R
2afe 2afe <halt> ; Flow R
2aff 2aff <halt> ; Flow R
2b00 ; --------------------------------------------------------------------------------------
2b00 ; 2B00 - 2C32 CSA_TEST
2b00 ; Comes from:
2b00 ; 031e C from color DIAGNOSTIC_START
2b00 ; --------------------------------------------------------------------------------------
2b00 2b00 seq_br_type 3 Unconditional Branch; Flow J 0x2b09
seq_branch_adr 2b09 0x2b09
seq_en_micro 0
2b01 ; --------------------------------------------------------------------------------------
2b01 ; Comes from:
2b01 ; 2b52 C from color 0x2b00
2b01 ; --------------------------------------------------------------------------------------
2b01 2b01 fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
2b02 2b02 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b03 2b03 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b04 2b04 seq_b_timing 0 Early Condition; Flow J cc=False 0x2b01
seq_br_type 0 Branch False
seq_branch_adr 2b01 0x2b01
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_rand 2 DEC_LOOP_COUNTER
2b05 2b05 fiu_tivi_src c mar_0xc; Flow C cc=False 0x2c1d
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
2b06 2b06 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b07 2b07 seq_b_timing 0 Early Condition; Flow C cc=True 0x2c1d
seq_br_type 5 Call True
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b08 2b08 ioc_adrbs 1 val ; Flow R
seq_br_type a Unconditional Return
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
2b09 2b09 seq_en_micro 0
typ_a_adr 3b TR17:1b
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 20 VR17:00
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b0a 2b0a seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 0 PASS_A
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
2b0b 2b0b seq_br_type 1 Branch True; Flow J cc=True 0x2b0a
seq_branch_adr 2b0a 0x2b0a
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_rand e CHECK_CLASS_SYSTEM_B
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 28 VR10:08
val_frame 10
val_rand 1 INC_LOOP_COUNTER
2b0c 2b0c ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 13 ONES
2b0d 2b0d seq_en_micro 0
val_a_adr 24 VR04:04
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2b0e 2b0e seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b0f 2b0f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2b12
seq_br_type 1 Branch True
seq_branch_adr 2b12 0x2b12
seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b10 2b10 seq_b_timing 0 Early Condition; Flow J cc=False 0x2b0e
seq_br_type 0 Branch False
seq_branch_adr 2b0e 0x2b0e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
val_rand 2 DEC_LOOP_COUNTER
2b11 2b11 seq_br_type 7 Unconditional Call; Flow C 0x2c29
seq_branch_adr 2c29 CANNOT_ALIGN_BOT_ERROR
seq_en_micro 0
2b12 2b12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2b
seq_br_type 5 Call True
seq_branch_adr 2c2b TYP_VAL_BOT_UNEQUAL_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 02 GP02
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2b13 2b13 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2b
seq_br_type 5 Call True
seq_branch_adr 2c2b TYP_VAL_BOT_UNEQUAL_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 02 GP02
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2b14 2b14 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 13 ONES
2b15 2b15 seq_en_micro 0
typ_a_adr 25 TR10:05
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 28 VR10:08
val_alu_func 0 PASS_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2b16 2b16 seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2b17 2b17 seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b18 2b18 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b19 2b19 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2d
seq_br_type 5 Call True
seq_branch_adr 2c2d DEC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2b1a 2b1a seq_b_timing 0 Early Condition; Flow J cc=False 0x2b17
seq_br_type 0 Branch False
seq_branch_adr 2b17 0x2b17
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 1c DEC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 1c DEC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2b1b 2b1b seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 14 BOT - 1
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 14 BOT - 1
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b1c 2b1c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c31
seq_br_type 5 Call True
seq_branch_adr 2c31 CSA_BOTM1_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b1d 2b1d seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b1e 2b1e seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b1f 2b1f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2d
seq_br_type 5 Call True
seq_branch_adr 2c2d DEC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR16:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 16
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR10:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2b20 2b20 seq_en_micro 0
typ_a_adr 3f TR16:1f
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 16
val_a_adr 33 VR10:13
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_frame 10
2b21 2b21 seq_en_micro 0
val_a_adr 2b VR16:0b
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2b22 2b22 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b23 2b23 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b24 2b24 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2f
seq_br_type 5 Call True
seq_branch_adr 2c2f INC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 03 GP03
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2b25 2b25 seq_b_timing 0 Early Condition; Flow J cc=False 0x2b22
seq_br_type 0 Branch False
seq_branch_adr 2b22 0x2b22
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 7 INC_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 7 INC_A
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2b26 2b26 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 14 BOT - 1
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 14 BOT - 1
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b27 2b27 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c31
seq_br_type 5 Call True
seq_branch_adr 2c31 CSA_BOTM1_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3c TR17:1c
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b28 2b28 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b29 2b29 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b2a 2b2a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2f
seq_br_type 5 Call True
seq_branch_adr 2c2f INC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b2b 2b2b seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b2c 2b2c seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b2d 2b2d seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b2e 2b2e seq_en_micro 0
val_a_adr 21 VR15:01
val_alu_func 1c DEC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2b2f 2b2f seq_b_timing 0 Early Condition; Flow J cc=False 0x2b2f
seq_br_type 0 Branch False
seq_branch_adr 2b2f 0x2b2f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
val_rand 2 DEC_LOOP_COUNTER
2b30 2b30 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b31 2b31 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2d
seq_br_type 5 Call True
seq_branch_adr 2c2d DEC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR16:1f
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 16
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 33 VR10:13
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 10
2b32 2b32 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 14 BOT - 1
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 14 BOT - 1
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b33 2b33 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c31
seq_br_type 5 Call True
seq_branch_adr 2c31 CSA_BOTM1_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b34 2b34 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b35 2b35 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b36 2b36 seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b37 2b37 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b38 2b38 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b39 2b39 seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b3a 2b3a seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b3b 2b3b seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b3c 2b3c seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b3d 2b3d seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b3e 2b3e seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b3f 2b3f seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b40 2b40 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b41 2b41 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b42 2b42 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b43 2b43 seq_en_micro 0
typ_csa_cntl 4 DEC_CSA_BOTTOM
2b44 2b44 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b45 2b45 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b46 2b46 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b47 2b47 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b48 2b48 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b49 2b49 seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b4a 2b4a seq_en_micro 0
typ_csa_cntl 5 INC_CSA_BOTTOM
2b4b 2b4b seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 15 BOT
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 15 BOT
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b4c 2b4c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c2f
seq_br_type 5 Call True
seq_branch_adr 2c2f INC_CSA_BOT_ERROR
seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late))
seq_en_micro 0
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TR17:1b
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 01 GP01
val_alu_func 19 X_XOR_B
val_b_adr 20 VR17:00
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2b4d 2b4d ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_frame 17
2b4e 2b4e ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
2b4f 2b4f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b50 2b50 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b51 2b51 seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 23 VR17:03
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b52 2b52 seq_br_type 7 Unconditional Call; Flow C 0x2b01
seq_branch_adr 2b01 0x2b01
seq_en_micro 0
2b53 2b53 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2b54 2b54 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_frame 17
2b55 2b55 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b56 2b56 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b57 2b57 fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
2b58 2b58 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b59 2b59 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b5a 2b5a fiu_tivi_src c mar_0xc; Flow C cc=False 0x2c1d
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 27 VR04:07
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 4
2b5b 2b5b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b5c 2b5c seq_b_timing 0 Early Condition; Flow C cc=True 0x2c1d
seq_br_type 5 Call True
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2b5d 2b5d ioc_adrbs 1 val ; Flow C 0x2b60
seq_br_type 7 Unconditional Call
seq_branch_adr 2b60 0x2b60
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
2b5e 2b5e ioc_adrbs 1 val ; Flow C 0x2b60
seq_br_type 7 Unconditional Call
seq_branch_adr 2b60 0x2b60
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 27 VR04:07
val_frame 4
2b5f 2b5f seq_br_type 3 Unconditional Branch; Flow J 0x2b66
seq_branch_adr 2b66 0x2b66
seq_en_micro 0
2b60 ; --------------------------------------------------------------------------------------
2b60 ; Comes from:
2b60 ; 2b5d C from color 0x2b00
2b60 ; 2b5e C from color 0x2b00
2b60 ; --------------------------------------------------------------------------------------
2b60 2b60 seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 25 VR04:05
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2b61 2b61 fiu_tivi_src c mar_0xc
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 20 VR05:00
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_frame 5
val_rand 9 PASS_A_HIGH
2b62 2b62 fiu_tivi_src c mar_0xc; Flow C cc=True 0x2c1b
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand a PASS_B_HIGH
2b63 2b63 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1 A_PLUS_B
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2b64 2b64 fiu_tivi_src c mar_0xc; Flow J cc=False 0x2b62
ioc_adrbs 1 val
ioc_tvbs 3 fiu+fiu
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2b62 0x2b62
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 05 GP05
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_rand 9 PASS_A_HIGH
2b65 2b65 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2b66 2b66 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 13 ONES
2b67 2b67 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b68 2b68 fiu_mem_start 10 start_physical_tag_wr
fiu_tivi_src 3 tar_frame
ioc_adrbs 1 val
ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 25 VR17:05
val_alu_func 1e A_AND_B
val_b_adr 16 CSA/VAL_BUS
val_frame 17
2b69 2b69 ioc_load_wdr 0
seq_en_micro 0
val_b_adr 26 VR17:06
val_frame 17
2b6a 2b6a seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 20 VR17:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b6b 2b6b seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2b6c 2b6c fiu_mem_start 3 start-wr
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b6d 2b6d ioc_load_wdr 0
seq_en_micro 0
typ_b_adr 05 GP05
val_b_adr 05 GP05
2b6e 2b6e seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_latch 1
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2b6f 2b6f fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2b6d
seq_b_timing 1 Latch Condition
seq_br_type 1 Branch True
seq_branch_adr 2b6d 0x2b6d
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
2b70 2b70 seq_b_timing 0 Early Condition; Flow J cc=False 0x2b71
seq_br_type 0 Branch False
seq_branch_adr 2b71 0x2b71
seq_cond_sel 6a PAGE_CROSSING~
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 3b TR17:1b
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 20 VR17:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b71 2b71 seq_en_micro 0
typ_alu_func 13 ONES
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
2b72 2b72 seq_br_type 1 Branch True; Flow J cc=True 0x2b71
seq_branch_adr 2b71 0x2b71
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_rand e CHECK_CLASS_SYSTEM_B
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2b73 2b73 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b74 2b74 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 3b TR17:1b
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 20 VR17:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b75 2b75 seq_en_micro 0
2b76 2b76 seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 0 PASS_A
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
2b77 2b77 seq_br_type 1 Branch True; Flow J cc=True 0x2b75
seq_branch_adr 2b75 0x2b75
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_rand e CHECK_CLASS_SYSTEM_B
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2b78 2b78 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 3b TR17:1b
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 20 VR17:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b79 2b79 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1f
seq_br_type 5 Call True
seq_branch_adr 2c1f CSA_INIT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2b7a 2b7a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1f
seq_br_type 5 Call True
seq_branch_adr 2c1f CSA_INIT_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2b7b 2b7b seq_br_type 1 Branch True; Flow J cc=True 0x2b79
seq_branch_adr 2b79 0x2b79
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_rand e CHECK_CLASS_SYSTEM_B
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2b7c 2b7c ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b7d 2b7d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 3b TR17:1b
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 20 VR17:00
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b7e 2b7e fiu_tivi_src c mar_0xc; Flow C cc=True 0x2c1b
ioc_tvbs 3 fiu+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2b7f 2b7f ioc_adrbs 1 val ; Flow C cc=False 0x2c1b
seq_br_type 4 Call False
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 05 GP05
2b80 2b80 fiu_mem_start 2 start-rd
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
2b81 2b81 seq_br_type 4 Call False; Flow C cc=False 0x2c1b
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b82 2b82 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b83 2b83 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_rand e CHECK_CLASS_SYSTEM_B
2b84 2b84 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
2b85 2b85 seq_br_type 1 Branch True; Flow J cc=True 0x2b80
seq_branch_adr 2b80 0x2b80
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 21 VR17:01
val_frame 17
2b86 2b86 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 2e TR16:0e
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b87 2b87 seq_en_micro 0
2b88 2b88 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b89 2b89 fiu_mem_start 3 start-wr
seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2b8a 2b8a ioc_load_wdr 0 ; Flow J cc=False 0x2c1b
seq_br_type 0 Branch False
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
typ_b_adr 05 GP05
val_b_adr 05 GP05
2b8b 2b8b seq_b_timing 0 Early Condition; Flow J cc=False 0x2b89
seq_br_type 0 Branch False
seq_branch_adr 2b89 0x2b89
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
2b8c 2b8c seq_en_micro 0
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
2b8d 2b8d seq_en_micro 0
val_a_adr 10 TOP
val_alu_func 0 PASS_A
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b8e 2b8e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c23
seq_br_type 5 Call True
seq_branch_adr 2c23 CSA_WRITE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2b8f 2b8f seq_en_micro 0
typ_a_adr 10 TOP
typ_alu_func 0 PASS_A
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
2b90 2b90 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c23
seq_br_type 5 Call True
seq_branch_adr 2c23 CSA_WRITE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_csa_cntl 3 POP_CSA
2b91 2b91 seq_br_type 1 Branch True; Flow J cc=True 0x2b8d
seq_branch_adr 2b8d 0x2b8d
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_rand e CHECK_CLASS_SYSTEM_B
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 28 VR17:08
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2b92 2b92 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 13 ONES
2b93 2b93 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 2e TR16:0e
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2b94 2b94 seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2b95 2b95 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 24 VR17:04
val_frame 17
2b96 2b96 fiu_mem_start 2 start-rd
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
2b97 2b97 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2c1b
seq_br_type 1 Branch True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2b98 2b98 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3e GP01
val_c_mux_sel 2 ALU
2b99 2b99 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c25
seq_br_type 5 Call True
seq_branch_adr 2c25 MEM_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
2b9a 2b9a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c25
seq_br_type 5 Call True
seq_branch_adr 2c25 MEM_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 01 GP01
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2b9b 2b9b seq_b_timing 0 Early Condition; Flow J cc=False 0x2b96
seq_br_type 0 Branch False
seq_branch_adr 2b96 0x2b96
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
2b9c 2b9c seq_en_micro 0
2b9d 2b9d seq_en_micro 0
2b9e 2b9e seq_br_type 7 Unconditional Call; Flow C 0x2be8
seq_branch_adr 2be8 0x2be8
seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 27 VR17:07
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 17
2b9f 2b9f seq_br_type 7 Unconditional Call; Flow C 0x2be8
seq_branch_adr 2be8 0x2be8
seq_en_micro 0
val_a_adr 27 VR17:07
val_alu_func 1 A_PLUS_B
val_b_adr 29 VR17:09
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 17
2ba0 2ba0 seq_br_type 7 Unconditional Call; Flow C 0x2be8
seq_branch_adr 2be8 0x2be8
seq_en_micro 0
val_a_adr 27 VR17:07
val_alu_func 1 A_PLUS_B
val_b_adr 2e VR17:0e
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 17
2ba1 2ba1 seq_br_type 7 Unconditional Call; Flow C 0x2be8
seq_branch_adr 2be8 0x2be8
seq_en_micro 0
val_a_adr 27 VR17:07
val_alu_func 1 A_PLUS_B
val_b_adr 2a VR17:0a
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
val_frame 17
2ba2 2ba2 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 17
2ba3 2ba3 seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2ba4 2ba4 seq_en_micro 0
typ_b_adr 05 GP05
typ_csa_cntl 2 PUSH_CSA
val_b_adr 05 GP05
2ba5 2ba5 seq_en_micro 0
typ_b_adr 05 GP05
typ_csa_cntl 2 PUSH_CSA
val_b_adr 05 GP05
2ba6 2ba6 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2ba7 2ba7 seq_br_type 4 Call False; Flow C cc=False 0x2c1b
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2ba8 2ba8 seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2ba9 2ba9 ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 34 TR04:14
typ_csa_cntl 1 START_POP_DOWN
typ_frame 4
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2baa 2baa seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
2bab 2bab ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bac 2bac seq_br_type 4 Call False; Flow C cc=False 0x2c1b
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bad 2bad seq_b_timing 0 Early Condition; Flow C cc=False 0x2c1d
seq_br_type 4 Call False
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2bae 2bae ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 3b TR16:1b
typ_csa_cntl 1 START_POP_DOWN
typ_frame 16
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_frame 17
2baf 2baf seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
2bb0 2bb0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bb1 2bb1 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
2bb2 2bb2 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 17
2bb3 2bb3 seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bb4 2bb4 seq_en_micro 0
typ_b_adr 05 GP05
typ_csa_cntl 2 PUSH_CSA
val_b_adr 05 GP05
2bb5 2bb5 seq_en_micro 0
typ_b_adr 05 GP05
typ_csa_cntl 2 PUSH_CSA
val_b_adr 05 GP05
2bb6 2bb6 ioc_adrbs 1 val ; Flow J cc=True 0x2bb9
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2bb9 0x2bb9
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 34 TR04:14
typ_csa_cntl 1 START_POP_DOWN
typ_frame 4
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bb7 2bb7 seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
2bb8 2bb8 seq_br_type 7 Unconditional Call; Flow C 0x2c27
seq_branch_adr 2c27 BAD_HINT_ERROR
seq_en_micro 0
2bb9 2bb9 seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
2bba 2bba ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 1 START_POP_DOWN
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 22 VR17:02
val_frame 17
2bbb 2bbb seq_en_micro 0
2bbc 2bbc seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
2bbd 2bbd ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
2bbe 2bbe ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bbf 2bbf seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bc0 2bc0 seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bc1 2bc1 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
2bc2 2bc2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bc3 2bc3 seq_b_timing 0 Early Condition; Flow J cc=False 0x2bc1
seq_br_type 0 Branch False
seq_branch_adr 2bc1 0x2bc1
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2bc4 2bc4 ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 34 TR04:14
typ_csa_cntl 1 START_POP_DOWN
typ_frame 4
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bc5 2bc5 seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bc6 2bc6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bc7 2bc7 seq_b_timing 0 Early Condition; Flow J cc=False 0x2bc6
seq_br_type 0 Branch False
seq_branch_adr 2bc6 0x2bc6
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
val_rand 2 DEC_LOOP_COUNTER
2bc8 2bc8 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bc9 2bc9 ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 2b VR17:0b
val_alu_func 1a PASS_B
val_b_adr 2f VR17:0f
val_frame 17
val_rand 9 PASS_A_HIGH
2bca 2bca seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bcb 2bcb seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bcc 2bcc seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
2bcd 2bcd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bce 2bce seq_b_timing 0 Early Condition; Flow J cc=False 0x2bcc
seq_br_type 0 Branch False
seq_branch_adr 2bcc 0x2bcc
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2bcf 2bcf ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 34 TR04:14
typ_csa_cntl 1 START_POP_DOWN
typ_frame 4
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bd0 2bd0 seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bd1 2bd1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bd2 2bd2 seq_b_timing 0 Early Condition; Flow J cc=False 0x2bd1
seq_br_type 0 Branch False
seq_branch_adr 2bd1 0x2bd1
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
val_rand 2 DEC_LOOP_COUNTER
2bd3 2bd3 ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl b LOAD_MAR_DATA
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bd4 2bd4 seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bd5 2bd5 seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bd6 2bd6 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
2bd7 2bd7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bd8 2bd8 seq_b_timing 0 Early Condition; Flow J cc=False 0x2bd6
seq_br_type 0 Branch False
seq_branch_adr 2bd6 0x2bd6
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2bd9 2bd9 ioc_adrbs 1 val
seq_en_micro 0
seq_int_reads 0 TYP VAL BUS
seq_random 0e Load_control_top+?
typ_b_adr 34 TR04:14
typ_csa_cntl 1 START_POP_DOWN
typ_frame 4
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bda 2bda seq_en_micro 0
typ_csa_cntl 7 FINISH_POP_DOWN
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bdb 2bdb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c1b
seq_br_type 5 Call True
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2bdc 2bdc seq_b_timing 0 Early Condition; Flow J cc=False 0x2bdb
seq_br_type 0 Branch False
seq_branch_adr 2bdb 0x2bdb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
val_rand 2 DEC_LOOP_COUNTER
2bdd 2bdd ioc_adrbs 1 val
seq_en_micro 0
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 2d VR04:0d
val_frame 4
2bde 2bde seq_en_micro 0
typ_csa_cntl 3 POP_CSA
2bdf 2bdf seq_en_micro 0
2be0 2be0 seq_b_timing 0 Early Condition; Flow C cc=True 0x2c1d
seq_br_type 5 Call True
seq_branch_adr 2c1d OUT_OF_RANGE_ERROR
seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE
seq_en_micro 0
2be1 2be1 seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 3c TR17:1c
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 21 VR17:01
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
val_frame 17
2be2 2be2 fiu_mem_start 2 start-rd; Flow C cc=False 0x2c1b
seq_br_type 4 Call False
seq_branch_adr 2c1b CSA_HIT_ERROR
seq_cond_sel 63 CSA_HIT
seq_en_micro 0
2be3 2be3 seq_en_micro 0
2be4 2be4 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2c21
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
val_a_adr 21 VR17:01
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 17
2be5 2be5 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2c21
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 3c TR17:1c
typ_alu_func 19 X_XOR_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 17
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
2be6 2be6 seq_en_micro 0
typ_csa_cntl 3 POP_CSA
2be7 2be7 seq_br_type a Unconditional Return; Flow R
seq_cond_sel 6b CACHE_MISS~
seq_en_micro 0
2be8 ; --------------------------------------------------------------------------------------
2be8 ; Comes from:
2be8 ; 2b9e C from color 0x2b00
2be8 ; 2b9f C from color 0x2b00
2be8 ; 2ba0 C from color 0x2b00
2be8 ; 2ba1 C from color 0x2b00
2be8 ; --------------------------------------------------------------------------------------
2be8 2be8 ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 13 ONES
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_alu_func 1a PASS_B
val_b_adr 2c VR17:0c
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2be9 2be9 fiu_mem_start 3 start-wr
ioc_adrbs 1 val
seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 27 VR17:07
val_frame 17
2bea 2bea fiu_mem_start 4 continue
ioc_load_wdr 0
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_b_adr 05 GP05
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 20 VR10:00
val_alu_func 7 INC_A
val_b_adr 20 VR10:00
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_frame 10
2beb 2beb fiu_mem_start 4 continue; Flow J cc=False 0x2beb
ioc_load_wdr 0
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2beb 0x2beb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_b_adr 05 GP05
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2bec 2bec ioc_load_wdr 0
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_b_adr 05 GP05
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_b_adr 05 GP05
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bed 2bed ioc_adrbs 1 val
seq_en_micro 0
typ_a_adr 34 TR14:14
typ_alu_func 7 INC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_csa_cntl 0 LOAD_CONTROL_TOP
typ_frame 14
val_alu_func 1a PASS_B
val_b_adr 08 GP08
2bee 2bee seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_rand e CHECK_CLASS_SYSTEM_B
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2bef 2bef seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 05 GP05
typ_c_adr 2e TOP + 1
typ_c_mux_sel 0 ALU
typ_csa_cntl 2 PUSH_CSA
val_alu_func 1a PASS_B
val_b_adr 05 GP05
val_c_adr 2e TOP + 1
val_c_mux_sel 2 ALU
2bf0 2bf0 seq_b_timing 0 Early Condition; Flow J cc=False 0x2bef
seq_br_type 0 Branch False
seq_branch_adr 2bef 0x2bef
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2bf1 2bf1 fiu_load_var 1 hold_var
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 08 GP08
2bf2 2bf2 fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_var 1 hold_var
fiu_offs_lit 73
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_en_micro 0
2bf3 2bf3 ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 2d VR17:0d
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bf4 2bf4 ioc_fiubs 1 val
seq_en_micro 0
typ_c_adr 28 LOOP_COUNTER
typ_c_source 0 FIU_BUS
val_a_adr 17 LOOP_COUNTER
2bf5 2bf5 fiu_mem_start 2 start-rd
ioc_adrbs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
typ_rand e CHECK_CLASS_SYSTEM_B
val_alu_func 1a PASS_B
val_b_adr 27 VR17:07
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2bf6 2bf6 fiu_mem_start 4 continue
seq_en_micro 0
typ_mar_cntl 6 INCREMENT_MAR
2bf7 2bf7 fiu_mem_start 4 continue; Flow J cc=False 0x2bf7
ioc_tvbs c mem+mem+csa+dummy
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2bf7 0x2bf7
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_mar_cntl 6 INCREMENT_MAR
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2bf8 2bf8 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3c GP03
val_c_mux_sel 2 ALU
2bf9 2bf9 ioc_tvbs c mem+mem+csa+dummy
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3b GP04
val_c_mux_sel 2 ALU
2bfa 2bfa ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 2d VR17:0d
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2bfb 2bfb ioc_fiubs 1 val
seq_en_micro 0
typ_c_adr 28 LOOP_COUNTER
typ_c_source 0 FIU_BUS
val_a_adr 17 LOOP_COUNTER
2bfc 2bfc seq_en_micro 0
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_rand e CHECK_CLASS_SYSTEM_B
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 1 INC_LOOP_COUNTER
2bfd 2bfd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2c01
seq_br_type 1 Branch True
seq_branch_adr 2c01 0x2c01
seq_cond_sel 00 VAL.ALU_ZERO(late)
seq_en_micro 0
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 2d VR17:0d
val_frame 17
2bfe 2bfe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c25
seq_br_type 5 Call True
seq_branch_adr 2c25 MEM_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 05 GP05
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2bff 2bff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c25
seq_br_type 5 Call True
seq_branch_adr 2c25 MEM_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 05 GP05
typ_alu_func 7 INC_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 05 GP05
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c00 2c00 seq_br_type 3 Unconditional Branch; Flow J 0x2bfd
seq_branch_adr 2bfd 0x2bfd
seq_en_micro 0
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 05 GP05
val_alu_func 7 INC_A
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2c01 2c01 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 06 GP06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2c02 2c02 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 7 INC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c03 2c03 seq_b_timing 0 Early Condition; Flow J cc=False 0x2c01
seq_br_type 0 Branch False
seq_branch_adr 2c01 0x2c01
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
2c04 2c04 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 06 GP06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2c05 2c05 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 06 GP06
typ_alu_func 7 INC_A
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
val_a_adr 03 GP03
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c06 2c06 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
seq_en_micro 0
typ_a_adr 04 GP04
typ_alu_func 19 X_XOR_B
typ_b_adr 06 GP06
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
val_a_adr 06 GP06
val_alu_func 7 INC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2c07 2c07 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2c21
seq_br_type 5 Call True
seq_branch_adr 2c21 CSA_READ_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 04 GP04
val_alu_func 19 X_XOR_B
val_b_adr 06 GP06
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c08 2c08 ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 28 VR17:08
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2c09 2c09 fiu_load_var 1 hold_var
fiu_mem_start 3 start-wr
fiu_tivi_src 2 tar_fiu
ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_mar_cntl e LOAD_MAR_CONTROL
val_a_adr 2d VR17:0d
val_alu_func 1a PASS_B
val_b_adr 27 VR17:07
val_frame 17
2c0a 2c0a fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x2c0a
fiu_load_var 1 hold_var
fiu_mem_start 4 continue
fiu_offs_lit 40
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_load_wdr 0
ioc_tvbs 1 typ+fiu
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2c0a 0x2c0a
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_b_adr 20 TR10:00
typ_frame 10
typ_mar_cntl 6 INCREMENT_MAR
val_rand 2 DEC_LOOP_COUNTER
2c0b 2c0b ioc_load_wdr 0
ioc_tvbs 1 typ+fiu
seq_en_micro 0
typ_b_adr 20 TR10:00
typ_frame 10
2c0c 2c0c seq_en_micro 0
2c0d 2c0d seq_en_micro 0
val_alu_func 1a PASS_B
val_b_adr 28 VR17:08
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2c0e 2c0e fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x2c23
fiu_load_var 1 hold_var
fiu_offs_lit 40
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
ioc_tvbs 1 typ+fiu
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c23 CSA_WRITE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
val_a_adr 10 TOP
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c0f 2c0f seq_b_timing 0 Early Condition; Flow J cc=False 0x2c0e
seq_br_type 0 Branch False
seq_branch_adr 2c0e 0x2c0e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
typ_csa_cntl 3 POP_CSA
val_rand 2 DEC_LOOP_COUNTER
2c10 2c10 ioc_adrbs 1 val
ioc_fiubs 1 val
seq_en_micro 0
typ_c_adr 38 GP07
typ_c_source 0 FIU_BUS
typ_csa_cntl 0 LOAD_CONTROL_TOP
val_a_adr 27 VR17:07
val_alu_func 13 ONES
val_frame 17
2c11 2c11 fiu_len_fill_lit 45 zero-fill 0x5
fiu_load_var 1 hold_var
fiu_offs_lit 73
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
fiu_vmux_sel 1 fill value
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 08 GP08
2c12 2c12 ioc_tvbs 1 typ+fiu
seq_en_micro 0
val_a_adr 28 VR17:08
val_alu_func 1 A_PLUS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2c13 2c13 fiu_load_var 1 hold_var
fiu_tivi_src 2 tar_fiu
ioc_fiubs 1 val
seq_en_micro 0
val_a_adr 2d VR17:0d
val_frame 17
val_rand 1 INC_LOOP_COUNTER
2c14 2c14 fiu_mem_start 2 start-rd
ioc_adrbs 2 typ
seq_en_micro 0
typ_alu_func 1a PASS_B
typ_b_adr 07 GP07
typ_mar_cntl e LOAD_MAR_CONTROL
val_alu_func 1a PASS_B
val_b_adr 06 GP06
2c15 2c15 ioc_tvbs 1 typ+fiu
seq_en_micro 0
typ_a_adr 07 GP07
typ_alu_func 7 INC_A
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_rand 0 NO_OP
val_alu_func 1a PASS_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3a GP05
val_c_mux_sel 2 ALU
2c16 2c16 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2c25
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2c25 MEM_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
seq_en_micro 0
typ_b_adr 16 CSA/VAL_BUS
val_a_adr 05 GP05
val_alu_func 19 X_XOR_B
val_b_adr 16 CSA/VAL_BUS
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
2c17 2c17 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x2c14
fiu_load_var 1 hold_var
fiu_offs_lit 40
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_vmux_sel 1 fill value
seq_b_timing 0 Early Condition
seq_br_type 0 Branch False
seq_branch_adr 2c14 0x2c14
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
seq_en_micro 0
val_rand 2 DEC_LOOP_COUNTER
2c18 2c18 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c19 ERROR_HALT:
2c19 2c19 <halt> ; Flow R
2c1a 2c1a seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c1b ; --------------------------------------------------------------------------------------
2c1b ; Comes from:
2c1b ; 2b02 C True from color 0x2b01
2c1b ; 2b06 C True from color 0x2b01
2c1b ; 2b62 C True from color 0x2b60
2c1b ; --------------------------------------------------------------------------------------
2c1b CSA_HIT_ERROR:
2c1b 2c1b <halt> ; Flow R
2c1c 2c1c seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c1d ; --------------------------------------------------------------------------------------
2c1d ; Comes from:
2c1d ; 2b03 C False from color 0x2b01
2c1d ; 2b05 C False from color 0x2b01
2c1d ; 2b07 C True from color 0x2b01
2c1d ; 2b50 C False from color 0x2b00
2c1d ; 2b56 C False from color 0x2b00
2c1d ; 2b59 C False from color 0x2b00
2c1d ; 2b5a C False from color 0x2b00
2c1d ; 2b5c C True from color 0x2b00
2c1d ; 2b63 C False from color 0x2b60
2c1d ; 2ba8 C False from color 0x2b00
2c1d ; 2bad C False from color 0x2b00
2c1d ; 2be0 C True from color 0x2b00
2c1d ; --------------------------------------------------------------------------------------
2c1d OUT_OF_RANGE_ERROR:
2c1d 2c1d <halt> ; Flow R
2c1e 2c1e seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c1f ; --------------------------------------------------------------------------------------
2c1f ; Comes from:
2c1f ; 2b79 C True from color 0x2b00
2c1f ; 2b7a C True from color 0x2b00
2c1f ; --------------------------------------------------------------------------------------
2c1f CSA_INIT_ERROR:
2c1f 2c1f <halt> ; Flow R
2c20 2c20 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c21 ; --------------------------------------------------------------------------------------
2c21 ; Comes from:
2c21 ; 2b83 C True from color 0x2b00
2c21 ; 2b84 C True from color 0x2b00
2c21 ; 2be4 C True from color 0x2b00
2c21 ; 2be5 C True from color 0x2b00
2c21 ; 2c01 C True from color 0x2be8
2c21 ; 2c02 C True from color 0x2be8
2c21 ; 2c04 C True from color 0x2be8
2c21 ; 2c05 C True from color 0x2be8
2c21 ; 2c06 C True from color 0x2be8
2c21 ; 2c07 C True from color 0x2be8
2c21 ; --------------------------------------------------------------------------------------
2c21 CSA_READ_ERROR:
2c21 2c21 <halt> ; Flow R
2c22 2c22 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c23 ; --------------------------------------------------------------------------------------
2c23 ; Comes from:
2c23 ; 2b8e C True from color 0x2b00
2c23 ; 2b90 C True from color 0x2b00
2c23 ; 2c0e C True from color 0x2be8
2c23 ; --------------------------------------------------------------------------------------
2c23 CSA_WRITE_ERROR:
2c23 2c23 <halt> ; Flow R
2c24 2c24 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c25 ; --------------------------------------------------------------------------------------
2c25 ; Comes from:
2c25 ; 2b99 C True from color 0x2b00
2c25 ; 2b9a C True from color 0x2b00
2c25 ; 2bfe C True from color 0x2be8
2c25 ; 2bff C True from color 0x2be8
2c25 ; 2c16 C True from color 0x2be8
2c25 ; --------------------------------------------------------------------------------------
2c25 MEM_ERROR:
2c25 2c25 <halt> ; Flow R
2c26 2c26 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c27 ; --------------------------------------------------------------------------------------
2c27 ; Comes from:
2c27 ; 2bb8 C from color 0x2b00
2c27 ; --------------------------------------------------------------------------------------
2c27 BAD_HINT_ERROR:
2c27 2c27 <halt> ; Flow R
2c28 2c28 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c29 ; --------------------------------------------------------------------------------------
2c29 ; Comes from:
2c29 ; 2b11 C from color 0x2b00
2c29 ; --------------------------------------------------------------------------------------
2c29 CANNOT_ALIGN_BOT_ERROR:
2c29 2c29 <halt> ; Flow R
2c2a 2c2a seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c2b ; --------------------------------------------------------------------------------------
2c2b ; Comes from:
2c2b ; 2b12 C True from color 0x2b00
2c2b ; 2b13 C True from color 0x2b00
2c2b ; --------------------------------------------------------------------------------------
2c2b TYP_VAL_BOT_UNEQUAL_ERROR:
2c2b 2c2b <halt> ; Flow R
2c2c 2c2c seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c2d ; --------------------------------------------------------------------------------------
2c2d ; Comes from:
2c2d ; 2b19 C True from color 0x2b00
2c2d ; 2b1f C True from color 0x2b00
2c2d ; 2b31 C True from color 0x2b00
2c2d ; --------------------------------------------------------------------------------------
2c2d DEC_CSA_BOT_ERROR:
2c2d 2c2d <halt> ; Flow R
2c2e 2c2e seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c2f ; --------------------------------------------------------------------------------------
2c2f ; Comes from:
2c2f ; 2b24 C True from color 0x2b00
2c2f ; 2b2a C True from color 0x2b00
2c2f ; 2b4c C True from color 0x2b00
2c2f ; --------------------------------------------------------------------------------------
2c2f INC_CSA_BOT_ERROR:
2c2f 2c2f <halt> ; Flow R
2c30 2c30 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c31 ; --------------------------------------------------------------------------------------
2c31 ; Comes from:
2c31 ; 2b1c C True from color 0x2b00
2c31 ; 2b27 C True from color 0x2b00
2c31 ; 2b33 C True from color 0x2b00
2c31 ; --------------------------------------------------------------------------------------
2c31 CSA_BOTM1_ERROR:
2c31 2c31 <halt> ; Flow R
2c32 2c32 seq_br_type a Unconditional Return; Flow R
seq_en_micro 0
2c33 2c33 <halt> ; Flow R
2c34 2c34 <halt> ; Flow R
2c35 2c35 <halt> ; Flow R
2c36 2c36 <halt> ; Flow R
2c37 2c37 <halt> ; Flow R
2c38 2c38 <halt> ; Flow R
2c39 2c39 <halt> ; Flow R
2c3a 2c3a <halt> ; Flow R
2c3b 2c3b <halt> ; Flow R
2c3c 2c3c <halt> ; Flow R
2c3d 2c3d <halt> ; Flow R
2c3e 2c3e <halt> ; Flow R
2c3f 2c3f <halt> ; Flow R
2c40 2c40 <halt> ; Flow R
2c41 2c41 <halt> ; Flow R
2c42 2c42 <halt> ; Flow R
2c43 2c43 <halt> ; Flow R
2c44 2c44 <halt> ; Flow R
2c45 2c45 <halt> ; Flow R
2c46 2c46 <halt> ; Flow R
2c47 2c47 <halt> ; Flow R
2c48 2c48 <halt> ; Flow R
2c49 2c49 <halt> ; Flow R
2c4a 2c4a <halt> ; Flow R
2c4b 2c4b <halt> ; Flow R
2c4c 2c4c <halt> ; Flow R
2c4d 2c4d <halt> ; Flow R
2c4e 2c4e <halt> ; Flow R
2c4f 2c4f <halt> ; Flow R
2c50 2c50 <halt> ; Flow R
2c51 2c51 <halt> ; Flow R
2c52 2c52 <halt> ; Flow R
2c53 2c53 <halt> ; Flow R
2c54 2c54 <halt> ; Flow R
2c55 2c55 <halt> ; Flow R
2c56 2c56 <halt> ; Flow R
2c57 2c57 <halt> ; Flow R
2c58 2c58 <halt> ; Flow R
2c59 2c59 <halt> ; Flow R
2c5a 2c5a <halt> ; Flow R
2c5b 2c5b <halt> ; Flow R
2c5c 2c5c <halt> ; Flow R
2c5d 2c5d <halt> ; Flow R
2c5e 2c5e <halt> ; Flow R
2c5f 2c5f <halt> ; Flow R
2c60 2c60 <halt> ; Flow R
2c61 2c61 <halt> ; Flow R
2c62 2c62 <halt> ; Flow R
2c63 2c63 <halt> ; Flow R
2c64 2c64 <halt> ; Flow R
2c65 2c65 <halt> ; Flow R
2c66 2c66 <halt> ; Flow R
2c67 2c67 <halt> ; Flow R
2c68 2c68 <halt> ; Flow R
2c69 2c69 <halt> ; Flow R
2c6a 2c6a <halt> ; Flow R
2c6b 2c6b <halt> ; Flow R
2c6c 2c6c <halt> ; Flow R
2c6d 2c6d <halt> ; Flow R
2c6e 2c6e <halt> ; Flow R
2c6f 2c6f <halt> ; Flow R
2c70 2c70 <halt> ; Flow R
2c71 2c71 <halt> ; Flow R
2c72 2c72 <halt> ; Flow R
2c73 2c73 <halt> ; Flow R
2c74 2c74 <halt> ; Flow R
2c75 2c75 <halt> ; Flow R
2c76 2c76 <halt> ; Flow R
2c77 2c77 <halt> ; Flow R
2c78 2c78 <halt> ; Flow R
2c79 2c79 <halt> ; Flow R
2c7a 2c7a <halt> ; Flow R
2c7b 2c7b <halt> ; Flow R
2c7c 2c7c <halt> ; Flow R
2c7d 2c7d <halt> ; Flow R
2c7e 2c7e <halt> ; Flow R
2c7f 2c7f <halt> ; Flow R
2c80 2c80 <halt> ; Flow R
2c81 2c81 <halt> ; Flow R
2c82 2c82 <halt> ; Flow R
2c83 2c83 <halt> ; Flow R
2c84 2c84 <halt> ; Flow R
2c85 2c85 <halt> ; Flow R
2c86 2c86 <halt> ; Flow R
2c87 2c87 <halt> ; Flow R
2c88 2c88 <halt> ; Flow R
2c89 2c89 <halt> ; Flow R
2c8a 2c8a <halt> ; Flow R
2c8b 2c8b <halt> ; Flow R
2c8c 2c8c <halt> ; Flow R
2c8d 2c8d <halt> ; Flow R
2c8e 2c8e <halt> ; Flow R
2c8f 2c8f <halt> ; Flow R
2c90 2c90 <halt> ; Flow R
2c91 2c91 <halt> ; Flow R
2c92 2c92 <halt> ; Flow R
2c93 2c93 <halt> ; Flow R
2c94 2c94 <halt> ; Flow R
2c95 2c95 <halt> ; Flow R
2c96 2c96 <halt> ; Flow R
2c97 2c97 <halt> ; Flow R
2c98 2c98 <halt> ; Flow R
2c99 2c99 <halt> ; Flow R
2c9a 2c9a <halt> ; Flow R
2c9b 2c9b <halt> ; Flow R
2c9c 2c9c <halt> ; Flow R
2c9d 2c9d <halt> ; Flow R
2c9e 2c9e <halt> ; Flow R
2c9f 2c9f <halt> ; Flow R
2ca0 2ca0 <halt> ; Flow R
2ca1 2ca1 <halt> ; Flow R
2ca2 2ca2 <halt> ; Flow R
2ca3 2ca3 <halt> ; Flow R
2ca4 2ca4 <halt> ; Flow R
2ca5 2ca5 <halt> ; Flow R
2ca6 2ca6 <halt> ; Flow R
2ca7 2ca7 <halt> ; Flow R
2ca8 2ca8 <halt> ; Flow R
2ca9 2ca9 <halt> ; Flow R
2caa 2caa <halt> ; Flow R
2cab 2cab <halt> ; Flow R
2cac 2cac <halt> ; Flow R
2cad 2cad <halt> ; Flow R
2cae 2cae <halt> ; Flow R
2caf 2caf <halt> ; Flow R
2cb0 2cb0 <halt> ; Flow R
2cb1 2cb1 <halt> ; Flow R
2cb2 2cb2 <halt> ; Flow R
2cb3 2cb3 <halt> ; Flow R
2cb4 2cb4 <halt> ; Flow R
2cb5 2cb5 <halt> ; Flow R
2cb6 2cb6 <halt> ; Flow R
2cb7 2cb7 <halt> ; Flow R
2cb8 2cb8 <halt> ; Flow R
2cb9 2cb9 <halt> ; Flow R
2cba 2cba <halt> ; Flow R
2cbb 2cbb <halt> ; Flow R
2cbc 2cbc <halt> ; Flow R
2cbd 2cbd <halt> ; Flow R
2cbe 2cbe <halt> ; Flow R
2cbf 2cbf <halt> ; Flow R
2cc0 2cc0 <halt> ; Flow R
2cc1 2cc1 <halt> ; Flow R
2cc2 2cc2 <halt> ; Flow R
2cc3 2cc3 <halt> ; Flow R
2cc4 2cc4 <halt> ; Flow R
2cc5 2cc5 <halt> ; Flow R
2cc6 2cc6 <halt> ; Flow R
2cc7 2cc7 <halt> ; Flow R
2cc8 2cc8 <halt> ; Flow R
2cc9 2cc9 <halt> ; Flow R
2cca 2cca <halt> ; Flow R
2ccb 2ccb <halt> ; Flow R
2ccc 2ccc <halt> ; Flow R
2ccd 2ccd <halt> ; Flow R
2cce 2cce <halt> ; Flow R
2ccf 2ccf <halt> ; Flow R
2cd0 2cd0 <halt> ; Flow R
2cd1 2cd1 <halt> ; Flow R
2cd2 2cd2 <halt> ; Flow R
2cd3 2cd3 <halt> ; Flow R
2cd4 2cd4 <halt> ; Flow R
2cd5 2cd5 <halt> ; Flow R
2cd6 2cd6 <halt> ; Flow R
2cd7 2cd7 <halt> ; Flow R
2cd8 2cd8 <halt> ; Flow R
2cd9 2cd9 <halt> ; Flow R
2cda 2cda <halt> ; Flow R
2cdb 2cdb <halt> ; Flow R
2cdc 2cdc <halt> ; Flow R
2cdd 2cdd <halt> ; Flow R
2cde 2cde <halt> ; Flow R
2cdf 2cdf <halt> ; Flow R
2ce0 2ce0 <halt> ; Flow R
2ce1 2ce1 <halt> ; Flow R
2ce2 2ce2 <halt> ; Flow R
2ce3 2ce3 <halt> ; Flow R
2ce4 2ce4 <halt> ; Flow R
2ce5 2ce5 <halt> ; Flow R
2ce6 2ce6 <halt> ; Flow R
2ce7 2ce7 <halt> ; Flow R
2ce8 2ce8 <halt> ; Flow R
2ce9 2ce9 <halt> ; Flow R
2cea 2cea <halt> ; Flow R
2ceb 2ceb <halt> ; Flow R
2cec 2cec <halt> ; Flow R
2ced 2ced <halt> ; Flow R
2cee 2cee <halt> ; Flow R
2cef 2cef <halt> ; Flow R
2cf0 2cf0 <halt> ; Flow R
2cf1 2cf1 <halt> ; Flow R
2cf2 2cf2 <halt> ; Flow R
2cf3 2cf3 <halt> ; Flow R
2cf4 2cf4 <halt> ; Flow R
2cf5 2cf5 <halt> ; Flow R
2cf6 2cf6 <halt> ; Flow R
2cf7 2cf7 <halt> ; Flow R
2cf8 2cf8 <halt> ; Flow R
2cf9 2cf9 <halt> ; Flow R
2cfa 2cfa <halt> ; Flow R
2cfb 2cfb <halt> ; Flow R
2cfc 2cfc <halt> ; Flow R
2cfd 2cfd <halt> ; Flow R
2cfe 2cfe <halt> ; Flow R
2cff 2cff <halt> ; Flow R
2d00 2d00 <halt> ; Flow R
2d01 2d01 <halt> ; Flow R
2d02 2d02 <halt> ; Flow R
2d03 2d03 <halt> ; Flow R
2d04 2d04 <halt> ; Flow R
2d05 2d05 <halt> ; Flow R
2d06 2d06 <halt> ; Flow R
2d07 2d07 <halt> ; Flow R
2d08 2d08 <halt> ; Flow R
2d09 2d09 <halt> ; Flow R
2d0a 2d0a <halt> ; Flow R
2d0b 2d0b <halt> ; Flow R
2d0c 2d0c <halt> ; Flow R
2d0d 2d0d <halt> ; Flow R
2d0e 2d0e <halt> ; Flow R
2d0f 2d0f <halt> ; Flow R
2d10 2d10 <halt> ; Flow R
2d11 2d11 <halt> ; Flow R
2d12 2d12 <halt> ; Flow R
2d13 2d13 <halt> ; Flow R
2d14 2d14 <halt> ; Flow R
2d15 2d15 <halt> ; Flow R
2d16 2d16 <halt> ; Flow R
2d17 2d17 <halt> ; Flow R
2d18 2d18 <halt> ; Flow R
2d19 2d19 <halt> ; Flow R
2d1a 2d1a <halt> ; Flow R
2d1b 2d1b <halt> ; Flow R
2d1c 2d1c <halt> ; Flow R
2d1d 2d1d <halt> ; Flow R
2d1e 2d1e <halt> ; Flow R
2d1f 2d1f <halt> ; Flow R
2d20 2d20 <halt> ; Flow R
2d21 2d21 <halt> ; Flow R
2d22 2d22 <halt> ; Flow R
2d23 2d23 <halt> ; Flow R
2d24 2d24 <halt> ; Flow R
2d25 2d25 <halt> ; Flow R
2d26 2d26 <halt> ; Flow R
2d27 2d27 <halt> ; Flow R
2d28 2d28 <halt> ; Flow R
2d29 2d29 <halt> ; Flow R
2d2a 2d2a <halt> ; Flow R
2d2b 2d2b <halt> ; Flow R
2d2c 2d2c <halt> ; Flow R
2d2d 2d2d <halt> ; Flow R
2d2e 2d2e <halt> ; Flow R
2d2f 2d2f <halt> ; Flow R
2d30 2d30 <halt> ; Flow R
2d31 2d31 <halt> ; Flow R
2d32 2d32 <halt> ; Flow R
2d33 2d33 <halt> ; Flow R
2d34 2d34 <halt> ; Flow R
2d35 2d35 <halt> ; Flow R
2d36 2d36 <halt> ; Flow R
2d37 2d37 <halt> ; Flow R
2d38 2d38 <halt> ; Flow R
2d39 2d39 <halt> ; Flow R
2d3a 2d3a <halt> ; Flow R
2d3b 2d3b <halt> ; Flow R
2d3c 2d3c <halt> ; Flow R
2d3d 2d3d <halt> ; Flow R
2d3e 2d3e <halt> ; Flow R
2d3f 2d3f <halt> ; Flow R
2d40 2d40 <halt> ; Flow R
2d41 2d41 <halt> ; Flow R
2d42 2d42 <halt> ; Flow R
2d43 2d43 <halt> ; Flow R
2d44 2d44 <halt> ; Flow R
2d45 2d45 <halt> ; Flow R
2d46 2d46 <halt> ; Flow R
2d47 2d47 <halt> ; Flow R
2d48 2d48 <halt> ; Flow R
2d49 2d49 <halt> ; Flow R
2d4a 2d4a <halt> ; Flow R
2d4b 2d4b <halt> ; Flow R
2d4c 2d4c <halt> ; Flow R
2d4d 2d4d <halt> ; Flow R
2d4e 2d4e <halt> ; Flow R
2d4f 2d4f <halt> ; Flow R
2d50 2d50 <halt> ; Flow R
2d51 2d51 <halt> ; Flow R
2d52 2d52 <halt> ; Flow R
2d53 2d53 <halt> ; Flow R
2d54 2d54 <halt> ; Flow R
2d55 2d55 <halt> ; Flow R
2d56 2d56 <halt> ; Flow R
2d57 2d57 <halt> ; Flow R
2d58 2d58 <halt> ; Flow R
2d59 2d59 <halt> ; Flow R
2d5a 2d5a <halt> ; Flow R
2d5b 2d5b <halt> ; Flow R
2d5c 2d5c <halt> ; Flow R
2d5d 2d5d <halt> ; Flow R
2d5e 2d5e <halt> ; Flow R
2d5f 2d5f <halt> ; Flow R
2d60 2d60 <halt> ; Flow R
2d61 2d61 <halt> ; Flow R
2d62 2d62 <halt> ; Flow R
2d63 2d63 <halt> ; Flow R
2d64 2d64 <halt> ; Flow R
2d65 2d65 <halt> ; Flow R
2d66 2d66 <halt> ; Flow R
2d67 2d67 <halt> ; Flow R
2d68 2d68 <halt> ; Flow R
2d69 2d69 <halt> ; Flow R
2d6a 2d6a <halt> ; Flow R
2d6b 2d6b <halt> ; Flow R
2d6c 2d6c <halt> ; Flow R
2d6d 2d6d <halt> ; Flow R
2d6e 2d6e <halt> ; Flow R
2d6f 2d6f <halt> ; Flow R
2d70 2d70 <halt> ; Flow R
2d71 2d71 <halt> ; Flow R
2d72 2d72 <halt> ; Flow R
2d73 2d73 <halt> ; Flow R
2d74 2d74 <halt> ; Flow R
2d75 2d75 <halt> ; Flow R
2d76 2d76 <halt> ; Flow R
2d77 2d77 <halt> ; Flow R
2d78 2d78 <halt> ; Flow R
2d79 2d79 <halt> ; Flow R
2d7a 2d7a <halt> ; Flow R
2d7b 2d7b <halt> ; Flow R
2d7c 2d7c <halt> ; Flow R
2d7d 2d7d <halt> ; Flow R
2d7e 2d7e <halt> ; Flow R
2d7f 2d7f <halt> ; Flow R
2d80 2d80 <halt> ; Flow R
2d81 2d81 <halt> ; Flow R
2d82 2d82 <halt> ; Flow R
2d83 2d83 <halt> ; Flow R
2d84 2d84 <halt> ; Flow R
2d85 2d85 <halt> ; Flow R
2d86 2d86 <halt> ; Flow R
2d87 2d87 <halt> ; Flow R
2d88 2d88 <halt> ; Flow R
2d89 2d89 <halt> ; Flow R
2d8a 2d8a <halt> ; Flow R
2d8b 2d8b <halt> ; Flow R
2d8c 2d8c <halt> ; Flow R
2d8d 2d8d <halt> ; Flow R
2d8e 2d8e <halt> ; Flow R
2d8f 2d8f <halt> ; Flow R
2d90 2d90 <halt> ; Flow R
2d91 2d91 <halt> ; Flow R
2d92 2d92 <halt> ; Flow R
2d93 2d93 <halt> ; Flow R
2d94 2d94 <halt> ; Flow R
2d95 2d95 <halt> ; Flow R
2d96 2d96 <halt> ; Flow R
2d97 2d97 <halt> ; Flow R
2d98 2d98 <halt> ; Flow R
2d99 2d99 <halt> ; Flow R
2d9a 2d9a <halt> ; Flow R
2d9b 2d9b <halt> ; Flow R
2d9c 2d9c <halt> ; Flow R
2d9d 2d9d <halt> ; Flow R
2d9e 2d9e <halt> ; Flow R
2d9f 2d9f <halt> ; Flow R
2da0 2da0 <halt> ; Flow R
2da1 2da1 <halt> ; Flow R
2da2 2da2 <halt> ; Flow R
2da3 2da3 <halt> ; Flow R
2da4 2da4 <halt> ; Flow R
2da5 2da5 <halt> ; Flow R
2da6 2da6 <halt> ; Flow R
2da7 2da7 <halt> ; Flow R
2da8 2da8 <halt> ; Flow R
2da9 2da9 <halt> ; Flow R
2daa 2daa <halt> ; Flow R
2dab 2dab <halt> ; Flow R
2dac 2dac <halt> ; Flow R
2dad 2dad <halt> ; Flow R
2dae 2dae <halt> ; Flow R
2daf 2daf <halt> ; Flow R
2db0 2db0 <halt> ; Flow R
2db1 2db1 <halt> ; Flow R
2db2 2db2 <halt> ; Flow R
2db3 2db3 <halt> ; Flow R
2db4 2db4 <halt> ; Flow R
2db5 2db5 <halt> ; Flow R
2db6 2db6 <halt> ; Flow R
2db7 2db7 <halt> ; Flow R
2db8 2db8 <halt> ; Flow R
2db9 2db9 <halt> ; Flow R
2dba 2dba <halt> ; Flow R
2dbb 2dbb <halt> ; Flow R
2dbc 2dbc <halt> ; Flow R
2dbd 2dbd <halt> ; Flow R
2dbe 2dbe <halt> ; Flow R
2dbf 2dbf <halt> ; Flow R
2dc0 2dc0 <halt> ; Flow R
2dc1 2dc1 <halt> ; Flow R
2dc2 2dc2 <halt> ; Flow R
2dc3 2dc3 <halt> ; Flow R
2dc4 2dc4 <halt> ; Flow R
2dc5 2dc5 <halt> ; Flow R
2dc6 2dc6 <halt> ; Flow R
2dc7 2dc7 <halt> ; Flow R
2dc8 2dc8 <halt> ; Flow R
2dc9 2dc9 <halt> ; Flow R
2dca 2dca <halt> ; Flow R
2dcb 2dcb <halt> ; Flow R
2dcc 2dcc <halt> ; Flow R
2dcd 2dcd <halt> ; Flow R
2dce 2dce <halt> ; Flow R
2dcf 2dcf <halt> ; Flow R
2dd0 2dd0 <halt> ; Flow R
2dd1 2dd1 <halt> ; Flow R
2dd2 2dd2 <halt> ; Flow R
2dd3 2dd3 <halt> ; Flow R
2dd4 2dd4 <halt> ; Flow R
2dd5 2dd5 <halt> ; Flow R
2dd6 2dd6 <halt> ; Flow R
2dd7 2dd7 <halt> ; Flow R
2dd8 2dd8 <halt> ; Flow R
2dd9 2dd9 <halt> ; Flow R
2dda 2dda <halt> ; Flow R
2ddb 2ddb <halt> ; Flow R
2ddc 2ddc <halt> ; Flow R
2ddd 2ddd <halt> ; Flow R
2dde 2dde <halt> ; Flow R
2ddf 2ddf <halt> ; Flow R
2de0 2de0 <halt> ; Flow R
2de1 2de1 <halt> ; Flow R
2de2 2de2 <halt> ; Flow R
2de3 2de3 <halt> ; Flow R
2de4 2de4 <halt> ; Flow R
2de5 2de5 <halt> ; Flow R
2de6 2de6 <halt> ; Flow R
2de7 2de7 <halt> ; Flow R
2de8 2de8 <halt> ; Flow R
2de9 2de9 <halt> ; Flow R
2dea 2dea <halt> ; Flow R
2deb 2deb <halt> ; Flow R
2dec 2dec <halt> ; Flow R
2ded 2ded <halt> ; Flow R
2dee 2dee <halt> ; Flow R
2def 2def <halt> ; Flow R
2df0 2df0 <halt> ; Flow R
2df1 2df1 <halt> ; Flow R
2df2 2df2 <halt> ; Flow R
2df3 2df3 <halt> ; Flow R
2df4 2df4 <halt> ; Flow R
2df5 2df5 <halt> ; Flow R
2df6 2df6 <halt> ; Flow R
2df7 2df7 <halt> ; Flow R
2df8 2df8 <halt> ; Flow R
2df9 2df9 <halt> ; Flow R
2dfa 2dfa <halt> ; Flow R
2dfb 2dfb <halt> ; Flow R
2dfc 2dfc <halt> ; Flow R
2dfd 2dfd <halt> ; Flow R
2dfe 2dfe <halt> ; Flow R
2dff 2dff <halt> ; Flow R
2e00 ; --------------------------------------------------------------------------------------
2e00 ; 2E00 - 2ECE SYS_IOC_TEST
2e00 ; Comes from:
2e00 ; 0320 C from color DIAGNOSTIC_START
2e00 ; --------------------------------------------------------------------------------------
2e00 2e00 ioc_random f disable delay timer
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2e01 2e01 ioc_random d disable slice timer
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
2e02 2e02 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e03 2e03 seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e04 2e04 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e05 2e05 typ_a_adr 30 TR05:10
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e06 2e06 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
2e07 2e07 seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e08 2e08 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e09 2e09 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2e06
seq_br_type 0 Branch False
seq_branch_adr 2e06 0x2e06
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e0a 2e0a seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_a_adr 36 TR17:16
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e0b 2e0b seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e0c 2e0c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e0d 2e0d typ_a_adr 03 GP03
typ_alu_func 6 A_MINUS_B
typ_b_adr 30 TR05:10
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e0e 2e0e seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
2e0f 2e0f seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e10 2e10 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e11 2e11 typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR05:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e12 2e12 seq_br_type 1 Branch True; Flow J cc=True 0x2e0e
seq_branch_adr 2e0e 0x2e0e
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e13 2e13 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e14 2e14 seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e15 2e15 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e16 2e16 typ_a_adr 30 TR05:10
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e17 2e17 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
2e18 2e18 seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e19 2e19 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e1a 2e1a seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2e17
seq_br_type 0 Branch False
seq_branch_adr 2e17 0x2e17
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 03 GP03
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e1b 2e1b typ_a_adr 36 TR17:16
typ_alu_func 0 PASS_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e1c 2e1c seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
2e1d 2e1d seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e1e 2e1e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e1f 2e1f typ_a_adr 03 GP03
typ_alu_func 6 A_MINUS_B
typ_b_adr 30 TR05:10
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e20 2e20 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
2e21 2e21 seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e22 2e22 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec7
seq_br_type 5 Call True
seq_branch_adr 2ec7 TIMER_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 03 GP03
typ_alu_func 19 X_XOR_B
typ_b_adr 01 GP01
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e23 2e23 typ_a_adr 03 GP03
typ_alu_func 1 A_PLUS_B
typ_b_adr 2f TR05:0f
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 5
2e24 2e24 seq_br_type 1 Branch True; Flow J cc=True 0x2e20
seq_branch_adr 2e20 0x2e20
seq_cond_sel 20 TYP.ALU_CARRY(late)
typ_a_adr 03 GP03
typ_alu_func 3 LEFT_I_A
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
2e25 2e25 typ_a_adr 36 TR17:16
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 17
2e26 2e26 typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e27 2e27 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_a_adr 2a TR16:0a
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 16
2e28 2e28 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
2e29 2e29 ioc_random e enable delay timer; Flow C 0x2eba
seq_br_type 7 Unconditional Call
seq_branch_adr 2eba 0x2eba
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
2e2a 2e2a fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
ioc_random f disable delay timer
typ_b_adr 35 TR17:15
typ_frame 17
2e2b 2e2b seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e2c 2e2c seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e2d 2e2d seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e2e 2e2e seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e2f 2e2f seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e30 2e30 seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e31 2e31 seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e32 2e32 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec9
seq_br_type 5 Call True
seq_branch_adr 2ec9 TIMER_COUNT_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e33 2e33 typ_a_adr 34 TR05:14
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e34 2e34 typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e35 2e35 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_a_adr 2a TR14:0a
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
2e36 2e36 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
2e37 2e37 ioc_random c enable slice timer; Flow C 0x2eba
seq_br_type 7 Unconditional Call
seq_branch_adr 2eba 0x2eba
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
2e38 2e38 fiu_load_tar 1 hold_tar
fiu_tivi_src 8 type_var
ioc_random d disable slice timer
typ_b_adr 34 TR17:14
typ_frame 17
2e39 2e39 seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e3a 2e3a seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e3b 2e3b seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e3c 2e3c seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e3d 2e3d seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e3e 2e3e seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e3f 2e3f seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e40 2e40 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ec9
seq_br_type 5 Call True
seq_branch_adr 2ec9 TIMER_COUNT_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 01 GP01
typ_alu_func 19 X_XOR_B
typ_b_adr 03 GP03
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
2e41 2e41 typ_a_adr 3c TR05:1c
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e42 2e42 typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e43 2e43 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_a_adr 3b TR14:1b
typ_alu_func 0 PASS_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 14
2e44 2e44 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
2e45 2e45 ioc_random c enable slice timer
typ_a_adr 03 GP03
typ_alu_func 0 PASS_A
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
2e46 2e46 ioc_random e enable delay timer; Flow C 0x2eba
seq_br_type 7 Unconditional Call
seq_branch_adr 2eba 0x2eba
seq_en_micro 0
2e47 2e47 ioc_random d disable slice timer
2e48 2e48 ioc_random f disable delay timer
seq_en_micro 0
2e49 2e49 seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e4a 2e4a seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e4b 2e4b seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e4c 2e4c seq_br_type 7 Unconditional Call; Flow C 0x2ebd
seq_branch_adr 2ebd 0x2ebd
2e4d 2e4d seq_br_type 7 Unconditional Call; Flow C 0x2ec4
seq_branch_adr 2ec4 0x2ec4
2e4e 2e4e seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e4f 2e4f seq_br_type 7 Unconditional Call; Flow C 0x2ec5
seq_branch_adr 2ec5 0x2ec5
2e50 2e50 seq_br_type 7 Unconditional Call; Flow C 0x2eb7
seq_branch_adr 2eb7 0x2eb7
2e51 2e51 ioc_random a clear slice event
2e52 2e52 ioc_random b clear delay event
2e53 2e53 seq_int_reads 0 TYP VAL BUS
seq_random 67 Load_break_mask+?
val_b_adr 22 VR10:02
val_frame 10
2e54 2e54 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2e55 2e55 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 37 TR17:17
typ_frame 17
val_b_adr 2e VR16:0e
val_frame 16
2e56 2e56 typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e57 2e57 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e58 2e58 ioc_random e enable delay timer
val_a_adr 2d VR15:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2e59 2e59 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e59
seq_br_type 0 Branch False
seq_branch_adr 2e59 0x2e59
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e5a 2e5a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2e5b 2e5b <halt> ; Flow R
2e5c ; --------------------------------------------------------------------------------------
2e5c ; 0x0300 Illegal -
2e5c ; --------------------------------------------------------------------------------------
2e5c MACRO_Illegal_-:
2e5c 2e5c dispatch_brk_class 0 ; Flow J cc=True 0x2e62
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 2e5c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2e62 0x2e62
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2e5d 2e5d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecd
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e5e 2e5e val_a_adr 28 VR04:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2e5f 2e5f seq_b_timing 0 Early Condition; Flow J cc=False 0x2e5f
seq_br_type 0 Branch False
seq_branch_adr 2e5f 0x2e5f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e60 2e60 typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2e61 2e61 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2e62 2e62 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecd
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e63 2e63 ioc_random f disable delay timer
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2e64 2e64 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2e65 2e65 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 38 TR17:18
typ_frame 17
val_b_adr 2f VR16:0f
val_frame 16
2e66 2e66 typ_a_adr 33 TR05:13
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e67 2e67 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e68 2e68 ioc_random c enable slice timer
val_a_adr 2c VR16:0c
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2e69 2e69 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e69
seq_br_type 0 Branch False
seq_branch_adr 2e69 0x2e69
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e6a 2e6a fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2e6b 2e6b <halt> ; Flow R
2e6c ; --------------------------------------------------------------------------------------
2e6c ; 0x0310 Illegal -
2e6c ; --------------------------------------------------------------------------------------
2e6c MACRO_Illegal_-:
2e6c 2e6c dispatch_brk_class 0 ; Flow J cc=True 0x2e72
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 2e6c
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2e72 0x2e72
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 08 GP08
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2e6d 2e6d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecb
seq_br_type 5 Call True
seq_branch_adr 2ecb SLICE_MACRO_EVENT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e6e 2e6e val_a_adr 28 VR04:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2e6f 2e6f seq_b_timing 0 Early Condition; Flow J cc=False 0x2e6f
seq_br_type 0 Branch False
seq_branch_adr 2e6f 0x2e6f
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e70 2e70 typ_alu_func 13 ONES
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
2e71 2e71 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2e72 2e72 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecb
seq_br_type 5 Call True
seq_branch_adr 2ecb SLICE_MACRO_EVENT_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e73 2e73 ioc_random d disable slice timer
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
2e74 2e74 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2e75 2e75 seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 39 TR17:19
typ_frame 17
val_b_adr 30 VR16:10
val_frame 16
2e76 2e76 typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e77 2e77 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e78 2e78 typ_a_adr 34 TR05:14
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e79 2e79 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e7a 2e7a ioc_random c enable slice timer
val_a_adr 2d VR15:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2e7b 2e7b ioc_random e enable delay timer
2e7c 2e7c seq_b_timing 0 Early Condition; Flow J cc=False 0x2e7c
seq_br_type 0 Branch False
seq_branch_adr 2e7c 0x2e7c
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e7d 2e7d typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2e7e 2e7e fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2e7f 2e7f <halt> ; Flow R
2e80 ; --------------------------------------------------------------------------------------
2e80 ; 0x0320 Declare_Variable Record,Duplicate
2e80 ; --------------------------------------------------------------------------------------
2e80 MACRO_Declare_Variable_Record,Duplicate:
2e80 2e80 dispatch_brk_class 0 ; Flow J cc=True 0x2e86
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 2e80
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2e86 0x2e86
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 08 GP08
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2e81 2e81 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2e8c
seq_br_type 1 Branch True
seq_branch_adr 2e8c 0x2e8c
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e82 2e82 val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2e83 2e83 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e83
seq_br_type 0 Branch False
seq_branch_adr 2e83 0x2e83
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e84 2e84 typ_alu_func 13 ONES
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
2e85 2e85 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2e86 2e86 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecb
seq_br_type 5 Call True
seq_branch_adr 2ecb SLICE_MACRO_EVENT_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e87 2e87 ioc_random d disable slice timer
typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
2e88 2e88 val_a_adr 28 VR04:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2e89 2e89 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e89
seq_br_type 0 Branch False
seq_branch_adr 2e89 0x2e89
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e8a 2e8a typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2e8b 2e8b fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2e8c 2e8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecd
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e8d 2e8d ioc_random f disable delay timer
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2e8e 2e8e seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2e8f 2e8f seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 3a TR17:1a
typ_frame 17
val_b_adr 31 VR16:11
val_frame 16
2e90 2e90 typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e91 2e91 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e92 2e92 ioc_random c enable slice timer
val_a_adr 2d VR16:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2e93 2e93 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e93
seq_br_type 0 Branch False
seq_branch_adr 2e93 0x2e93
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2e94 2e94 typ_c_adr 37 GP08
typ_c_mux_sel 0 ALU
val_c_adr 37 GP08
val_c_mux_sel 2 ALU
2e95 2e95 ioc_random d disable slice timer
2e96 2e96 typ_a_adr 32 TR05:12
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 5
2e97 2e97 seq_br_type 7 Unconditional Call; Flow C 0x2ebf
seq_branch_adr 2ebf 0x2ebf
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e98 2e98 ioc_random a clear slice event
2e99 2e99 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2e9a ; --------------------------------------------------------------------------------------
2e9a ; 0x0330 Illegal -
2e9a ; --------------------------------------------------------------------------------------
2e9a MACRO_Illegal_-:
2e9a 2e9a dispatch_brk_class 0 ; Flow C cc=True 0x2ecb
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 2e9a
seq_b_timing 3 Late Condition, Hint False
seq_br_type 5 Call True
seq_branch_adr 2ecb SLICE_MACRO_EVENT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 08 GP08
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2e9b 2e9b typ_a_adr 39 TR10:19
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 34 VR16:14
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
2e9c 2e9c seq_br_type 7 Unconditional Call; Flow C 0x2ea3
seq_branch_adr 2ea3 0x2ea3
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e9d 2e9d typ_a_adr 3a TR10:1a
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 10
val_a_adr 3b VR16:1b
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 16
2e9e 2e9e seq_br_type 7 Unconditional Call; Flow C 0x2ea3
seq_branch_adr 2ea3 0x2ea3
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2e9f 2e9f typ_a_adr 36 TR17:16
typ_alu_func 0 PASS_A
typ_c_adr 3b GP04
typ_c_mux_sel 0 ALU
typ_frame 17
val_a_adr 2c VR10:0c
val_alu_func 0 PASS_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
val_frame 10
2ea0 2ea0 seq_br_type 7 Unconditional Call; Flow C 0x2ea3
seq_branch_adr 2ea3 0x2ea3
typ_a_adr 04 GP04
typ_alu_func 18 NOT_A_AND_B
typ_b_adr 36 TR17:16
typ_c_adr 3c GP03
typ_c_mux_sel 0 ALU
typ_frame 17
2ea1 2ea1 ioc_random f disable delay timer
2ea2 2ea2 ioc_random d disable slice timer; Flow R
seq_br_type a Unconditional Return
2ea3 ; --------------------------------------------------------------------------------------
2ea3 ; Comes from:
2ea3 ; 2e9c C from color MACRO_Illegal_-
2ea3 ; 2e9e C from color MACRO_Illegal_-
2ea3 ; 2ea0 C from color MACRO_Illegal_-
2ea3 ; --------------------------------------------------------------------------------------
2ea3 2ea3 seq_int_reads 0 TYP VAL BUS
seq_random 5f Load_current_lex+?
typ_b_adr 20 TR10:00
typ_frame 10
val_b_adr 20 VR10:00
val_frame 10
2ea4 2ea4 seq_br_type 7 Unconditional Call; Flow C 0x2ec0
seq_branch_adr 2ec0 0x2ec0
seq_int_reads 0 TYP VAL BUS
seq_random 0c Load_ibuff+?
typ_b_adr 38 TR10:18
typ_frame 10
val_b_adr 3a VR16:1a
val_frame 16
2ea5 2ea5 ioc_random e enable delay timer
val_a_adr 06 GP06
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2ea6 2ea6 fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
typ_mar_cntl e LOAD_MAR_CONTROL
val_c_adr 38 GP07
val_c_mux_sel 2 ALU
2ea7 2ea7 <halt> ; Flow R
2ea8 ; --------------------------------------------------------------------------------------
2ea8 ; 0x0340 Complete_Type Array,By_Component_Completion
2ea8 ; --------------------------------------------------------------------------------------
2ea8 MACRO_Complete_Type_Array,By_Component_Completion:
2ea8 2ea8 dispatch_brk_class 0 ; Flow J cc=True 0x2eaf
dispatch_csa_valid 0
dispatch_ibuff_fill 1
dispatch_ignore 1
dispatch_uadr 2ea8
fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
seq_b_timing 3 Late Condition, Hint False
seq_br_type 1 Branch True
seq_branch_adr 2eaf 0x2eaf
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 07 GP07
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
2ea9 2ea9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2eae
seq_br_type 1 Branch True
seq_branch_adr 2eae 0x2eae
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2eaa 2eaa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecd
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2eab 2eab val_a_adr 2d VR15:0d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2eac 2eac seq_b_timing 0 Early Condition; Flow J cc=False 0x2eac
seq_br_type 0 Branch False
seq_branch_adr 2eac 0x2eac
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2ead 2ead fiu_mem_start 2 start-rd; Flow R
ioc_adrbs 3 seq
seq_br_type e Unconditional Dispatch
seq_random 04 Load_save_offset+?
typ_mar_cntl e LOAD_MAR_CONTROL
2eae 2eae seq_br_type 3 Unconditional Branch; Flow J 0x2eac
seq_branch_adr 2eac 0x2eac
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_a_adr 3c VR16:1c
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2eaf 2eaf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2eb6
seq_br_type 1 Branch True
seq_branch_adr 2eb6 0x2eb6
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 07 GP07
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2eb0 2eb0 seq_br_type 1 Branch True; Flow J cc=True 0x2eb4
seq_branch_adr 2eb4 0x2eb4
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
2eb1 2eb1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ecd
seq_br_type 5 Call True
seq_branch_adr 2ecd GP_MACRO_EVENT_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 06 GP06
val_alu_func 19 X_XOR_B
val_b_adr 22 VR10:02
val_frame 10
2eb2 2eb2 val_a_adr 06 GP06
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2eb3 2eb3 seq_br_type 3 Unconditional Branch; Flow J 0x2eac
seq_branch_adr 2eac 0x2eac
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_a_adr 3f VR15:1f
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 15
2eb4 2eb4 val_a_adr 06 GP06
val_alu_func 1c DEC_A
val_c_adr 39 GP06
val_c_mux_sel 2 ALU
2eb5 2eb5 seq_br_type 3 Unconditional Branch; Flow J 0x2eac
seq_branch_adr 2eac 0x2eac
typ_alu_func 13 ONES
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
val_a_adr 3d VR16:1d
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 16
2eb6 2eb6 ioc_random f disable delay timer; Flow R
seq_br_type a Unconditional Return
typ_c_adr 38 GP07
typ_c_mux_sel 0 ALU
2eb7 ; --------------------------------------------------------------------------------------
2eb7 ; Comes from:
2eb7 ; 2e2d C from color 0x2e00
2eb7 ; 2e30 C from color 0x2e00
2eb7 ; 2e3b C from color 0x2e00
2eb7 ; 2e3e C from color 0x2e00
2eb7 ; 2e4b C from color 0x2e00
2eb7 ; 2e4e C from color 0x2e00
2eb7 ; 2e50 C from color 0x2e00
2eb7 ; --------------------------------------------------------------------------------------
2eb7 2eb7 seq_br_type 0 Branch False; Flow J cc=False 0x2ec9
seq_branch_adr 2ec9 TIMER_COUNT_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 01 GP01
typ_alu_func 6 A_MINUS_B
typ_b_adr 05 GP05
2eb8 2eb8 typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR05:10
typ_c_adr 39 GP06
typ_c_mux_sel 0 ALU
typ_frame 5
2eb9 2eb9 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False
; Flow J cc=True 0x2ec9
seq_br_type 9 Return False
seq_branch_adr 2ec9 TIMER_COUNT_ERROR
seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late)
typ_a_adr 01 GP01
typ_alu_func 5 DEC_A_MINUS_B
typ_b_adr 06 GP06
2eba ; --------------------------------------------------------------------------------------
2eba ; Comes from:
2eba ; 2e29 C from color 0x2e00
2eba ; 2e37 C from color 0x2e00
2eba ; 2e46 C from color 0x2e00
2eba ; --------------------------------------------------------------------------------------
2eba 2eba seq_b_timing 0 Early Condition; Flow R cc=True
seq_br_type 8 Return True
seq_branch_adr 2ebb 0x2ebb
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 28 VR17:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2ebb 2ebb seq_b_timing 0 Early Condition; Flow J cc=False 0x2ebb
seq_br_type 0 Branch False
seq_branch_adr 2ebb 0x2ebb
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2ebc 2ebc seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x2ebb
seq_br_type 8 Return True
seq_branch_adr 2ebb 0x2ebb
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
typ_a_adr 05 GP05
typ_alu_func 1 A_PLUS_B
typ_b_adr 30 TR05:10
typ_c_adr 3a GP05
typ_c_mux_sel 0 ALU
typ_frame 5
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 28 VR17:08
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 17
2ebd ; --------------------------------------------------------------------------------------
2ebd ; Comes from:
2ebd ; 2e2b C from color 0x2e00
2ebd ; 2e2e C from color 0x2e00
2ebd ; 2e39 C from color 0x2e00
2ebd ; 2e3c C from color 0x2e00
2ebd ; 2e49 C from color 0x2e00
2ebd ; 2e4c C from color 0x2e00
2ebd ; --------------------------------------------------------------------------------------
2ebd 2ebd val_a_adr 26 VR04:06
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2ebe 2ebe seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x2ebe
seq_br_type 8 Return True
seq_branch_adr 2ebe 0x2ebe
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2ebf ; --------------------------------------------------------------------------------------
2ebf ; Comes from:
2ebf ; 0111 C from color ME_SL_TIME
2ebf ; 2e13 C from color 0x2e00
2ebf ; 2e17 C from color 0x2e00
2ebf ; 2e1c C from color 0x2e00
2ebf ; 2e20 C from color 0x2e00
2ebf ; 2e27 C from color 0x2e00
2ebf ; 2e36 C from color 0x2e00
2ebf ; 2e44 C from color 0x2e00
2ebf ; 2e67 C from color MACRO_Illegal_-
2ebf ; 2e77 C from color MACRO_Illegal_-
2ebf ; 2e91 C from color MACRO_Declare_Variable_Record,Duplicate
2ebf ; 2e97 C from color MACRO_Declare_Variable_Record,Duplicate
2ebf ; --------------------------------------------------------------------------------------
2ebf 2ebf ioc_random 6 load slice timer; Flow J 0x2ec2
seq_br_type 3 Unconditional Branch
seq_branch_adr 2ec2 0x2ec2
seq_en_micro 0
typ_b_adr 03 GP03
2ec0 ; --------------------------------------------------------------------------------------
2ec0 ; Comes from:
2ec0 ; 0109 C from color ME_GP_TIME
2ec0 ; 2e02 C from color 0x2e00
2ec0 ; 2e06 C from color 0x2e00
2ec0 ; 2e0a C from color 0x2e00
2ec0 ; 2e0e C from color 0x2e00
2ec0 ; 2e28 C from color 0x2e00
2ec0 ; 2e35 C from color 0x2e00
2ec0 ; 2e43 C from color 0x2e00
2ec0 ; 2e57 C from color 0x2e00
2ec0 ; 2e79 C from color MACRO_Illegal_-
2ec0 ; 2ea4 C from color 0x2ea3
2ec0 ; --------------------------------------------------------------------------------------
2ec0 2ec0 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_load_tar 1 hold_tar
fiu_offs_lit 10
fiu_op_sel 3 insert
fiu_rdata_src 0 rotator
fiu_tivi_src 6 fiu_fiu
ioc_fiubs 2 typ
typ_a_adr 03 GP03
2ec1 2ec1 ioc_random 7 load delay timer; Flow J 0x2ec2
ioc_tvbs 2 fiu+val
seq_br_type 3 Unconditional Branch
seq_branch_adr 2ec2 0x2ec2
2ec2 2ec2 val_a_adr 25 VR04:05
val_alu_func 0 PASS_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 4
2ec3 2ec3 seq_b_timing 0 Early Condition; Flow R cc=True
; Flow J cc=False 0x2ec3
seq_br_type 8 Return True
seq_branch_adr 2ec3 0x2ec3
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
val_rand 2 DEC_LOOP_COUNTER
2ec4 ; --------------------------------------------------------------------------------------
2ec4 ; Comes from:
2ec4 ; 2e14 C from color 0x2e00
2ec4 ; 2e18 C from color 0x2e00
2ec4 ; 2e1d C from color 0x2e00
2ec4 ; 2e21 C from color 0x2e00
2ec4 ; 2e31 C from color 0x2e00
2ec4 ; 2e3a C from color 0x2e00
2ec4 ; 2e3d C from color 0x2e00
2ec4 ; 2e4a C from color 0x2e00
2ec4 ; 2e4d C from color 0x2e00
2ec4 ; --------------------------------------------------------------------------------------
2ec4 2ec4 ioc_random 9 read timer/checkbits/errorid; Flow R
ioc_tvbs 4 ioc+ioc
seq_br_type a Unconditional Return
typ_a_adr 36 TR17:16
typ_alu_func 1e A_AND_B
typ_b_adr 16 CSA/VAL_BUS
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 17
2ec5 ; --------------------------------------------------------------------------------------
2ec5 ; Comes from:
2ec5 ; 2e03 C from color 0x2e00
2ec5 ; 2e07 C from color 0x2e00
2ec5 ; 2e0b C from color 0x2e00
2ec5 ; 2e0f C from color 0x2e00
2ec5 ; 2e2c C from color 0x2e00
2ec5 ; 2e2f C from color 0x2e00
2ec5 ; 2e3f C from color 0x2e00
2ec5 ; 2e4f C from color 0x2e00
2ec5 ; --------------------------------------------------------------------------------------
2ec5 2ec5 fiu_len_fill_lit 3f sign-fill 0x3f
fiu_offs_lit 10
fiu_rdata_src 0 rotator
fiu_tivi_src 8 type_var
fiu_vmux_sel 1 fill value
ioc_fiubs 0 fiu
ioc_random 9 read timer/checkbits/errorid
ioc_tvbs 4 ioc+ioc
typ_c_adr 3e GP01
typ_c_source 0 FIU_BUS
2ec6 2ec6 seq_br_type a Unconditional Return; Flow R
typ_a_adr 36 TR17:16
typ_alu_func 1e A_AND_B
typ_b_adr 01 GP01
typ_c_adr 3e GP01
typ_c_mux_sel 0 ALU
typ_frame 17
2ec7 ; --------------------------------------------------------------------------------------
2ec7 ; Comes from:
2ec7 ; 2e04 C True from color 0x2e00
2ec7 ; 2e08 C True from color 0x2e00
2ec7 ; 2e0c C True from color 0x2e00
2ec7 ; 2e10 C True from color 0x2e00
2ec7 ; 2e15 C True from color 0x2e00
2ec7 ; 2e19 C True from color 0x2e00
2ec7 ; 2e1e C True from color 0x2e00
2ec7 ; 2e22 C True from color 0x2e00
2ec7 ; --------------------------------------------------------------------------------------
2ec7 TIMER_ERROR:
2ec7 2ec7 <halt> ; Flow R
2ec8 2ec8 seq_br_type a Unconditional Return; Flow R
2ec9 ; --------------------------------------------------------------------------------------
2ec9 ; Comes from:
2ec9 ; 2e32 C True from color 0x2e00
2ec9 ; 2e40 C True from color 0x2e00
2ec9 ; --------------------------------------------------------------------------------------
2ec9 TIMER_COUNT_ERROR:
2ec9 2ec9 <halt> ; Flow R
2eca 2eca seq_br_type a Unconditional Return; Flow R
2ecb ; --------------------------------------------------------------------------------------
2ecb ; Comes from:
2ecb ; 0110 C True from color ME_SL_TIME
2ecb ; 2e6d C True from color MACRO_Illegal_-
2ecb ; 2e72 C True from color MACRO_Illegal_-
2ecb ; 2e86 C True from color MACRO_Declare_Variable_Record,Duplicate
2ecb ; 2e9a C True from color MACRO_Illegal_-
2ecb ; --------------------------------------------------------------------------------------
2ecb SLICE_MACRO_EVENT_ERROR:
2ecb 2ecb <halt> ; Flow R
2ecc 2ecc seq_br_type a Unconditional Return; Flow R
2ecd ; --------------------------------------------------------------------------------------
2ecd ; Comes from:
2ecd ; 0108 C True from color ME_GP_TIME
2ecd ; 2e5d C True from color MACRO_Illegal_-
2ecd ; 2e62 C True from color MACRO_Illegal_-
2ecd ; 2e8c C True from color MACRO_Declare_Variable_Record,Duplicate
2ecd ; 2eaa C True from color MACRO_Complete_Type_Array,By_Component_Completion
2ecd ; 2eb1 C True from color MACRO_Complete_Type_Array,By_Component_Completion
2ecd ; --------------------------------------------------------------------------------------
2ecd GP_MACRO_EVENT_ERROR:
2ecd 2ecd <halt> ; Flow R
2ece 2ece seq_br_type a Unconditional Return; Flow R
2ecf 2ecf <halt> ; Flow R
2ed0 2ed0 <halt> ; Flow R
2ed1 2ed1 <halt> ; Flow R
2ed2 2ed2 <halt> ; Flow R
2ed3 2ed3 <halt> ; Flow R
2ed4 2ed4 <halt> ; Flow R
2ed5 2ed5 <halt> ; Flow R
2ed6 2ed6 <halt> ; Flow R
2ed7 2ed7 <halt> ; Flow R
2ed8 2ed8 <halt> ; Flow R
2ed9 2ed9 <halt> ; Flow R
2eda 2eda <halt> ; Flow R
2edb 2edb <halt> ; Flow R
2edc 2edc <halt> ; Flow R
2edd 2edd <halt> ; Flow R
2ede 2ede <halt> ; Flow R
2edf 2edf <halt> ; Flow R
2ee0 2ee0 <halt> ; Flow R
2ee1 2ee1 <halt> ; Flow R
2ee2 2ee2 <halt> ; Flow R
2ee3 2ee3 <halt> ; Flow R
2ee4 2ee4 <halt> ; Flow R
2ee5 2ee5 <halt> ; Flow R
2ee6 2ee6 <halt> ; Flow R
2ee7 2ee7 <halt> ; Flow R
2ee8 2ee8 <halt> ; Flow R
2ee9 2ee9 <halt> ; Flow R
2eea 2eea <halt> ; Flow R
2eeb 2eeb <halt> ; Flow R
2eec 2eec <halt> ; Flow R
2eed 2eed <halt> ; Flow R
2eee 2eee <halt> ; Flow R
2eef 2eef <halt> ; Flow R
2ef0 2ef0 <halt> ; Flow R
2ef1 2ef1 <halt> ; Flow R
2ef2 2ef2 <halt> ; Flow R
2ef3 2ef3 <halt> ; Flow R
2ef4 2ef4 <halt> ; Flow R
2ef5 2ef5 <halt> ; Flow R
2ef6 2ef6 <halt> ; Flow R
2ef7 2ef7 <halt> ; Flow R
2ef8 2ef8 <halt> ; Flow R
2ef9 2ef9 <halt> ; Flow R
2efa 2efa <halt> ; Flow R
2efb 2efb <halt> ; Flow R
2efc 2efc <halt> ; Flow R
2efd 2efd <halt> ; Flow R
2efe 2efe <halt> ; Flow R
2eff 2eff <halt> ; Flow R
2f00 2f00 <halt> ; Flow R
2f01 2f01 <halt> ; Flow R
2f02 2f02 <halt> ; Flow R
2f03 2f03 <halt> ; Flow R
2f04 2f04 <halt> ; Flow R
2f05 2f05 <halt> ; Flow R
2f06 2f06 <halt> ; Flow R
2f07 2f07 <halt> ; Flow R
2f08 2f08 <halt> ; Flow R
2f09 2f09 <halt> ; Flow R
2f0a 2f0a <halt> ; Flow R
2f0b 2f0b <halt> ; Flow R
2f0c 2f0c <halt> ; Flow R
2f0d 2f0d <halt> ; Flow R
2f0e 2f0e <halt> ; Flow R
2f0f 2f0f <halt> ; Flow R
2f10 2f10 <halt> ; Flow R
2f11 2f11 <halt> ; Flow R
2f12 2f12 <halt> ; Flow R
2f13 2f13 <halt> ; Flow R
2f14 2f14 <halt> ; Flow R
2f15 2f15 <halt> ; Flow R
2f16 2f16 <halt> ; Flow R
2f17 2f17 <halt> ; Flow R
2f18 2f18 <halt> ; Flow R
2f19 2f19 <halt> ; Flow R
2f1a 2f1a <halt> ; Flow R
2f1b 2f1b <halt> ; Flow R
2f1c 2f1c <halt> ; Flow R
2f1d 2f1d <halt> ; Flow R
2f1e 2f1e <halt> ; Flow R
2f1f 2f1f <halt> ; Flow R
2f20 2f20 <halt> ; Flow R
2f21 2f21 <halt> ; Flow R
2f22 2f22 <halt> ; Flow R
2f23 2f23 <halt> ; Flow R
2f24 2f24 <halt> ; Flow R
2f25 2f25 <halt> ; Flow R
2f26 2f26 <halt> ; Flow R
2f27 2f27 <halt> ; Flow R
2f28 2f28 <halt> ; Flow R
2f29 2f29 <halt> ; Flow R
2f2a 2f2a <halt> ; Flow R
2f2b 2f2b <halt> ; Flow R
2f2c 2f2c <halt> ; Flow R
2f2d 2f2d <halt> ; Flow R
2f2e 2f2e <halt> ; Flow R
2f2f 2f2f <halt> ; Flow R
2f30 2f30 <halt> ; Flow R
2f31 2f31 <halt> ; Flow R
2f32 2f32 <halt> ; Flow R
2f33 2f33 <halt> ; Flow R
2f34 2f34 <halt> ; Flow R
2f35 2f35 <halt> ; Flow R
2f36 2f36 <halt> ; Flow R
2f37 2f37 <halt> ; Flow R
2f38 2f38 <halt> ; Flow R
2f39 2f39 <halt> ; Flow R
2f3a 2f3a <halt> ; Flow R
2f3b 2f3b <halt> ; Flow R
2f3c 2f3c <halt> ; Flow R
2f3d 2f3d <halt> ; Flow R
2f3e 2f3e <halt> ; Flow R
2f3f 2f3f <halt> ; Flow R
2f40 2f40 <halt> ; Flow R
2f41 2f41 <halt> ; Flow R
2f42 2f42 <halt> ; Flow R
2f43 2f43 <halt> ; Flow R
2f44 2f44 <halt> ; Flow R
2f45 2f45 <halt> ; Flow R
2f46 2f46 <halt> ; Flow R
2f47 2f47 <halt> ; Flow R
2f48 2f48 <halt> ; Flow R
2f49 2f49 <halt> ; Flow R
2f4a 2f4a <halt> ; Flow R
2f4b 2f4b <halt> ; Flow R
2f4c 2f4c <halt> ; Flow R
2f4d 2f4d <halt> ; Flow R
2f4e 2f4e <halt> ; Flow R
2f4f 2f4f <halt> ; Flow R
2f50 2f50 <halt> ; Flow R
2f51 2f51 <halt> ; Flow R
2f52 2f52 <halt> ; Flow R
2f53 2f53 <halt> ; Flow R
2f54 2f54 <halt> ; Flow R
2f55 2f55 <halt> ; Flow R
2f56 2f56 <halt> ; Flow R
2f57 2f57 <halt> ; Flow R
2f58 2f58 <halt> ; Flow R
2f59 2f59 <halt> ; Flow R
2f5a 2f5a <halt> ; Flow R
2f5b 2f5b <halt> ; Flow R
2f5c 2f5c <halt> ; Flow R
2f5d 2f5d <halt> ; Flow R
2f5e 2f5e <halt> ; Flow R
2f5f 2f5f <halt> ; Flow R
2f60 2f60 <halt> ; Flow R
2f61 2f61 <halt> ; Flow R
2f62 2f62 <halt> ; Flow R
2f63 2f63 <halt> ; Flow R
2f64 2f64 <halt> ; Flow R
2f65 2f65 <halt> ; Flow R
2f66 2f66 <halt> ; Flow R
2f67 2f67 <halt> ; Flow R
2f68 2f68 <halt> ; Flow R
2f69 2f69 <halt> ; Flow R
2f6a 2f6a <halt> ; Flow R
2f6b 2f6b <halt> ; Flow R
2f6c 2f6c <halt> ; Flow R
2f6d 2f6d <halt> ; Flow R
2f6e 2f6e <halt> ; Flow R
2f6f 2f6f <halt> ; Flow R
2f70 2f70 <halt> ; Flow R
2f71 2f71 <halt> ; Flow R
2f72 2f72 <halt> ; Flow R
2f73 2f73 <halt> ; Flow R
2f74 2f74 <halt> ; Flow R
2f75 2f75 <halt> ; Flow R
2f76 2f76 <halt> ; Flow R
2f77 2f77 <halt> ; Flow R
2f78 2f78 <halt> ; Flow R
2f79 2f79 <halt> ; Flow R
2f7a 2f7a <halt> ; Flow R
2f7b 2f7b <halt> ; Flow R
2f7c 2f7c <halt> ; Flow R
2f7d 2f7d <halt> ; Flow R
2f7e 2f7e <halt> ; Flow R
2f7f 2f7f <halt> ; Flow R
2f80 2f80 <halt> ; Flow R
2f81 2f81 <halt> ; Flow R
2f82 2f82 <halt> ; Flow R
2f83 2f83 <halt> ; Flow R
2f84 2f84 <halt> ; Flow R
2f85 2f85 <halt> ; Flow R
2f86 2f86 <halt> ; Flow R
2f87 2f87 <halt> ; Flow R
2f88 2f88 <halt> ; Flow R
2f89 2f89 <halt> ; Flow R
2f8a 2f8a <halt> ; Flow R
2f8b 2f8b <halt> ; Flow R
2f8c 2f8c <halt> ; Flow R
2f8d 2f8d <halt> ; Flow R
2f8e 2f8e <halt> ; Flow R
2f8f 2f8f <halt> ; Flow R
2f90 2f90 <halt> ; Flow R
2f91 2f91 <halt> ; Flow R
2f92 2f92 <halt> ; Flow R
2f93 2f93 <halt> ; Flow R
2f94 2f94 <halt> ; Flow R
2f95 2f95 <halt> ; Flow R
2f96 2f96 <halt> ; Flow R
2f97 2f97 <halt> ; Flow R
2f98 2f98 <halt> ; Flow R
2f99 2f99 <halt> ; Flow R
2f9a 2f9a <halt> ; Flow R
2f9b 2f9b <halt> ; Flow R
2f9c 2f9c <halt> ; Flow R
2f9d 2f9d <halt> ; Flow R
2f9e 2f9e <halt> ; Flow R
2f9f 2f9f <halt> ; Flow R
2fa0 2fa0 <halt> ; Flow R
2fa1 2fa1 <halt> ; Flow R
2fa2 2fa2 <halt> ; Flow R
2fa3 2fa3 <halt> ; Flow R
2fa4 2fa4 <halt> ; Flow R
2fa5 2fa5 <halt> ; Flow R
2fa6 2fa6 <halt> ; Flow R
2fa7 2fa7 <halt> ; Flow R
2fa8 2fa8 <halt> ; Flow R
2fa9 2fa9 <halt> ; Flow R
2faa 2faa <halt> ; Flow R
2fab 2fab <halt> ; Flow R
2fac 2fac <halt> ; Flow R
2fad 2fad <halt> ; Flow R
2fae 2fae <halt> ; Flow R
2faf 2faf <halt> ; Flow R
2fb0 2fb0 <halt> ; Flow R
2fb1 2fb1 <halt> ; Flow R
2fb2 2fb2 <halt> ; Flow R
2fb3 2fb3 <halt> ; Flow R
2fb4 2fb4 <halt> ; Flow R
2fb5 2fb5 <halt> ; Flow R
2fb6 2fb6 <halt> ; Flow R
2fb7 2fb7 <halt> ; Flow R
2fb8 2fb8 <halt> ; Flow R
2fb9 2fb9 <halt> ; Flow R
2fba 2fba <halt> ; Flow R
2fbb 2fbb <halt> ; Flow R
2fbc 2fbc <halt> ; Flow R
2fbd 2fbd <halt> ; Flow R
2fbe 2fbe <halt> ; Flow R
2fbf 2fbf <halt> ; Flow R
2fc0 2fc0 <halt> ; Flow R
2fc1 2fc1 <halt> ; Flow R
2fc2 2fc2 <halt> ; Flow R
2fc3 2fc3 <halt> ; Flow R
2fc4 2fc4 <halt> ; Flow R
2fc5 2fc5 <halt> ; Flow R
2fc6 2fc6 <halt> ; Flow R
2fc7 2fc7 <halt> ; Flow R
2fc8 2fc8 <halt> ; Flow R
2fc9 2fc9 <halt> ; Flow R
2fca 2fca <halt> ; Flow R
2fcb 2fcb <halt> ; Flow R
2fcc 2fcc <halt> ; Flow R
2fcd 2fcd <halt> ; Flow R
2fce 2fce <halt> ; Flow R
2fcf 2fcf <halt> ; Flow R
2fd0 2fd0 <halt> ; Flow R
2fd1 2fd1 <halt> ; Flow R
2fd2 2fd2 <halt> ; Flow R
2fd3 2fd3 <halt> ; Flow R
2fd4 2fd4 <halt> ; Flow R
2fd5 2fd5 <halt> ; Flow R
2fd6 2fd6 <halt> ; Flow R
2fd7 2fd7 <halt> ; Flow R
2fd8 2fd8 <halt> ; Flow R
2fd9 2fd9 <halt> ; Flow R
2fda 2fda <halt> ; Flow R
2fdb 2fdb <halt> ; Flow R
2fdc 2fdc <halt> ; Flow R
2fdd 2fdd <halt> ; Flow R
2fde 2fde <halt> ; Flow R
2fdf 2fdf <halt> ; Flow R
2fe0 2fe0 <halt> ; Flow R
2fe1 2fe1 <halt> ; Flow R
2fe2 2fe2 <halt> ; Flow R
2fe3 2fe3 <halt> ; Flow R
2fe4 2fe4 <halt> ; Flow R
2fe5 2fe5 <halt> ; Flow R
2fe6 2fe6 <halt> ; Flow R
2fe7 2fe7 <halt> ; Flow R
2fe8 2fe8 <halt> ; Flow R
2fe9 2fe9 <halt> ; Flow R
2fea 2fea <halt> ; Flow R
2feb 2feb <halt> ; Flow R
2fec 2fec <halt> ; Flow R
2fed 2fed <halt> ; Flow R
2fee 2fee <halt> ; Flow R
2fef 2fef <halt> ; Flow R
2ff0 2ff0 <halt> ; Flow R
2ff1 2ff1 <halt> ; Flow R
2ff2 2ff2 <halt> ; Flow R
2ff3 2ff3 <halt> ; Flow R
2ff4 2ff4 <halt> ; Flow R
2ff5 2ff5 <halt> ; Flow R
2ff6 2ff6 <halt> ; Flow R
2ff7 2ff7 <halt> ; Flow R
2ff8 2ff8 <halt> ; Flow R
2ff9 2ff9 <halt> ; Flow R
2ffa 2ffa <halt> ; Flow R
2ffb 2ffb <halt> ; Flow R
2ffc 2ffc <halt> ; Flow R
2ffd 2ffd <halt> ; Flow R
2ffe 2ffe <halt> ; Flow R
2fff 2fff <halt> ; Flow R
3000 ; --------------------------------------------------------------------------------------
3000 ; 3000 - 32AA RF_TEST
3000 ; Comes from:
3000 ; 0322 C from color 0x0104
3000 ; 0324 C from color 0x0106
3000 ; --------------------------------------------------------------------------------------
3000 3000 seq_br_type 1 Branch True; Flow J cc=True 0x3002
seq_branch_adr 3002 0x3002
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
3001 3001 seq_br_type 7 Unconditional Call; Flow C 0x3247
seq_branch_adr 3247 VAL_ALU_ZERO_CHECK_FAILED
3002 3002 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3247
seq_br_type 5 Call True
seq_branch_adr 3247 VAL_ALU_ZERO_CHECK_FAILED
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
3003 3003 seq_br_type 1 Branch True; Flow J cc=True 0x3005
seq_branch_adr 3005 0x3005
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 13 ONES
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
3004 3004 seq_br_type 7 Unconditional Call; Flow C 0x3249
seq_branch_adr 3249 VAL_ALU_ONES_CHECK_FAILED
3005 3005 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3249
seq_br_type 5 Call True
seq_branch_adr 3249 VAL_ALU_ONES_CHECK_FAILED
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_alu_func 13 ONES
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
3006 3006 val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3007 3007 seq_br_type 1 Branch True; Flow J cc=True 0x3009
seq_branch_adr 3009 0x3009
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 19 X_XOR_B
val_b_adr 3f VGPf
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
3008 3008 seq_br_type 7 Unconditional Call; Flow C 0x324b
seq_branch_adr 324b VAL_REG_COMPARE_FAILED
3009 3009 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x324b
seq_br_type 5 Call True
seq_branch_adr 324b VAL_REG_COMPARE_FAILED
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3f VGPf
val_alu_func 19 X_XOR_B
val_b_adr 3f VGPf
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
300a 300a val_alu_func 13 ONES
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
300b 300b val_a_adr 3f VGPf
val_alu_func 7 INC_A
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
val_frame 1f
300c 300c seq_b_timing 0 Early Condition; Flow J cc=True 0x300e
seq_br_type 1 Branch True
seq_branch_adr 300e 0x300e
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
300d 300d seq_br_type 7 Unconditional Call; Flow C 0x324f
seq_branch_adr 324f VAL_INC_A_FAILED
300e 300e val_alu_func 13 ONES
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
300f 300f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3251
seq_br_type 5 Call True
seq_branch_adr 3251 VAL_START_BIT64_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3f VGPf
val_alu_func 7 INC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
3010 3010 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 0 PASS_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
3011 3011 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3012 3012 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3013 3013 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3014 3014 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3015 3015 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3016 3016 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3017 3017 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3018 3018 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3019 3019 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301a 301a seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301b 301b seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301c 301c seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301d 301d seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301e 301e seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
301f 301f seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3020 3020 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3021 3021 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3022 3022 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3023 3023 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3024 3024 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3025 3025 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3026 3026 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3027 3027 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3028 3028 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3029 3029 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302a 302a seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302b 302b seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302c 302c seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302d 302d seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302e 302e seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
302f 302f seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3030 3030 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3031 3031 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3032 3032 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3033 3033 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3034 3034 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3035 3035 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3036 3036 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3037 3037 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3038 3038 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3039 3039 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303a 303a seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303b 303b seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303c 303c seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303d 303d seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303e 303e seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
303f 303f seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3040 3040 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3041 3041 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3042 3042 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3043 3043 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3044 3044 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3045 3045 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3046 3046 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3047 3047 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3048 3048 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3049 3049 seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304a 304a seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304b 304b seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304c 304c seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304d 304d seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304e 304e seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
304f 304f seq_br_type 4 Call False; Flow C cc=False 0x3253
seq_branch_adr 3253 VAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3050 3050 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3255
seq_br_type 5 Call True
seq_branch_adr 3255 VAL_FINAL_BIT64_ERROR
seq_cond_sel 0a VAL.ALU_LT_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3051 3051 val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3052 3052 val_a_adr 3f VGPf
val_alu_func 7 INC_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3053 3053 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3257
seq_br_type 5 Call True
seq_branch_adr 3257 VAL_START_ALU_NE_0_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3f VGPf
val_alu_func 1c DEC_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
3054 3054 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 0 PASS_A
val_c_adr 3d GP02
val_c_mux_sel 2 ALU
val_frame 1f
3055 3055 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3056 3056 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3057 3057 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3058 3058 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3059 3059 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305a 305a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305b 305b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305c 305c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305d 305d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305e 305e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
305f 305f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3060 3060 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3061 3061 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3062 3062 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3063 3063 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3064 3064 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3065 3065 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3066 3066 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3067 3067 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3068 3068 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3069 3069 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306a 306a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306b 306b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306c 306c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306d 306d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306e 306e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
306f 306f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3070 3070 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3071 3071 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3072 3072 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3073 3073 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3074 3074 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3075 3075 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3076 3076 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3077 3077 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3078 3078 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3079 3079 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307a 307a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307b 307b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307c 307c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307d 307d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307e 307e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
307f 307f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3080 3080 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3081 3081 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3082 3082 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3083 3083 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3084 3084 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3085 3085 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3086 3086 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3087 3087 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3088 3088 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3089 3089 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308a 308a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308b 308b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308c 308c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308d 308d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308e 308e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
308f 308f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3090 3090 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3091 3091 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3092 3092 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3093 3093 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3259
seq_br_type 5 Call True
seq_branch_adr 3259 VAL_ALU_NE_0_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3094 3094 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x325b
seq_br_type 5 Call True
seq_branch_adr 325b VAL_FINAL_ALU_NE_0_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3095 3095 seq_br_type 1 Branch True; Flow J cc=True 0x3097
seq_branch_adr 3097 0x3097
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
3096 3096 seq_br_type 7 Unconditional Call; Flow C 0x325d
seq_branch_adr 325d TYP_ALU_ZERO_CHECK_FAILED
3097 3097 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x325d
seq_br_type 5 Call True
seq_branch_adr 325d TYP_ALU_ZERO_CHECK_FAILED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
3098 3098 seq_br_type 1 Branch True; Flow J cc=True 0x309a
seq_branch_adr 309a 0x309a
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 13 ONES
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
3099 3099 seq_br_type 7 Unconditional Call; Flow C 0x325f
seq_branch_adr 325f TYP_ALU_ONES_CHECK_FAILED
309a 309a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x325f
seq_br_type 5 Call True
seq_branch_adr 325f TYP_ALU_ONES_CHECK_FAILED
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_alu_func 13 ONES
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
309b 309b typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
309c 309c seq_br_type 1 Branch True; Flow J cc=True 0x309e
seq_branch_adr 309e 0x309e
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TGPf
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
309d 309d seq_br_type 7 Unconditional Call; Flow C 0x3261
seq_branch_adr 3261 TYP_REG_COMPARE_FAILED
309e 309e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3261
seq_br_type 5 Call True
seq_branch_adr 3261 TYP_REG_COMPARE_FAILED
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TGPf
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
309f 309f typ_alu_func 13 ONES
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30a0 30a0 typ_a_adr 3f TGPf
typ_alu_func 7 INC_A
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
typ_frame 1f
30a1 30a1 seq_b_timing 0 Early Condition; Flow J cc=True 0x30a3
seq_br_type 1 Branch True
seq_branch_adr 30a3 0x30a3
seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early)
30a2 30a2 seq_br_type 7 Unconditional Call; Flow C 0x3265
seq_branch_adr 3265 TYP_INC_A_FAILED
30a3 30a3 typ_alu_func 13 ONES
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30a4 30a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3267
seq_br_type 5 Call True
seq_branch_adr 3267 TYP_START_BIT64_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 7 INC_A
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
30a5 30a5 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 0 PASS_A
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
30a6 30a6 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30a7 30a7 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30a8 30a8 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30a9 30a9 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30aa 30aa seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ab 30ab seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ac 30ac seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ad 30ad seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ae 30ae seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30af 30af seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b0 30b0 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b1 30b1 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b2 30b2 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b3 30b3 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b4 30b4 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b5 30b5 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b6 30b6 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b7 30b7 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b8 30b8 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30b9 30b9 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ba 30ba seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30bb 30bb seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30bc 30bc seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30bd 30bd seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30be 30be seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30bf 30bf seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c0 30c0 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c1 30c1 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c2 30c2 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c3 30c3 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c4 30c4 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c5 30c5 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c6 30c6 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c7 30c7 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c8 30c8 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30c9 30c9 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ca 30ca seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30cb 30cb seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30cc 30cc seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30cd 30cd seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ce 30ce seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30cf 30cf seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d0 30d0 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d1 30d1 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d2 30d2 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d3 30d3 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d4 30d4 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d5 30d5 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d6 30d6 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d7 30d7 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d8 30d8 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30d9 30d9 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30da 30da seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30db 30db seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30dc 30dc seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30dd 30dd seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30de 30de seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30df 30df seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e0 30e0 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e1 30e1 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e2 30e2 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e3 30e3 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e4 30e4 seq_br_type 4 Call False; Flow C cc=False 0x3269
seq_branch_adr 3269 TYP_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e5 30e5 seq_br_type 5 Call True; Flow C cc=True 0x326b
seq_branch_adr 326b TYP_FINAL_BIT64_ERROR
seq_cond_sel 22 TYP.ALU_LT_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e6 30e6 typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e7 30e7 typ_a_adr 3f TGPf
typ_alu_func 7 INC_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30e8 30e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326d
seq_br_type 5 Call True
seq_branch_adr 326d TYP_START_ALU_NE_0_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 1c DEC_A
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
30e9 30e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 0 PASS_A
typ_c_adr 3d GP02
typ_c_mux_sel 0 ALU
typ_frame 1f
30ea 30ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30eb 30eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ec 30ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ed 30ed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ee 30ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ef 30ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f0 30f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f1 30f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f2 30f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f3 30f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f4 30f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f5 30f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f6 30f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f7 30f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f8 30f8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30f9 30f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30fa 30fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30fb 30fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30fc 30fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30fd 30fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30fe 30fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
30ff 30ff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3100 3100 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3101 3101 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3102 3102 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3103 3103 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3104 3104 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3105 3105 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3106 3106 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3107 3107 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3108 3108 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3109 3109 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310a 310a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310b 310b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310c 310c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310d 310d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310e 310e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
310f 310f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3110 3110 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3111 3111 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3112 3112 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3113 3113 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3114 3114 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3115 3115 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3116 3116 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3117 3117 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3118 3118 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3119 3119 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311a 311a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311b 311b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311c 311c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311d 311d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311e 311e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
311f 311f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3120 3120 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3121 3121 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3122 3122 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3123 3123 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3124 3124 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3125 3125 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3126 3126 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3127 3127 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3128 3128 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x326f
seq_br_type 5 Call True
seq_branch_adr 326f TYP_ALU_NE_0_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
3129 3129 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3271
seq_br_type 5 Call True
seq_branch_adr 3271 TYP_FINAL_ALU_NE_0_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
312a 312a typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
312b 312b typ_a_adr 3f TGPf
typ_alu_func 7 INC_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 7 INC_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
312c 312c typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
312d 312d typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
312e 312e typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
312f 312f typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3130 3130 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3131 3131 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3132 3132 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3133 3133 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3134 3134 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3135 3135 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3136 3136 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3137 3137 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3138 3138 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3139 3139 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313a 313a typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313b 313b typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313c 313c typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313d 313d typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313e 313e typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
313f 313f typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3140 3140 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3141 3141 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3142 3142 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3143 3143 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3144 3144 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3145 3145 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3146 3146 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3147 3147 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3148 3148 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3149 3149 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314a 314a typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314b 314b typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314c 314c typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314d 314d typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314e 314e typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
314f 314f typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3150 3150 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3151 3151 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3152 3152 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3153 3153 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3154 3154 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3155 3155 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3156 3156 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3157 3157 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3158 3158 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3159 3159 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315a 315a typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315b 315b typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315c 315c typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315d 315d typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315e 315e typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
315f 315f typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3160 3160 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3161 3161 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3162 3162 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3163 3163 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3164 3164 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3165 3165 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3166 3166 typ_a_adr 3f TGPf
typ_alu_func 3 LEFT_I_A
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 3 LEFT_I_A
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3167 3167 typ_a_adr 3f TGPf
typ_alu_func 4 LEFT_I_A_INC
typ_c_adr 00 TGPf
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 4 LEFT_I_A_INC
val_c_adr 00 VGPf
val_c_mux_sel 2 ALU
val_frame 1f
3168 3168 typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3169 3169 typ_a_adr 3f TGPf
typ_alu_func 0 PASS_A
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3f VGPf
val_alu_func 0 PASS_A
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
316a 316a typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
316b 316b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3293
seq_br_type 5 Call True
seq_branch_adr 3293 VAL_REG_BAD_LOAD
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3f VGPf
val_frame 1f
316c 316c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
316d 316d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
316e 316e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3297
seq_br_type 5 Call True
seq_branch_adr 3297 TYP_REG_BAD_LOAD
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TGPf
typ_frame 1f
316f 316f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
3170 3170 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
3171 3171 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3172 3172 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
3173 3173 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
3174 3174 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
3175 3175 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
3176 3176 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
3177 3177 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3178 3178 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
3179 3179 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
317a 317a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
317b 317b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
317c 317c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
317d 317d typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
317e 317e typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
317f 317f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
3180 3180 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
3181 3181 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
3182 3182 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
3183 3183 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3184 3184 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
3185 3185 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
3186 3186 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
3187 3187 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
3188 3188 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
3189 3189 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
318a 318a typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
318b 318b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
318c 318c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
318d 318d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
318e 318e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
318f 318f typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3190 3190 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
3191 3191 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
3192 3192 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
3193 3193 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
3194 3194 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
3195 3195 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
3196 3196 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
3197 3197 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
3198 3198 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
3199 3199 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
319a 319a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
319b 319b typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
319c 319c typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
319d 319d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
319e 319e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
319f 319f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31a0 31a0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31a1 31a1 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31a2 31a2 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31a3 31a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31a4 31a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31a5 31a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31a6 31a6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31a7 31a7 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31a8 31a8 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31a9 31a9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31aa 31aa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31ab 31ab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31ac 31ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31ad 31ad typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31ae 31ae typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31af 31af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31b0 31b0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31b1 31b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31b2 31b2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31b3 31b3 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31b4 31b4 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31b5 31b5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31b6 31b6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31b7 31b7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31b8 31b8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31b9 31b9 typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31ba 31ba typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31bb 31bb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31bc 31bc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31bd 31bd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31be 31be seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31bf 31bf typ_a_adr 3e TGPe
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 01 TGPe
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3e VGPe
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 01 VGPe
val_c_mux_sel 2 ALU
val_frame 1f
31c0 31c0 typ_a_adr 3d TGPd
typ_alu_func 1 A_PLUS_B
typ_b_adr 3f TGPf
typ_c_adr 02 TGPd
typ_c_mux_sel 0 ALU
typ_frame 1f
val_a_adr 3d VGPd
val_alu_func 1 A_PLUS_B
val_b_adr 3f VGPf
val_c_adr 02 VGPd
val_c_mux_sel 2 ALU
val_frame 1f
31c1 31c1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31c2 31c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3295
seq_br_type 5 Call True
seq_branch_adr 3295 VAL_NIBBLE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31c3 31c3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
31c4 31c4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3299
seq_br_type 5 Call True
seq_branch_adr 3299 TYP_NIBBLE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
31c5 31c5 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
typ_alu_func 13 ONES
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
val_alu_func 13 ONES
val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
31c6 31c6 seq_b_timing 0 Early Condition; Flow J cc=False 0x31c6
seq_br_type 0 Branch False
seq_branch_adr 31c6 0x31c6
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
31c7 31c7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3273
seq_br_type 5 Call True
seq_branch_adr 3273 TYP_A_SIDE_ZERO_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 0 PASS_A
31c8 31c8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3275
seq_br_type 5 Call True
seq_branch_adr 3275 TYP_B_SIDE_ZERO_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 1a PASS_B
typ_b_adr 13 LOOP_REG
31c9 31c9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3277
seq_br_type 5 Call True
seq_branch_adr 3277 TYP_A_B_ZERO_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
31ca 31ca seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3279
seq_br_type 5 Call True
seq_branch_adr 3279 VAL_A_SIDE_ZERO_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 0 PASS_A
31cb 31cb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x327b
seq_br_type 5 Call True
seq_branch_adr 327b VAL_B_SIDE_ZERO_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 1a PASS_B
val_b_adr 13 LOOP_REG
31cc 31cc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x327d
seq_br_type 5 Call True
seq_branch_adr 327d VAL_A_B_ZERO_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31cd 31cd seq_b_timing 0 Early Condition; Flow J cc=False 0x31c7
seq_br_type 0 Branch False
seq_branch_adr 31c7 0x31c7
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
31ce 31ce fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
31cf 31cf seq_b_timing 0 Early Condition; Flow J cc=False 0x31cf
seq_br_type 0 Branch False
seq_branch_adr 31cf 0x31cf
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_alu_func 13 ONES
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_alu_func 13 ONES
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
31d0 31d0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x327f
seq_br_type 5 Call True
seq_branch_adr 327f TYP_A_SIDE_ONES_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 10 NOT_A
31d1 31d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3281
seq_br_type 5 Call True
seq_branch_adr 3281 TYP_B_SIDE_ONES_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_alu_func 15 NOT_B
typ_b_adr 13 LOOP_REG
31d2 31d2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3283
seq_br_type 5 Call True
seq_branch_adr 3283 TYP_A_B_ONES_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
31d3 31d3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3285
seq_br_type 5 Call True
seq_branch_adr 3285 VAL_A_SIDE_ONES_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 10 NOT_A
31d4 31d4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3287
seq_br_type 5 Call True
seq_branch_adr 3287 VAL_B_SIDE_ONES_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_alu_func 15 NOT_B
val_b_adr 13 LOOP_REG
31d5 31d5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3289
seq_br_type 5 Call True
seq_branch_adr 3289 VAL_A_B_ONES_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31d6 31d6 seq_b_timing 0 Early Condition; Flow J cc=False 0x31d0
seq_br_type 0 Branch False
seq_branch_adr 31d0 0x31d0
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
31d7 31d7 fiu_mem_start 18 acknowledge_refresh
fiu_tivi_src c mar_0xc
31d8 31d8 seq_b_timing 0 Early Condition; Flow J cc=False 0x31d8
seq_br_type 0 Branch False
seq_branch_adr 31d8 0x31d8
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 0 PASS_A
typ_c_adr 2c LOOP_REG
typ_c_mux_sel 0 ALU
typ_rand d SET_PASS_PRIVACY_BIT
val_a_adr 17 LOOP_COUNTER
val_alu_func 0 PASS_A
val_c_adr 2c LOOP_REG
val_c_mux_sel 2 ALU
val_rand 2 DEC_LOOP_COUNTER
31d9 31d9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x328b
seq_br_type 5 Call True
seq_branch_adr 328b TYP_COUNTER_CONTENTS_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 17 LOOP_COUNTER
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
31da 31da seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x328d
seq_br_type 5 Call True
seq_branch_adr 328d TYP_COMPARE_ERROR
seq_cond_sel 19 TYP.ALU_NONZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
31db 31db seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x328b
seq_br_type 5 Call True
seq_branch_adr 328b TYP_COUNTER_CONTENTS_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 17 LOOP_COUNTER
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31dc 31dc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x328d
seq_br_type 5 Call True
seq_branch_adr 328d TYP_COMPARE_ERROR
seq_cond_sel 01 VAL.ALU_NONZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31dd 31dd seq_b_timing 0 Early Condition; Flow J cc=False 0x31d9
seq_br_type 0 Branch False
seq_branch_adr 31d9 0x31d9
seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early)
typ_rand d SET_PASS_PRIVACY_BIT
val_rand 2 DEC_LOOP_COUNTER
31de 31de fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x31e0
fiu_tivi_src c mar_0xc
seq_br_type 1 Branch True
seq_branch_adr 31e0 0x31e0
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VGPf
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31df 31df seq_br_type 7 Unconditional Call; Flow C 0x329b
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
31e0 31e0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3e VGPe
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31e1 31e1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3d VGPd
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31e2 31e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3b VGPb
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31e3 31e3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 37 VGP7
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31e4 31e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 2f VCSAf
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1f
31e5 31e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VR1e:1f
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1e
31e6 31e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VR1d:1f
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1d
31e7 31e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VR1b:1f
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1b
31e8 31e8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VR17:1f
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 17
31e9 31e9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 3f VR0f:1f
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame f
31ea 31ea seq_br_type 1 Branch True; Flow J cc=True 0x31ec
seq_branch_adr 31ec 0x31ec
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VGPf
val_frame 1f
31eb 31eb seq_br_type 7 Unconditional Call; Flow C 0x329f
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
31ec 31ec seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3e VGPe
val_frame 1f
31ed 31ed seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3d VGPd
val_frame 1f
31ee 31ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3b VGPb
val_frame 1f
31ef 31ef seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 37 VGP7
val_frame 1f
31f0 31f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 2f VCSAf
val_frame 1f
31f1 31f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VR1e:1f
val_frame 1e
31f2 31f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VR1d:1f
val_frame 1d
31f3 31f3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VR1b:1f
val_frame 1b
31f4 31f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VR17:1f
val_frame 17
31f5 31f5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 3f VR0f:1f
val_frame f
31f6 31f6 val_c_adr 28 LOOP_COUNTER
val_c_mux_sel 2 ALU
31f7 31f7 seq_br_type 1 Branch True; Flow J cc=True 0x31f9
seq_branch_adr 31f9 0x31f9
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR00:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31f8 31f8 seq_br_type 7 Unconditional Call; Flow C 0x329b
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
31f9 31f9 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 21 VR00:01
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31fa 31fa seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 22 VR00:02
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31fb 31fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 24 VR00:04
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31fc 31fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 28 VR00:08
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31fd 31fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329b
seq_br_type 5 Call True
seq_branch_adr 329b VAL_A_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 30 VR00:10
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
31fe 31fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR01:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 1
31ff 31ff seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR02:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 2
3200 3200 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR04:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 4
3201 3201 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR08:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 8
3202 3202 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329d
seq_br_type 5 Call True
seq_branch_adr 329d VAL_A_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 20 VR10:00
val_alu_func 19 X_XOR_B
val_b_adr 13 LOOP_REG
val_frame 10
3203 3203 seq_br_type 1 Branch True; Flow J cc=True 0x3205
seq_branch_adr 3205 0x3205
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR00:00
3204 3204 seq_br_type 7 Unconditional Call; Flow C 0x329f
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
3205 3205 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 21 VR00:01
3206 3206 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 22 VR00:02
3207 3207 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 24 VR00:04
3208 3208 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 28 VR00:08
3209 3209 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x329f
seq_br_type 5 Call True
seq_branch_adr 329f VAL_B_SIDE_ADDR_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 30 VR00:10
320a 320a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR01:00
val_frame 1
320b 320b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR02:00
val_frame 2
320c 320c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR04:00
val_frame 4
320d 320d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR08:00
val_frame 8
320e 320e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a1
seq_br_type 5 Call True
seq_branch_adr 32a1 VAL_B_SIDE_FRAME_ERROR
seq_cond_sel 00 VAL.ALU_ZERO(late)
val_a_adr 13 LOOP_REG
val_alu_func 19 X_XOR_B
val_b_adr 20 VR10:00
val_frame 10
320f 320f typ_alu_func 13 ONES
typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
3210 3210 seq_br_type 1 Branch True; Flow J cc=True 0x3211
seq_branch_adr 3211 0x3211
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TGPf
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3211 3211 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3e TGPe
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3212 3212 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3d TGPd
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3213 3213 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3b TGPb
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3214 3214 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 37 TGP7
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3215 3215 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 2f TCSAf
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1f
3216 3216 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TR1e:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1e
3217 3217 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TR1d:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1d
3218 3218 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TR1b:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1b
3219 3219 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TR17:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 17
321a 321a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 3f TR0f:1f
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame f
321b 321b seq_br_type 1 Branch True; Flow J cc=True 0x321d
seq_branch_adr 321d 0x321d
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TGPf
typ_frame 1f
321c 321c seq_br_type 7 Unconditional Call; Flow C 0x32a7
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
321d 321d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3e TGPe
typ_frame 1f
321e 321e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3d TGPd
typ_frame 1f
321f 321f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3b TGPb
typ_frame 1f
3220 3220 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 37 TGP7
typ_frame 1f
3221 3221 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 2f TCSAf
typ_frame 1f
3222 3222 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR1e:1f
typ_frame 1e
3223 3223 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR1d:1f
typ_frame 1d
3224 3224 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR1b:1f
typ_frame 1b
3225 3225 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR17:1f
typ_frame 17
3226 3226 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 3f TR0f:1f
typ_frame f
3227 3227 typ_c_adr 28 LOOP_COUNTER
typ_c_mux_sel 0 ALU
3228 3228 seq_br_type 1 Branch True; Flow J cc=True 0x322a
seq_branch_adr 322a 0x322a
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR00:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
3229 3229 seq_br_type 7 Unconditional Call; Flow C 0x32a3
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
322a 322a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 21 TR00:01
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
322b 322b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 22 TR00:02
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
322c 322c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 24 TR00:04
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
322d 322d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 28 TR00:08
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
322e 322e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3
seq_br_type 5 Call True
seq_branch_adr 32a3 TYP_A_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 30 TR00:10
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
322f 322f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR01:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 1
3230 3230 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR02:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 2
3231 3231 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR04:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 4
3232 3232 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR08:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 8
3233 3233 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5
seq_br_type 5 Call True
seq_branch_adr 32a5 TYP_A_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 20 TR10:00
typ_alu_func 19 X_XOR_B
typ_b_adr 13 LOOP_REG
typ_frame 10
3234 3234 seq_br_type 1 Branch True; Flow J cc=True 0x3236
seq_branch_adr 3236 0x3236
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR00:00
3235 3235 seq_br_type 7 Unconditional Call; Flow C 0x32a7
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
3236 3236 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 21 TR00:01
3237 3237 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 22 TR00:02
3238 3238 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 24 TR00:04
3239 3239 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 28 TR00:08
323a 323a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7
seq_br_type 5 Call True
seq_branch_adr 32a7 TYP_B_SIDE_ADDR_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 30 TR00:10
323b 323b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR01:00
typ_frame 1
323c 323c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR02:00
typ_frame 2
323d 323d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR04:00
typ_frame 4
323e 323e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR08:00
typ_frame 8
323f 323f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9
seq_br_type 5 Call True
seq_branch_adr 32a9 TYP_B_SIDE_FRAME_ERROR
seq_cond_sel 18 TYP.ALU_ZERO(late)
typ_a_adr 13 LOOP_REG
typ_alu_func 19 X_XOR_B
typ_b_adr 20 TR10:00
typ_frame 10
3240 3240 seq_br_type a Unconditional Return; Flow R
3241 VAL_INC_FAILED:
3241 3241 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3242 3242 seq_br_type a Unconditional Return; Flow R
3243 TYP_COUNTER_ERROR:
3243 3243 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3244 3244 seq_br_type a Unconditional Return; Flow R
3245 TYP_INC_FAILED:
3245 3245 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3246 3246 seq_br_type a Unconditional Return; Flow R
3247 ; --------------------------------------------------------------------------------------
3247 ; Comes from:
3247 ; 3001 C from color 0x3000
3247 ; 3002 C True from color 0x3000
3247 ; --------------------------------------------------------------------------------------
3247 VAL_ALU_ZERO_CHECK_FAILED:
3247 3247 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3248 3248 seq_br_type a Unconditional Return; Flow R
3249 ; --------------------------------------------------------------------------------------
3249 ; Comes from:
3249 ; 3004 C from color 0x3000
3249 ; 3005 C True from color 0x3000
3249 ; --------------------------------------------------------------------------------------
3249 VAL_ALU_ONES_CHECK_FAILED:
3249 3249 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
324a 324a seq_br_type a Unconditional Return; Flow R
324b ; --------------------------------------------------------------------------------------
324b ; Comes from:
324b ; 3008 C from color 0x3000
324b ; 3009 C True from color 0x3000
324b ; --------------------------------------------------------------------------------------
324b VAL_REG_COMPARE_FAILED:
324b 324b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
324c 324c seq_br_type a Unconditional Return; Flow R
324d VAL_REG_INC_FAILED:
324d 324d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
324e 324e seq_br_type a Unconditional Return; Flow R
324f ; --------------------------------------------------------------------------------------
324f ; Comes from:
324f ; 300d C from color 0x3000
324f ; --------------------------------------------------------------------------------------
324f VAL_INC_A_FAILED:
324f 324f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3250 3250 seq_br_type a Unconditional Return; Flow R
3251 ; --------------------------------------------------------------------------------------
3251 ; Comes from:
3251 ; 300f C True from color 0x3000
3251 ; --------------------------------------------------------------------------------------
3251 VAL_START_BIT64_ERROR:
3251 3251 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3252 3252 seq_br_type a Unconditional Return; Flow R
3253 ; --------------------------------------------------------------------------------------
3253 ; Comes from:
3253 ; 3010 C False from color 0x3000
3253 ; 3011 C False from color 0x3000
3253 ; 3012 C False from color 0x3000
3253 ; 3013 C False from color 0x3000
3253 ; 3014 C False from color 0x3000
3253 ; 3015 C False from color 0x3000
3253 ; 3016 C False from color 0x3000
3253 ; 3017 C False from color 0x3000
3253 ; 3018 C False from color 0x3000
3253 ; 3019 C False from color 0x3000
3253 ; 301a C False from color 0x3000
3253 ; 301b C False from color 0x3000
3253 ; 301c C False from color 0x3000
3253 ; 301d C False from color 0x3000
3253 ; 301e C False from color 0x3000
3253 ; 301f C False from color 0x3000
3253 ; 3020 C False from color 0x3000
3253 ; 3021 C False from color 0x3000
3253 ; 3022 C False from color 0x3000
3253 ; 3023 C False from color 0x3000
3253 ; 3024 C False from color 0x3000
3253 ; 3025 C False from color 0x3000
3253 ; 3026 C False from color 0x3000
3253 ; 3027 C False from color 0x3000
3253 ; 3028 C False from color 0x3000
3253 ; 3029 C False from color 0x3000
3253 ; 302a C False from color 0x3000
3253 ; 302b C False from color 0x3000
3253 ; 302c C False from color 0x3000
3253 ; 302d C False from color 0x3000
3253 ; 302e C False from color 0x3000
3253 ; 302f C False from color 0x3000
3253 ; 3030 C False from color 0x3000
3253 ; 3031 C False from color 0x3000
3253 ; 3032 C False from color 0x3000
3253 ; 3033 C False from color 0x3000
3253 ; 3034 C False from color 0x3000
3253 ; 3035 C False from color 0x3000
3253 ; 3036 C False from color 0x3000
3253 ; 3037 C False from color 0x3000
3253 ; 3038 C False from color 0x3000
3253 ; 3039 C False from color 0x3000
3253 ; 303a C False from color 0x3000
3253 ; 303b C False from color 0x3000
3253 ; 303c C False from color 0x3000
3253 ; 303d C False from color 0x3000
3253 ; 303e C False from color 0x3000
3253 ; 303f C False from color 0x3000
3253 ; 3040 C False from color 0x3000
3253 ; 3041 C False from color 0x3000
3253 ; 3042 C False from color 0x3000
3253 ; 3043 C False from color 0x3000
3253 ; 3044 C False from color 0x3000
3253 ; 3045 C False from color 0x3000
3253 ; 3046 C False from color 0x3000
3253 ; 3047 C False from color 0x3000
3253 ; 3048 C False from color 0x3000
3253 ; 3049 C False from color 0x3000
3253 ; 304a C False from color 0x3000
3253 ; 304b C False from color 0x3000
3253 ; 304c C False from color 0x3000
3253 ; 304d C False from color 0x3000
3253 ; 304e C False from color 0x3000
3253 ; 304f C False from color 0x3000
3253 ; --------------------------------------------------------------------------------------
3253 VAL_BIT64_ERROR:
3253 3253 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3254 3254 seq_br_type a Unconditional Return; Flow R
3255 ; --------------------------------------------------------------------------------------
3255 ; Comes from:
3255 ; 3050 C True from color 0x3000
3255 ; --------------------------------------------------------------------------------------
3255 VAL_FINAL_BIT64_ERROR:
3255 3255 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3256 3256 seq_br_type a Unconditional Return; Flow R
3257 ; --------------------------------------------------------------------------------------
3257 ; Comes from:
3257 ; 3053 C True from color 0x3000
3257 ; --------------------------------------------------------------------------------------
3257 VAL_START_ALU_NE_0_ERROR:
3257 3257 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3258 3258 seq_br_type a Unconditional Return; Flow R
3259 ; --------------------------------------------------------------------------------------
3259 ; Comes from:
3259 ; 3054 C True from color 0x3000
3259 ; 3055 C True from color 0x3000
3259 ; 3056 C True from color 0x3000
3259 ; 3057 C True from color 0x3000
3259 ; 3058 C True from color 0x3000
3259 ; 3059 C True from color 0x3000
3259 ; 305a C True from color 0x3000
3259 ; 305b C True from color 0x3000
3259 ; 305c C True from color 0x3000
3259 ; 305d C True from color 0x3000
3259 ; 305e C True from color 0x3000
3259 ; 305f C True from color 0x3000
3259 ; 3060 C True from color 0x3000
3259 ; 3061 C True from color 0x3000
3259 ; 3062 C True from color 0x3000
3259 ; 3063 C True from color 0x3000
3259 ; 3064 C True from color 0x3000
3259 ; 3065 C True from color 0x3000
3259 ; 3066 C True from color 0x3000
3259 ; 3067 C True from color 0x3000
3259 ; 3068 C True from color 0x3000
3259 ; 3069 C True from color 0x3000
3259 ; 306a C True from color 0x3000
3259 ; 306b C True from color 0x3000
3259 ; 306c C True from color 0x3000
3259 ; 306d C True from color 0x3000
3259 ; 306e C True from color 0x3000
3259 ; 306f C True from color 0x3000
3259 ; 3070 C True from color 0x3000
3259 ; 3071 C True from color 0x3000
3259 ; 3072 C True from color 0x3000
3259 ; 3073 C True from color 0x3000
3259 ; 3074 C True from color 0x3000
3259 ; 3075 C True from color 0x3000
3259 ; 3076 C True from color 0x3000
3259 ; 3077 C True from color 0x3000
3259 ; 3078 C True from color 0x3000
3259 ; 3079 C True from color 0x3000
3259 ; 307a C True from color 0x3000
3259 ; 307b C True from color 0x3000
3259 ; 307c C True from color 0x3000
3259 ; 307d C True from color 0x3000
3259 ; 307e C True from color 0x3000
3259 ; 307f C True from color 0x3000
3259 ; 3080 C True from color 0x3000
3259 ; 3081 C True from color 0x3000
3259 ; 3082 C True from color 0x3000
3259 ; 3083 C True from color 0x3000
3259 ; 3084 C True from color 0x3000
3259 ; 3085 C True from color 0x3000
3259 ; 3086 C True from color 0x3000
3259 ; 3087 C True from color 0x3000
3259 ; 3088 C True from color 0x3000
3259 ; 3089 C True from color 0x3000
3259 ; 308a C True from color 0x3000
3259 ; 308b C True from color 0x3000
3259 ; 308c C True from color 0x3000
3259 ; 308d C True from color 0x3000
3259 ; 308e C True from color 0x3000
3259 ; 308f C True from color 0x3000
3259 ; 3090 C True from color 0x3000
3259 ; 3091 C True from color 0x3000
3259 ; 3092 C True from color 0x3000
3259 ; 3093 C True from color 0x3000
3259 ; --------------------------------------------------------------------------------------
3259 VAL_ALU_NE_0_ERROR:
3259 3259 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
325a 325a seq_br_type a Unconditional Return; Flow R
325b ; --------------------------------------------------------------------------------------
325b ; Comes from:
325b ; 3094 C True from color 0x3000
325b ; --------------------------------------------------------------------------------------
325b VAL_FINAL_ALU_NE_0_ERROR:
325b 325b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
325c 325c seq_br_type a Unconditional Return; Flow R
325d ; --------------------------------------------------------------------------------------
325d ; Comes from:
325d ; 3096 C from color 0x3000
325d ; 3097 C True from color 0x3000
325d ; --------------------------------------------------------------------------------------
325d TYP_ALU_ZERO_CHECK_FAILED:
325d 325d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
325e 325e seq_br_type a Unconditional Return; Flow R
325f ; --------------------------------------------------------------------------------------
325f ; Comes from:
325f ; 3099 C from color 0x3000
325f ; 309a C True from color 0x3000
325f ; --------------------------------------------------------------------------------------
325f TYP_ALU_ONES_CHECK_FAILED:
325f 325f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3260 3260 seq_br_type a Unconditional Return; Flow R
3261 ; --------------------------------------------------------------------------------------
3261 ; Comes from:
3261 ; 309d C from color 0x3000
3261 ; 309e C True from color 0x3000
3261 ; --------------------------------------------------------------------------------------
3261 TYP_REG_COMPARE_FAILED:
3261 3261 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3262 3262 seq_br_type a Unconditional Return; Flow R
3263 TYP_REG_INC_FAILED:
3263 3263 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3264 3264 seq_br_type a Unconditional Return; Flow R
3265 ; --------------------------------------------------------------------------------------
3265 ; Comes from:
3265 ; 30a2 C from color 0x3000
3265 ; --------------------------------------------------------------------------------------
3265 TYP_INC_A_FAILED:
3265 3265 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3266 3266 seq_br_type a Unconditional Return; Flow R
3267 ; --------------------------------------------------------------------------------------
3267 ; Comes from:
3267 ; 30a4 C True from color 0x3000
3267 ; --------------------------------------------------------------------------------------
3267 TYP_START_BIT64_ERROR:
3267 3267 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3268 3268 seq_br_type a Unconditional Return; Flow R
3269 ; --------------------------------------------------------------------------------------
3269 ; Comes from:
3269 ; 30a5 C False from color 0x3000
3269 ; 30a6 C False from color 0x3000
3269 ; 30a7 C False from color 0x3000
3269 ; 30a8 C False from color 0x3000
3269 ; 30a9 C False from color 0x3000
3269 ; 30aa C False from color 0x3000
3269 ; 30ab C False from color 0x3000
3269 ; 30ac C False from color 0x3000
3269 ; 30ad C False from color 0x3000
3269 ; 30ae C False from color 0x3000
3269 ; 30af C False from color 0x3000
3269 ; 30b0 C False from color 0x3000
3269 ; 30b1 C False from color 0x3000
3269 ; 30b2 C False from color 0x3000
3269 ; 30b3 C False from color 0x3000
3269 ; 30b4 C False from color 0x3000
3269 ; 30b5 C False from color 0x3000
3269 ; 30b6 C False from color 0x3000
3269 ; 30b7 C False from color 0x3000
3269 ; 30b8 C False from color 0x3000
3269 ; 30b9 C False from color 0x3000
3269 ; 30ba C False from color 0x3000
3269 ; 30bb C False from color 0x3000
3269 ; 30bc C False from color 0x3000
3269 ; 30bd C False from color 0x3000
3269 ; 30be C False from color 0x3000
3269 ; 30bf C False from color 0x3000
3269 ; 30c0 C False from color 0x3000
3269 ; 30c1 C False from color 0x3000
3269 ; 30c2 C False from color 0x3000
3269 ; 30c3 C False from color 0x3000
3269 ; 30c4 C False from color 0x3000
3269 ; 30c5 C False from color 0x3000
3269 ; 30c6 C False from color 0x3000
3269 ; 30c7 C False from color 0x3000
3269 ; 30c8 C False from color 0x3000
3269 ; 30c9 C False from color 0x3000
3269 ; 30ca C False from color 0x3000
3269 ; 30cb C False from color 0x3000
3269 ; 30cc C False from color 0x3000
3269 ; 30cd C False from color 0x3000
3269 ; 30ce C False from color 0x3000
3269 ; 30cf C False from color 0x3000
3269 ; 30d0 C False from color 0x3000
3269 ; 30d1 C False from color 0x3000
3269 ; 30d2 C False from color 0x3000
3269 ; 30d3 C False from color 0x3000
3269 ; 30d4 C False from color 0x3000
3269 ; 30d5 C False from color 0x3000
3269 ; 30d6 C False from color 0x3000
3269 ; 30d7 C False from color 0x3000
3269 ; 30d8 C False from color 0x3000
3269 ; 30d9 C False from color 0x3000
3269 ; 30da C False from color 0x3000
3269 ; 30db C False from color 0x3000
3269 ; 30dc C False from color 0x3000
3269 ; 30dd C False from color 0x3000
3269 ; 30de C False from color 0x3000
3269 ; 30df C False from color 0x3000
3269 ; 30e0 C False from color 0x3000
3269 ; 30e1 C False from color 0x3000
3269 ; 30e2 C False from color 0x3000
3269 ; 30e3 C False from color 0x3000
3269 ; 30e4 C False from color 0x3000
3269 ; --------------------------------------------------------------------------------------
3269 TYP_BIT64_ERROR:
3269 3269 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
326a 326a seq_br_type a Unconditional Return; Flow R
326b ; --------------------------------------------------------------------------------------
326b ; Comes from:
326b ; 30e5 C True from color 0x3000
326b ; --------------------------------------------------------------------------------------
326b TYP_FINAL_BIT64_ERROR:
326b 326b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
326c 326c seq_br_type a Unconditional Return; Flow R
326d ; --------------------------------------------------------------------------------------
326d ; Comes from:
326d ; 30e8 C True from color 0x3000
326d ; --------------------------------------------------------------------------------------
326d TYP_START_ALU_NE_0_ERROR:
326d 326d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
326e 326e seq_br_type a Unconditional Return; Flow R
326f ; --------------------------------------------------------------------------------------
326f ; Comes from:
326f ; 30e9 C True from color 0x3000
326f ; 30ea C True from color 0x3000
326f ; 30eb C True from color 0x3000
326f ; 30ec C True from color 0x3000
326f ; 30ed C True from color 0x3000
326f ; 30ee C True from color 0x3000
326f ; 30ef C True from color 0x3000
326f ; 30f0 C True from color 0x3000
326f ; 30f1 C True from color 0x3000
326f ; 30f2 C True from color 0x3000
326f ; 30f3 C True from color 0x3000
326f ; 30f4 C True from color 0x3000
326f ; 30f5 C True from color 0x3000
326f ; 30f6 C True from color 0x3000
326f ; 30f7 C True from color 0x3000
326f ; 30f8 C True from color 0x3000
326f ; 30f9 C True from color 0x3000
326f ; 30fa C True from color 0x3000
326f ; 30fb C True from color 0x3000
326f ; 30fc C True from color 0x3000
326f ; 30fd C True from color 0x3000
326f ; 30fe C True from color 0x3000
326f ; 30ff C True from color 0x3000
326f ; 3100 C True from color 0x3000
326f ; 3101 C True from color 0x3000
326f ; 3102 C True from color 0x3000
326f ; 3103 C True from color 0x3000
326f ; 3104 C True from color 0x3000
326f ; 3105 C True from color 0x3000
326f ; 3106 C True from color 0x3000
326f ; 3107 C True from color 0x3000
326f ; 3108 C True from color 0x3000
326f ; 3109 C True from color 0x3000
326f ; 310a C True from color 0x3000
326f ; 310b C True from color 0x3000
326f ; 310c C True from color 0x3000
326f ; 310d C True from color 0x3000
326f ; 310e C True from color 0x3000
326f ; 310f C True from color 0x3000
326f ; 3110 C True from color 0x3000
326f ; 3111 C True from color 0x3000
326f ; 3112 C True from color 0x3000
326f ; 3113 C True from color 0x3000
326f ; 3114 C True from color 0x3000
326f ; 3115 C True from color 0x3000
326f ; 3116 C True from color 0x3000
326f ; 3117 C True from color 0x3000
326f ; 3118 C True from color 0x3000
326f ; 3119 C True from color 0x3000
326f ; 311a C True from color 0x3000
326f ; 311b C True from color 0x3000
326f ; 311c C True from color 0x3000
326f ; 311d C True from color 0x3000
326f ; 311e C True from color 0x3000
326f ; 311f C True from color 0x3000
326f ; 3120 C True from color 0x3000
326f ; 3121 C True from color 0x3000
326f ; 3122 C True from color 0x3000
326f ; 3123 C True from color 0x3000
326f ; 3124 C True from color 0x3000
326f ; 3125 C True from color 0x3000
326f ; 3126 C True from color 0x3000
326f ; 3127 C True from color 0x3000
326f ; 3128 C True from color 0x3000
326f ; --------------------------------------------------------------------------------------
326f TYP_ALU_NE_0_ERROR:
326f 326f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3270 3270 seq_br_type a Unconditional Return; Flow R
3271 ; --------------------------------------------------------------------------------------
3271 ; Comes from:
3271 ; 3129 C True from color 0x3000
3271 ; --------------------------------------------------------------------------------------
3271 TYP_FINAL_ALU_NE_0_ERROR:
3271 3271 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3272 3272 seq_br_type a Unconditional Return; Flow R
3273 ; --------------------------------------------------------------------------------------
3273 ; Comes from:
3273 ; 31c7 C True from color 0x3000
3273 ; --------------------------------------------------------------------------------------
3273 TYP_A_SIDE_ZERO_ERROR:
3273 3273 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3274 3274 seq_br_type a Unconditional Return; Flow R
3275 ; --------------------------------------------------------------------------------------
3275 ; Comes from:
3275 ; 31c8 C True from color 0x3000
3275 ; --------------------------------------------------------------------------------------
3275 TYP_B_SIDE_ZERO_ERROR:
3275 3275 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3276 3276 seq_br_type a Unconditional Return; Flow R
3277 ; --------------------------------------------------------------------------------------
3277 ; Comes from:
3277 ; 31c9 C True from color 0x3000
3277 ; --------------------------------------------------------------------------------------
3277 TYP_A_B_ZERO_ERROR:
3277 3277 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3278 3278 seq_br_type a Unconditional Return; Flow R
3279 ; --------------------------------------------------------------------------------------
3279 ; Comes from:
3279 ; 31ca C True from color 0x3000
3279 ; --------------------------------------------------------------------------------------
3279 VAL_A_SIDE_ZERO_ERROR:
3279 3279 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
327a 327a seq_br_type a Unconditional Return; Flow R
327b ; --------------------------------------------------------------------------------------
327b ; Comes from:
327b ; 31cb C True from color 0x3000
327b ; --------------------------------------------------------------------------------------
327b VAL_B_SIDE_ZERO_ERROR:
327b 327b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
327c 327c seq_br_type a Unconditional Return; Flow R
327d ; --------------------------------------------------------------------------------------
327d ; Comes from:
327d ; 31cc C True from color 0x3000
327d ; --------------------------------------------------------------------------------------
327d VAL_A_B_ZERO_ERROR:
327d 327d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
327e 327e seq_br_type a Unconditional Return; Flow R
327f ; --------------------------------------------------------------------------------------
327f ; Comes from:
327f ; 31d0 C True from color 0x3000
327f ; --------------------------------------------------------------------------------------
327f TYP_A_SIDE_ONES_ERROR:
327f 327f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3280 3280 seq_br_type a Unconditional Return; Flow R
3281 ; --------------------------------------------------------------------------------------
3281 ; Comes from:
3281 ; 31d1 C True from color 0x3000
3281 ; --------------------------------------------------------------------------------------
3281 TYP_B_SIDE_ONES_ERROR:
3281 3281 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3282 3282 seq_br_type a Unconditional Return; Flow R
3283 ; --------------------------------------------------------------------------------------
3283 ; Comes from:
3283 ; 31d2 C True from color 0x3000
3283 ; --------------------------------------------------------------------------------------
3283 TYP_A_B_ONES_ERROR:
3283 3283 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3284 3284 seq_br_type a Unconditional Return; Flow R
3285 ; --------------------------------------------------------------------------------------
3285 ; Comes from:
3285 ; 31d3 C True from color 0x3000
3285 ; --------------------------------------------------------------------------------------
3285 VAL_A_SIDE_ONES_ERROR:
3285 3285 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3286 3286 seq_br_type a Unconditional Return; Flow R
3287 ; --------------------------------------------------------------------------------------
3287 ; Comes from:
3287 ; 31d4 C True from color 0x3000
3287 ; --------------------------------------------------------------------------------------
3287 VAL_B_SIDE_ONES_ERROR:
3287 3287 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3288 3288 seq_br_type a Unconditional Return; Flow R
3289 ; --------------------------------------------------------------------------------------
3289 ; Comes from:
3289 ; 31d5 C True from color 0x3000
3289 ; --------------------------------------------------------------------------------------
3289 VAL_A_B_ONES_ERROR:
3289 3289 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
328a 328a seq_br_type a Unconditional Return; Flow R
328b ; --------------------------------------------------------------------------------------
328b ; Comes from:
328b ; 31d9 C True from color 0x3000
328b ; 31db C True from color 0x3000
328b ; --------------------------------------------------------------------------------------
328b TYP_COUNTER_CONTENTS_ERROR:
328b 328b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
328c 328c seq_br_type a Unconditional Return; Flow R
328d ; --------------------------------------------------------------------------------------
328d ; Comes from:
328d ; 31da C True from color 0x3000
328d ; 31dc C True from color 0x3000
328d ; --------------------------------------------------------------------------------------
328d TYP_COMPARE_ERROR:
328d 328d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
328e 328e seq_br_type a Unconditional Return; Flow R
328f VAL_COUNTER_CONTENTS_ERROR:
328f 328f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3290 3290 seq_br_type a Unconditional Return; Flow R
3291 VAL_COMPARE_ERROR:
3291 3291 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3292 3292 seq_br_type a Unconditional Return; Flow R
3293 ; --------------------------------------------------------------------------------------
3293 ; Comes from:
3293 ; 316b C True from color 0x3000
3293 ; --------------------------------------------------------------------------------------
3293 VAL_REG_BAD_LOAD:
3293 3293 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3294 3294 seq_br_type a Unconditional Return; Flow R
3295 ; --------------------------------------------------------------------------------------
3295 ; Comes from:
3295 ; 316c C True from color 0x3000
3295 ; 316d C True from color 0x3000
3295 ; 3173 C True from color 0x3000
3295 ; 3174 C True from color 0x3000
3295 ; 3179 C True from color 0x3000
3295 ; 317a C True from color 0x3000
3295 ; 317f C True from color 0x3000
3295 ; 3180 C True from color 0x3000
3295 ; 3185 C True from color 0x3000
3295 ; 3186 C True from color 0x3000
3295 ; 318b C True from color 0x3000
3295 ; 318c C True from color 0x3000
3295 ; 3191 C True from color 0x3000
3295 ; 3192 C True from color 0x3000
3295 ; 3197 C True from color 0x3000
3295 ; 3198 C True from color 0x3000
3295 ; 319d C True from color 0x3000
3295 ; 319e C True from color 0x3000
3295 ; 31a3 C True from color 0x3000
3295 ; 31a4 C True from color 0x3000
3295 ; 31a9 C True from color 0x3000
3295 ; 31aa C True from color 0x3000
3295 ; 31af C True from color 0x3000
3295 ; 31b0 C True from color 0x3000
3295 ; 31b5 C True from color 0x3000
3295 ; 31b6 C True from color 0x3000
3295 ; 31bb C True from color 0x3000
3295 ; 31bc C True from color 0x3000
3295 ; 31c1 C True from color 0x3000
3295 ; 31c2 C True from color 0x3000
3295 ; --------------------------------------------------------------------------------------
3295 VAL_NIBBLE_ERROR:
3295 3295 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3296 3296 seq_br_type a Unconditional Return; Flow R
3297 ; --------------------------------------------------------------------------------------
3297 ; Comes from:
3297 ; 316e C True from color 0x3000
3297 ; --------------------------------------------------------------------------------------
3297 TYP_REG_BAD_LOAD:
3297 3297 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
3298 3298 seq_br_type a Unconditional Return; Flow R
3299 ; --------------------------------------------------------------------------------------
3299 ; Comes from:
3299 ; 316f C True from color 0x3000
3299 ; 3170 C True from color 0x3000
3299 ; 3175 C True from color 0x3000
3299 ; 3176 C True from color 0x3000
3299 ; 317b C True from color 0x3000
3299 ; 317c C True from color 0x3000
3299 ; 3181 C True from color 0x3000
3299 ; 3182 C True from color 0x3000
3299 ; 3187 C True from color 0x3000
3299 ; 3188 C True from color 0x3000
3299 ; 318d C True from color 0x3000
3299 ; 318e C True from color 0x3000
3299 ; 3193 C True from color 0x3000
3299 ; 3194 C True from color 0x3000
3299 ; 3199 C True from color 0x3000
3299 ; 319a C True from color 0x3000
3299 ; 319f C True from color 0x3000
3299 ; 31a0 C True from color 0x3000
3299 ; 31a5 C True from color 0x3000
3299 ; 31a6 C True from color 0x3000
3299 ; 31ab C True from color 0x3000
3299 ; 31ac C True from color 0x3000
3299 ; 31b1 C True from color 0x3000
3299 ; 31b2 C True from color 0x3000
3299 ; 31b7 C True from color 0x3000
3299 ; 31b8 C True from color 0x3000
3299 ; 31bd C True from color 0x3000
3299 ; 31be C True from color 0x3000
3299 ; 31c3 C True from color 0x3000
3299 ; 31c4 C True from color 0x3000
3299 ; --------------------------------------------------------------------------------------
3299 TYP_NIBBLE_ERROR:
3299 3299 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
329a 329a seq_br_type a Unconditional Return; Flow R
329b ; --------------------------------------------------------------------------------------
329b ; Comes from:
329b ; 31df C from color 0x3000
329b ; 31e0 C True from color 0x3000
329b ; 31e1 C True from color 0x3000
329b ; 31e2 C True from color 0x3000
329b ; 31e3 C True from color 0x3000
329b ; 31e4 C True from color 0x3000
329b ; 31f8 C from color 0x3000
329b ; 31f9 C True from color 0x3000
329b ; 31fa C True from color 0x3000
329b ; 31fb C True from color 0x3000
329b ; 31fc C True from color 0x3000
329b ; 31fd C True from color 0x3000
329b ; --------------------------------------------------------------------------------------
329b VAL_A_SIDE_ADDR_ERROR:
329b 329b ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
329c 329c seq_br_type a Unconditional Return; Flow R
329d ; --------------------------------------------------------------------------------------
329d ; Comes from:
329d ; 31e5 C True from color 0x3000
329d ; 31e6 C True from color 0x3000
329d ; 31e7 C True from color 0x3000
329d ; 31e8 C True from color 0x3000
329d ; 31e9 C True from color 0x3000
329d ; 31fe C True from color 0x3000
329d ; 31ff C True from color 0x3000
329d ; 3200 C True from color 0x3000
329d ; 3201 C True from color 0x3000
329d ; 3202 C True from color 0x3000
329d ; --------------------------------------------------------------------------------------
329d VAL_A_SIDE_FRAME_ERROR:
329d 329d ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
329e 329e seq_br_type a Unconditional Return; Flow R
329f ; --------------------------------------------------------------------------------------
329f ; Comes from:
329f ; 31eb C from color 0x3000
329f ; 31ec C True from color 0x3000
329f ; 31ed C True from color 0x3000
329f ; 31ee C True from color 0x3000
329f ; 31ef C True from color 0x3000
329f ; 31f0 C True from color 0x3000
329f ; 3204 C from color 0x3000
329f ; 3205 C True from color 0x3000
329f ; 3206 C True from color 0x3000
329f ; 3207 C True from color 0x3000
329f ; 3208 C True from color 0x3000
329f ; 3209 C True from color 0x3000
329f ; --------------------------------------------------------------------------------------
329f VAL_B_SIDE_ADDR_ERROR:
329f 329f ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32a0 32a0 seq_br_type a Unconditional Return; Flow R
32a1 ; --------------------------------------------------------------------------------------
32a1 ; Comes from:
32a1 ; 31f1 C True from color 0x3000
32a1 ; 31f2 C True from color 0x3000
32a1 ; 31f3 C True from color 0x3000
32a1 ; 31f4 C True from color 0x3000
32a1 ; 31f5 C True from color 0x3000
32a1 ; 320a C True from color 0x3000
32a1 ; 320b C True from color 0x3000
32a1 ; 320c C True from color 0x3000
32a1 ; 320d C True from color 0x3000
32a1 ; 320e C True from color 0x3000
32a1 ; --------------------------------------------------------------------------------------
32a1 VAL_B_SIDE_FRAME_ERROR:
32a1 32a1 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32a2 32a2 seq_br_type a Unconditional Return; Flow R
32a3 ; --------------------------------------------------------------------------------------
32a3 ; Comes from:
32a3 ; 3211 C True from color 0x3000
32a3 ; 3212 C True from color 0x3000
32a3 ; 3213 C True from color 0x3000
32a3 ; 3214 C True from color 0x3000
32a3 ; 3215 C True from color 0x3000
32a3 ; 3229 C from color 0x3000
32a3 ; 322a C True from color 0x3000
32a3 ; 322b C True from color 0x3000
32a3 ; 322c C True from color 0x3000
32a3 ; 322d C True from color 0x3000
32a3 ; 322e C True from color 0x3000
32a3 ; --------------------------------------------------------------------------------------
32a3 TYP_A_SIDE_ADDR_ERROR:
32a3 32a3 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32a4 32a4 seq_br_type a Unconditional Return; Flow R
32a5 ; --------------------------------------------------------------------------------------
32a5 ; Comes from:
32a5 ; 3216 C True from color 0x3000
32a5 ; 3217 C True from color 0x3000
32a5 ; 3218 C True from color 0x3000
32a5 ; 3219 C True from color 0x3000
32a5 ; 321a C True from color 0x3000
32a5 ; 322f C True from color 0x3000
32a5 ; 3230 C True from color 0x3000
32a5 ; 3231 C True from color 0x3000
32a5 ; 3232 C True from color 0x3000
32a5 ; 3233 C True from color 0x3000
32a5 ; --------------------------------------------------------------------------------------
32a5 TYP_A_SIDE_FRAME_ERROR:
32a5 32a5 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32a6 32a6 seq_br_type a Unconditional Return; Flow R
32a7 ; --------------------------------------------------------------------------------------
32a7 ; Comes from:
32a7 ; 321c C from color 0x3000
32a7 ; 321d C True from color 0x3000
32a7 ; 321e C True from color 0x3000
32a7 ; 321f C True from color 0x3000
32a7 ; 3220 C True from color 0x3000
32a7 ; 3221 C True from color 0x3000
32a7 ; 3235 C from color 0x3000
32a7 ; 3236 C True from color 0x3000
32a7 ; 3237 C True from color 0x3000
32a7 ; 3238 C True from color 0x3000
32a7 ; 3239 C True from color 0x3000
32a7 ; 323a C True from color 0x3000
32a7 ; --------------------------------------------------------------------------------------
32a7 TYP_B_SIDE_ADDR_ERROR:
32a7 32a7 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32a8 32a8 seq_br_type a Unconditional Return; Flow R
32a9 ; --------------------------------------------------------------------------------------
32a9 ; Comes from:
32a9 ; 3222 C True from color 0x3000
32a9 ; 3223 C True from color 0x3000
32a9 ; 3224 C True from color 0x3000
32a9 ; 3225 C True from color 0x3000
32a9 ; 3226 C True from color 0x3000
32a9 ; 323b C True from color 0x3000
32a9 ; 323c C True from color 0x3000
32a9 ; 323d C True from color 0x3000
32a9 ; 323e C True from color 0x3000
32a9 ; 323f C True from color 0x3000
32a9 ; --------------------------------------------------------------------------------------
32a9 TYP_B_SIDE_FRAME_ERROR:
32a9 32a9 ioc_random 14 clear cpu running; Flow R
seq_random 01 Halt+?
32aa 32aa seq_br_type a Unconditional Return; Flow R
32ab 32ab ioc_fiubs 2 typ
ioc_load_wdr 0
32ac 32ac ioc_fiubs 2 typ
ioc_load_wdr 0
32ad 32ad ioc_fiubs 2 typ
ioc_load_wdr 0
32ae 32ae ioc_fiubs 2 typ
ioc_load_wdr 0
32af 32af ioc_fiubs 2 typ
ioc_load_wdr 0
32b0 32b0 ioc_fiubs 2 typ
ioc_load_wdr 0
32b1 32b1 ioc_fiubs 2 typ
ioc_load_wdr 0
32b2 32b2 ioc_fiubs 2 typ
ioc_load_wdr 0
32b3 32b3 ioc_fiubs 2 typ
ioc_load_wdr 0
32b4 32b4 ioc_fiubs 2 typ
ioc_load_wdr 0
32b5 32b5 ioc_fiubs 2 typ
ioc_load_wdr 0
32b6 32b6 ioc_fiubs 2 typ
ioc_load_wdr 0
32b7 32b7 ioc_fiubs 2 typ
ioc_load_wdr 0
32b8 32b8 ioc_fiubs 2 typ
ioc_load_wdr 0
32b9 32b9 ioc_fiubs 2 typ
ioc_load_wdr 0
32ba 32ba ioc_fiubs 2 typ
ioc_load_wdr 0
32bb 32bb ioc_fiubs 2 typ
ioc_load_wdr 0
32bc 32bc ioc_fiubs 2 typ
ioc_load_wdr 0
32bd 32bd ioc_fiubs 2 typ
ioc_load_wdr 0
32be 32be ioc_fiubs 2 typ
ioc_load_wdr 0
32bf 32bf ioc_fiubs 2 typ
ioc_load_wdr 0
32c0 32c0 <default>
PyReveng3/R1000.Disassembly disass_ucode.py /tmp/_aa_r1k_dfs/r1k_dfs/e3/e3b4e8973.tmp.0.18465 /tmp/_aa_r1k_dfs/r1k_dfs/e3/e3b4e8973.tmp.1.18466
FN /tmp/_aa_r1k_dfs/r1k_dfs/e3/e3b4e8973.tmp.0.18465
CX <__main__.R1kUcode object at 0x2509d9224950> CX.M <word_mem 0x100-0x32c1, @14 bits, 0 attr>
Case table at 0x1e17 lacks width <leaf 0x1e4c-0x1e4d R1KUCODE>
Case table at 0x1e17 lacks width <leaf 0x1e51-0x1e52 R1KUCODE>
Case table at 0x20fa lacks width <leaf 0x20f8-0x20f9 R1KUCODE>
Case table at 0x20fe lacks width <leaf 0x20fc-0x20fd R1KUCODE>
? None <leaf 0x32c0-0x32c1 R1KUCODE>
fiu_fill_mode_src 1 {1}
fiu_len_fill_lit 1 {127}
fiu_len_fill_reg_ctl 1 {3}
fiu_length_src 1 {1}
fiu_load_mdr 1 {0}
fiu_load_oreg 1 {0}
fiu_load_tar 1 {0}
fiu_load_var 1 {0}
fiu_mem_start 1 {2}
fiu_offs_lit 1 {0}
fiu_offset_src 1 {1}
fiu_op_sel 1 {0}
fiu_oreg_src 1 {1}
fiu_parity 1 {0}
fiu_rdata_src 1 {1}
fiu_tivi_src 1 {0}
fiu_vmux_sel 1 {2}
ioc_adrbs 1 {3}
ioc_fiubs 1 {3}
ioc_load_wdr 1 {1}
ioc_parity 1 {1}
ioc_random 1 {0}
ioc_tvbs 1 {0}
seq_latch 1 {0}
seq_lex_adr 1 {0}
typ_c_lit 1 {3}
typ_c_source 1 {1}
typ_mar_cntl 1 {14}
typ_priv_check 1 {7}
val_c_source 1 {1}
val_m_a_src 1 {3}
val_m_b_src 1 {3}
Stranger in color <Color 1 0x104-0x323 #4> <Stretch 106 6> <Color 2 0x106-0x325 #3>
Stranger in color <Color 2 0x106-0x325 #3> <Stretch 107 7> <Color 3 0x107-0x107 #1>
Stranger in color <Color 105 0x188-0x22d #44> <Stretch 18b 139> <Color 106 0x18b-0x18b #1>
Stranger in color <Color 2516 0x1ee3-0x2060 #369> <Stretch 2037 7991> <Color 2517 0x2037-0x2037 #1>
Stranger in color <Color 2528 0x2064-0x2076 #18> <Stretch 2066 8038> <Color 2529 0x2066-0x2066 #1>
Stranger in color <Color 2581 0x20ee-0x20fe #14> <Stretch 20f5 8181> <Color 2582 0x20f5-0x20f5 #1>
Stranger in color <Color 2587 0x219d-0x2240 #18> <Stretch 21a2 8354> <Color 2588 0x21a2-0x2244 #35>
Stranger in color <Color 2588 0x21a2-0x2244 #35> <Stretch 21ab 8363> <Color 2589 0x21ab-0x21ad #3>
Stranger in color <Color 2590 0x21ae-0x2246 #18> <Stretch 21b3 8371> <Color 2591 0x21b3-0x224a #35>
Stranger in color <Color 2591 0x21b3-0x224a #35> <Stretch 21bc 8380> <Color 2587 0x219d-0x2240 #18>
Stranger in color <Color 3076 0x2400-0x2726 #396> <Stretch 24fd 9213> <Color 3077 0x24fd-0x2502 #6>
Stranger in color <Color 3314 0x2800-0x29d5 #414> <Stretch 2876 10102> <Color 3315 0x2876-0x287a #5>
Stranger in color <Color 3620 0x2b00-0x2c1b #219> <Stretch 2b01 10753> <Color 3621 0x2b01-0x2b08 #8>
Stranger in color <Color 4121 0x2eb7-0x2ec9 #4> <Stretch 2eba 11706> <Color 4122 0x2eba-0x2ebc #3>
PFX /tmp/_aa_r1k_dfs/r1k_dfs/e3/e3b4e8973.tmp