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Current Status

Test Wall Clock SystemC Ratio Exp run Exp fail
expmon_reset_all 194.764 0.084657 1/2300.6 0 0
expmon_test_fiu 5650.484 22.357757 1/252.7 95 4
expmon_test_ioc 1857.896 11.497539 1/161.6 29 0
expmon_test_mem32 701.663 1.000000 1/701.7 13 10
expmon_test_seq 5851.747 14.467354 1/404.5 108 23
expmon_test_typ 6925.884 6.794901 1/1019.3 72 49
expmon_test_val 7341.391 7.583500 1/968.1 65 19
novram 369.061 0.115628 1/3191.8 0 0

2022-01-17 CI for SystemC

Continuous Integration is all the rage these days, and it is convenient, so we have started to implement something that could conceivably look like it for our project.

Right now it is simply some shell scripts executing a handful of tests, recording relevant artifacts and statistics, and we will snapshot this into the table at the top of this page as events warrant.

The first two tests, "novram" and "expmon_reset_all" runs with all the boards, and are an attempt to get a feel for the overall, full system performance. The remaining six tests run with only the relevant board enabled, in addition to the obligatory IOC and those are about making things work, but also indicates which boards soak up most resources.

Getting MEM32 into the table required us to work up some GAL-bitmap -> SystemC python code, and at least for the DISTPAL and DIBRPAL in the DFSM on MEM32, they now seem to do the right thing.

There is obviously plenty of room for improvements.

2022-01-10 SystemC performance is weird

As often aluded to, the performance of a SystemC simulation is … not ideal … from a usability point of view, so we spend a lot of time thinking about it and measuring it, and it is not at all intuitive for software people like us.

Take the following (redrawn) sheet from the IOC schematic (click for full size)


This is the 2048x16 bit FIFO buffer through which the IOC sends replies the the R1000 CPU.

None of the tests in the "TEST_IOC.EM" file gets anywhere near this FIFO, yet the simulation runs 15% faster if this sheet is commented out, because this sheet uses a lot of free-running clocks:

   1 * 2X~     @ 20 MHz        20 MHz
   2 * H2.PHD  @ 10 MHz        20 MHz
   2 * H1E     @ 10 MHz        20 MHz
   1 * H2E     @ 10 MHz        10 MHz
   1 * Q1~      @ 5 MHz         5 MHz
   2 * Q2~      @ 5 MHz        10 MHz
   1 * Q3~      @ 5 MHz         5 MHz
   Simulation load             90 MHz

Where the clocks feed into edge sensitive chip, for instance "Q1~" to "FOREG0" (left center), only one of the flanks need to be simulated, but when state sensitive gates like "2X~" into "FFNAN0A" (near the top), the "FOO" class instance is called for both flanks, effectively doubling the frequency of the 10MHz clock signal.

To make matters even worse, there is an identical FIFO feeding requests the opposite way, from R1000 to IOC, on the next sheet.

And to really drive the point home, all the simulation runs will have to include the IOC board.

In SystemC a FIFO is one of the primitive objects, which can simulate these two pages much faster than this, but to do that we need enough of the machine simulated well enough, to run the experiments which tests the FIFOs.

Until then, we can save oceans of time by simply commenting these two FIFOs out.

2022-01-08 Making headway with FIU

We are making headway with the simulated FIU board, currently 19 tests fail, the 16 "Execute from WCS" and three parity-related tests. We hope the 16 WCS tests have a common cause.

On the FIU we have found the first test-case which depends on undocumented behaviour: TEST_ABUS_PARITY.FIU fails if OFFREG does not have even parity when the test starts.

Simulating the IOC and FIU boards, the simulation currently clocks around 1/380 of hardware speed, if the TYP, VAL and SEQ boards are also simulated, speed drops to 1/3000 of hardware speed. Not bad, not certainly not good.

We have started playing with "mega-symbols" for instance 64bit versions of the 74F240, 74F244 and 74F374. There is a speed advantage, but the major advantage right now is that debugging operates on the entire bus-width at the same time.


  • 2014-2018 - The project got stuck for lack of a sufficiently beefy 5V power-supply, and then phk disappeared while he built a new house.

Many thanks to

  • Erlo Haugen
  • Grady Booch
  • Grek Bek
  • Pierre-Alain Muller
  • Pascal Leroy
  • Michael Druke
  • Pascal Leroy